platform/kernel/u-boot.git
16 years agoMerge branch 'master' of git://www.denx.de/git/u-boot-mpc83xx
Wolfgang Denk [Mon, 7 Apr 2008 21:59:10 +0000 (23:59 +0200)]
Merge branch 'master' of git://denx.de/git/u-boot-mpc83xx

Conflicts:

lib_ppc/board.c

Signed-off-by: Wolfgang Denk <wd@denx.de>
16 years agoMerge branch 'master' of git://www.denx.de/git/u-boot-cfi-flash
Wolfgang Denk [Mon, 7 Apr 2008 21:55:47 +0000 (23:55 +0200)]
Merge branch 'master' of git://denx.de/git/u-boot-cfi-flash

16 years agoMerge branch 'master' of git://www.denx.de/git/u-boot-ppc4xx
Wolfgang Denk [Mon, 7 Apr 2008 21:52:32 +0000 (23:52 +0200)]
Merge branch 'master' of git://denx.de/git/u-boot-ppc4xx

16 years agoppc4xx: Fix 4xx enet driver to support 460GT EMAC2+3
Stefan Roese [Thu, 3 Apr 2008 12:50:34 +0000 (14:50 +0200)]
ppc4xx: Fix 4xx enet driver to support 460GT EMAC2+3

This patch fixes a problem with the RGMII setup of the 460GT. The 460GT
has 2 RGMII instances and we need to configure the 2nd RGMII instance
for the EMAC2+3 channels.

Signed-off-by: Stefan Roese <sr@denx.de>
16 years agoppc4xx: Canyonlands: Init SATA/PCIe port correctly
Stefan Roese [Wed, 2 Apr 2008 06:39:33 +0000 (08:39 +0200)]
ppc4xx: Canyonlands: Init SATA/PCIe port correctly

Canyonlands (460EX) shares the first PCIe interface with the SoC SATA
interface. This usage can be configured with the jumper J6. This patch
correctly configures the SATA/PCIe PHY for SATA usage when this jumper
is installed.

Signed-off-by: Stefan Roese <sr@denx.de>
16 years agoppc4xx: Add CFG_MEM_TOP_HIDE to Denali SPD-based SDRAM setup
Larry Johnson [Mon, 31 Mar 2008 01:33:04 +0000 (20:33 -0500)]
ppc4xx: Add CFG_MEM_TOP_HIDE to Denali SPD-based SDRAM setup

Signed-off-by: Larry Johnson <lrj@acm.org>
16 years agoppc4xx: Small whitespace fix of esd patches
Stefan Roese [Mon, 31 Mar 2008 10:20:48 +0000 (12:20 +0200)]
ppc4xx: Small whitespace fix of esd patches

Signed-off-by: Stefan Roese <sr@denx.de>
16 years agoppc4xx: Cleanup PMC440 board support
Matthias Fuchs [Sun, 30 Mar 2008 16:52:44 +0000 (18:52 +0200)]
ppc4xx: Cleanup PMC440 board support

Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
16 years agoppc4xx: Add ptm configuration variables for PMC440
Matthias Fuchs [Sun, 30 Mar 2008 16:52:06 +0000 (18:52 +0200)]
ppc4xx: Add ptm configuration variables for PMC440

Add support for the ptm1la, ptm1ms, ptm2la and ptm2ms
environment variables.

Cleanup pci_target_init.

Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
16 years agoppc4xx: Minor updates for DU440 boards
Matthias Fuchs [Sun, 30 Mar 2008 16:01:15 +0000 (18:01 +0200)]
ppc4xx: Minor updates for DU440 boards

Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
16 years agoMTD/CFI: flash_read64 is defined a weak function (for SPARC)
Daniel Hellstrom [Fri, 28 Mar 2008 19:40:19 +0000 (20:40 +0100)]
MTD/CFI: flash_read64 is defined a weak function (for SPARC)

SPARC has implemented __raw_readq, it reads 64-bit from any 32-bit address.
SPARC CPUs implement flash_read64 which calls __raw_readq.

For current SPARC architectures (LEON2 and LEON3) each read from the
FLASH must lead to a cache miss. This is because FLASH can not be set
non-cacheable since program code resides there, and alternatively disabling
cache is poor from performance view, or doing a cache flush between each
read is even poorer.

Forcing a cache miss on a SPARC is done by a special instruction "lda" -
load alternative space, the alternative space number (ASI) is processor
implementation spcific and can be found by including <asm/processor.h>.

Signed-off-by: Daniel Hellstrom <daniel@gaisler.com>
16 years agoMake MPC83xx one step closer to full relocation.
Joakim Tjernlund [Fri, 28 Mar 2008 14:41:25 +0000 (15:41 +0100)]
Make MPC83xx one step closer to full relocation.

Remove a few absolute references to CFG_MONITOR_BASE for ppc/mpc83xx
and use GOT relative reference.

Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
16 years agompc8323erdb: fix EEPROM page size and get MAC from EEPROM
Michael Barkowski [Thu, 27 Mar 2008 18:34:43 +0000 (14:34 -0400)]
mpc8323erdb: fix EEPROM page size and get MAC from EEPROM

This patch fixes eeprom page size so that you can now write more than
64 bytes at a time.

It also makes the board take MAC addresses, if found, from EEPROM.

User should place up to 4 addresses at offset 0x7f00, for
eth{,1,2,3}addr.  Any unused addresses should be zero.  This group of
four six-byte values should have it's CRC at the end.  crc32 and
eeprom commands can be used to accomplish this.

If CRC fails, MAC addresses come from the environment.  If CRC
succeeds, the environment is overwritten at startup.

Signed-off-by: Michael Barkowski <michael.barkowski@freescale.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
16 years agompc8323erdb: define CONFIG_PCI_SKIP_HOST_BRIDGE
Michael Barkowski [Fri, 28 Mar 2008 19:15:38 +0000 (15:15 -0400)]
mpc8323erdb: define CONFIG_PCI_SKIP_HOST_BRIDGE

Commit 55774b512fdf63c0516d441cc5da7c54bbffb7f2 broke the onboard USB
controller on the PCI bus in Linux on the MPC8323ERDB.

This fixes it by defining CONFIG_PCI_SKIP_HOST_BRIDGE in the board's
config file.

Signed-off-by: Michael Barkowski <michael.barkowski@freescale.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
16 years agompc83xx: cleanup System Part and Revision ID Register (SPRIDR) code
Kim Phillips [Fri, 28 Mar 2008 15:19:07 +0000 (10:19 -0500)]
mpc83xx: cleanup System Part and Revision ID Register (SPRIDR) code

in the spirit of commit 1ced121600b2060ab2ff9f0fddd9421fd70a0dc6,
85xx's "Update SVR numbers to expand support", simplify SPRIDR processing
and processor ID display.  Add REVID_{MAJ,MIN}OR macros to make
REVID dependent code simpler.  Also added PARTID_NO_E and IS_E_PROCESSOR
convenience macros.

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
16 years agompc83xx: display ddr frequency in board_add_ram_info banner
Kim Phillips [Fri, 28 Mar 2008 15:18:53 +0000 (10:18 -0500)]
mpc83xx: display ddr frequency in board_add_ram_info banner

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
16 years agompc83xx: unreinvent mem_clk
Kim Phillips [Fri, 28 Mar 2008 15:18:40 +0000 (10:18 -0500)]
mpc83xx: unreinvent mem_clk

delete ddr_clk and use mem_clk instead.  Rename other ddr_*_clk to
mem_*_clk for consistency's sake.

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
16 years agompc83xx: enable the SATA interface on mpc8315 rdb and mpc837x rdb boards
Kim Phillips [Fri, 28 Mar 2008 19:31:23 +0000 (14:31 -0500)]
mpc83xx: enable the SATA interface on mpc8315 rdb and mpc837x rdb boards

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
16 years agompc83xx: enable the SATA interface on mpc837xemds board
Dave Liu [Wed, 26 Mar 2008 14:57:19 +0000 (22:57 +0800)]
mpc83xx: enable the SATA interface on mpc837xemds board

Enable the first two SATA interfaces on MPC837xEMDS board,
The two SATA ports are on LYNX1. (SATA0/1 on J4/5)

Signed-off-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
16 years agompc83xx: initialize serdes for MPC837xEMDS boards
Dave Liu [Wed, 26 Mar 2008 14:56:36 +0000 (22:56 +0800)]
mpc83xx: initialize serdes for MPC837xEMDS boards

This patch is stolen from Anton Vorontsov's patch
for mpc837xerdb boards.

The reference clk and xcorevdd voltage of serdes1/2
is same between mpc837xemds and mpc837xerdb.

8377E: LYNX1- 2 SATA LYNX2- 2 PCIE
8378E: LYNX1- 2 SGMII LYNX2- 2 PCIE
8379E: LYNX1- 2 SATA LYNX2- 2 SATA

Signed-off-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
16 years agoppc4xx: Canyonlands: Print SATA/PCIe configuration and board revision
Stefan Roese [Fri, 28 Mar 2008 13:09:04 +0000 (14:09 +0100)]
ppc4xx: Canyonlands: Print SATA/PCIe configuration and board revision

Canyonlands (460EX) shares the first PCIe interface with the SoC SATA
interface. This usage can be configured with the jumper J6. This patch
displays the current configuration upon bootup and changes the PCIe
init loop, to only initialize the availabel PCIe slots.

Signed-off-by: Stefan Roese <sr@denx.de>
16 years agoMTD/CFI: Add support for 16bit legacy AMD flash
Tor Krill [Fri, 28 Mar 2008 10:29:10 +0000 (11:29 +0100)]
MTD/CFI: Add support for 16bit legacy AMD flash

Add entry for 512Kx16 AMD flash to jedec_table.
Read out 16bit device id if chipwidth is 16bit.
Fixed coding style after Stefans feedback

Signed-off-by: Tor Krill <tor@excito.com>
16 years agoppc: Small change to CFG_MEM_TOP_HIDE description
Stefan Roese [Fri, 28 Mar 2008 10:02:53 +0000 (11:02 +0100)]
ppc: Small change to CFG_MEM_TOP_HIDE description

Signed-off-by: Stefan Roese <sr@denx.de>
16 years agoFix host tool build breakage, take two
Bartlomiej Sieka [Thu, 27 Mar 2008 14:06:40 +0000 (15:06 +0100)]
Fix host tool build breakage, take two

Revert commit 87c8431f and fix build breakage so that the build continues
to work on FC systems.

Signed-off-by: Bartlomiej Sieka <tur@semihalf.com>
16 years agoppc4xx: Enable ECC on LWMON5
Stefan Roese [Wed, 19 Mar 2008 08:36:47 +0000 (09:36 +0100)]
ppc4xx: Enable ECC on LWMON5

Since all ECC related problems seem to be resolved on LWMON5, this patch
now enables ECC support.

We have to write the ECC bytes by zeroing and flushing in smaller
steps, since the whole 256MByte takes too long for the external
watchdog.

Signed-off-by: Stefan Roese <sr@denx.de>
16 years agoppc4xx: Updates to Korat-specific code
Larry Johnson [Mon, 17 Mar 2008 16:10:35 +0000 (11:10 -0500)]
ppc4xx: Updates to Korat-specific code

This patch contains updates for changes for the Korat PPC440EPx board.
These changes include:

(1) Support for "permanent" and "upgradable" copies of U-Boot, as
described in the new "doc/README.korat" file;

(2) a new memory map for the registers in the board's CPLD;

(3) a revised format for manufacturer's data in serial EEPROM; and

(4) changes to track updates to U-Boot for the Sequoia board.

Signed-off-by: Larry Johnson <lrj@acm.org>
16 years agoppc4xx: PPC405EP Set EMAC noise filter bits
Markus Brunner [Thu, 27 Mar 2008 09:46:25 +0000 (10:46 +0100)]
ppc4xx: PPC405EP Set EMAC noise filter bits

This bug was introduced with commit aee747f19b460a0e9da20ff21e90fdaac1cec359
which enabled CFG_4xx_GPIO_TABLE for PPC405 and unintentionally
disabled the setting of the emac noise filter bits for PPC405EP when CFG_4xx_GPIO_TABLE is set.

Signed-off-by: Markus Brunner <super.firetwister@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
16 years agoppc4xx: Reconfigure PLL for 667MHz processor for PPC440EPx
Mike Nuss [Wed, 20 Feb 2008 16:54:20 +0000 (11:54 -0500)]
ppc4xx: Reconfigure PLL for 667MHz processor for PPC440EPx

On PPC440EPx without a bootstrap I2C EEPROM, the PLL can be reconfigured
after startup to change the speed of the clocks. This patch adds the
option CFG_PLL_RECONFIG. If this option is set to 667, the CPU
initialization code will reconfigure the PLL to run the system with a CPU
frequency of 667MHz and PLB frequency of 166MHz, without the need for an
external EEPROM.

Signed-off-by: Mike Nuss <mike@terascala.com>
Acked-by: Stefan Roese <sr@denx.de>
16 years agonew-image: Fix host tool build breakage
Haavard Skinnemoen [Thu, 27 Mar 2008 08:12:40 +0000 (09:12 +0100)]
new-image: Fix host tool build breakage

Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
16 years agoppc: Set CFG_MEM_TOP_HIDE to 0 if not already defined
Stefan Roese [Thu, 27 Mar 2008 09:24:03 +0000 (10:24 +0100)]
ppc: Set CFG_MEM_TOP_HIDE to 0 if not already defined

Signed-off-by: Stefan Roese <sr@denx.de>
16 years agoppc4xx: Add fdt support to Prodrive alpr
Stefan Roese [Wed, 19 Mar 2008 09:23:43 +0000 (10:23 +0100)]
ppc4xx: Add fdt support to Prodrive alpr

Since this board will probably be ported to arch/powerpc in the
near future, we add device tree support now. This way we are
"ready" for arch/powerpc from now on.

Signed-off-by: Stefan Roese <sr@denx.de>
16 years agoppc4xx: Enable cache support on the ALPR board
Pieter Voorthuijsen [Mon, 17 Mar 2008 08:27:56 +0000 (09:27 +0100)]
ppc4xx: Enable cache support on the ALPR board

Signed-off-by: Pieter Voorthuijsen <pv@prodrive.nl>
16 years agoppc: Add CFG_MEM_TOP_HIDE option to hide memory area that doesn't get "touched"
Stefan Roese [Wed, 26 Mar 2008 09:14:11 +0000 (10:14 +0100)]
ppc: Add CFG_MEM_TOP_HIDE option to hide memory area that doesn't get "touched"

If CFG_MEM_TOP_HIDE is defined in the board config header, this specified
memory area will get subtracted from the top (end) of ram and won't get
"touched" at all by U-Boot. By fixing up gd->ram_size the Linux kernel
should gets passed the now "corrected" memory size and won't touch it
either. This should work for arch/ppc and arch/powerpc. Only Linux board
ports in arch/powerpc with bootwrapper support, which recalculate the
memory size from the SDRAM controller setup, will have to get fixed
in Linux additionally.

This patch enables this config option on some PPC440EPx boards as a workaround
for the CHIP 11 errata. Here the description from the AMCC documentation:

CHIP_11: End of memory range area restricted access.
Category: 3

Overview:
The 440EPx DDR controller does not acknowledge any
transaction which is determined to be crossing over the
end-of-memory-range boundary, even if the starting address is
within valid memory space. Any such transaction from any PLB4
master will result in a PLB time-out on PLB4 bus.

Impact:
In case of such misaligned bursts, PLB4 masters will not
retrieve any data at all, just the available data up to the
end of memory, especially the 440 CPU. For example, if a CPU
instruction required an operand located in memory within the
last 7 words of memory, the DCU master would burst read 8
words to update the data cache and cross over the
end-of-memory-range boundary. Such a DCU read would not be
answered by the DDR controller, resulting in a PLB4 time-out
and ultimately in a Machine Check interrupt. The data would
be inaccessible to the CPU.

Workaround:
Forbid any application to access the last 256 bytes of DDR
memory. For example, make your operating system believe that
the last 256 bytes of DDR memory are absent. AMCC has a patch
that does this, available for Linux.

This patch sets CFG_MEM_TOP_HIDE for the following 440EPx boards:
lwmon5, korat, sequoia

The other remaining 440EPx board were intentionally not included
since it is not clear to me, if they use the end of ram for some
other purpose. This is unclear, since these boards have CONFIG_PRAM
defined and even comments like this:

PMC440.h:
/* esd expects pram at end of physical memory.
 * So no logbuffer at the moment.
 */

It is strongly recommended to not use the last 256 bytes on those
boards too. Patches from the board maintainers are welcome.

Signed-off-by: Stefan Roese <sr@denx.de>
16 years agoppc4xx: Fix Canyonlands linker script (remove bogus ASSERT)
Stefan Roese [Thu, 27 Mar 2008 09:09:05 +0000 (10:09 +0100)]
ppc4xx: Fix Canyonlands linker script (remove bogus ASSERT)

Signed-off-by: Stefan Roese <sr@denx.de>
16 years agoppc4xx: Correctly pass phyiscal FLASH base address into dtb
Stefan Roese [Tue, 25 Mar 2008 16:51:13 +0000 (17:51 +0100)]
ppc4xx: Correctly pass phyiscal FLASH base address into dtb

The routine ft_board_setup() configures the EBC NOR mappings for the
Linux physmap_of driver. Since on 460EX/GT we remap the FLASH from
0x4.fc00.0000 to 0x4.cc00.0000 because of the max. 16MByte boot-CS
problem, we need to pass the corrected address here too.

Signed-off-by: Stefan Roese <sr@denx.de>
16 years agoppc4xx: Fix compilation warning in 4xx_enet.c
Stefan Roese [Wed, 19 Mar 2008 15:35:12 +0000 (16:35 +0100)]
ppc4xx: Fix compilation warning in 4xx_enet.c

Signed-off-by: Stefan Roese <sr@denx.de>
16 years agoppc4xx: Add AMCC Glacier 406GT eval board support
Stefan Roese [Wed, 19 Mar 2008 15:20:49 +0000 (16:20 +0100)]
ppc4xx: Add AMCC Glacier 406GT eval board support

This patch adds support for the AMCC Glacier 460GT eval board.
The main difference to the Canyonlands board are listed here:

- 4 ethernet ports instead of 2
- no SATA port
- no USB port

Currently EMAC2+3 are not working. This will be fixed in a later
release.

Signed-off-by: Stefan Roese <sr@denx.de>
16 years agoppc4xx: Mask 'vec' with 0x1f in uic_interrupt() for bit set/clear
Stefan Roese [Thu, 27 Mar 2008 07:47:26 +0000 (08:47 +0100)]
ppc4xx: Mask 'vec' with 0x1f in uic_interrupt() for bit set/clear

Signed-off-by: Stefan Roese <sr@denx.de>
16 years agoMerge branch 'master' of git+ssh://10.10.0.7/home/wd/git/u-boot/master
Wolfgang Denk [Wed, 26 Mar 2008 23:19:13 +0000 (00:19 +0100)]
Merge branch 'master' of git+ssh://10.10.0.7/home/wd/git/u-boot/master

16 years agoFix out of tree building issue
Anatolij Gustschin [Wed, 26 Mar 2008 20:05:43 +0000 (21:05 +0100)]
Fix out of tree building issue

Currently U-Boot building in some external directory
doesn't work. This patch tries to fix the problem.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
16 years agoMerge branch 'master' of git://www.denx.de/git/u-boot-mpc85xx
Wolfgang Denk [Wed, 26 Mar 2008 23:16:34 +0000 (00:16 +0100)]
Merge branch 'master' of git://denx.de/git/u-boot-mpc85xx

16 years agoMerge branch 'master' of git://www.denx.de/git/u-boot-usb
Wolfgang Denk [Wed, 26 Mar 2008 23:16:18 +0000 (00:16 +0100)]
Merge branch 'master' of git://denx.de/git/u-boot-usb

16 years agoREADME: update documentation (availability, links, etc.)
Anatolij Gustschin [Wed, 26 Mar 2008 17:13:33 +0000 (18:13 +0100)]
README: update documentation (availability, links, etc.)

Fix typo in README

Signed-off-by: Anatolij Gustschin <agust@denx.de>
16 years agoFix compilation error in cmd_usb.c
Anatolij Gustschin [Wed, 26 Mar 2008 16:47:44 +0000 (17:47 +0100)]
Fix compilation error in cmd_usb.c

This patch fixes compilation error
cmd_usb.c: In function 'do_usb':
cmd_usb.c:552: error: void value not ignored as it ought to be

Signed-off-by: Anatolij Gustschin <agust@denx.de>
16 years agoAdd support for setting the I2C bus speed in fsl_i2c.c
Timur Tabi [Fri, 14 Mar 2008 22:45:29 +0000 (17:45 -0500)]
Add support for setting the I2C bus speed in fsl_i2c.c

Add support to the Freescale I2C driver (fsl_i2c.c) for setting and querying
the I2C bus speed.  Current 8[356]xx boards define the CFG_I2C_SPEED macro,
but fsl_i2c.c ignores it and uses conservative value when programming the
I2C bus speed.

Signed-off-by: Timur Tabi <timur@freescale.com>
Acked-by: Andy Fleming <afleming@freescale.com>
16 years agoCoding style cleanup, update CHANGELOG
Wolfgang Denk [Wed, 26 Mar 2008 23:03:57 +0000 (00:03 +0100)]
Coding style cleanup, update CHANGELOG

Signed-off-by: Wolfgang Denk <wd@denx.de>
16 years agodrivers: add the support for Freescale SATA controller
Dave Liu [Wed, 26 Mar 2008 14:55:32 +0000 (22:55 +0800)]
drivers: add the support for Freescale SATA controller

Add the Freescale on-chip SATA controller driver to u-boot,
The SATA controller is used on the 837x and 8315 targets,
The driver can be used to load kernel, fs and dtb.

The features list:
- 1.5/3 Gbps link speed
- LBA48, LBA28 support
- DMA and FPDMA support
- Two ports support

Signed-off-by: Dave Liu <daveliu@freescale.com>
16 years agoata: add the readme for SATA command line
Dave Liu [Wed, 26 Mar 2008 14:54:44 +0000 (22:54 +0800)]
ata: add the readme for SATA command line

Signed-off-by: Dave Liu <daveliu@freescale.com>
16 years agoata: enable the sata initialize on boot up
Dave Liu [Wed, 26 Mar 2008 14:53:24 +0000 (22:53 +0800)]
ata: enable the sata initialize on boot up

Signed-off-by: Dave Liu <daveliu@freescale.com>
16 years agoata: add the fis struct for SATA
Dave Liu [Wed, 26 Mar 2008 14:52:36 +0000 (22:52 +0800)]
ata: add the fis struct for SATA

Signed-off-by: Dave Liu <daveliu@freescale.com>
16 years agoata: add the libata support
Dave Liu [Wed, 26 Mar 2008 14:51:44 +0000 (22:51 +0800)]
ata: add the libata support

add simple libata support in u-boot

Signed-off-by: Dave Liu <daveliu@freescale.com>
16 years agoata: make the ata_piix driver using new SATA framework
Dave Liu [Wed, 26 Mar 2008 14:50:45 +0000 (22:50 +0800)]
ata: make the ata_piix driver using new SATA framework

original ata_piix driver is using IDE framework, not real
SATA framework. For now, the ata_piix driver is only used
by x86 sc520_cdp board. This patch makes the ata_piix driver
use the new SATA framework, so

- remove the duplicated command stuff
- remove the CONFIG_CMD_IDE define in the sc520_cdp.h
- add the CONFIG_CMD_SATA define to sc520_cdp.h

Signed-off-by: Dave Liu <daveliu@freescale.com>
16 years agoata: add the support for SATA framework
Dave Liu [Wed, 26 Mar 2008 14:49:44 +0000 (22:49 +0800)]
ata: add the support for SATA framework

- add the SATA framework
- add the SATA command line

Signed-off-by: Dave Liu <daveliu@freescale.com>
16 years agoata: merge the header of ata_piix driver
Dave Liu [Wed, 26 Mar 2008 14:48:18 +0000 (22:48 +0800)]
ata: merge the header of ata_piix driver

move the sata.h from include/ to drivers/block/ata_piix.h

Signed-off-by: Dave Liu <daveliu@freescale.com>
16 years agoata: merge the ata_piix driver
Dave Liu [Wed, 26 Mar 2008 14:47:06 +0000 (22:47 +0800)]
ata: merge the ata_piix driver

move the cmd_sata.c from common/ to drivers/ata_piix.c,
the cmd_sata.c have some part of ata_piix controller drivers.
consolidate the driver to have better framework.

Signed-off-by: Dave Liu <daveliu@freescale.com>
16 years agoUSB, Storage: fix a bug introduced in commit
Markus Klotzbuecher [Wed, 26 Mar 2008 17:26:43 +0000 (18:26 +0100)]
USB, Storage: fix a bug introduced in commit
f6b44e0e4d18fe507833a0f76d24a9aa72c123f1 that will cause usb_stor_info
to only print only information on one storage device, but not for
multiple.

Signed-off-by: Markus Klotzbuecher <mk@denx.de>
16 years agoFix compilation error in cmd_usb.c
Anatolij Gustschin [Wed, 26 Mar 2008 16:47:44 +0000 (17:47 +0100)]
Fix compilation error in cmd_usb.c

This patch fixes compilation error
cmd_usb.c: In function 'do_usb':
cmd_usb.c:552: error: void value not ignored as it ought to be

Signed-off-by: Anatolij Gustschin <agust@denx.de>
Signed-off-by: Markus Klotzbuecher <mk@denx.de>
16 years ago85xx: Add cpu_mp_lmb_reserve helper to reserve boot page
Kumar Gala [Wed, 26 Mar 2008 13:53:53 +0000 (08:53 -0500)]
85xx: Add cpu_mp_lmb_reserve helper to reserve boot page

Provide a board_lmb_reserve helper function to ensure we reserve
the page of memory we are using for the boot page translation code.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
16 years ago85xx: Update multicore boot mechanism to ePAPR v0.81 spec
Kumar Gala [Wed, 26 Mar 2008 13:34:25 +0000 (08:34 -0500)]
85xx: Update multicore boot mechanism to ePAPR v0.81 spec

The following changes are needed to be inline with ePAPR v0.81:

* r4, r5 and now always set to 0 on boot release
* r7 is used to pass the size of the initial map area (IMA)
* EPAPR_MAGIC value changed for book-e processors
* changes in the spin table layout
* spin table supports a 64-bit physical release address

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
16 years agoFSL: Clean up board/freescale/common/Makefile
Jon Loeliger [Wed, 19 Mar 2008 20:02:07 +0000 (15:02 -0500)]
FSL: Clean up board/freescale/common/Makefile

Each file that can be built here now follows some
CONFIG_ option so that they are appropriately built
or not, as needed.  And CONFIG_ defines were added
to various board config files to make sure that happens.

The other board/freescale/*/Makefiles no longer need
to reach up and over into ../common to build their
individually needed files any more.

Boards that are CDS specific were renamed with cds_ prefix.

Signed-off-by: Jon Loeliger <jdl@freescale.com>
16 years ago85xx: Fix merge duplication
Kumar Gala [Thu, 28 Feb 2008 04:00:27 +0000 (22:00 -0600)]
85xx: Fix merge duplication

ft_fixup_cpu() got duplicated in some merge snafu.  Remove the duplicate.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
16 years ago85xx: Expand CCSR space with more DDR controller registers.
James Yang [Tue, 12 Feb 2008 22:35:07 +0000 (16:35 -0600)]
85xx: Expand CCSR space with more DDR controller registers.

Signed-off-by: James Yang <James.Yang@freescale.com>
Signed-off-by: Jon Loeliger <jdl@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
16 years ago85xx: Speed up get_ddr_freq() and get_bus_freq()
James Yang [Sat, 9 Feb 2008 00:05:08 +0000 (18:05 -0600)]
85xx: Speed up get_ddr_freq() and get_bus_freq()

get_ddr_freq() and get_bus_freq() used get_sys_info() each time they were
called.  However, get_sys_info() recalculates extraneous information when
called each time.  Have get_ddr_freq() and get_bus_freq() return memoized
values from global_data instead.

Signed-off-by: James Yang <James.Yang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
16 years ago85xx: Show DDR memory data rate in addition to the memory clock frequency.
James Yang [Fri, 8 Feb 2008 22:46:27 +0000 (16:46 -0600)]
85xx: Show DDR memory data rate in addition to the memory clock frequency.

Show the DDR memory data rate in addition to the memory clock
frequency.  For DDR/DDR2 memories the memory data rate is 2x the
memory clock.

Signed-off-by: James Yang <James.Yang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
16 years ago85xx: get_tbclk() speed up and rounding fix
James Yang [Fri, 8 Feb 2008 22:44:53 +0000 (16:44 -0600)]
85xx: get_tbclk() speed up and rounding fix

Speed up get_tbclk() by referencing pre-computed bus clock
frequency value from global data instead of sys_info_t.  Fix
rounding of result to nearest; previously it was rounding
upwards.

Signed-off-by: James Yang <James.Yang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
16 years agoUpdate SVR numbers to expand support
Andy Fleming [Wed, 6 Feb 2008 07:19:40 +0000 (01:19 -0600)]
Update SVR numbers to expand support

FSL has taken to using SVR[16:23] as an SOC sub-version field.  This
is used to distinguish certain variants within an SOC family.  To
account for this, we add the SVR_SOC_VER() macro, and update the SVR_*
constants to reflect the larger value.  We also add SVR numbers for all
of the current variants.  Finally, to make things neater, rather than
use an enormous switch statement to print out the CPU type, we create
and array of SVR/name pairs (using a macro), and print out the CPU name
that matches the SVR SOC version.

Signed-off-by: Andy Fleming <afleming@freescale.com>
16 years agoAdd the Freescale PCI device IDs
Andy Fleming [Wed, 6 Feb 2008 07:12:57 +0000 (01:12 -0600)]
Add the Freescale PCI device IDs

Signed-off-by: Andy Fleming <afleming@freescale.com>
16 years ago85xx: Added support for multicore boot mechanism
Kumar Gala [Thu, 14 Feb 2008 17:04:23 +0000 (11:04 -0600)]
85xx: Added support for multicore boot mechanism

Added the cpu command that provides a generic mechanism to get status,
reset, and release secondary cores in multicore processors.

Added support for using the ePAPR defined spin-table mechanism on 85xx.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Andy Fleming <afleming@freescale.com>
16 years ago85xx: Added support for multicore boot mechanism
Kumar Gala [Thu, 17 Jan 2008 22:48:33 +0000 (16:48 -0600)]
85xx: Added support for multicore boot mechanism

Added the cpu command that provides a generic mechanism to get status,
reset, and release secondary cores in multicore processors.

Added support for using the ePAPR defined spin-table mechanism on 85xx.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
16 years ago85xx: Add the concept of CFG_CCSRBAR_PHYS
Kumar Gala [Wed, 30 Jan 2008 20:55:14 +0000 (14:55 -0600)]
85xx: Add the concept of CFG_CCSRBAR_PHYS

When we go to 36-bit physical addresses we need to keep the concept of
the physical CCSRBAR address seperate from the virtual one.

For the majority of boards CFG_CCSBAR_PHYS == CFG_CCSRBAR

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
16 years agoCoding style cleanup.
Wolfgang Denk [Wed, 26 Mar 2008 14:38:47 +0000 (15:38 +0100)]
Coding style cleanup.

Signed-off-by: Wolfgang Denk <wd@denx.de>
16 years agoAdd CFG_RTC_DS1337_NOOSC to turn off OSC output
Joakim Tjernlund [Wed, 26 Mar 2008 12:02:13 +0000 (13:02 +0100)]
Add CFG_RTC_DS1337_NOOSC to turn off OSC output

The default settings for RTC DS1337 keeps the OSC
output, 32,768 Hz, on. This add CFG_RTC_DS1337_NOOSC to
turn it off.

Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
16 years agoCleanup coding style, update CHANGELOG
Wolfgang Denk [Wed, 26 Mar 2008 10:48:46 +0000 (11:48 +0100)]
Cleanup coding style, update CHANGELOG

Signed-off-by: Wolfgang Denk <wd@denx.de>
16 years agoMerge branch 'master_merge_new-image' of /home/tur/git/u-boot
Wolfgang Denk [Wed, 26 Mar 2008 09:41:48 +0000 (10:41 +0100)]
Merge branch 'master_merge_new-image' of /home/tur/git/u-boot

16 years agoREADME: update documentation (availability, links, etc.)
Wolfgang Denk [Wed, 26 Mar 2008 09:40:12 +0000 (10:40 +0100)]
README: update documentation (availability, links, etc.)

Signed-off-by: Wolfgang Denk <wd@denx.de>
16 years agoMerge branch 'new-image' of git://www.denx.de/git/u-boot-testing
Bartlomiej Sieka [Wed, 26 Mar 2008 08:38:06 +0000 (09:38 +0100)]
Merge branch 'new-image' of git://denx.de/git/u-boot-testing

Conflicts:

common/cmd_bootm.c
cpu/mpc8xx/cpu.c

Signed-off-by: Bartlomiej Sieka <tur@semihalf.com>
16 years agoUSB Storage, add meaningful return value
Aras Vaichas [Tue, 25 Mar 2008 01:09:07 +0000 (12:09 +1100)]
USB Storage, add meaningful return value

This patch changes the "usb storage" command to return success if it
finds a USB storage device, otherwise it returns error.

Signed-off-by: Markus Klotzbuecher <mk@denx.de>
16 years ago83xx/fdt_support: let user specifiy FSL USB Dual-Role controller role
Anton Vorontsov [Fri, 14 Mar 2008 20:20:18 +0000 (23:20 +0300)]
83xx/fdt_support: let user specifiy FSL USB Dual-Role controller role

Linux understands "host" (default), "peripheral" and "otg" (broken).
Though, U-Boot doesn't restrict dr_mode variable to these values (think
of renames in future).

Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
16 years agotsec: fix link detection for the RTL8211B PHY
Anton Vorontsov [Fri, 14 Mar 2008 20:20:30 +0000 (23:20 +0300)]
tsec: fix link detection for the RTL8211B PHY

RTL8211B sets link state register after autonegotiation complete,
so with bootdelay=0 RTL8211B will report lack of the link.

To fix this, we should wait for aneg to complete, even if the
link is currently down.

Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
16 years agompc83xx: add "fsl,soc" and "fsl,immr" compatible fixups
Anton Vorontsov [Mon, 24 Mar 2008 17:47:09 +0000 (20:47 +0300)]
mpc83xx: add "fsl,soc" and "fsl,immr" compatible fixups

device_type = "soc" is being deprecated, newer device trees will use
"fsl,soc" and/or "fsl,immr" for the soc nodes.

This patch also adds clock-frequency property for soc nodes (the same
value as bus-frequency).

Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
16 years agoModified the DDR SDRAM clock control register to delay MCK/MCK_B 3/4 clock
Joe D'Abbraccio [Mon, 24 Mar 2008 17:00:59 +0000 (13:00 -0400)]
Modified the DDR SDRAM clock control register to delay MCK/MCK_B 3/4 clock

With the original value of 1/2 clock cycle delay, the system ran relatively
stable except when we run benchmarks that are intensive users of memory.
When I run samba connected disk with a HDBENCH test, the system locks-up
or reboots sporadically.

Signed-off by: Joe D'Abbraccio <Joe.D'abbraccio@freescale.com>

16 years agompc83xx: Set PCI I/O bus-address base to zero.
Scott Wood [Mon, 24 Mar 2008 17:44:13 +0000 (12:44 -0500)]
mpc83xx: Set PCI I/O bus-address base to zero.

The device trees for these boards describe PCI I/O as starting from
address zero from the device's perspective.

Placing I/O elsewhere may cause problems with certain PCI boards, and may
cause problems with Linux.

Signed-off-by: Scott Wood <scottwood@freescale.com>
16 years agompc83xx: MPC8360E-RDK: use 33.3(3)MHz CLKIN/SYS_CLK
Anton Vorontsov [Mon, 24 Mar 2008 17:47:05 +0000 (20:47 +0300)]
mpc83xx: MPC8360E-RDK: use 33.3(3)MHz CLKIN/SYS_CLK

At least on the "33MHz Pilot" board crystal is actually 33.3MHz.
This patch fixes "system time drifting" problem.

Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
16 years agompc83xx: MPC8360E-RDK: define CONFIG_OF_STDOUT_VIA_ALIAS
Anton Vorontsov [Mon, 24 Mar 2008 17:47:02 +0000 (20:47 +0300)]
mpc83xx: MPC8360E-RDK: define CONFIG_OF_STDOUT_VIA_ALIAS

This is needed to update /choosen/linux,stdout-path properly.

Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
16 years agompc83xx: MPC8360E-RDK: add dhcp command
Anton Vorontsov [Mon, 24 Mar 2008 17:47:00 +0000 (20:47 +0300)]
mpc83xx: MPC8360E-RDK: add dhcp command

Plus modify environment to use it and remove bootfile env variable,
it is internal and CONFIG_BOOTFILE is used for these purposes.

Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
16 years agompc83xx: MPC8360E-RDK: rework ddr setup, enable ecc
Anton Vorontsov [Mon, 24 Mar 2008 17:46:57 +0000 (20:46 +0300)]
mpc83xx: MPC8360E-RDK: rework ddr setup, enable ecc

Current DDR setup easily causes memory corruption, this patch fixes it.

Also fix TIMING_CFG0_MRS_CYC definition.

Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
16 years agompc83xx: MPC8360E-RDK: configure pario pins for AD7843 and FHCI
Anton Vorontsov [Mon, 24 Mar 2008 17:46:53 +0000 (20:46 +0300)]
mpc83xx: MPC8360E-RDK: configure pario pins for AD7843 and FHCI

This patch adds qe pario pins configuration for AD7843 ADC/Touchscreen
controller and FHCI (QE USB).

Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
16 years agompc83xx: MPC8360E-RDK: add support for NAND
Anton Vorontsov [Mon, 24 Mar 2008 17:46:51 +0000 (20:46 +0300)]
mpc83xx: MPC8360E-RDK: add support for NAND

Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
16 years agompc83xx: MPC8360E-RDK: use RGMII_RXID interface mode
Anton Vorontsov [Mon, 24 Mar 2008 17:46:46 +0000 (20:46 +0300)]
mpc83xx: MPC8360E-RDK: use RGMII_RXID interface mode

This is needed for BCM PHYs to work on this board.

Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
16 years agouec: add support for Broadcom BCM5481 Gigabit PHY
Anton Vorontsov [Mon, 24 Mar 2008 17:46:34 +0000 (20:46 +0300)]
uec: add support for Broadcom BCM5481 Gigabit PHY

This patch adds basic support for Broadcom BCM5481 PHY.

RXD-RXC delay quirk comes from MPC8360E-RDK BSP source, author is
Peter Barada <peterb@logicpd.com>.

Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
16 years agouec: add support for RGMII_RXID interface mode
Anton Vorontsov [Mon, 24 Mar 2008 17:46:28 +0000 (20:46 +0300)]
uec: add support for RGMII_RXID interface mode

PHY drivers will use it to setup software delay between RXD and RXC
signals.

Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
16 years agouec: add support for gbit mii status readings
Anton Vorontsov [Mon, 24 Mar 2008 17:46:24 +0000 (20:46 +0300)]
uec: add support for gbit mii status readings

Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
16 years ago83xx: define CONFIG_OF_STDOUT_VIA_ALIAS for the MPC837XERDB boards
Anton Vorontsov [Mon, 24 Mar 2008 14:40:47 +0000 (17:40 +0300)]
83xx: define CONFIG_OF_STDOUT_VIA_ALIAS for the MPC837XERDB boards

This is primarily for the early console support.

Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
16 years ago83xx: initialize serdes for MPC837XRDB boards
Anton Vorontsov [Mon, 24 Mar 2008 14:40:43 +0000 (17:40 +0300)]
83xx: initialize serdes for MPC837XRDB boards

On the MPC8377ERDB: 2 SATA and 2 PCI-E.
On the MPC8378ERDB: 2 PCI-E
On the MPC8379ERDB: 4 SATA

Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
16 years ago83xx: serdes setup routines
Anton Vorontsov [Mon, 24 Mar 2008 14:40:32 +0000 (17:40 +0300)]
83xx: serdes setup routines

This patch adds few routines to configure serdes on 837x targets.

Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
16 years ago83xx: split COBJS onto separate lines
Anton Vorontsov [Mon, 24 Mar 2008 14:40:27 +0000 (17:40 +0300)]
83xx: split COBJS onto separate lines

..plus get rid of some #ifdefs in the .c files.

Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
16 years ago83xx: nand support for MPC837XRDB boards
Anton Vorontsov [Mon, 24 Mar 2008 14:40:23 +0000 (17:40 +0300)]
83xx: nand support for MPC837XRDB boards

Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
16 years agoEnable CONFIG_FLASH_SHOW_PROGRESS on the MPC8360EMDS.
Jerry Van Baren [Wed, 19 Mar 2008 01:44:41 +0000 (21:44 -0400)]
Enable CONFIG_FLASH_SHOW_PROGRESS on the MPC8360EMDS.

Signed-off-by: Gerald Van Baren <vanbaren@cideas.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
16 years agompc8323erdb: remove RTC and add EEPROM
Michael Barkowski [Thu, 20 Mar 2008 17:15:39 +0000 (13:15 -0400)]
mpc8323erdb: remove RTC and add EEPROM

There's no on-board RTC on the MPC8323ERDB, but there is an EEPROM.

Signed-off-by: Michael Barkowski <michael.barkowski@freescale.com>
Acked-by: Kim Phillips <kim.phillips@freescale.com>
16 years agompc8323erdb: Improve the system performance
Michael Barkowski [Thu, 20 Mar 2008 17:15:34 +0000 (13:15 -0400)]
mpc8323erdb: Improve the system performance

The following changes are based on kernel UCC ethernet performance:

1.  Make the CSB bus pipeline depth as 4, and enable the repeat mode
2.  Optimize transactions between QE and CSB.  Added CFG_SPCR_OPT
    switch to enable this setting.

The following changes are based on the App Note AN3369 and
verified to improve memory latency using LMbench:

3.  CS0_CONFIG[AP_n_EN] is changed from 1 to 0
4.  CS0_CONFIG[ODT_WR_CONFIG] set to 1.  Was a reserved setting
    previously.
5.  TIMING_CFG_1[WRREC] is changed from 3clks to 2clks  (based on
    Twr=15ns, and this was already the setting in DDR_MODE)
6.  TIMING_CFG_1[PRETOACT] is changed from 3clks to 2clks. (based on
    Trp=15ns)
7.  TIMING_CFG_1[ACTTOPRE] is changed from 9clks to 6clks. (based on
    Tras=40ns)
8.  TIMING_CFG_1[ACTTORW] is changed from 3clks to 2clks. (based on
    Trcd=15ns)
9.  TIMING_CFG_1[REFREC] changed from 21 clks to 11clks.  (based on
    Trfc=75ns)
10. TIMING_CFG_2[FOUR_ACT] is changed from 10 clks to 7clks.  (based
    on Tfaw=50ns)
11. TIMING_CFG_2[ADD_LAT] and DDR_MODE[AL] changed from 0 to 1 (based
    on CL=3 and WL=2).

Signed-off-by: Michael Barkowski <michael.barkowski@freescale.com>
Acked-by: Kim Phillips <kim.phillips@freescale.com>