Naoki Hayama [Thu, 8 Oct 2020 04:16:38 +0000 (13:16 +0900)]
README: Update directory hierarchy
Removed:
- /arch/openrisc
Added:
- /arch/xtensa
- /env
Signed-off-by: Naoki Hayama <naoki.hayama@lineo.co.jp>
Naoki Hayama [Thu, 8 Oct 2020 04:16:25 +0000 (13:16 +0900)]
README: Update source code location
This patch include these updates
- Git repository has moved to GitLab
- HTTPS access to the file server is allowed
- pre-built images are no longer available
Signed-off-by: Naoki Hayama <naoki.hayama@lineo.co.jp>
Naoki Hayama [Thu, 8 Oct 2020 04:16:18 +0000 (13:16 +0900)]
README: Update links to mailing list archives
This patch includes these updates
- Change http://lists.denx.de/pipermail/u-boot
to https://lists.denx.de/pipermail/u-boot
- http://dir.gmane.org/gmane.comp.boot-loaders.u-boot
is broken, so remove it
- Another archive https://marc.info/?l=u-boot
is available, so add it
Additional information:
dir.gmane.org has moved to news.gmane.io, but it only allows
access to the archive via NNTP.
- Server: news.gmane.io
- Group : gmane.comp.boot-loaders.u-boot
I don't include this information in this patch because
it's not very useful without web interfaces.
Signed-off-by: Naoki Hayama <naoki.hayama@lineo.co.jp>
Sean Anderson [Wed, 7 Oct 2020 18:37:44 +0000 (14:37 -0400)]
timer: Return count from timer_ops.get_count
No timer drivers return an error from get_count. Instead of possibly
returning an error, just return the count directly.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Sean Anderson [Wed, 7 Oct 2020 18:37:43 +0000 (14:37 -0400)]
doc: Document timer API
This adds kerneldocs for <timer.h>.
I don't know who should maintain doc/api/timer.rst, since the timer
subsystem seems to be maintained by SoC maintainers. MAINTAINERS is left
un-updated for the moment.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Heinrich Schuchardt [Wed, 7 Oct 2020 16:11:48 +0000 (18:11 +0200)]
common: rename getc() to getchar()
The sandbox is built with the SDL2 library with invokes the X11 library
which in turn calls getc(). But getc() in glibc is defined as
int getc(FILE *)
This does not match our definition.
int getc(void)
The sandbox crashes when called with parameter -l.
Rename our library symbol getc() to getchar().
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Rasmus Villemoes [Wed, 7 Oct 2020 07:36:03 +0000 (09:36 +0200)]
cli_hush.c: remove broken sanity check
This code is intended do prevent one from setting a shell variable abc
by doing
abc=123
if an environment variable named abc already exists. However, the
check is broken, since the env_get is done before the split on =, so
we look up whether an environment variable "abc=123" exists, which is
obviously never the case.
One could move the code to below the split on =, but instead, just
remove it, saving a little .text: The check has never worked as
intended (it goes all the way back to the initial git commit), and it
would anyway not guard against one first setting the shell variable,
then doing 'env set abc xyz'.
Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Heiko Schocher [Wed, 7 Oct 2020 06:06:54 +0000 (08:06 +0200)]
common, autoboot: sync functionality with Kconfig description
add back again special case: -2
autoboot with no delay and no check for abort
as described in Kconfig option, see common/Kconfig
help text for option BOOTDELAY.
Signed-off-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Naoki Hayama [Wed, 7 Oct 2020 02:22:24 +0000 (11:22 +0900)]
cosmetic: image: Fix comments and the order of definitions
Fix some comments about functions.
Move genimg_get_comp_name() above genimg_get_short_name() because
genimg_get_comp_name() is related to get_table_entry_name().
Signed-off-by: Naoki Hayama <naoki.hayama@lineo.co.jp>
Reviewed-by: Simon Glass <sjg@chromium.org>
Naoki Hayama [Wed, 7 Oct 2020 02:21:55 +0000 (11:21 +0900)]
mkimage: Skip adding non-existent IDs to a list
In show_valid_options(), this patch introduces checking whether
a category has an entry ID. If not, adding it to a list for output
is skipped before calling qsort().
This patch will affect all kinds of image header categories
(-A, -C, -O and -T flags).
Signed-off-by: Naoki Hayama <naoki.hayama@lineo.co.jp>
Reviewed-by: Simon Glass <sjg@chromium.org>
Naoki Hayama [Wed, 7 Oct 2020 02:21:25 +0000 (11:21 +0900)]
image: Add a function to modify category information
Add a generic function which can check whether a category has an
entry ID.
Signed-off-by: Naoki Hayama <naoki.hayama@lineo.co.jp>
Reviewed-by: Simon Glass <sjg@chromium.org>
Ovidiu Panait [Fri, 25 Sep 2020 18:12:56 +0000 (21:12 +0300)]
Kconfig: Use hex values for CONFIG_{SPL,TPL}_SIZE_LIMIT
CONFIG_{SPL,TPL}_SIZE_LIMIT are defined as hex (SPL_SIZE_LIMIT was
converted in
b51882d0 ("spl: Convert CONFIG_SPL_SIZE_LIMIT to hex"), but
there are still places that reference integer values. Change those to hex
as well. Also, update the Makefile to check for 0x0 instead of 0.
This also fixes the following build error when CONFIG_SPL_SIZE_LIMIT
is set by menuconfig to 0x0:
...
spl/u-boot-spl.bin exceeds file size limit:
limit: 0 bytes
actual: 0x80f0 bytes
excess: 0x80f0 bytes
Signed-off-by: Ovidiu Panait <ovidiu.panait@windriver.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Simon Glass [Mon, 28 Sep 2020 00:46:24 +0000 (18:46 -0600)]
tpm: cr50: Correct logging statements
Fix up some logging statements in this file. Most of them should use
log_debug(), apart from one error.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Mon, 28 Sep 2020 00:46:23 +0000 (18:46 -0600)]
i2c: designware: Use log_debug() for debugging
We don't want the debug output to be visible in a normal boot. Silence it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher<hs@denx.de>
Simon Glass [Mon, 28 Sep 2020 00:46:22 +0000 (18:46 -0600)]
board: Show memory for frame buffers
When debugging is enabled, show the memory allocated to video frame
buffers.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Mon, 28 Sep 2020 00:46:18 +0000 (18:46 -0600)]
bloblist: Place on a 4KB boundary
It is much easier to read the bloblist addresses if it starts on a 4KB
boundary. Update it to align it accordingly.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Mon, 28 Sep 2020 00:46:17 +0000 (18:46 -0600)]
syscon: Drop the logging in syscon_get_by_driver_data()
This function can be called when it is not known whether it will find
anything. This results in confusing log messages if the device is not
found. It is better for the caller to log the failure, if necessary.
Drop the logging from this function.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Mon, 28 Sep 2020 00:46:13 +0000 (18:46 -0600)]
log: Add missing category names
Add some category names that were missed in recent changes. Update the
comment as a reminder.
Signed-off-by: Simon Glass <sjg@chromium.org>
Tom Rini [Thu, 22 Oct 2020 12:25:41 +0000 (08:25 -0400)]
Merge tag 'u-boot-stm32-
20201021' of https://gitlab.denx.de/u-boot/custodians/u-boot-stm
- Activate CMD_EXPORTENV/CMD_IMPORTENV/CMD_ELF for STM32MP15 defconfig
- Fix stm32prog command: parsing of FlashLayout without partition
- Update MAINTAINERS for ARM STM STM32MP
- Manage eth1addr on dh board with KS8851
- Limit size of cacheable DDR in pre-reloc stage in stm32mp1
- Use mmc_of_parse() to read host capabilities in mmc:sdmmc2 driver
Tom Rini [Thu, 22 Oct 2020 12:25:14 +0000 (08:25 -0400)]
Merge branch '2021.01-rc' of https://github.com/lftan/u-boot
- fix Gen5 enable of EMAC via FPGA
Tom Rini [Wed, 21 Oct 2020 23:13:05 +0000 (19:13 -0400)]
Merge tag 'efi-2021-01-rc1-2' of https://gitlab.denx.de/u-boot/custodians/u-boot-efi
Pull request for UEFI sub-system for efi-2021-01-rc1 (2)
A use after free in the UEFI network stack is fixed.
Marek Vasut [Mon, 19 Oct 2020 21:40:26 +0000 (23:40 +0200)]
Revert "Fix data abort caused by mis-aligning FIT data"
This reverts commit
eb39d8ba5f0d1468b01b89a2a464d18612d3ea76.
The commit breaks booting of fitImage by SPL, the system simply hangs.
This is because on arm32, the fitImage and all of its content can be
aligned to 4 bytes and U-Boot expects just that.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Reuben Dowle <reuben.dowle@4rf.com>
Cc: Tom Rini <trini@konsulko.com>
Signed-off-by: Marek Vasut <marex@denx.de>
Patrick Delaunay [Thu, 15 Oct 2020 12:28:17 +0000 (14:28 +0200)]
stm32mp: stm32prog: accept device without partition
When partitions are not available on a device the command stm32prog raises
an error but a device can have no partition to check in init_device()
and the command need to continue to the next part_id.
This patch correct an issue for ram0 target, when block_dev and mtd
are NULL.
For example with the simple flashlayout file:
Opt Part Name Type Device Offset Binary
- 0x01 fsbl Binary none 0x0 tf-a-serialboot.stm32
- 0x03 ssbl Binary none 0x0 u-boot.stm32
P 0x10 kernel System ram0 0xC2000000 uImage.bin
P 0x11 dtb FileSytem ram0 0xC4000000 stm32mp157f-ev1.dtb
Fixes:
ffc405e63b94 ("stm32mp: stm32prog: add upport of partial update")
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Patrick Delaunay [Thu, 15 Oct 2020 12:46:34 +0000 (14:46 +0200)]
configs: stm32mp15: activate CMD_ELF
Activate CONFIG_CMD_ELF to accept the command "bootelf".
This patch simplifies the file stm32mp defconfig, as we have
no reason to deactivate this command.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Patrick Delaunay [Thu, 15 Oct 2020 12:31:51 +0000 (14:31 +0200)]
configs: stm32mp15: activate CMD_EXPORTENV
Activate CONFIG_CMD_EXPORTENV to accept the command "env export".
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Patrick Delaunay [Thu, 15 Oct 2020 12:31:50 +0000 (14:31 +0200)]
configs: stm32mp15: activate CMD_IMPORTENV
Activate CONFIG_CMD_IMPORTENV to accept the command "env import".
This command is useful in script to include some variable.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Patrick Delaunay [Tue, 6 Oct 2020 11:52:26 +0000 (13:52 +0200)]
MAINTAINERS: Add STM32MP1 RNG driver in stm32mp platform
Add the STM32MP1 RNG driver in the list of drivers supported by
the STMicroelectronics STM32MP15x series.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Patrick Delaunay [Tue, 6 Oct 2020 11:59:41 +0000 (13:59 +0200)]
MAINTAINERS: Add stm32 and stm regexp for ARM STM STM32MP platform
Add files and directories regex "stm32" and "stm" in "ARM STM STM32MP"
platform to avoid missing files or drivers supported by the
STMicroelectronics series STM32MP15x.
This patch adds the rules already used in Linux kernel for
ARM/STM32 ARCHITECTURE.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Patrick Delaunay [Fri, 2 Oct 2020 12:08:54 +0000 (14:08 +0200)]
arm: stm32: cleanup arch gpio.h
Cosmetic update of gpio.h:
- remove enumerate: stm32_gpio_port, stm32_gpio_pin
because STM32_GPIO_XXX values are unused
- move STM32_GPIOS_PER_BANK in stm32_gpio.c
as its value is IP dependent and not arch dependent
No functional change as number of banks and number of gpio by banks
is managed by device tree since since DM migration and
commit
8f651ca60ba1 ("pinctrl: stm32: Add get_pins_count() ops").
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Marek Vasut [Thu, 8 Oct 2020 13:14:58 +0000 (15:14 +0200)]
ARM: dts: stm32: Do not set eth1addr if KS8851 has EEPROM
In case the KS8851 has external EEPROM attached to it, do not set
eth1addr at all. The network stack will read the MAC out of the
KS8851 and set eth1addr accordingly.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
Patrick Delaunay [Fri, 4 Sep 2020 10:55:19 +0000 (12:55 +0200)]
stm32mp: limit size of cacheable DDR in pre-reloc stage
In pre-reloc stage, U-Boot marks cacheable the DDR limited by
the new config CONFIG_DDR_CACHEABLE_SIZE.
This patch allows to avoid any speculative access to DDR protected by
firewall and used by OP-TEE; the "no-map" reserved memory
node in DT are assumed after this limit:
STM32_DDR_BASE + DDR_CACHEABLE_SIZE.
Without security, in basic boot, the value is equal to STM32_DDR_SIZE.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Alexandru Gagniuc [Wed, 9 Sep 2020 21:54:02 +0000 (16:54 -0500)]
mmc: stm32_sdmmc2: Use mmc_of_parse() to read host capabilities
mmc_of_parse() can populate the 'f_max' and 'host_caps' fields of
struct mmc_config from devicetree.
The same logic is duplicated in stm32_sdmmc2_probe(). Use
mmc_of_parse(), which is more generic.
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Alexandru Gagniuc [Tue, 15 Sep 2020 19:51:46 +0000 (14:51 -0500)]
mmc: mmc_of_parse: Enable 52 MHz support with "cap-mmc-highspeed"
"cap-mmc-highspeed" enables support for 26 MHz MMC, but there is no
additional flag to enable 52 MHz MMC. In Linux. "cap-mmc-highspeed"
is used for MMC HS at both 26MHz and 52MHz.
Use the same approach and enable MMC_CAP(MMC_HS_52) host capability
when "cap-mmc-highspeed" is found in the devicetree. In the event an
MMC card doesn't support 52 MHz, it will be clocked at a speed based
on its EXT CSD, even on 52 MHz host controllers
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
Tested-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Ralph Siemsen [Tue, 29 Sep 2020 18:52:05 +0000 (14:52 -0400)]
arm: socfpga: fix Gen5 enable of EMAC via FPGA
An earlier conversion from struct to defines introduced two errors, both
related to setup of EMAC routed via the FPGA. One of the offsets was
incorrect, and the EMAC0/EMAC1 were swapped.
The effect of this was rather odd: both ports could operate at gigabit,
but one of them would fail to transmit when operating at 100Mbit.
Fixes:
db5741f7a85ec3ee79b64496172afaa7dc2cb225 ("arm: socfpga: Convert system manager from struct to defines")
Signed-off-by: Ralph Siemsen <ralph.siemsen@linaro.org>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
Tom Rini [Tue, 20 Oct 2020 12:02:53 +0000 (08:02 -0400)]
Merge https://gitlab.denx.de/u-boot/custodians/u-boot-sh
- Assorted R-Car Gen3 updates
Tom Rini [Tue, 20 Oct 2020 12:01:46 +0000 (08:01 -0400)]
Merge https://gitlab.denx.de/u-boot/custodians/u-boot-usb
- MediaTek USB host support
Lad Prabhakar [Wed, 14 Oct 2020 15:45:59 +0000 (16:45 +0100)]
pinctrl: renesas: pfc-r8a77990: Sync PFC tables with Linux 5.9
Sync the R8A77990 SoC PFC tables with Linux 5.9 , commit
bbf5c979011a.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Lad Prabhakar [Fri, 16 Oct 2020 07:37:14 +0000 (08:37 +0100)]
clk: renesas: Import R8A774C0 clock tables from Linux 5.9
Import RZ/G2E (R8A774C0) clock tables from Linux 5.9 commit
bbf5c979011a ("Linux 5.9").
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Biju Das [Wed, 14 Oct 2020 17:17:36 +0000 (18:17 +0100)]
clk: renesas: Add R8A774E1 clock tables
This sync's the RZ/G2H clock tables with mainline linux 5.9 commit
bbf5c979011a ("Linux 5.9").
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Biju Das [Wed, 14 Oct 2020 17:17:35 +0000 (18:17 +0100)]
clk: renesas: Add R8A774B1 clock tables
This sync's the RZ/G2N clock tables with mainline linux 5.9 commit
bbf5c979011a ("Linux 5.9").
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Lad Prabhakar [Fri, 16 Oct 2020 07:37:13 +0000 (08:37 +0100)]
arm: dts: r8a774c0: Import DTS from Linux 5.9
Import R8A774C0 (RZ/G2E) SoC DTSI and headers from Linux 5.9
commit
bbf5c979011a ("Linux 5.9").
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Lad Prabhakar [Fri, 16 Oct 2020 07:37:12 +0000 (08:37 +0100)]
arm: renesas: Add config option for R8A774C0 SoC
Add config support for RZ/G2E (a.k.a R8A774C0) SoC.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Biju Das [Mon, 12 Oct 2020 15:16:15 +0000 (16:16 +0100)]
arm: renesas: Add config option for R8A774E1 SoC
Add config support for RZ/G2H(a.k.a R8A774E1) SoC.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Biju Das [Mon, 12 Oct 2020 15:16:14 +0000 (16:16 +0100)]
arm: renesas: Add config option for R8A774B1 SoC
Add config support for RZ/G2N(a.k.a R8A774B1) SoC.
Also fixed the alignment issue on R8A774A1 config.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Biju Das [Tue, 29 Sep 2020 10:09:44 +0000 (11:09 +0100)]
clk: renesas: r8a774a1-cpg-mssr: Add R8A774A1 RPC clock
Add RPC entry into the R8A774A1 clock driver tables.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Biju Das [Wed, 30 Sep 2020 12:19:34 +0000 (13:19 +0100)]
spi: renesas_rpc_spi: Add R-Car Gen3 and RZ/G2 fallback compatibility string
Add fallback compatibility string for R-Car Gen3 and RZ/G2.
Also sorted the compatible string as per SoC ID.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Chunfeng Yun [Wed, 14 Oct 2020 07:08:33 +0000 (15:08 +0800)]
MAINTAINERS: add USB driver to ARM MEDIATEK
Add MediaTek USB3 Dual-Role controller driver to ARM MEDIATEK,
and add myself as a maintainer for it.
Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Chunfeng Yun [Wed, 14 Oct 2020 07:08:32 +0000 (15:08 +0800)]
configs: mt8512: enable fastboot and USB host related configs
Enable mtu3, xhci, tphy drivers.
Device mode: enable fastboot;
Host mode: enable USB, FAT commands, and fixed regulator,
mass storage drivers;
Due to device mode is enabled by default, comment out
the host mode config here.
Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Chunfeng Yun [Wed, 14 Oct 2020 07:08:31 +0000 (15:08 +0800)]
arm: dts: mt8512: add usb related nodes
Add usb, usb phy, and fixed regulators nodes
Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
Acked-by: Bin Meng <bmeng.cn@gmail.com>
Chunfeng Yun [Wed, 14 Oct 2020 07:08:30 +0000 (15:08 +0800)]
usb: gadget: Add bcdDevice for the MTU3 USB Gadget Controller
Add an entry in usb_gadget_controller_number() for the MTU3
gadget controller. It is used to bind the USB Ethernet driver.
Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Chunfeng Yun [Fri, 16 Oct 2020 03:38:39 +0000 (11:38 +0800)]
usb: add MediaTek USB3 DRD driver
This patch adds support for the MediaTek USB3 DRD controller,
its host side is based on xHCI, this driver supports device mode
and host mode.
Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
Acked-by: Bin Meng <bmeng.cn@gmail.com>
Chunfeng Yun [Wed, 14 Oct 2020 07:08:28 +0000 (15:08 +0800)]
usb: common: add define of usb_speed_string()
There is only declaration of usb_speed_string(), but no definition,
so add it to avoid build error when call it.
Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Chunfeng Yun [Wed, 14 Oct 2020 07:08:27 +0000 (15:08 +0800)]
usb: add USB_SPEED_SUPER_PLUS
Add enum USB_SPEED_SUPER_PLUS for USB3.1
Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Chunfeng Yun [Wed, 14 Oct 2020 07:08:26 +0000 (15:08 +0800)]
dt-bindings: usb: mtu3: add bindings for MediaTek USB3 DRD
Add dt-binding for MediaTek USB3 DRD Driver which it's ported
from the Linux kernel DTS binding:
Documentation/devicetree/bindings/usb/mediatek,mtu3.txt
Commit ID:
34d0545978b6 ("dt-bindings: usb: mtu3: fix typo of DMA clock name")
Due to Dual-Role switch is not supported in Uboot, some properties
are removed or changed.
Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Chunfeng Yun [Wed, 14 Oct 2020 07:08:25 +0000 (15:08 +0800)]
dt-binding: usb: add bindings for some common properties
Add bindings for common properties, include maximum-speed,
dr_mode and phy_type
Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Naoki Hayama [Mon, 12 Oct 2020 09:35:42 +0000 (18:35 +0900)]
usb: musb-new: Fix typo in caution message
%s/Occured/Occurred/
Signed-off-by: Naoki Hayama <naoki.hayama@lineo.co.jp>
Chance.Yang [Tue, 6 Oct 2020 02:55:49 +0000 (10:55 +0800)]
usb: dwc2: Fix control OUT transfer issue
In buffer DMA mode, gadget should re-configure EP 0 to received SETUP
packets when doeptsiz.xfersize is equal to a setup packet size(8 bytes)
and EP 0 is in WAIT_FOR_SETUP state.
Since EP 0 is not enabled in WAIT_FOR_SETUP state, SETUP packets is NOT
received from RxFifo and wriiten to the external memory.
Signed-off-by: Chance.Yang <chance.yang@vatics.com>
Heinrich Schuchardt [Tue, 29 Sep 2020 20:03:01 +0000 (22:03 +0200)]
usb: xhci: avoid type conversion of void *
void * can be assigned to any pointer variable. Avoid unnecessary
conversions.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Patrick Wildt [Wed, 7 Oct 2020 09:04:33 +0000 (11:04 +0200)]
efi_loader: fix use after free in receive path
With DM enabled the ethernet code will receive a packet, call
the push method that's set by the EFI network implementation
and then free the packet. Unfortunately the push methods only
sets a flag that the packet needs to be handled, but the code
that provides the packet to an EFI application runs after the
packet has already been freed.
To rectify this issue, adjust the push method to accept the packet
and store it in a temporary buffer. The EFI application then gets
the data copied from that buffer. This way the packet is cached
until is is needed.
The DM Ethernet stack tries to receive 32 packets at once, thus
we better allocate as many buffers as the stack.
Signed-off-by: Patrick Wildt <patrick@blueri.se>
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Patrick Wildt [Wed, 7 Oct 2020 09:03:30 +0000 (11:03 +0200)]
net: add a define for the number of packets received as batch
With a define for the magic number of packets received as batch
we can make sure that the EFI network stack caches the same amount
of packets.
Signed-off-by: Patrick Wildt <patrick@blueri.se>
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Tom Rini [Mon, 19 Oct 2020 13:29:05 +0000 (09:29 -0400)]
Merge tag 'u-boot-atmel-2021.01-b' of https://gitlab.denx.de/u-boot/custodians/u-boot-atmel
Second set of u-boot-atmel features for 2021.01 cycle:
This feature set brings the rework of the clock tree for sam9x60 SoC.
This makes the clock tree fully compatible with Common Clock Framework
and allows full clock configuration in U-Boot. This means that the
sam9x60 boards can boot now using U-Boot.
This also includes the definitions for sam9x60 SiPs and a divisor fix
for the clock on sama7g5 SoC.
Eugen Hristev [Wed, 1 Jul 2020 07:44:21 +0000 (10:44 +0300)]
clk: at91: sama7g5: add 5th divisor for mck0 layout and characteristics
This SoC has the 5th divisor for the mck0 master clock.
Adapt the characteristics accordingly.
Reported-by: Mihai Sain <mihai.sain@microchip.com>
Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Eugen Hristev [Wed, 1 Jul 2020 07:42:58 +0000 (10:42 +0300)]
clk: at91: clk-master: add 5th divisor for mck master
clk-master can have 5 divisors with a field width of 3 bits
on some products.
Change the mask and number of divisors accordingly.
Reported-by: Mihai Sain <mihai.sain@microchip.com>
Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Nicolas Ferre [Wed, 7 Oct 2020 14:53:44 +0000 (16:53 +0200)]
ARM: at91: Add chip ID for SAM9X60 SiP
SAM9X60 SiP (System in Package) are added for SoC identification.
Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Claudiu Beznea [Wed, 7 Oct 2020 15:17:14 +0000 (18:17 +0300)]
ARM: dts: sam9x60: use alphabetical order
Use alphabetical order for entries in sam9x60ek-u-boot.dtsi
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Claudiu Beznea [Wed, 7 Oct 2020 15:17:13 +0000 (18:17 +0300)]
configs: sam9x60ek: update defconfigs for CCF
Update defconfigs for using common clock framework compatible
clocks.
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Claudiu Beznea [Wed, 7 Oct 2020 15:17:12 +0000 (18:17 +0300)]
ARM: dts: sam9x60: use CCF compatibles for PMC
Use CCF compatible for PMC. With this, the board/SoC will be
able to boot.
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Claudiu Beznea [Wed, 7 Oct 2020 15:17:11 +0000 (18:17 +0300)]
ARM: dts: sam9x60: use slow clock CCF compatible bindings
Use slow clock CCF compatible DT bindings. This will not break
the above functionality as the SoC is not booting with current
PMC bindings.
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Claudiu Beznea [Wed, 7 Oct 2020 15:17:10 +0000 (18:17 +0300)]
ARM: dts: sam9x60: use u-boot,dm-pre-reloc
Use u-boot,dm-pre-reloc for slow xtal and main xtal.
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Claudiu Beznea [Wed, 7 Oct 2020 15:17:09 +0000 (18:17 +0300)]
ARM: dts: sam9x60ek: add clock frequencies to board file
Slow Xtal and Main Xtal are board specific. Add their proper
frequency to board file.
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Claudiu Beznea [Wed, 7 Oct 2020 15:17:08 +0000 (18:17 +0300)]
clk: at91: sam9x60: add support compatible with CCF
Add SAM9X60 clock support compatible with CCF.
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Claudiu Beznea [Wed, 7 Oct 2020 15:17:07 +0000 (18:17 +0300)]
board: atmel: sam9x60ek: add SYS_MALLOC_F_LEN to SYS_INIT_SP_ADDR
Heap base address is computed based on SYS_INIT_SP_ADDR by
subtracting the SYS_MALLOC_F_LEN value in
board_init_f_init_reserve().
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Tom Rini [Mon, 19 Oct 2020 01:19:06 +0000 (21:19 -0400)]
Merge tag 'video-for-2021.01' of https://gitlab.denx.de/u-boot/custodians/u-boot-video
- add dw-mipi-dsi phy timings and Tx escape clock configuration
- fix pwm backlight duty cycle calculation
- migrate CONFIG_VIDEO_BMP_* and CONFIG_BMP_* to Kconfig
Patrick Delaunay [Mon, 28 Sep 2020 09:30:16 +0000 (11:30 +0200)]
configs: migrate CONFIG_BMP_16/24/32BPP to defconfigs
Done with:
./tools/moveconfig.py BMP_16BPP BMP_24BPP BMP_32BPP
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Patrick Delaunay [Mon, 28 Sep 2020 09:30:15 +0000 (11:30 +0200)]
configs: migrate CONFIG_VIDEO_BMP_RLE8 to defconfigs
Done with:
./tools/moveconfig.py VIDEO_BMP_RLE8
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Patrick Delaunay [Mon, 28 Sep 2020 09:30:14 +0000 (11:30 +0200)]
configs: migrate CONFIG_VIDEO_BMP_GZIP to defconfigs
Done with:
./tools/moveconfig.py VIDEO_BMP_GZIP
The 3 suspicious migration because CMD_BMP and SPLASH_SCREEN
are not activated in these defconfigs:
- trats_defconfig
- s5pc210_universal_defconfig
- trats2_defconfig
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Dario Binacchi [Sun, 11 Oct 2020 12:28:04 +0000 (14:28 +0200)]
video: backlight: fix pwm's duty cycle calculation
For levels equal to the maximum value, the duty cycle must be equal to
the period.
Signed-off-by: Dario Binacchi <dariobin@libero.it>
Reviewed-by: Simon Glass <sjg@chromium.org>
Dario Binacchi [Sun, 11 Oct 2020 12:28:03 +0000 (14:28 +0200)]
video: backlight: fix pwm data structure description
The description of the 'max_level' field was incorrectly assigned to the
'min_level' field.
Signed-off-by: Dario Binacchi <dariobin@libero.it>
Neil Armstrong [Fri, 2 Oct 2020 09:16:09 +0000 (11:16 +0200)]
video: dw-mipi-dsi: permit configuring the escape clock rate
The Amlogic D-PHY in the Amlogic AXG SoC Family does support a frequency
higher than 10MHz for the TX Escape Clock, thus make the target rate
configurable.
This is based on the Linux commit [1] and adapted to the U-Boot driver.
[1]
a328ca7e4af3 ("drm/bridge: dw-mipi-dsi: permit configuring the escape clock rate")
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Neil Armstrong [Fri, 2 Oct 2020 09:16:08 +0000 (11:16 +0200)]
video: dw-mipi-dsi: driver-specific configuration of phy timings
The timing values for dw-dsi are often dependent on the used display and
according to Philippe Cornu will most likely also depend on the used phy
technology in the soc-specific implementation.
To solve this and allow specific implementations to define them as needed
add a new get_timing callback to phy_ops and call this from the dphy_timing
function to retrieve the necessary values for the specific mode.
This is based on the Linux commit [1] and adapted to the U-Boot driver.
[1]
25ed8aeb9c39 ("drm/bridge/synopsys: dsi: driver-specific configuration of phy timings")
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Sean Anderson [Tue, 13 Oct 2020 19:20:52 +0000 (15:20 -0400)]
test: Fix sandbox tests failing to build
syslog_test.h is in test/log/, not include/
Fixes:
52d3df7fef ("log: Allow LOG_DEBUG to always enable log output")
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tom Rini [Fri, 16 Oct 2020 13:56:15 +0000 (09:56 -0400)]
Merge https://gitlab.denx.de/u-boot/custodians/u-boot-marvell
- Fix Octeon SPI driver for Octeon TX2
- Fix and enhance Octeon watchdog driver
- Misc minor enhancements to Octeon TX/TX2
Tom Rini [Fri, 16 Oct 2020 13:44:51 +0000 (09:44 -0400)]
Merge branch '2020-10-15-further-cleanup_dev_xxx'
- Bring in the next round of dev_xxx cleanup patches.
Sean Anderson [Mon, 5 Oct 2020 01:39:57 +0000 (21:39 -0400)]
dm: Don't undefine dev_xxx macros
Now that linux/compat.h does not define these macros, we do not need to
undefine them.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Sean Anderson [Mon, 5 Oct 2020 01:39:56 +0000 (21:39 -0400)]
linux/compat.h: Remove redefinition of dev_xxx macros
All users of these functions now include dm/device_compat.h directly.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tom Rini [Fri, 16 Oct 2020 12:41:37 +0000 (08:41 -0400)]
usb: dwc3: Include device_compat.h in dwc3-octeon-glue.c
Necessary for dev_xxx.
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Fri, 16 Oct 2020 01:44:43 +0000 (21:44 -0400)]
clk: at91: Include device_compat.h in compat.c
Necessary for dev_xxx.
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Fri, 16 Oct 2020 01:44:15 +0000 (21:44 -0400)]
arm: fsl-layerscape: Include device_compat.h in soc.c
Necessary for dev_xxx.
Signed-off-by: Tom Rini <trini@konsulko.com>
Sean Anderson [Mon, 5 Oct 2020 01:39:55 +0000 (21:39 -0400)]
usb: musb-new: mt85xx: Fix not calling dev_err with a device
This driver doesn't use DM (in the correct places), so we use a device and
not a udevice. We also need to include device_compat.h
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Sean Anderson [Mon, 5 Oct 2020 01:39:54 +0000 (21:39 -0400)]
usb: musb-new: Include device_compat.h
This was included, but was ifdef'd out. We also need dm.h for struct
udevice.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Sean Anderson [Mon, 5 Oct 2020 01:39:53 +0000 (21:39 -0400)]
usb: xhci: Include device_compat.h
This header is necessary for the dev_xxx macros.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Sean Anderson [Mon, 5 Oct 2020 01:39:52 +0000 (21:39 -0400)]
timer: Include device_compat.h
Necessary for dev_xxx.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Sean Anderson [Mon, 5 Oct 2020 01:39:51 +0000 (21:39 -0400)]
tee: optee: Include device_compat.h
Necessary for dev_xxx.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Sean Anderson [Mon, 5 Oct 2020 01:39:50 +0000 (21:39 -0400)]
spi: fsl_qspi: Include device_compat.h
Necessary for dev_xxx.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Sean Anderson [Mon, 5 Oct 2020 01:39:49 +0000 (21:39 -0400)]
spi: nxp_fspi: Include device_compat.h
Necessary for dev_xxx.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Stefan Roese [Wed, 23 Sep 2020 09:01:32 +0000 (11:01 +0200)]
arm: octeontx: Add CMD_WDT
Enable WDT command for Octeon TX/TX2 boards.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Aaron Williams <awilliams@marvell.com>
Cc: Suneel Garapati <sgarapati@marvell.com>
Cc: Chandrakala Chavva <cchavva@marvell.com>
Suneel Garapati [Wed, 23 Sep 2020 09:01:31 +0000 (11:01 +0200)]
watchdog: octeontx_wdt: Add support for start and stop
This patch enhances the Octeon TX/TX2 watchdog driver to fully enable
the WDT. With this changes, the "wdt" command is now also supported
on these platforms.
Signed-off-by: Suneel Garapati <sgarapati@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Aaron Williams <awilliams@marvell.com>
Cc: Suneel Garapati <sgarapati@marvell.com>
Cc: Chandrakala Chavva <cchavva@marvell.com>
Stefan Roese [Wed, 23 Sep 2020 09:01:30 +0000 (11:01 +0200)]
arm: octeontx: Select CLK
Clock support is needed for all Octeon TX/TX2 boards. This patch selects
CONFIG_CLK so that it is available.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Aaron Williams <awilliams@marvell.com>
Cc: Suneel Garapati <sgarapati@marvell.com>
Cc: Chandrakala Chavva <cchavva@marvell.com>
Stefan Roese [Wed, 23 Sep 2020 09:01:29 +0000 (11:01 +0200)]
mmc: octeontx_hsmmc.c: Remove test debug message
Remove a left-over debug test message from the Octeon TX / TX2
MMC driver.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Aaron Williams <awilliams@marvell.com>
Cc: Suneel Garapati <sgarapati@marvell.com>
Cc: Chandrakala Chavva <cchavva@marvell.com>
Stefan Roese [Wed, 5 Aug 2020 13:07:30 +0000 (15:07 +0200)]
spi: octeon_spi: Use a fixed 100MHz input clock on Octeon TX2
Octeon TX2 sets the TB100_EN bit in the config register. We need to use
a fixed 100MHz clock for this as well to work properly.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Aaron Williams <awilliams@marvell.com>
Cc: Suneel Garapati <sgarapati@marvell.com>
Cc: Chandrakala Chavva <cchavva@marvell.com>
Cc: Jagan Teki <jagan@amarulasolutions.com>