zink: cache transfer maps

vk spec disallows mapping memory regions more than once, but we always
map the full memory range, so we can just refcount and store the pointer
onto the resource object for reuse to avoid issues here

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9725>

zink: break out buffer mapping part of zink_transfer_map

no functional changes, but this is going to get much more complex in
the near future

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9725>

ci: update xfails for ppc64le and s390x

tests are passing now

Acked-by: Daniel Stone <daniel@fooishbar.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9773>

ci: update list of expected CTS failures for RADV

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9756>

gitlab-ci: Build meson-mingw32-x86_64 w/o zlib.

To prevent hard requirement of zlib from creeping in, as
https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9689

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9727>

android: anv: add libcutils shared dependency

My previous patch merged as 2b1930a50a0b was incomplete

Fixes the following building error:

FAILED: out/target/product/x86_64/obj/SHARED_LIBRARIES/vulkan.anv_intermediates/LINKED/vulkan.anv.so
...
ld.lld: error: undefined symbol: property_get
>>> referenced by os_misc.c:193 (external/mesa/src/util/os_misc.c:193)
>>>               os_misc.o:(os_get_option) in archive out/target/product/x86_64/obj/STATIC_LIBRARIES/libmesa_util_intermediates/libmesa_util.a

Cc: 21.0 <mesa-stable@lists.freedesktop.org>
Fixes: eeecc21d935c ("util: Add property_get() fallback for android")
Fixes: 2b1930a50a0b ("android: radv: add libcutils shared dependency")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9744>

freedreno: Split out devicetree helpers

The freedreno pps datasource is going to need the same, so split out
helpers that can be re-used.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9758>

freedreno/fdperf: Use os_read_file()

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9758>

freedreno: Make headers C++ happy

We'll need a few of these for the C++ based gfx-pps performance counter
collector datasource.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9758>

freedreno/a6xx: Disable sample averaging on depth/stencil resolves.

From the GLES 3.2 spec:

"If the source formats are integer types or stencil values, a single
sample’s value is selected for each pixel. If the source formats are
floating-point or normalized types, the sample values for each pixel are
resolved in an implementation-dependent manner. If the source formats are
depth values, sample values are resolved in an implementation-dependent
manner where the result will be between the minimum and maximum depth
values in the pixel."

For Z24S8 we were doing an average, which would be invalid for the stencil
data, and apparently the CTS didn't catch that.  For Z32F, our averaging
was technically legal, but given the Vulkan spec's requirement of sample 0
support but not sample average support for depth and stencil resolves, it
suggests that our averaging behavior was unusual.  Let's not spend power
on producing surprising results.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9661>

freedreno/a6xx: Rename the RB_BLIT_INFO.INTEGER field to SAMPLE_0.

As @samuelig found, this is the field for disabling sample averaging and
using sample 0 instead.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9661>

iris: Delete stale comment in iris_lost_context_state

Hasn't been necessary since b338bb70e0df3839718315140f217d173cc6d460.
Caught by Dave Airlie.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9752>

.mailmap: fix email for Daniel Schürmann

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9755>

turnip: expose several already implemented extensions

They were promoted to Vulkan 1.1 and we already support them.

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9757>

freedreno/computerator: Add script for finding reg file size

This helps with finding the various parameters introduced in the last
commit.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9498>

freedreno: Report max_waves in shaderdb output

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9498>

freedreno/computerator: Use threadsize calculated by ir3

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9498>

freedreno: Use threadsize calculated by ir3

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9498>

turnip: Use threadsize calculated by ir3

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9498>

ir3: Calcuate max_waves and threadsize

max_waves is just for shader-db stats for now, but threadsize will
replace the various mechanisms used to determine threadsize across the
different gen's. Calculating these correctly entails adding a bunch of
details about the sizes of various things to ir3. In the future we will
use the guts of the max_waves calculation to inform RA decisions as
well, which is why the max_waves calculation is broken up into register
dependent/independent pieces.

Something should be said about the units of reg_size_vec4. These units
were chosen for two reasons:

1. As said in the comment, it makes some calculations easier.
2. For a4xx/a5xx, where we don't know as much because we haven't done
   the same sorts of experiments to probe for the HW configuration, it
   corresponds more directly to things that are known. The existing code
   switches to the smaller threadsize when r24.x or higher is used,
   which translates directly to a reg_size_vec4 of 48. If we chose
   different units (e.g. multiplying by wave_granularity and/or
   threadsize_base), then to match the same behavior we'd have to set
   reg_size_vec4 based on some other parameters that aren't 100% known.
   If someone comes along and updates them, they might inadvertantly
   break it.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9498>

freedreno: Add local_size to ir3_shader_variant

We want to use the local_size when available to calculate the threadsize
in ir3, and we need it to work with e.g. computerator where we don't
have a nir shader. Add a local_size field and use that in computerator
instead of of a separate structure that's inaccessable to core ir3.

Also set a dummy local_size in the tests to avoid a divide-by-zero.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9498>

v3dv: Add support for the on-disk shader cache

Quoting Jason's commit message (afa8f5892), that also applies here:

"The Vulkan API provides a mechanism for applications to cache their
own shaders and manage on-disk pipeline caching themselves.
Generally, this is what I would recommend to application developers
and I've resisted implementing driver-side transparent caching in the
Vulkan driver for a long time.  However, not all applications do this
and, for some use-cases, it's just not practical."

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9403>

v3dv/device: avoid unused-result warning with asprintf

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9403>

v3dv/pipeline: compute sha1 for no-op fragment shaders correctly

We should use the nir shader, as with internal vkShaderModule, instead
of just the name.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9403>

v3dv/pipeline: don't create a variant if compilation failed

Also return the proper Vulkan result for this case, that is somewhat
tricky. Technically Create[Graphics/Compute]Pipeline only allow OOM
errors. So for this case, there is only the alternative of the generic
VK_ERROR_UNKNOWN, even if we known the cause of the error. From spec:

 "VK_ERROR_UNKNOWN will be returned by an implementation when an
  unexpected error occurs that cannot be attributed to valid behavior
  of the application and implementation. Under these conditions, it
  may be returned from any command returning a VkResult"

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9403>

v3dv/pipeline: try to get the shader variant directly from the cache

Until now we were always doing a two-step cache lookup, as we were
using the NIR shaders to fill up the key to lookup for the compiled
shaders. But since we were already generating the sha1 key with the
original SPIR-V shader (or its internal NIR representation) any info
we were collecting from from NIR is already implicit in the original
shader, so we can avoid using the NIR in most cases.

Because the v3d_key that is used to compile a shader is populated with
data coming directly from the NIR shader or produced during NIR
lowerings, we can't use it directly as part of the pipeline cache
entry. We could split them, but that would be confusing, so we add a
new struct, v3dv_pipeline_key used specifically to search for the
compiled shaders on the pipeline cache. v3d_key would be still used to
compile the shaders.

As we are using the same sha1 key for all compiled shaders in a
pipeline, we can also group all of them in the same cache entry, so we
don't need a lookup for each stage. This also allows to cache pipeline
data shared by all the stages (like the descriptor maps).

While we are here, we also create a single BO to store the assembly
for all the pipeline stages.

Finally, we remove the link to the variant on the pipeline stage
struct, to avoid the confusion of having two links to the same
data. This mostly means that we stop to use the pipeline stage
structures after the pipeline is created, so we can freed them.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9403>

v3dv/pipeline: use broadcom_shader_stage as pipeline/variant stage type

So we could avoid using gl_shader_stage plus a is_coord boolean, that
only applies to VERTEX.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9403>

v3dv: define broadcom shader stages

Mostly the same that main mesa gl_shader_stage, but including the
coordinate shader. This would allow to loop over all the available
stages (for example if we need to free them, compute the max spill
size, etc).

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9403>

v3dv/pipeline: remove v3d_key from shader_variant and pipeline stage

We stopped to re-use them after pippeline creation long ago, so let's
reduce the size of both structs, and avoid serialize/deserialize for
the variant case.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9403>

v3dv/pipeline: remove compiled_variant_count field

We are not really compiling several variants, or at least not on the
same pipeline.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9403>

v3dv/pipeline: move topology to pipeline

So now we only store it once per pipeline, instead of once per
pipeline stage.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9403>

v3dv/pipeline: use driver_location_map instead of nir utilities

If we were able to get a shader variant from the pipeline cache, we
will not have the nir shader available.

Note that this is what we were doing on the driver before the nir io
helpers were available.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9403>

broadcom/compiler: add driver_location_map at vs prog data

This maps the nir shader data.location to its final
data.driver_location. In general we are using the driver location as
index (like vattr_sizes on the same struct), so having this map is
useful if what we have is the data.location, and we don't have
available the original nir shader.

v2: use memset instead of for loop, and nir_foreach_shader_in_variable
    instead of nir_foreach_variable_with_modes (Iago)

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9403>

broadcom/compiler: add local_size in v3d_compute_prog_data

As we plan to try to get directly the compiled variant from the cache,
it would be possible to not have available the nir shaders, so we add
this info on prog data.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9403>

v3dv/pipeline: remove pipeline->use_push_constants

In the past we used this boolean for several things, it is really
superfluous right now.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9403>

v3dv/pipeline: remove pregenerate_variant

Right now we were not pre-generating several variants, but we decided
to let this method, just in case we need that idea back. This ended
being a bad idea. Several months have passed without that need, so
having that method just adds confusion. Also, if we need to add a
multiple-variant in the future, perhaps we would need to do it
different, so let's not template in advance.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9403>

v3dv/pipeline_cache: add more details when dumping debug info

We tweak a little some of the individual messages, and add a new
option to dump the stats when the pipeline destroy.

As we are here we also we also tweak the names of the global options
to make it more clear.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9403>

vk: consolidate dynamic descriptor binding sorting

this code was duplicated across several drivers

Reviewed-by: Adam Jackson <ajax@redhat.com>
turnip changes Reviewed-by: Hyunjun Ko <zzoon@igalia.com>

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9480>

docs: Add calendar entries for 21.1 release candidates.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9605>

docs: Extend calendar entries for 21.0 by 1 releases.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9605>

docs: missing lvp win32surface ext in features.txt

Acked-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9702>

nvc0: fix reported driver queries for Pascal and later GPUs

We haven't added the sm/metric info post-GM200. So make sure we don't
report available queries there. Additionally, fix the group retrieval to
take into account that either driver stats or SM stats may not be
available.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9740>

nvc0: ensure sufficient push space for indirect data

There may be up to 3 pushbuf data's submitted in this function, make
sure that we allocate enough room for these.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9740>

nv50: add appropriate space check before adding new pushbuffer

nouveau_pushbuf_data does not check that there are available pushes in
the current batch. So add a space check for this. Avoids crashes with
the HUD and glxspheres.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9740>

nv50,nvc0: remove explicit target argument from view creation

Before texture views were supported, this was needed in some cases.
However with texture views (added eons ago), there is now a target
attribute in the template. Use it and remove the explicit argument.

Should help prevent bugs with inconsistencies between the stored
template target and the one that's used to create the view.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9740>

nv50: initialize target for blit source surfaces

This target is used to determine whether MS scaling factors are to be
uploaded.

Fixes: 1288ac7632b3 ("nv50: don't try to upload MSAA settings for BUFFER textures")
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9740>

ir3: update info about applicability of saturation modifier

On a6xx saturation doesn't work on cat4 and on bary.f

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9751>

r60/sfn: don't lower scomp

The backend has the corresponding ops.

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Kristian H. Kristensen <hoegsberg@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9452>

r600/sfn: lower find_msb variants to find_msb_rev

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Kristian H. Kristensen <hoegsberg@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9452>

r600/sfn: optimize comp+csel using fused ops

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Kristian H. Kristensen <hoegsberg@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9452>

r600/sfn: Add algebraic lowering for fsin and  fcos

* fsin and fcos require normalization of the input
* bitfield_insert requires an additional shift of the insert value

v2: drop bitfield_insert lowering code, it is already avaibable as
    compiler option (Rhys Perry)

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Kristian H. Kristensen <hoegsberg@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9452>

nir: Add r600 specific sin and cos variants

r600 expect the input values to be normalited by divinding by 2 *PI, so
add an opcode to be able to lower this in nir.

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Kristian H. Kristensen <hoegsberg@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9452>

nir: Add opcodes for fused comp + csel and optimizations

Some backends, like r600 support a fused version of int and float compare
against zero and and csel. Adding these opcodes here makes it possible to
optimize this in nir.

v2: Add rules for float compare + csel

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Kristian H. Kristensen <hoegsberg@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9452>

nir: add opcodes for *find_msb_rev and lowering

Some hardware supports a version of find_msb where the bits are counted
starting at the high bit, and this needs some lowering to obtain the
value that is expected by *find_msb

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Kristian H. Kristensen <hoegsberg@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9452>

radv: lower view_index to zero if multiview is disabled

Apparently, gl_ViewIndex can be used if multiview is disabled.

See https://gitlab.freedesktop.org/mesa/mesa/-/issues/4446

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9718>

zink: implement a global framebuffer cache

this uses the same mechanics as surface caching, but it
also requires that surfaces keep refs of the framebuffers they're
attached to so that they can invalidate the fb object upon destruction,
as, similar to program objects, the fb objects are "owned" by their attachments

loosely based on patches by Antonio Caggiano

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9665>

zink: use a custom surface referencing function whenever unrefing a surface

pipe_surface_reference uses surface->context, which is not reliable when sharing
surfaces between contexts. since a surface will never be destroyed outside of
zink if its context is dead, forcing surfaces to go directly to the screen object
prevents accessing dead contexts

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9665>

zink: break out surface destroy function into a screen function

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9665>

zink: use surface references for fb attachments

this guarantees the lifetimes of framebuffer surfaces

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9665>

zink: add explicit surface/bufferview batch-tracking functions

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9665>

zink: make fb ref func return bool on free

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9665>

broadcom/compiler: use nir_lower_undef_to_zero

total instructions in shared programs: 13731663 -> 13721549 (-0.07%)
instructions in affected programs: 98242 -> 88128 (-10.29%)
helped: 191
HURT: 131
Instructions are helped.

total threads in shared programs: 412272 -> 412296 (<.01%)
threads in affected programs: 24 -> 48 (100.00%)
helped: 12
HURT: 0
Threads are helped.

total uniforms in shared programs: 3780693 -> 3779137 (-0.04%)
uniforms in affected programs: 10564 -> 9008 (-14.73%)
helped: 114
HURT: 7
Uniforms are helped.

total max-temps in shared programs: 2319942 -> 2319528 (-0.02%)
max-temps in affected programs: 4191 -> 3777 (-9.88%)
helped: 113
HURT: 22
Max-temps are helped.

total sfu-stalls in shared programs: 31584 -> 31616 (0.10%)
sfu-stalls in affected programs: 217 -> 249 (14.75%)
helped: 51
HURT: 54
Inconclusive result (value mean confidence interval includes 0).

total inst-and-stalls in shared programs: 13763247 -> 13753165 (-0.07%)
inst-and-stalls in affected programs: 98719 -> 88637 (-10.21%)
helped: 187
HURT: 134
Inst-and-stalls are helped.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9681>

broadcom/compiler: optimize constant vfpack

total instructions in shared programs: 13733627 -> 13731663 (-0.01%)
instructions in affected programs: 174140 -> 172176 (-1.13%)
helped: 1597
HURT: 310
Instructions are helped.

total uniforms in shared programs: 3784601 -> 3780693 (-0.10%)
uniforms in affected programs: 58678 -> 54770 (-6.66%)
helped: 2886
HURT: 3
Uniforms are helped.

total max-temps in shared programs: 2322714 -> 2319942 (-0.12%)
max-temps in affected programs: 15729 -> 12957 (-17.62%)
helped: 2189
HURT: 1
Max-temps are helped.

total spills in shared programs: 6010 -> 6012 (0.03%)
spills in affected programs: 61 -> 63 (3.28%)
helped: 0
HURT: 1

total fills in shared programs: 13494 -> 13497 (0.02%)
fills in affected programs: 89 -> 92 (3.37%)
helped: 0
HURT: 1

total sfu-stalls in shared programs: 31521 -> 31584 (0.20%)
sfu-stalls in affected programs: 328 -> 391 (19.21%)
helped: 30
HURT: 94
Inconclusive result (%-change mean confidence interval includes 0).

total inst-and-stalls in shared programs: 13765148 -> 13763247 (-0.01%)
inst-and-stalls in affected programs: 174237 -> 172336 (-1.09%)
helped: 1551
HURT: 316
Inst-and-stalls are helped.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9681>

broadcom/compiler: handle implicit uniform loads when optimizing constant alu

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9681>

radv: add RADV_DEBUG=novrsflatshading option

To easily debug if enabling VRS for flat shading is broken.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9515>

radv: enable VRS 2x2 coarse shading for flat shading on GFX10.3+

This should safe to enable and shouldn't degrade the quality.
It decreases the number of PS invocations by 4 when used.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9515>

radv: determine if a pipeline is candidate for flat shading

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9515>

radv: gather if the FS uses perspective or linear interpolations

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9515>

radv: restore previous MRT CB_SHADER_MASK logic

It was moved to the shader info pass to compute MRTs from the shader
outputs to fix some CTS failures but this is actually unnecessary.
The CTS failures were actually CTS bugs.

This reverts 70cc80805ce ("radv: compute CB_SHADER_MASK from the
fragment shader outputs") and 76ee45d3a88 ("radv: adjust CB_SHADER_MASK
for dual-source blending in the shader info pass").

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9703>

radv: Skip 0-sized index buffers only when necessary

This workaround is only needed on Navi10 and Navi14.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9429>

ac: Add has_zero_index_buffer_bug to ac_gpu_info

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9429>

radv: Fix improper max_index_count argument for indexed draws

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/3598
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9429>

radv: initialize CMASK with correct clear codes

From AMDVLK.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9650>

radv: fix clearing CMASK layers on GFX9+

The driver was clearing all layers.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9650>

ac/surface: init CMASK slice size on GFX9+

It was only set for GFX6-8.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9650>

intel/aub_viewer: fix decoding of sampler states

There's only 1 sampler state behind
3DSTATE_SAMPLER_STATE_POINTERS[_VS|_HS|_DS|_GS|_PS] and
3DSTATE_SAMPLER_STATE_POINTERS.[PointertoVSSamplerState|PointertoPSSamplerState|PointertoGSSamplerState].

Signed-off-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9707>

intel/aub_viewer: drop bogus check

state_addr == bo.addr, bo.size==0 is handled by another check

Signed-off-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9707>

intel/aub_viewer: catch invalid sampler state pointer

Signed-off-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9707>

intel/batch_decoder: assert on invalid sampler pointer

Signed-off-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9707>

intel/batch_decoder: fix decoding of sampler states

There's only 1 sampler state behind
3DSTATE_SAMPLER_STATE_POINTERS[_VS|_HS|_DS|_GS|_PS] and
3DSTATE_SAMPLER_STATE_POINTERS.[PointertoVSSamplerState|PointertoPSSamplerState|PointertoGSSamplerState].

Signed-off-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9707>

intel/batch_decoder: drop bogus check

state_addr == bo.addr, bo.size==0 is handled by another check

Signed-off-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9707>

intel/batch_decoder: catch invalid sampler state pointer

Signed-off-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9707>

i965: fix decode_get_bo

Similar fix to the iris one.

Signed-off-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9707>

iris: fix decode_get_bo

It tries to be helpful by returning BO metadata matching exactly
the requested address, but it "forgets" to fix the remaining size.
The only caller of this function (ctx_get_bo) already deals with
raw BO metadata, so return it as such instead of fixing size too.

Signed-off-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9707>

lima: relax checks of imported BO

We don't need stride of imported buffer to be equal to calculated
stride if the buffer is linear.

Fixes #3070

Reviewed-by: Erico Nunes <nunes.erico@gmail.com>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9646>

lavapipe: enable 8/16-bit storage extensions

Acked-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9643>

gallivm: use fp16 casts lowering

Acked-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9643>

nir: lower 64-bit floats to 32-bit first.

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Acked-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9643>

nir: port fp16 casting code from dxil

This moves the dxil pass to common code and makes dxil
use the new code.

Acked-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9643>

gallivm/nir: handle bool registers.

lowering to 32-bit bools doesn't get rid of register stores,
so handle those.

Acked-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9643>

gallivm: fix non-32bit ubo loads

8/16-bit storage requires ubo loads for the smaller types,
fix the ubo loading and bounds checking.

Acked-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9643>

lima/ppir: increase usage of pipeline regs

It's possible to increase usage of ppir_pipeline_reg_fmul and
ppir_pipeline_reg_vmul by reordering arguments in some cases, so let's
do that.

Reviewed-by: Erico Nunes <nunes.erico@gmail.com>
Signed-off-by: Arno Messiaen <arnomessiaen@gmail.com>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3232>

nir: Temporarily disable optimizations for MSVC ARM64

There's currently an MSVC optimizer bug which causes a stack overflow
in the compiler if it attempts to optimize fsat.

Acked-by: Rob Clark <robdclark@chromium.org>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9700>

gallium,st: add missing viewport swizzles

Viewports must be initialized with the appropriate swizzles (for
hardware that supports this feature).

Fixes: 90fcb3fef28 (st/mesa: add NV_viewport_swizzle support)
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9732>

freedreno/a6xx: Fix typo

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9535>

freedreno: Autotune bypass vs GMEM rendering decision

In some cases, like gl_driver2, we have all the characteristics that
make our current simplistic bypass vs GMEM decision pick GMEM (ie. batch
starts with a clear, has blend enabled, has a high draw count, etc),
but each draw touches very few pixels and the per-tile state-change
overhead leaves us CP limited.  We would be better in this case picking
the bypass path.

So use feedback from # of samples-passed in previous render passes to
the same FBO to give us a bit more information to make better choices.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/2798
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9535>

freedreno/a6xx: Fix sRGB/snorm vs sysmem clear path

This shows up when, thanks to the next patch, we decide to start doing
bypass instead of GMEM for some dEQP's

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9535>

freedreno: Add gmem_reason_mask

Older gens had more restrictions about GMEM bypass which do not apply to
newer generations.  Add a bitmask so we know which bits are not a hard
requirement for using GMEM.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9535>

freedreno/batch: Add a way to clone a batch key

For autotune, the lifetime of it's hashtable keys doesn't match the
batch, so we'll need to clone the key before inserting into the
hashtable.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9535>

freedreno/batch: Export key/hash fxns

We are going to re-use these for autotune.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9535>