Stephen Warren [Tue, 9 Jan 2018 00:41:25 +0000 (17:41 -0700)]
ARM: Tegra: p2771-0000: use calculate env var feature
Request that all environment variables containing hard-coded address be
calculated at boot time instead.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Stephen Warren [Tue, 9 Jan 2018 00:41:24 +0000 (17:41 -0700)]
ARM: Tegra186: calculate load addresses at boot
In the presence of potentially fragemented memory, we cannot hard-code
addresses into environment variables such as kernel_addr_r. Instead, we
must calculate those addresses at run-time based on available memory
locations. Implement the code to perform such runtime calculation, based
on requirements described in environment variables, to allow the user
full control over the allocation.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Stephen Warren [Thu, 4 Jan 2018 18:07:14 +0000 (11:07 -0700)]
ARM: Tegra186: don't map memory not in RAM banks
Tegra186 currently restricts its DRAM usage to entries in the /memory node
in the DTB passed to it. However, the MMU configuration always maps the
entire first 2GB of RAM. This could allow the CPU to speculatively access
RAM that isn't part of the in-use banks. This patch switches to runtime
construction of the table that's used to construct the MMU translation
tables, and thus prevents access to RAM that's not part of a valid bank.
Note: This patch is intended to prevent access to RAM regions which U-Boot
does not need to access, with the primary purpose of avoiding theoretical
speculative access to physical regions for which the HW will throw errors
(e.g. carve-outs that the CPU has no permission to access at a bus level,
bad ECC pages, etc.). In particular, this patch is not deliberately
related to the speculation-related security issues that were recently
announced. The apparent similarity is a coincidence.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Stephen Warren [Wed, 3 Jan 2018 21:32:35 +0000 (14:32 -0700)]
ARM: tegra: p2771-000: increase max DRAM bank count
On this platform, there may be up to 1024 unusable chunks of memory.
Increase CONFIG_NR_DRAM_BANKS so that U-Boot can remember all the banks
required to represent such fragmented memory.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Stephen Warren [Wed, 3 Jan 2018 21:32:34 +0000 (14:32 -0700)]
ARM: Tegra186: search for best RAM bank
In the future, the list of DRAM regions passed to U-Boot in the DTB may
be quite long and fragmented. Due to this, U-Boot must search through the
regions to find the best region to relocate into, rather than relying on
the current assumption that the top of bank 0 is a reasonable relocation
target. This change implements such searching.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Stephen Warren [Fri, 5 Jan 2018 20:04:54 +0000 (13:04 -0700)]
ARM: bootm: don't assume sp is in DRAM bank 0
arch_lmb_reserve() currently assumes that the stack pointer is within DRAM
bank 0. This is not necessarily true. Enhance the code to search through
DRAM banks until the bank that does contain SP is found, and then reserve
the tail of that bank.
Fixes:
2d1916e48bd8 ("ARM: add flat device tree support")
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Stephen Warren [Wed, 3 Jan 2018 21:32:33 +0000 (14:32 -0700)]
ARM: Tegra186: mem parsing fixes from downstream
Apply a few small fixes for the DTB /memory node parsing from NVIDIA's
downstream U-Boot:
- Allow arbitrary number of DRAM banks.
- Correctly calculate the number of DRAM banks.
- Clip PCIe memory in the same way as U-Boot CPU memory use.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Stephen Warren [Wed, 3 Jan 2018 21:31:52 +0000 (14:31 -0700)]
ARM: tegra: use LINUX_KERNEL_IMAGE_HEADER
Enable CONFIG_LINUX_KERNEL_IMAGE_HEADER for all 64-bit Tegra boards.
cboot (the boot SW that runs before U-Boot) will eventually use this
information.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Stephen Warren [Wed, 3 Jan 2018 21:31:51 +0000 (14:31 -0700)]
ARMv8: add optional Linux kernel image header
Allow placing a Linux kernel image header at the start of the U-Boot
binary. This is useful since the image header reports the amount of memory
(BSS and similar) that U-Boot needs to use, but that isn't part of the
binary size. This can be used by the code that loads U-Boot into memory to
determine where to load U-Boot, based on other users of memory.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Stephen Warren [Wed, 20 Dec 2017 01:30:37 +0000 (18:30 -0700)]
ARM: tegra: use CONFIG_SYS_INIT_SP_BSS_OFFSET
Enable CONFIG_SYS_INIT_SP_BSS_OFFSET for all 64-bit Tegra boards. Place
the stack/... 512KiB from the end of the U-Boot binary. This should be
plenty to accommodate the current DTBs (max 64 KiB), early malloc region
(6KiB), stack usage, and plenty of slack, while still not placing it too
far away from the U-Boot binary.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Stephen Warren [Wed, 20 Dec 2017 01:30:36 +0000 (18:30 -0700)]
ARMv8: Allow dynamic early stack pointer
U-Boot typically uses a hard-coded value for the stack pointer before
relocation. Implement option SYS_INIT_SP_BSS_OFFSET to instead calculate
the initial SP at run-time. This is useful to avoid hard-coding addresses
into U-Boot, so that can be loaded and executed at arbitrary addresses and
thus avoid using arbitrary addresses at runtime. This option's value is
the offset added to &_bss_start in order to calculate the stack pointer.
This offset should be large enough so that the early malloc region, global
data (gd), and early stack usage do not overlap any appended DTB.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Stephen Warren [Wed, 20 Dec 2017 01:30:35 +0000 (18:30 -0700)]
ARM: tegra: remove SPL config for non-SPL SoCs
No 64-bit Tegra uses SPL. Remove various unused definitions from config
headers.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Stephen Warren [Wed, 20 Dec 2017 01:30:34 +0000 (18:30 -0700)]
ARM: tegra: don't use CONFIG_SPL_TEXT_BASE when no SPL
64-bit Tegra don't use SPL, and soon won't define CONFIG_SPL_TEXT_BASE
when building. Fix the binman .dts file so that it doesn't use undefined
values.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Tom Rini [Thu, 11 Jan 2018 19:14:19 +0000 (14:14 -0500)]
Merge git://git.denx.de/u-boot-sunxi
Jagan Teki [Wed, 10 Jan 2018 08:50:06 +0000 (14:20 +0530)]
configs: sun50i: Enable eMMC on a64-olinuxino
a64-olinuxino has 8GiB eMMC, enable it.
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Tom Rini [Thu, 11 Jan 2018 18:43:36 +0000 (13:43 -0500)]
Merge git://git.denx.de/u-boot-video
Tom Rini [Thu, 11 Jan 2018 16:18:49 +0000 (11:18 -0500)]
Merge git://git.denx.de/u-boot-fsl-qoriq
Tom Rini [Thu, 11 Jan 2018 16:18:41 +0000 (11:18 -0500)]
Merge git://git.denx.de/u-boot-socfpga
Tom Rini [Thu, 11 Jan 2018 16:18:29 +0000 (11:18 -0500)]
Merge git://git.denx.de/u-boot-usb
Hannes Schmelzer [Tue, 9 Jan 2018 18:01:36 +0000 (19:01 +0100)]
board/BuR: drop LCDC clock manipulation from board code
The clock selection is done now from the am335x-fb code, so there is no
more need doing this in the board code.
Signed-off-by: Hannes Schmelzer <oe5hpm@oevsv.at>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
Hannes Schmelzer [Tue, 9 Jan 2018 18:01:35 +0000 (19:01 +0100)]
board/BuR: provide real clock-frequency instead a divider
Actual am335x-fb implementation takes now a real clock frequency instead
a divider. So this component doesn't need to know anymore some base
frequency of the LCDC, we simply provide the pixel-clock frequency.
Signed-off-by: Hannes Schmelzer <oe5hpm@oevsv.at>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
Hannes Schmelzer [Tue, 9 Jan 2018 18:01:34 +0000 (19:01 +0100)]
am335x-fb: setup display PLL
The LCDC IP-core an be feed from several clock sources, one of those is
a dedicated DPLL for generating a dividable base-clock for this IP-core.
The TRM specifies the maximum input frequency for the LCCD with 200 MHz,
so we must not exceed this value with the PLL frequency (which can lock
much higher).
This patch tries every combination of multipliers and divisors of the
PLL and the IP-core itself for getting as near as possible the the
requested panel->pxl_clk.
Signed-off-by: Hannes Schmelzer <oe5hpm@oevsv.at>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
Hannes Schmelzer [Tue, 9 Jan 2018 18:01:33 +0000 (19:01 +0100)]
am335x-fb: cosmetic: fix coding style
Signed-off-by: Hannes Schmelzer <oe5hpm@oevsv.at>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
Hannes Schmelzer [Tue, 9 Jan 2018 18:01:32 +0000 (19:01 +0100)]
am335x-fb: cosmetic: update-copyright
Signed-off-by: Hannes Schmelzer <oe5hpm@oevsv.at>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
Hannes Schmelzer [Tue, 9 Jan 2018 18:01:31 +0000 (19:01 +0100)]
mach-omap2: add AM335x Display PLL register definition
Adds the register definition of the Display DPLL
Signed-off-by: Hannes Schmelzer <oe5hpm@oevsv.at>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
Sumit Garg [Sat, 6 Jan 2018 03:34:25 +0000 (09:04 +0530)]
ls1088ardb: Add SD Secure boot target support
Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com>
Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
[YS: run moveconfig.py -s]
Reviewed-by: York Sun <york.sun@nxp.com>
Sumit Garg [Sat, 6 Jan 2018 03:34:24 +0000 (09:04 +0530)]
armv8: ls1088a: SPL size reduction
Using changes in this patch we were able to reduce approx 8k
size of u-boot-spl.bin image. Following is breif description of
changes to reduce SPL size:
1. Changes in board/freescale/ls1088a/Makefile to remove
compilation of eth.c and cpld.c in case of SPL build.
2. Changes in board/freescale/ls1088a/ls1088a.c to keep
board_early_init_f funcations in case of SPL build.
3. Changes in ls1088a_common.h & ls1088ardb.h to remove driver
specific macros due to which static data was being compiled in
case of SPL build.
Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Sumit Garg [Sat, 6 Jan 2018 03:34:23 +0000 (09:04 +0530)]
armv8: fsl-layerscape: SPL size reduction
Compile-off mp.c and libfdt.c in case of SPL build. SPL size reduces
by approx 2k.
Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Bao Xiaowei [Tue, 19 Dec 2017 02:32:44 +0000 (10:32 +0800)]
Powerpc: T208xQDS: Modify the comment of the CONFIG_FSL_PCIE_RESET macro
Remove duplicate macro CONFIG_FSL_PCIE_RESET and update its comment.
It enables PCIe reset to fix link width 2x - 4x.
Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Alison Wang [Thu, 28 Dec 2017 05:00:55 +0000 (13:00 +0800)]
armv8: Implement workaround for Cortex-A53 erratum 855873
855873: An eviction might overtake a cache clean operation
Workaround: The erratum can be avoided by upgrading cache clean by
address operations to cache clean and invalidate operations. For
Cortex-A53 r0p3 and later release, this can be achieved by setting
CPUACTLR.ENDCCASCI to 1.
This patch is to implement the workaround for this erratum.
Signed-off-by: Alison Wang <alison.wang@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Ahmed Mansour [Fri, 15 Dec 2017 21:01:01 +0000 (16:01 -0500)]
configs: Move SYS_DPAA_QBMAN to Kconfig
The CONFIG_SYS_DPAA_QBMAN define is used by DPAA1 freescale SOCs to
add device tree fixups that allow deep sleep in Linux. The define was
placed in header files included by a number of boards, but was not
explicitly documented in any of the Kconfigs. A description was added
to the drivers/networking menuconfig and default selection for
current SOCs that have this part
Signed-off-by: Ahmed Mansour <ahmed.mansour@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Ahmed Mansour [Fri, 15 Dec 2017 21:01:00 +0000 (16:01 -0500)]
drivers/misc: Share qbman init between archs
This patch adds changes necessary to move functionality present in
PowerPC folders with ARM architectures that have DPAA1 QBMan hardware
- Create new board/freescale/common/fsl_portals.c to house shared
device tree fixups for DPAA1 devices with ARM and PowerPC cores
- Add new header file to top includes directory to allow files in
both architectures to grab the function prototypes
- Port inhibit_portals() from PowerPC to ARM. This function is used in
setup to disable interrupts on all QMan and BMan portals. It is
needed because the interrupts are enabled by default for all portals
including unused/uninitialised portals. When the kernel attempts to
go to deep sleep the unused portals prevent it from doing so
Signed-off-by: Ahmed Mansour <ahmed.mansour@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Yuantian Tang [Mon, 11 Dec 2017 05:12:09 +0000 (13:12 +0800)]
armv8: layerscape: sata: refine port register configuration
Sata registers PP2C and PP3C are used to control the configuration
of the PHY control OOB timing for the COMINIT/COMWAKE parameters
respectively. Calculate those parameters from port clock frequency.
Overwrite those registers with calculated values to get better OOB
timing.
Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Ashish Kumar [Fri, 8 Dec 2017 05:40:40 +0000 (11:10 +0530)]
armv8: ls1088 : MC alignment should always be fixed to 512MB
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Tom Rini [Wed, 10 Jan 2018 13:05:57 +0000 (08:05 -0500)]
Merge git://git.denx.de/u-boot-marvell
Tom Rini [Fri, 22 Dec 2017 03:13:22 +0000 (22:13 -0500)]
build: Drop CONFIG_SPL_BUILD guards in some cases
Given gcc-6.1 and later we can now safely have strings discarded when
the functions are unused. This lets us drop certain cases of not
building something so that we don't have the strings brought in when the
code was discarded. Simplify the code now by dropping guards we don't
need now.
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Chander Kashyap <k.chander@samsung.com>
Cc: Thomas Abraham <thomas.ab@samsung.com>
Cc: Vipin Kumar <vipin.kumar@st.com>
Cc: Wenyou Yang <wenyou.yang@microchip.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Jean-Jacques Hiblot [Thu, 21 Dec 2017 11:49:47 +0000 (12:49 +0100)]
fat write: Fixed a problem with the case of file names when writing files
commit
21a24c3bf35b ("fs/fat: fix case for FAT shortnames") made it
possible that get_name() returns file names with some upper cases.
find_directory_entry() must be updated to take this account, and use
case-insensitive functions to compare file names.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Masahiro Yamada [Thu, 21 Dec 2017 04:51:46 +0000 (13:51 +0900)]
linux/kernel.h: Add ALIGN_DOWN macro
Follow Linux commit
ed067d4a859f ("linux/kernel.h: Add ALIGN_DOWN
macro").
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Tuomas Tynkkynen [Thu, 21 Dec 2017 01:58:54 +0000 (03:58 +0200)]
sh: Drop unreferenced CONFIG_* defines
The following config symbols are only defined once and never referenced
anywhere else:
CONFIG_AP325RXA
CONFIG_AP_SH4A_4A
CONFIG_CPU_SH_TYPE_R
CONFIG_ECOVEC
CONFIG_ESPT
CONFIG_MIGO_R
CONFIG_MPR2
CONFIG_MS7720SE
CONFIG_MS7722SE
CONFIG_MS7750SE
CONFIG_R0P7734
CONFIG_R2DPLUS
CONFIG_RSK7203
CONFIG_RSK7264
CONFIG_RSK7269
CONFIG_SH7752EVB
CONFIG_SH7753EVB
CONFIG_SH7757LCR
CONFIG_SH7763RDP
CONFIG_SH7785LCR
Most of them are config symbols named after the respective boards which
seems to have been a standard practice at some point.
Signed-off-by: Tuomas Tynkkynen <tuomas@tuxera.com>
Tuomas Tynkkynen [Thu, 21 Dec 2017 01:58:53 +0000 (03:58 +0200)]
ARM: Drop unreferenced CONFIG_MACH_* defines
These macros are all defined once and never checked or used anywhere:
CONFIG_MACH_ASPENITE
CONFIG_MACH_DAVINCI_CALIMAIN
CONFIG_MACH_DOCKSTAR
CONFIG_MACH_EDMINIV2
CONFIG_MACH_GOFLEXHOME
CONFIG_MACH_GONI
CONFIG_MACH_GURUPLUG
CONFIG_MACH_KM_KIRKWOOD
CONFIG_MACH_OPENRD_BASE
CONFIG_MACH_SHEEVAPLUG
Almost all of them were only used for the mach_is_foo() logic in
arch/arm/asm/mach-types.h that were dropped in
commit
f9dadaef8b75fa ("arm: Re-sync asm/mach-types.h with
Linux Kernel v4.9")
Signed-off-by: Tuomas Tynkkynen <tuomas@tuxera.com>
Sekhar Nori [Wed, 20 Dec 2017 15:09:14 +0000 (20:39 +0530)]
configs: am57xx_evm: fix ethernet phy configuration
Configure AM57xx EVMs for the exact PHY part that is
present on the various boards. This makes U-Boot apply
configurations needed for this PHY like centering the
FLP timing.
For configurations to take effect, DM_ETH needs to be
enabled. Do that too.
Tested on BeagleBoard x15 and AM571x IDK.
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Philipp Tomsich [Wed, 20 Dec 2017 10:06:31 +0000 (11:06 +0100)]
Travis-CI: Split 't208xrdb t4qds t102*'-job into separate jobs
The 't208xrdb t4qds t102*' job is close to the time limit and
sometimes fails, so this splits it into 3 separate jobs.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Tuomas Tynkkynen [Mon, 18 Dec 2017 22:28:42 +0000 (00:28 +0200)]
PCI: Drop CONFIG_TSI108_PCI
Last user of this option went away in 2015 in commit:
d928664f41 ("powerpc: 74xx_7xx: remove 74xx_7xx cpu support")
Signed-off-by: Tuomas Tynkkynen <tuomas@tuxera.com>
Henry Zhang [Mon, 18 Dec 2017 08:13:30 +0000 (00:13 -0800)]
BCM283x ALT5 function for JTAG pins
BCM2835 ARM Peripherals doc shows gpio pins 4, 5, 6, 12 and 13 carry altenate
function, ALT5 for ARM JTAG
Signed-off-by: Henry Zhang <henryzhang62@yahoo.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Patrice Chotard [Tue, 12 Dec 2017 09:15:00 +0000 (10:15 +0100)]
configs: stm32f746-disco: enable MMC related flags
STM32F469-disco embeds an arm_pl180 mmc IP, so
enable CMD_MMC, DM_MMC and ARM_PL180_MMCI flags.
Also enables all filesystem command related flags :
_ CMD_EXT2
_ CMD_EXT4
_ CMD_FAT
_ CMD_FS_GENERIC
_ CMD_GPT
_ CMD_BOOTZ
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Patrice Chotard [Tue, 12 Dec 2017 09:14:59 +0000 (10:14 +0100)]
ARM: DTS: stm32: add MMC nodes for stm32f746-disco and stm32f769-disco
Add DT nodes to enable ARM_PL180_MMCI IP support for STM32F746
and STM32F769 discovery boards
There is a hardware issue on these boards, it misses a pullup on the GPIO line
used as card detect to allow correct SD card detection.
As workaround, cd-gpios property is not present in DT.
So SD card is always considered present in the slot.
Signed-off-by: Christophe Priouzeau <christophe.priouzeau@st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Patrice Chotard [Tue, 12 Dec 2017 08:49:45 +0000 (09:49 +0100)]
ARM: DTS: stm32: add SDIO controller support for stm32f469-disco
STM32F469 SoC uses an arm_pl180_mmci SDIO controller.
Signed-off-by: Andrea Merello <andrea.merello@gmail.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Patrice Chotard [Tue, 12 Dec 2017 08:49:44 +0000 (09:49 +0100)]
board: stm32: add stm32f469-discovery board support
This board offers :
_ STM32F469NIH6 microcontroller featuring 2 Mbytes of Flash memory
and 324 Kbytes of RAM in BGA216 package
_ On-board ST-LINK/V2-1 SWD debugger, supporting USB reenumeration capability:
_ Mbed-enabled (mbed.org)
_ USB functions: USB virtual COM port, mass storage, debug port
_ 4 inches 800x480 pixel TFT color LCD with MIPI DSI interface and capacitive
touch screen
_ SAI Audio DAC, with a stereo headphone output jack
_ 3 MEMS microphones
_ MicroSD card connector
_ I2C extension connector
_ 4Mx32bit SDRAM
_ 128-Mbit Quad-SPI NOR Flash
_ Reset and wake-up buttons
_ 4 color user LEDs
_ USB OTG FS with Micro-AB connector
_ Three power supply options:
_ Expansion connectors and Arduinoâ„¢ UNO V3 connectors
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Patrice Chotard [Tue, 12 Dec 2017 08:49:43 +0000 (09:49 +0100)]
ARM: DTS: stm32: add stm32f469-disco-u-boot dts file
_ Add gpio compatible and aliases for stm32f469
_ Add FMC sdram node
_ Add "u-boot,dm-pre-reloc" for rcc, fmc, fixed-clock, pinctrl,
pwrcfg and gpio nodes.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Patrice Chotard [Tue, 12 Dec 2017 08:49:42 +0000 (09:49 +0100)]
ARM: DTS: add STM32F469 Discovery board support
This DT file comes from kernel v4.15-rc1
stm32f469-pinctrl.dtsi header has been updated with correct
STMicroelectronics Copyright.
Remove the paragraph about writing to the Free Software
Foundation's mailing address as requested by checkpatch.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Patrice Chotard [Tue, 12 Dec 2017 08:49:41 +0000 (09:49 +0100)]
ram: stm32: add memory mapping selection support
This allows to controls the memory internal mapping at
address 0x0000 0000.
We can either map at 0x0000 0000 :
_ main flash memory
_ system flash memory
_ FMC bank1 (NOR/PSRAM 1 and 2)
_ embedded SRAM
_ FMC/SDRAM bank1
This is needed for future STM32F469-disco board
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Patrice Chotard [Tue, 12 Dec 2017 08:49:40 +0000 (09:49 +0100)]
board: stm32f429-disco: switch to DM STM32 pinctrl and gpio driver
Use available DM stm32f7_gpio.c and pinctrl_stm32.c drivers
instead of board GPIO initialization.
Remove stm32_gpio.c which is no more used and migrate
structs stm32_gpio_regs and stm32_gpio_priv into
arch-stm32f4/gpio.h to not break compilation.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Patrice Chotard [Tue, 12 Dec 2017 08:49:39 +0000 (09:49 +0100)]
board: stm32f429-disco: switch to DM STM32 clock driver
Use available DM clk_stm32f.c driver instead of dedicated
mach-stm32/stm32f4/clock.c.
Migrate periph_clock defines from stm32_periph.h directly in
CLK driver. These periph_clock defines will be removed when STMMAC,
TIMER2 and SYSCFG drivers will support DM CLK.
Enable also CLK flag.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Patrice Chotard [Tue, 12 Dec 2017 08:49:38 +0000 (09:49 +0100)]
mach-stm32: stmf32f4: timer: remove clock_get() call
In order to use common clock driver between STM32F4 and
STM32F7, remove clock_get() call
As APB_PSC is always set to 2, only case when
clock_get(CLOCK_AHB) != clock_get(CLOCK_APB1) is kept
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Patrice Chotard [Tue, 12 Dec 2017 08:49:37 +0000 (09:49 +0100)]
board: stm32f429-disco: switch to DM STM32 serial driver
Remove serial_stm32.c driver and uart init from board file,
use available DM serial_stm32x7.c driver compatible for
STM32F4/F7 and H7 SoCs.
The serial_stm32x7.c driver will be renamed later with a more
generic name as it's shared with all STM32 Socs.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Patrice Chotard [Tue, 12 Dec 2017 08:49:36 +0000 (09:49 +0100)]
configs: stm32f429-disco: enable MISC, STM32_RCC, DM_RESET and STM32_RESET
This allows to support rcc MFD driver.
By enabling all these flags, we need to increase malloc area to avoid
crash during early stage.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Patrice Chotard [Tue, 12 Dec 2017 08:49:35 +0000 (09:49 +0100)]
pinctrl: stm32: add stm32f4 pinctrl compatible strings
STM32F4 SoCs uses the same pinctrl block as found into
STM32F7 and H7 SoCs.
We can add "st,stm32f429-pinctrl" and "st,stm32f469-pinctrl"
compatible string into pinctrl_stm32.c.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Patrice Chotard [Tue, 12 Dec 2017 08:49:34 +0000 (09:49 +0100)]
board: stm32f429-discovery: switch to DM STM32 sdram driver
Use available DM stm32_sdram.c driver instead of board
SDRAM initialization.
For that, enable OF_CONTROL, OF_EMBED and STM32_SDRAM flags.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Patrice Chotard [Tue, 12 Dec 2017 08:49:33 +0000 (09:49 +0100)]
ARM: DTS: stm32: add stm32f429-disco-u-boot dts file
_ Add gpio compatible and aliases for stm32f429
_ Add FMC sdram node with associated new bindings value to
manage second bank (ie bank 1).
_ Add "u-boot,dm-pre-reloc" for rcc, fmc, fixed-clock, pinctrl,
pwrcfg and gpio nodes.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Patrice Chotard [Tue, 12 Dec 2017 08:49:32 +0000 (09:49 +0100)]
ARM: DTS: stm32: add STM32F429 SoC and its Discovery board support
All these files comes from kernel v4.15-rc1.
Update some header with correct STMicroelectronics Copyright.
Remove the paragraph about writing to the Free Software
Foundation's mailing address as requested by checkpatch.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Chris Packham [Mon, 8 Jan 2018 03:17:12 +0000 (16:17 +1300)]
ARM: mvebu: correct reference for "ethernet1" on DB-88F6820-AMC
The DB-88F6820-AMC connects ethernet@34000 and ethernet@70000 which are
labeled as eth2 and eth0 in armada-38x.dts. The ethernet@30000 (eth1) is
not used on the AMC board.
This eliminates the following bootup message
Device 'ethernet@70000': seq 0 is in use by 'ethernet@34000'
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Eddie Cai [Fri, 15 Dec 2017 00:17:13 +0000 (08:17 +0800)]
rockchip: rk3288: enable rockusb support on rk3288 based device
this patch enable rockusb support on rk3288 based device.
Signed-off-by: Eddie Cai <eddie.cai.linux@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Eddie Cai [Fri, 15 Dec 2017 00:17:12 +0000 (08:17 +0800)]
rockchip:usb: add a simple readme for rockusb
add a simple readme to introduce rockusb and tell people how to use it
Signed-off-by: Eddie Cai <eddie.cai.linux@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Eddie Cai [Fri, 15 Dec 2017 00:17:11 +0000 (08:17 +0800)]
usb: rockchip: add rockusb command
this patch add rockusb command. the usage is
rockusb <USB_controller> <devtype> <dev[:part]>
e.g. rockusb 0 mmc 0
Signed-off-by: Eddie Cai <eddie.cai.linux@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Eddie Cai [Fri, 15 Dec 2017 00:17:10 +0000 (08:17 +0800)]
usb: rockchip: add the rockusb gadget
this patch implement rockusb protocol on the device side. this is based on
USB download gadget infrastructure. the rockusb function implements the rd,
wl, rid commands. it can work with rkdeveloptool
Signed-off-by: Eddie Cai <eddie.cai.linux@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Chen-Yu Tsai [Sat, 30 Dec 2017 12:44:07 +0000 (20:44 +0800)]
musb: sunxi: Use base address from device tree
Now that the musb sunxi glue driver is completely device model / device
tree driven, we should use the base address from the device tree,
instead of hard-coding it in the source code.
Fixes:
3a61b080acee ("musb: sunxi: switch to the device model")
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Tuomas Tynkkynen [Fri, 22 Dec 2017 22:30:56 +0000 (00:30 +0200)]
ARM: sunxi: Remove left-over cd-inverted property from pcDuino3
Commit
8620f384098b ("dm: sunxi: Linksprite_pcDuino3: Correct polarity
of MMC card detect") claims that the Pcduino3 device tree had an
incorrect polarity for the card detect pin and thus changed the polarity
flag of the cd-gpios from GPIO_ACTIVE_HIGH to GPIO_ACTIVE_LOW.
Actually the DT was correct since according to the mmc binding, a
combination of GPIO_ACTIVE_HIGH + cd-inverted results in an active-low
polarity. But because the U-Boot driver lacks the code to look at the
cd-inverted property (unlike the Linux driver) it interpreted the
polarity of active-high. Thus, after that commit the DT is actually
wrong from the binding/Linux point of view.
To make both Linux and U-Boot interpret the DT in the same way, just
drop the left-over cd-inverted property. I've sent a Linux patch to
switch all sunxi DTs over to not using the cd-inverted property, so
eventually all sunxi boards in U-Boot will be consistent in not using
cd-inverted.
Signed-off-by: Tuomas Tynkkynen <tuomas@tuxera.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Maxime Ripard [Thu, 21 Dec 2017 12:55:52 +0000 (13:55 +0100)]
sunxi: maintainers: Add myself for the TBS A711
Support for that board got introduced recently without the maintainers
part. Let's fix that.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Chen-Yu Tsai [Thu, 7 Dec 2017 13:00:45 +0000 (21:00 +0800)]
sunxi: Add support for Libre Computer Board ALL-H3-CC H3 ver.
The Libre Computer Board ALL-H3-CC from Libre Technology is a Raspberry
Pi B+ form factor single board computer based on the Allwinner H3 SoC.
The board has 1GB DDR3 SDRAM, provided by 4 2Gb chips. The mounting holes
and connectors are in the exact same position as on the Raspberry Pi B+.
Raspberry Pi B+ like peripherals supported on this board include:
- Power input through micro-USB connector (without USB OTG)
- Native 100 Mbps ethernet using the internal PHY, as opposed to
USB-based on the RPi
- 4x USB 2.0 host ports, directly connected to the SoC, as opposed to
being connected through a USB 2.0 hub on the RPi
- TV and audio output on a 3.5mm TRRS jack
- HDMI output
- Micro-SD card slot
- Standard RPi B+ GPIO header, with the standard peripherals routed to
the same pins.
* 5V, 3.3V power, and ground
* I2C0 on the H3 is routed to I2C1 pins on the RPi header
* I2C1 on the H3 is routed to I2C0 pins on the RPi header
* UART1 on the H3 is routed to UART0 pins on the RPi header
* SPI0 on the H3 is routed to SPI0 pins on the RPi header,
with GPIO pin PA17 replacing the missing Chip Select 1
* I2S1 on the H3 is routed to PCM pins on the RPi header
- Additional peripherals from the H3 are available on different pins.
These include I2S0, JTAG, PWM1, SPDIF, SPI1, and UART3
In addition, there are a number of new features:
- Console UART header
- Consumer IR receiver
- Camera interface (not compatible with RPi)
- Onboard microphone
- eMMC expansion module port
- Heatsink mounting holes
This patch adds defconfig and dts files for this board. The dts file is
the same as the one submitted for inclusion in Linux, with some minor
revisions to match the dtsi file and old EMAC bindings in U-boot.
Since the OTG controller is wired to a USB host port, and the H3 has
proper USB hosts to handle host mode, the MUSB driver is not enabled.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Siarhei Siamashka [Sun, 13 Aug 2017 02:25:20 +0000 (05:25 +0300)]
arm: Exercise v7_arch_cp15_set_acr even without errata fixups
By applying this patch, we are ensuring that the code paths
responsible for applying errata workarounds are also exercised
on CPU revisions, which actually don't need these workarounds.
Only CONFIG_ARM_ERRATA_621766, CONFIG_ARM_ERRATA_454179,
CONFIG_ARM_ERRATA_725233 and CONFIG_ARM_ERRATA_430973 are
covered by this patch (Cortex-A8).
This improves code coverage when testing U-Boot builds
on newer hardware. In particular, the problematic commit
00bbe96ebabb ("arm: omap: Unify get_device_type() function")
would break both BeageBoard and BeagleBoard XM rather than
just older BeagleBoard.
As an additional bonus, we need fewer instructins and the SPL
size is reduced.
Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Tom Rini [Tue, 9 Jan 2018 18:28:51 +0000 (13:28 -0500)]
Merge git://git.denx.de/u-boot-rockchip
Miquel Raynal [Fri, 29 Dec 2017 14:31:56 +0000 (15:31 +0100)]
pinctrl: mvebu: Make drivers depend on the pinctrl framework
Armada pinctrl drivers shall not be compiled without the entire pinctrl
framework and thus lack a "depends on" condition, otherwise the driver
will simply not be probed.
Signed-off-by: Miquel Raynal <miquel.raynal@free-electrons.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Miquel Raynal [Thu, 28 Dec 2017 14:43:09 +0000 (15:43 +0100)]
ARM: mvebu: Allow MVNETA to be selected with Armada 3700 SoCs
Until now, Armada 3700 SoCs could not enable the mvneta driver, and thus
did not benefit from Ethernet support. Add ARMADA_3700 in the
"depends on" list of the MVNETA Kconfig entry.
Signed-off-by: Miquel Raynal <miquel.raynal@free-electrons.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Florian Klink [Sat, 23 Dec 2017 00:42:48 +0000 (01:42 +0100)]
arm: mvebu: ClearFog: document boot selection switches, update UART
Signed-off-by: Florian Klink <flokli@flokli.de>
Signed-off-by: Stefan Roese <sr@denx.de>
Andre Heider [Sat, 2 Dec 2017 09:46:37 +0000 (10:46 +0100)]
arm64: a37xx: use distro bootcmd
Signed-off-by: Andre Heider <a.heider@gmail.com>
Reviewed-by: Konstantin Porotchkin <kostap@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Andre Heider [Sat, 2 Dec 2017 09:46:36 +0000 (10:46 +0100)]
arm64: a37xx: defconfigs: enable CONFIG_DISTRO_DEFAULTS
Signed-off-by: Andre Heider <a.heider@gmail.com>
Reviewed-by: Konstantin Porotchkin <kostap@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Andre Heider [Sat, 2 Dec 2017 09:46:35 +0000 (10:46 +0100)]
arm64: a37xx: add distro compatible env vars
the values of dt_addr_r/kernel_addr_r/ramdisk_addr_r are taken from
the downstream 'u-boot-2017.03-armada-17.10' release.
the chosen values of scriptaddr and pxefile_addr_r are below fdt_addr_r,
in 1MB steps.
Signed-off-by: Andre Heider <a.heider@gmail.com>
Reviewed-by: Konstantin Porotchkin <kostap@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Andre Heider [Sat, 2 Dec 2017 09:46:34 +0000 (10:46 +0100)]
arm64: a37xx: use disto defaults
Signed-off-by: Andre Heider <a.heider@gmail.com>
Reviewed-by: Konstantin Porotchkin <kostap@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Konstantin Porotchkin [Thu, 30 Nov 2017 14:10:09 +0000 (16:10 +0200)]
tools: Add Marvell recovery image download script
Introduce the recovery image download script for usage with
Marvell Armada SoC families (excepting 37xx family).
Since Marvell BootROM uses a sliding window in UART buffer
for detecting escape sequence during the boot, it's easier
to interrupt the normal boot flow by sending a long stream
of chained escape sequences to the serial port instead of
periodically sending a single escape sequence as it is done
by kwboot utility.
Additional benefit of using this script is the ability to
adjust the escape sequence stream length withoiut need for
compilation.
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Igal Liberman <igall@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Tom Rini [Tue, 9 Jan 2018 13:45:02 +0000 (08:45 -0500)]
Merge git://git.denx.de/u-boot-uniphier
Masahiro Yamada [Sat, 6 Jan 2018 13:59:26 +0000 (22:59 +0900)]
ARM: uniphier: hide memory top by platform hook instead of CONFIG
I do not see a good reason to do this by a CONFIG option that affects
all SoCs. The ram_size can be adjusted by dram_init() at run-time.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Masahiro Yamada [Sat, 6 Jan 2018 13:59:25 +0000 (22:59 +0900)]
ARM: uniphier: enable CONFIG_MMC_SDHCI_SDMA for ARMv8 SoCs
I did not enable SDMA when I added sdhci-cadence support because LD20
boards are equipped with a large amount memory beyond 32 bit address
range, but SDMA does not support the 64bit address. U-Boot relocates
itself to the end of effectively available RAM. This would make the
MMC enumeration fail because the buffer for EXT_CSD allocated in the
stack would go too high, then SDMA would fail to transfer data.
Recent SDHCI-compatible controllers support ADMA, but unfortunately
U-Boot does not support ADMA.
In the previous commit, I hided the DRAM area that exceeds the 32 bit
address range. Now, I can enable CONFIG_MMC_SDHCI_SDMA.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Masahiro Yamada [Sat, 6 Jan 2018 13:59:24 +0000 (22:59 +0900)]
ARM: uniphier: do not use RAM that exceeds 32 bit address range
LD20 / PXs3 boards are equipped with a large amount of memory beyond
the 32 bit address range. U-Boot relocates itself to the end of the
available RAM.
This is a problem for DMA engines that only support 32 bit physical
address, like the SDMA of SDHCI controllers.
In fact, U-Boot does not need to run at the very end of RAM. It is
rather troublesome for drivers with DMA engines because U-Boot does
not have API like dma_set_mask(), so DMA silently fails, making the
driver debugging difficult.
Hide the memory region that exceeds the 32 bit address range. It can
be done by simply carving out gd->ram_size. It would also possible to
override get_effective_memsize() or to define CONFIG_MAX_MEM_MAPPED,
but dram_init() is a good enough place to do this job.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Tom Rini [Fri, 22 Dec 2017 17:19:22 +0000 (12:19 -0500)]
arm: socfpga: Guard commands with CONFIG_SPL_BUILD tests
In order for these commands to not be included in SPL we need to guard
compilation with CONFIG_SPL_BUILD checks. Reorganize some sections of
code slightly in order to avoid new warnings and mark the command
functions as static as they should have been before.
Cc: Marek Vasut <marex@denx.de>
Signed-off-by: Tom Rini <trini@konsulko.com>
Andrey Zhizhikin [Mon, 18 Dec 2017 13:04:57 +0000 (14:04 +0100)]
ARM: socfpga: Enable part command for socfpga platform
Enable CONFIG_CMD_PART item, as default environment requires it
and complains this command in unknown.
Signed-off-by: Andrey Zhizhikin <andrey.z@gmail.com>
Ran Wang [Wed, 20 Dec 2017 02:34:20 +0000 (10:34 +0800)]
arm64: layerscape: Move CONFIG_HAS_FSL_DR_USB to Kconfig
Rename to USB_EHCI_FSL, use Kconfig to select ehci accordingly.
Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
Ran Wang [Wed, 20 Dec 2017 02:34:19 +0000 (10:34 +0800)]
usb: ehci: fsl: Fix some compile warnings.
When enable CONFIG_HAS_FSL_DR_USB, we might encounter below compile
warning, apply this patch can fix it:
drivers/usb/host/ehci-fsl.c:109:4: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]
((u32)hccr + HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
^
drivers/usb/host/ehci-fsl.c:108:9: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
hcor = (struct ehci_hcor *)
^
drivers/usb/host/ehci-fsl.c:115:8: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]
(u32)hccr, (u32)hcor,
^
include/log.h:131:26: note: in definition of macro 'debug_cond'
printf(pr_fmt(fmt), ##args); \
^~~~
drivers/usb/host/ehci-fsl.c:114:2: note: in expansion of macro 'debug'
debug("ehci-fsl: init hccr %x and hcor %x hc_length %d\n",
^~~~~
drivers/usb/host/ehci-fsl.c:115:19: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]
(u32)hccr, (u32)hcor,
^
include/log.h:131:26: note: in definition of macro 'debug_cond'
printf(pr_fmt(fmt), ##args); \
^~~~
drivers/usb/host/ehci-fsl.c:114:2: note: in expansion of macro 'debug'
debug("ehci-fsl: init hccr %x and hcor %x hc_length %d\n",
^~~~~
Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
Ran Wang [Wed, 20 Dec 2017 02:34:18 +0000 (10:34 +0800)]
armv8: ls1012a: Add USB 2.0 controller phy type for ls1012aqds board
Without this propertiy, U-Boot will pop warning of 'USB phy type not
defined' when select CONFIG_HAS_FSL_DR_USB.
Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
Elaine Zhang [Tue, 19 Dec 2017 10:22:38 +0000 (18:22 +0800)]
rockchip: clk: bind reset driver
Bind rockchip reset to clock-controller with rockchip_reset_bind().
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Elaine Zhang [Tue, 19 Dec 2017 10:22:37 +0000 (18:22 +0800)]
rockchip: reset: support a (common) rockchip reset drivers
Create driver to support the soft reset (i.e. peripheral)
of all Rockchip SoCs.
Example of usage:
i2c driver:
ret = reset_get_by_name(dev, "i2c", &reset_ctl);
if (ret) {
error("reset_get_by_name() failed: %d\n", ret);
}
reset_assert(&reset_ctl);
udelay(50);
reset_deassert(&reset_ctl);
i2c dts node:
resets = <&cru SRST_P_I2C1>, <&cru SRST_I2C1>;
reset-names = "p_i2c", "i2c";
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
[Fixed commit tag:]
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Tom Rini [Tue, 9 Jan 2018 01:25:29 +0000 (20:25 -0500)]
Prepare v2018.01
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Mon, 8 Jan 2018 17:51:47 +0000 (12:51 -0500)]
Merge git://git.denx.de/u-boot-imx
Jagan Teki [Fri, 5 Jan 2018 07:04:23 +0000 (12:34 +0530)]
mtd: nand: mxs_nand_spl: Remove nand size print
It is not much needed to print nand size in SPL during nand boot,
and most of nand spl drivers doesn't print the same.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Jagan Teki [Fri, 5 Jan 2018 07:04:21 +0000 (12:34 +0530)]
board: engicam: Fix to remove legacy board/icorem6_rqs
board/icorem6_rqs/ is forgot to remove while moving
common board files together in
(sha1:
52aaddd6f415397bb2eae0d68a8cc1c5c4a98bb3)
"i..MX6: engicam: Add imx6q/imx6ul boards for existing boards"
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Stefan Agner [Fri, 5 Jan 2018 14:08:19 +0000 (15:08 +0100)]
imx: initialize and use generic timer on i.MX 6UL/ULL
The i.MX 6UL/ULL feature a Cortex-A7 CPU which suppor the ARM
generic timer. This change makes use of the ARM generic timer in
U-Boot.
This is crucial to make the ARM generic timers usable in Linux since
timer_init() initalizes the system counter module, which is necessary
to use the generic timers CP15 registers.
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Stefan Agner [Fri, 5 Jan 2018 14:08:18 +0000 (15:08 +0100)]
imx: introduce CONFIG_GPT_TIMER
Introduce a new config symbol to select the i.MX
General Purpose Timer (GPT).
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Stefan Agner [Fri, 5 Jan 2018 14:08:17 +0000 (15:08 +0100)]
imx: move CONFIG_SYSCOUNTER_TIMER to Kconfig
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Tom Rini [Mon, 8 Jan 2018 13:26:46 +0000 (08:26 -0500)]
Merge git://git.denx.de/u-boot-x86
Clemens Gruber [Sun, 7 Jan 2018 19:26:29 +0000 (20:26 +0100)]
crypto/fsl: fix BLOB encapsulation and decapsulation
The blob_encap and blob_decap functions were not flushing the dcache
before passing data to CAAM/DMA and not invalidating the dcache when
getting data back.
Therefore, blob encapsulation and decapsulation failed with errors like
the following due to data cache incoherency:
"
40000006: DECO: desc idx 0: Invalid KEY command"
To ensure coherency, we require the key_mod, src and dst buffers to be
aligned to the cache line size and flush/invalidate the memory regions.
The same requirements apply to the job descriptor.
Tested on an i.MX6Q board.
Reviewed-by: Sumit Garg <sumit.garg@nxp.com>
Signed-off-by: Clemens Gruber <clemens.gruber@pqgruber.com>
Andy Shevchenko [Thu, 4 Jan 2018 16:40:13 +0000 (18:40 +0200)]
x86: tangier: Add Bluetooth to ACPI table
As defined on reference board followed by Intel Edison a Bluetooth
device is attached to HSU0, i.e. PCI 0000:04.1.
Describe it in ACPI accordingly.
Note, we use BCM2E95 ID here as one most suitable for such device based
on the description in commit message of commit
89ab37b489d1
("Bluetooth: hci_bcm: Add support for BCM2E95 and BCM2E96")
in the Linux kernel source tree.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>