Craig Topper [Mon, 8 Jun 2020 01:55:33 +0000 (18:55 -0700)]
[X86] Improve (vzmovl (insert_subvector)) combine to handle a bitcast between the vzmovl and insert
This combine tries shrink a vzmovl if its input is an
insert_subvector. This patch improves it to turn
(vzmovl (bitcast (insert_subvector))) into
(insert_subvector (vzmovl (bitcast))) potentially allowing the
bitcast to be folded with a load.
Craig Topper [Mon, 8 Jun 2020 01:28:31 +0000 (18:28 -0700)]
[X86] Teach combineCVTP2I_CVTTP2I to handle STRICT_CVTTP2SI/STRICT_CVTTP2UI
Allows us to shrink 128-bit simple load to enable folding for
v2f32->v2i64 vcvttps2qq/vcvttps2uqq.
QingShan Zhang [Mon, 8 Jun 2020 01:31:07 +0000 (01:31 +0000)]
[Power9] Add addi post-ra scheduling heuristic
The instruction addi is usually used to post increase the loop indvar, which looks like this:
label_X:
load x, base(i)
...
y = op x
...
i = addi i, 1
goto label_X
However, for PowerPC, if there are too many vsx instructions that between y = op x and i = addi i, 1,
it will use all the hw resource that block the execution of i = addi, i, 1, which result in the stall
of the load instruction in next iteration. So, a heuristic is added to move the addi as early as possible
to have the load hide the latency of vsx instructions, if other heuristic didn't apply to avoid the starve.
Reviewed By: jji
Differential Revision: https://reviews.llvm.org/D80269
Jun Ma [Fri, 5 Jun 2020 01:40:30 +0000 (09:40 +0800)]
[clang] Implement VectorType logic not operator.
Differential Revision: https://reviews.llvm.org/D80979
Craig Topper [Sun, 7 Jun 2020 21:44:17 +0000 (14:44 -0700)]
[X86] Don't scalarize v2f32->v2i64 strict_fp_to_sint/uint with avx512dq and not avx512vl.
We can pad the v2f32 with 0s up to v8f32 and use a v8f32->v8i64
operation. This is what we end up with on non-strict nodes except
we don't pad with 0s since we don't care about exceptions.
Benjamin Kramer [Sun, 7 Jun 2020 20:36:10 +0000 (22:36 +0200)]
SmallPtrSet::find -> SmallPtrSet::count
The latter is more readable and more efficient. While there clean up
some double lookups. NFCI.
Fangrui Song [Sun, 7 Jun 2020 20:35:01 +0000 (13:35 -0700)]
Reland D80966 [codeview] Put !heapallocsite on calls to operator new
With a change to use `CGM.getCodeGenOpts().getDebugInfo() != codegenoptions::NoDebugInfo`
instead of `getDebugInfo()`,
to fix `Profile-<arch> :: instrprof-gcov-multithread_fork.test`
See CodeGenModule::CodeGenModule, `EmitGcovArcs || EmitGcovNotes` can
set `clang::CodeGen::CodeGenModule::DebugInfo`.
---
Clang marks calls to operator new as heap allocation sites, but the
operator declared at global scope returns a void pointer. There is no
explicit cast in the code, so the compiler has to write down the
allocated type itself.
Also generalize a cast to use CallBase, so that we mark heap alloc sites
when exceptions are enabled.
Differential Revision: https://reviews.llvm.org/D80966
Simon Pilgrim [Sun, 7 Jun 2020 20:08:35 +0000 (21:08 +0100)]
[X86][AVX2] combineSetCCMOVMSK - handle all_of patterns for PMOVMSKB(PACKSSBW(LO(X), HI(X)))
In the sign splat case, we can fold PMOVMSKB(PACKSSBW(LO(X), HI(X))) -> PMOVMSKB(BITCAST_v32i8(X)) without introducing a signmask + comparison (which unlike for any_of won't fold into a single TEST).
Mehdi Amini [Sun, 7 Jun 2020 19:32:36 +0000 (19:32 +0000)]
Revert "[MLIR] Lower shape.num_elements -> shape.reduce."
This reverts commit
e80617df894b00d12d5afb9d819e6ff9141cc29e.
This broke the build with `-DBUILD_SHARED_LIBS=ON`
Fangrui Song [Sun, 7 Jun 2020 19:27:11 +0000 (12:27 -0700)]
[Driver] Omit -mthread-model posix which is the CC1 default
Fangrui Song [Sun, 7 Jun 2020 18:25:40 +0000 (11:25 -0700)]
[gcov] Support .gcno/.gcda in gcov 8, 9 or 10 compatible formats
Benjamin Kramer [Sun, 7 Jun 2020 18:12:52 +0000 (20:12 +0200)]
[Driver] Simplify code. NFCI.
AK [Sun, 7 Jun 2020 17:14:22 +0000 (10:14 -0700)]
Add cl::ZeroOrMore to get around build system issues
It is quite common to get multiple instances of optimization flags while building.
The following optimizations does not have cl::ZeroOrMore which causes errors during the build.
Reviewers: alexbdv,spop
Differential Revision: https://reviews.llvm.org/D81187
Kang Zhang [Sun, 7 Jun 2020 16:35:32 +0000 (16:35 +0000)]
[NFC][PowerPC] Add a new case to test ctrloop for fp128
Fangrui Song [Sun, 7 Jun 2020 16:31:48 +0000 (09:31 -0700)]
[gcov] Fix instrprof-gcov-__gcov_flush-terminate.test
Simon Pilgrim [Sun, 7 Jun 2020 16:25:35 +0000 (17:25 +0100)]
CFG.h - reduce includes to forward declarations. NFC.
Benjamin Kramer [Sun, 7 Jun 2020 16:17:21 +0000 (18:17 +0200)]
Unbreak the build
Benjamin Kramer [Sun, 7 Jun 2020 16:06:03 +0000 (18:06 +0200)]
Try to make msvc crash less
llvm-project\clang\lib\Driver\Types.cpp(44): fatal error C1001: An internal error has occurred in the compiler.
(compiler file 'msc1.cpp', line 1518)
Simon Pilgrim [Sun, 7 Jun 2020 15:56:09 +0000 (16:56 +0100)]
DomTreeUpdater.h - refine includes. NFC.
We don't need any of its defs or many of its includes inside PostDominators.h - so split it and reduce the frontend load.
Fangrui Song [Sun, 7 Jun 2020 15:40:03 +0000 (08:40 -0700)]
[gcov][test] Delete UNSUPPORTED: host-byteorder-big-endian from test/profile tests
It seems that after
dc52ce424bb1818b3270e20927447bf17e062e66, all big-endian problems have been fixed.
01899bb4e41178af6f4cf7b32833e661fe1e3322 seems to have fixed XFAIL: * of
profile/instrprof-gcov-__gcov_flush-terminate.test
This essentially reverts commit
5a9b792d7251e19f69f96c9619cde49497c79a07 and
93d5ae3af18f3e5d4232510274d59c1b4e5b8e77.
Benjamin Kramer [Sun, 7 Jun 2020 15:41:02 +0000 (17:41 +0200)]
Put back definitions. We're still not C++17 :/
Benjamin Kramer [Sun, 7 Jun 2020 15:21:29 +0000 (17:21 +0200)]
Put compilation phases from Types.def into a bit set
This avoids a global constructor and is a bit more efficient for
"contained" queries. No functionality change intended.
Benjamin Kramer [Sun, 7 Jun 2020 15:15:31 +0000 (17:15 +0200)]
Remove global std::string. StringRef is sufficient. NFC.
Shawn Landden [Sun, 7 Jun 2020 14:27:26 +0000 (18:27 +0400)]
[AArch64] add test for large popcount; NFC
Sanjay Patel [Sun, 7 Jun 2020 15:13:50 +0000 (11:13 -0400)]
[Docs] fix typos for llvm-mca; NFC
Simon Pilgrim [Sun, 7 Jun 2020 14:59:12 +0000 (15:59 +0100)]
[X86][SSE] combineSetCCMOVMSK - add initial support for allof patterns.
Handle MOVMSK 'allof' comparisons (X86ISD::SUB X, AllBitsMask) as well as 'anyof' patterns.
This allows us to handle these patterns in the MOVMSK(BITCAST(X)) pattern to fix PR37087.
Fangrui Song [Sun, 7 Jun 2020 15:05:44 +0000 (08:05 -0700)]
[llvm-cov] Fix gcov version detection on big-endian
Xing GUO [Sun, 7 Jun 2020 14:55:07 +0000 (22:55 +0800)]
[ObjectYAML][test] Address comments in D80203
This patch addresses comments in [D80203](https://reviews.llvm.org/D80203?vs=on&id=266415&whitespace=ignore-most#2062287)
Reviewed By: jhenderson
Differential Revision: https://reviews.llvm.org/D80862
Xing GUO [Sun, 7 Jun 2020 14:43:37 +0000 (22:43 +0800)]
[DWARFYAML][debug_ranges] Fix inappropriate assertion. NFC.
Alexander Belyaev [Sun, 7 Jun 2020 14:25:11 +0000 (16:25 +0200)]
[MLIR] Lower shape.num_elements -> shape.reduce.
Differential Revision: https://reviews.llvm.org/D81279
Alexander Belyaev [Fri, 5 Jun 2020 15:01:43 +0000 (17:01 +0200)]
[mlir] Add verifier for `shape.yield`.
Differential Revision: https://reviews.llvm.org/D81262
Sanjay Patel [Sun, 7 Jun 2020 13:03:45 +0000 (09:03 -0400)]
[InstCombine] fold mask op into casted shift (PR46013)
https://rise4fun.com/Alive/Qply8
Pre: C2 == (-1 u>> zext(C1))
%a = ashr %x, C1
%s = sext %a to i16
%r = and i16 %s, C2
=>
%s2 = sext %x to i16
%r = lshr i16 %s2, zext(C1)
https://bugs.llvm.org/show_bug.cgi?id=46013
Sanjay Patel [Sat, 6 Jun 2020 14:53:45 +0000 (10:53 -0400)]
[InstCombine] add tests for bitmask of casted shift; NFC (PR46013)
Ties Stuij [Sun, 7 Jun 2020 12:45:16 +0000 (13:45 +0100)]
[clang][BFloat] Add reinterpret cast intrinsics
Summary:
This patch is part of a series implementing the Bfloat16 extension of the
Armv8.6-a architecture, as detailed here:
https://community.arm.com/developer/ip-products/processors/b/processors-ip-blog/posts/arm-architecture-developments-armv8-6-a
The bfloat type, and its properties is specified in the Arm C language
extension specification:
https://developer.arm.com/docs/ihi0055/d/procedure-call-standard-for-the-arm-64-bit-architecture
Subscribers: kristof.beyls, ilya-biryukov, MaskRay, jkorous, arphaman, kadircet, usaxena95, cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D79869
The following people contributed to this patch:
- Luke Cheeseman
- Alexandros Lamprineas
- Luke Geeson
- Ties Stuij
Simon Pilgrim [Sun, 7 Jun 2020 12:51:48 +0000 (13:51 +0100)]
AlignmentFromAssumptions.h - reduce includes to forward declarations. NFC.
Simon Pilgrim [Sun, 7 Jun 2020 12:16:31 +0000 (13:16 +0100)]
MemorySSAUpdater.h - reduce includes to forward declarations. NFC.
Simon Pilgrim [Sun, 7 Jun 2020 11:47:37 +0000 (12:47 +0100)]
DependenceAnalysis.h - reduce AliasAnalysis.h include to forward declaration. NFC.
This requires the replacement of legacy class AliasAnalysis usages with AAResults (which it typedefs to anyhow)
Simon Pilgrim [Sun, 7 Jun 2020 11:10:50 +0000 (12:10 +0100)]
MustExecute.h - remove unnecessary Instruction.h include. NFC.
We already have the Instruction forward declaration.
Simon Pilgrim [Sun, 7 Jun 2020 10:48:46 +0000 (11:48 +0100)]
ObjCARCAnalysisUtils.h - remove unused LLVMContext.h include. NFC.
Simon Pilgrim [Sun, 7 Jun 2020 10:44:27 +0000 (11:44 +0100)]
OrderedInstructions.h - reduce includes to forward declarations. NFC.
Simon Pilgrim [Sun, 7 Jun 2020 10:43:41 +0000 (11:43 +0100)]
[X86][SSE] Extend ICMP(MOVMSK(BITCAST(X))) tests to allof patterns as well as the existing noneof/anyof patterns.
Simon Pilgrim [Sun, 7 Jun 2020 10:19:45 +0000 (11:19 +0100)]
[X86][SSE] Attempt to widen MOVMSK vector input if the signbits are splatted.
As shown on PR37087, if we have a MOVMSK(BICAST(X)) from a wider vector, then by using MOVMSK from the wider type (32/64-bit elements) we can improve the chances of further combines with SimplifyDemandedBits/Elts and on some targets (skylake) can be more efficient.
Florian Hahn [Sun, 7 Jun 2020 10:11:27 +0000 (11:11 +0100)]
[Matrix] Implement * binary operator for MatrixType.
This patch implements the * binary operator for values of
MatrixType. It adds support for matrix * matrix, scalar * matrix and
matrix * scalar.
For the matrix, matrix case, the number of columns of the first operand
must match the number of rows of the second. For the scalar,matrix variants,
the element type of the matrix must match the scalar type.
Reviewers: rjmccall, anemet, Bigcheese, rsmith, martong
Reviewed By: rjmccall
Differential Revision: https://reviews.llvm.org/D76794
Jaroslav Sevcik [Mon, 1 Jun 2020 20:43:18 +0000 (20:43 +0000)]
Support build-ids of other sizes than 16 in UUID::SetFromStringRef
SBTarget::AddModule currently handles the UUID parameter in a very
weird way: UUIDs with more than 16 bytes are trimmed to 16 bytes. On
the other hand, shorter-than-16-bytes UUIDs are completely ignored. In
this patch, we change the parsing code to handle UUIDs of arbitrary
size.
To support arbitrary size UUIDs in SBTarget::AddModule, this patch
changes UUID::SetFromStringRef to parse UUIDs of arbitrary length. We
subtly change the semantics of SetFromStringRef - SetFromStringRef now
only succeeds if the entire input is consumed to prevent some
prefix-parsing confusion. This is up for discussion, but I believe
this is more consistent - we always return false for invalid UUIDs
rather than sometimes truncating to a valid prefix. Also, all the
call-sites except the API and interpreter seem to expect to consume
the entire input.
This also adds tests for adding existing modules 4-, 16-, and 20-byte
build-ids. Finally, we took the liberty of testing the minidump
scenario we care about - removing placeholder module from minidump and
replacing it with the real module.
Reviewed By: labath, friss
Differential Revision: https://reviews.llvm.org/D80755
Simon Pilgrim [Sun, 7 Jun 2020 09:48:11 +0000 (10:48 +0100)]
[X86][SSE] Add MOVMSK tests where we're using a more narrow vector elements than necessary
First step towards fixing PR37087
Xing GUO [Sun, 7 Jun 2020 07:47:14 +0000 (15:47 +0800)]
[ObjectYAML][DWARF] Support emitting .debug_ranges section in ELFYAML.
This patch enables yaml2elf to emit the .debug_ranges section.
Reviewed By: jhenderson
Differential Revision: https://reviews.llvm.org/D81217
Fangrui Song [Sun, 7 Jun 2020 06:11:31 +0000 (23:11 -0700)]
[gcov] Improve tests and lower the minimum supported version to gcov 3.4
global-ctor.ll no longer checks what it intended to check
(@_GLOBAL__sub_I_global-ctor.ll needs a !dbg to work).
Rewrite it.
gcov 3.4 and gcov 4.2 use the same format, thus we can lower the version
requirement to 3.4
Fangrui Song [Sun, 7 Jun 2020 03:36:46 +0000 (20:36 -0700)]
[gcov] Delete unneeded code
James Y Knight [Tue, 12 May 2020 14:36:34 +0000 (10:36 -0400)]
Simplify MachineVerifier's block-successor verification.
There's two properties we want to verify:
1. That the successors returned by analyzeBranch are in the CFG
successor list, and
2. That there are no extraneous successors are in the CFG successor
list.
The previous implementation mostly accomplished this, but in a very
convoluted manner.
Differential Revision: https://reviews.llvm.org/D79793
James Y Knight [Wed, 19 Feb 2020 15:41:28 +0000 (10:41 -0500)]
MachineBasicBlock::updateTerminator now requires an explicit layout successor.
Previously, it tried to infer the correct destination block from the
successor list, but this is a rather tricky propspect, given the
existence of successors that occur mid-block, such as invoke, and
potentially in the future, callbr/INLINEASM_BR. (INLINEASM_BR, in
particular would be problematic, because its successor blocks are not
distinct from "normal" successors, as EHPads are.)
Instead, require the caller to pass in the expected fallthrough
successor explicitly. In most callers, the correct block is
immediately clear. But, in MachineBlockPlacement, we do need to record
the original ordering, before starting to reorder blocks.
Unfortunately, the goal of decoupling the behavior of end-of-block
jumps from the successor list has not been fully accomplished in this
patch, as there is currently no other way to determine whether a block
is intended to fall-through, or end as unreachable. Further work is
needed there.
Differential Revision: https://reviews.llvm.org/D79605
Ben Shi [Sun, 7 Jun 2020 01:40:59 +0000 (18:40 -0700)]
[RISCV] Fix a typo in RISCVISelLowering.cpp
The 9th parameter of "static bool CC_RISCV(...)" is isFixed, not isRet.
Reviewed By: MaskRay
Differential Revision: https://reviews.llvm.org/D81333
Mike Edwards [Sat, 6 Jun 2020 23:53:58 +0000 (16:53 -0700)]
[LIT] NFC adding max-failures option to lit documentation.
Differential Revision: https://reviews.llvm.org/D81337
Craig Topper [Sun, 7 Jun 2020 00:24:06 +0000 (17:24 -0700)]
[X86] Correct some isel patterns for v1i1 KNOT/KANDN/KXNOR.
The KNOT pattern was missing. The others were
looking for a v1i1 -1 instead of a vector all ones.
Douglas Yung [Sat, 6 Jun 2020 23:30:46 +0000 (23:30 +0000)]
Revert "[codeview] Put !heapallocsite on calls to operator new"
This reverts commit
672ed5386024ba5cee53e19d637b7920a4889837.
This commit is hitting an assertion failure across multiple bots in the test:
Profile-<arch> :: instrprof-gcov-multithread_fork.test
Failing bots include:
http://lab.llvm.org:8011/builders/llvm-avr-linux/builds/2205
http://lab.llvm.org:8011/builders/clang-cmake-aarch64-lld/builds/8967
http://lab.llvm.org:8011/builders/clang-cmake-armv7-full/builds/10789
http://lab.llvm.org:8011/builders/sanitizer-x86_64-linux/builds/27750
http://lab.llvm.org:8011/builders/sanitizer-ppc64be-linux/builds/16751
Jan Kratochvil [Sat, 6 Jun 2020 21:31:30 +0000 (23:31 +0200)]
[lldb] [nfc] Fix comment in testcase DW_TAG_variable-DW_AT_const_value.s
Fangrui Song [Sat, 6 Jun 2020 18:58:26 +0000 (11:58 -0700)]
[gcov] Delete `XFAIL: host-byteorder-big-endian` for test/Transforms/GCOVProfiling/{exit-block.ll,function-numbering.ll}
LLVM GN Syncbot [Sat, 6 Jun 2020 18:22:19 +0000 (18:22 +0000)]
[gn build] Port
8422bc9efcb
Yaxun (Sam) Liu [Fri, 5 Jun 2020 20:49:38 +0000 (16:49 -0400)]
recommit "[HIP] Add default header and include path"
recommit
11d06b9511bd25aabbfad10dff548b0ce29135a5 with
fix for lit tests.
Fangrui Song [Sat, 6 Jun 2020 18:01:47 +0000 (11:01 -0700)]
[gcov] Support big-endian .gcno and simplify version handling in .gcda
Jonas Paulsson [Tue, 21 Apr 2020 16:16:29 +0000 (18:16 +0200)]
[SystemZ] Implement -fstack-clash-protection
Probing of allocated stack space is now done when this option is passed. The
purpose is to protect against the stack clash attack (see
https://www.qualys.com/2017/06/19/stack-clash/stack-clash.txt).
Review: Ulrich Weigand
Differential Revision: https://reviews.llvm.org/D78717
Jacques Pienaar [Sat, 6 Jun 2020 16:31:51 +0000 (09:31 -0700)]
[mlir] Change to re-enable cuda-runner tests
mlir-cuda-runner tests were failing post
https://reviews.llvm.org/D80676, small change to get those passing
again. More cleanup may be needed post.
Matt Arsenault [Sat, 6 Jun 2020 14:31:08 +0000 (10:31 -0400)]
AMDGPU/GlobalISel: Fix test failure in release build
The annoying behavior where the output is different due to the
legality check struck again, plus the subtarget predicate wasn't
really correctly set for DS FP atomics.
Some of the FP min/max instructions seem to be in the gfx6/gfx7
manuals, but IIRC this might have been one of the cases where the
manual got ahead of the actual hardware support, but I've left these
as-is for now since the assembler tests seem to expect them.
Simon Pilgrim [Sat, 6 Jun 2020 14:48:17 +0000 (15:48 +0100)]
EHPersonalities.h - reduce Triple.h include to forward declaration. NFC.
Move implicit include dependencies down to source files.
Sanjay Patel [Fri, 5 Jun 2020 21:16:29 +0000 (17:16 -0400)]
[DAGCombiner] clean-up FMA+FMUL folds; NFC
D80801 suggests some readability improvements before mocing this block.
Simon Pilgrim [Sat, 6 Jun 2020 14:18:25 +0000 (15:18 +0100)]
CFG.h - add missing GraphTraits.h include. NFC.
MSVC doesn't care that this isn't declared for default template args but gcc (sometimes) does.
Simon Pilgrim [Sat, 6 Jun 2020 14:06:03 +0000 (15:06 +0100)]
CFG.h - reduce includes to forward declarations. NFC.
Remove unnecessary includes from CFG.cpp.
Fix implicit include dependency in X86WinEHState.cpp.
Matt Arsenault [Sun, 24 May 2020 15:12:11 +0000 (11:12 -0400)]
AMDGPU/GlobalISel: Start rewriting load/store legality rules
The current set is an incomprehensible mess riddled with ordering
hacks for various limitations in the legalizer at the time of writing,
many of which have been fixed. This takes a very small step in
correcting this.
The core first change is to start checking for fully legal cases
first, rather than trying to figure out all of the actions that could
need to be performed. It's recommended to check the legal cases first
for faster legality checks in the common case. This still has a table
listing some common cases, but it needs measuring whether this really
helps or not.
More significantly, stop trying to allow any arbitrary type with a
legal bitwidth as a legal memory type, and start using the bitcast
legalize action for them. Allowing loads of these weird vector types
produced new burdens we don't need for handling all of the
legalization artifacts. Unlike the SelectionDAG handling, this is
still not casting 64 or 16-bit element vectors to 32-bit
vectors. These cases should still be handled by increasing/decreasing
the number of 16-bit elements. This is primarily to fix 8-bit element
vectors.
Another change is to stop trying to handle the load-widening based on
a higher alignment. We should still do this, but the way it was
handled wasn't really correct. We really need to modify the MMO's size
at the same time, and not just increase the result type. The
LegalizerHelper does not do this, and I think this would really
require a separate WidenMemory action (or to add a memory action
payload to the LegalizeMutation). These will now fail to legalize.
The structure of the legalizer rules makes writing concise rules here
difficult. It would be easier if the same function could answer the
query the query, and report the action to perform at the same
time. Instead these two are split into distinct predicate and action
functions. This is mostly tolerable for other cases, but the
load/store rules get pretty complicated so it's difficult to keep two
versions of these functions in sync.
dfukalov [Thu, 4 Jun 2020 23:18:18 +0000 (02:18 +0300)]
[AMDGPU] Increase max iterations count to analyze complete unroll
Summary: In some cases inner loops may not get boosts so try to analyze them deeper.
Reviewers: rampitec, mzolotukhin
Reviewed By: rampitec
Subscribers: arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, hiraditya, zzheng, kerbowa, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D81204
Simon Pilgrim [Sat, 6 Jun 2020 13:23:08 +0000 (14:23 +0100)]
LoopPassManager.h - add missing MemorySSA.h include
Fix buildbot failure due to rG5006e551d310 - oddly I can't reproduce this locally on my msvc expensive checks build.
Simon Pilgrim [Sat, 6 Jun 2020 13:06:25 +0000 (14:06 +0100)]
LoopAnalysisManager.h - reduce includes to forward declarations. NFC.
Move implicit include dependencies down to header/source files.
Paul Walker [Fri, 5 Jun 2020 11:49:44 +0000 (11:49 +0000)]
[SVE ACLE] Remove redundant bool_t typedef.
Subscribers: tschuett, cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D81252
Simon Pilgrim [Sat, 6 Jun 2020 12:30:00 +0000 (13:30 +0100)]
LegacyDivergenceAnalysis.h - reduce DivergenceAnalysis.h include to forward declaration. NFC.
Move implicit include dependencies down to source file.
Simon Pilgrim [Sat, 6 Jun 2020 11:59:22 +0000 (12:59 +0100)]
LoopInfoImpl.h - remove unused SetVector.h include. NFC.
Roman Lebedev [Sat, 6 Jun 2020 09:59:58 +0000 (12:59 +0300)]
[SCEV] ScalarEvolution::createSCEV(): Instruction::Or: drop bogus no-wrap flag detection
Summary:
That's just really wrong. While sure, if LHS is AddRec, and we could
propagate it's no-wrap flags, that doesn't make, because as long as
the operands of `or` had no common bits set, then the `add`
of these operands will never overflow: http://volta.cs.utah.edu:8080/z/gmt7Sy
IOW we need no propagation/detection, we are free to just set NUW+NSW.
But as rG39e3683534c83573da5c8b70c8adfb43948f601f shows,
even when the old code failed to "deduce" flags,
we'd eventually re-deduce them somewhere, later.
So let's just set them.
Reviewers: mkazantsev, reames, sanjoy, efriedma
Reviewed By: efriedma
Subscribers: efriedma, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D81246
Roman Lebedev [Sat, 6 Jun 2020 09:59:44 +0000 (12:59 +0300)]
[SCEV] ScalarEvolution::createSCEV(): clarify no-wrap flag propagation for shift by bitwidth-1
Summary:
There was this comment here previously:
```
- // It is currently not resolved how to interpret NSW for left
- // shift by BitWidth - 1, so we avoid applying flags in that
- // case. Remove this check (or this comment) once the situation
- // is resolved. See
- // http://lists.llvm.org/pipermail/llvm-dev/2015-April/084195.html
- // and http://reviews.llvm.org/D8890 .
```
But langref was fixed in rL286785, and the behavior is pretty obvious:
http://volta.cs.utah.edu:8080/z/MM4WZP
^ nuw can always be propagated. nsw can be propagated if
either nuw is specified, or the shift is by *less* than bitwidth-1.
This mimics similar D81189 Reassociate change, alive2 is happy about that one.
I'm not sure `NUW` isn't being printed, but that seems unrelated.
Reviewers: mkazantsev, reames, sanjoy, nlopes, craig.topper, efriedma
Reviewed By: efriedma
Subscribers: hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D81243
Nikita Popov [Sat, 6 Jun 2020 09:49:20 +0000 (11:49 +0200)]
[NewGVN] Remove alignment from LoadExpression (NFC)
The alignment is not actually used.
Nikita Popov [Sat, 6 Jun 2020 09:15:45 +0000 (11:15 +0200)]
[InstCombine] Remove unnecessary MaybeAlign use (NFC)
Alloca align is required now.
Marco Elver [Sat, 6 Jun 2020 09:18:46 +0000 (11:18 +0200)]
[ASan][Test] Fix globals test on 32-bit architectures
Buildbot reports failures on e.g. armv7 and thumbv7. Fix the test by
expecting either i32 or i64 for the size-argument.
Tres Popp [Sat, 6 Jun 2020 09:15:57 +0000 (11:15 +0200)]
Revert "[mlir] Canonicalization and folding of shape.cstr_broadcastable"
This reverts commit
6aab70945915ef1d565f1146734416029549a5a9.
Some users have failing builds with ShapeCanonicalization.td, so revert
for now.
Tres Popp [Sat, 6 Jun 2020 09:08:41 +0000 (11:08 +0200)]
Revert "[mlir] Folding and canonicalization of shape.cstr_eq"
This reverts commit
0a554e607ff6247b79d1c4f184999750e5ad53b9.
Some users have build failures when building ShapeCanonicalization.td,
so revert changes that created and rely on it.
Tres Popp [Fri, 5 Jun 2020 09:22:10 +0000 (11:22 +0200)]
[mlir] Move attr-dict to end of Shape dialect ops
Summary: This is to be consistent with most other assemblyFormat examles in MLIR.
Differential Revision: https://reviews.llvm.org/D81245
Lang Hames [Fri, 5 Jun 2020 21:08:15 +0000 (14:08 -0700)]
[ORC] Always use ObjectLinkingLayer/JITLink for MachO on x86-64 and arm64.
JITLink supports all code and relocation models, so there's no reason to
conditionalize using JITLink on the code or relocation model settings.
Clients wanting to use RTDyldObjectLinkingLayer/RuntimeDyld will now
need to use a custom object linking layer creator.
Wen-Heng (Jack) Chung [Fri, 5 Jun 2020 21:26:57 +0000 (16:26 -0500)]
[mlir][mlir-rocm-runner] Detect HIP version and AMD ISA version.
Summary:
Prior to ROCm / HIP 3.5, HSA code object V2 is the default binary format.
Starting from ROCm 3.5, HSA code object V3 becomes default.
Also invoke `rocm_agent_enumerator` to detect proper AMD ISA version on the
system. Use `gfx900` as the fallback value.
Reviewers: jerryyin yaxunl
Subscribers: mgorny, yaxunl, mehdi_amini, rriddle, jpienaar, shauheen, antiagainst, nicolasvasilache, arpith-jacob, mgester, lucyrfox, aartbik, liufengdb, stephenneuendorffer, Joonsoo, grosul1, frgossen, Kayjukh, jurahul, msifontes
Tags: #mlir
Differential Revision: https://reviews.llvm.org/D81309
LLVM GN Syncbot [Sat, 6 Jun 2020 01:50:36 +0000 (01:50 +0000)]
[gn build] Port
29203480632
Nico Weber [Sat, 6 Jun 2020 01:50:04 +0000 (21:50 -0400)]
Revert "recommit "[HIP] Add default header and include path""
This reverts commit
1fa43e0b34d9736f62c6c1b6c371a5e39cd1624d.
Still breaks tests on several bots, see https://reviews.llvm.org/D81176
Nico Weber [Sat, 6 Jun 2020 01:20:11 +0000 (21:20 -0400)]
Revert "Migrate the rest of COFFObjectFile to Error"
This reverts commit
b5289656b865d2a73cf90819e20a96fb8414ab0b.
__attribute__((optnone)) doesn't build with msvc, see
http://lab.llvm.org:8011/builders/clang-x64-windows-msvc/builds/16326
LLVM GN Syncbot [Sat, 6 Jun 2020 00:47:43 +0000 (00:47 +0000)]
[gn build] Port
1fa43e0b34d
Jessica Paquette [Fri, 5 Jun 2020 00:08:36 +0000 (17:08 -0700)]
[AArch64][GlobalISel] Move dup optimization into post-legalizer combiner
Since all of the other G_SHUFFLE_VECTOR transforms are going there, let's do
this with dup as well. This is nice, because it lets us split up the original
code into matching, register bank selection, and instruction selection.
- Create G_DUP, make it equivalent to AArch64dup
- Add a post-legalizer combine which is 90% a copy-and-paste from
tryOptVectorDup, except with shuffle matching closer to what SelectionDAG
does in `ShuffleVectorSDNode::isSplatMask`.
- Teach RegBankSelect about G_DUP. Since dup selection relies on the correct
register bank for FP/GPR dup selection, this is necessary.
- Kill `tryOptVectorDup`, since it's now entirely handled by G_DUP.
- Add testcases for the combine, RegBankSelect, and selection. The selection
test gives the same selection results as the old test.
Differential Revision: https://reviews.llvm.org/D81221
Diego Caballero [Sat, 6 Jun 2020 00:29:56 +0000 (17:29 -0700)]
[mlir] Fix representation of BF16 constants
This patch is a follow-up on https://reviews.llvm.org/D81127
BF16 constants were represented as 64-bit floating point values due to the lack
of support for BF16 in APFloat. APFloat was recently extended to support
BF16 so this patch is fixing the BF16 constant representation to be 16-bit.
Reviewed By: rriddle
Differential Revision: https://reviews.llvm.org/D81218
Yaxun (Sam) Liu [Fri, 5 Jun 2020 20:49:38 +0000 (16:49 -0400)]
recommit "[HIP] Add default header and include path"
recommit
11d06b9511bd25aabbfad10dff548b0ce29135a5 with
fix for lit tests.
Diego Caballero [Sat, 6 Jun 2020 00:06:42 +0000 (17:06 -0700)]
Fix convertBFloatAPFloatToAPInt for NaN/Inf values
Bfloat type has an 8-bit exponent so the exponent of NaN/Inf numbers
must be 0xff instead of 0x1f. This is probably a copy-paste mistake
from the half float type.
Reviewed By: lattner
Differential Revision: https://reviews.llvm.org/D81302
Richard Smith [Mon, 4 May 2020 23:56:47 +0000 (16:56 -0700)]
PR34581: Don't remove an 'if (p)' guarding a call to 'operator delete(p)' under -Oz.
Summary:
This transformation is correct for a builtin call to 'free(p)', but not
for 'operator delete(p)'. There is no guarantee that a user replacement
'operator delete' has no effect when called on a null pointer.
However, the principle behind the transformation *is* correct, and can
be applied more broadly: a 'delete p' expression is permitted to
unconditionally call 'operator delete(p)'. So do that in Clang under
-Oz where possible. We do this whether or not 'p' has trivial
destruction, since the destruction might turn out to be trivial after
inlining, and even for a class-specific (but non-virtual,
non-destroying, non-array) 'operator delete'.
Reviewers: davide, dnsampaio, rjmccall
Reviewed By: dnsampaio
Subscribers: hiraditya, cfe-commits, llvm-commits
Tags: #clang, #llvm
Differential Revision: https://reviews.llvm.org/D79378
stevewan [Fri, 5 Jun 2020 23:54:00 +0000 (19:54 -0400)]
[PowerPC] Do not special case Darwin on PowerPC in target cpu handling
Summary: This patch removes the special handling for Darwin on PowerPC in the default target cpu handling, because Darwin is no longer supported on the PowerPC platform.
Reviewers: hubert.reinterpretcast, daltenty
Reviewed By: hubert.reinterpretcast
Subscribers: wuzish, nemanjai, shchenz, steven.zhang, cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D81115
Philip Reames [Fri, 5 Jun 2020 21:48:52 +0000 (14:48 -0700)]
[Tests] Migrate a number of tests to gc-live bundle representation
Reid Kleckner [Fri, 5 Jun 2020 20:56:51 +0000 (13:56 -0700)]
Migrate the rest of COFFObjectFile to Error
Reid Kleckner [Fri, 5 Jun 2020 23:12:38 +0000 (16:12 -0700)]
Re-land "Migrate Binary::checkOffset from error_code to Error, NFC"
This reverts commit
38f3ba591e3a64fa5bbe684b3171c7bda6c5b527.
Fix the XCOFF error handling. Unlike std::error_code, Error must be
consumed or handled.
Fangrui Song [Fri, 5 Jun 2020 23:16:49 +0000 (16:16 -0700)]
Fix -Wunused-variable in -DLLVM_ENABLE_ASSERTIONS=off builds after
ebcbd5ba39c017bb621eefa3175a224aae85ddc8
Richard Smith [Fri, 5 Jun 2020 02:16:05 +0000 (19:16 -0700)]
PR46209: properly determine whether a copy assignment operator is
trivial.
We previously took a shortcut by assuming that if a subobject had a
trivial copy assignment operator (with a few side-conditions), we would
always invoke it, and could avoid going through overload resolution.
That turns out to not be correct in the presenve of ref-qualifiers (and
also won't be the case for copy-assignments with requires-clauses
either). Use the same logic for lazy declaration of copy-assignments
that we use for all other special member functions.
Previously committed as
c57f8a3a20540fcf9fbf98c0a73f381ec32fce2a. This
now also includes an extension of LLDB's workaround for handling special
members without the help of Sema to cover copy assignments.
Richard Smith [Fri, 5 Jun 2020 02:15:22 +0000 (19:15 -0700)]
Set the captures on a CXXRecordDecl representing a lambda closure type
before marking it complete.
No functionality change intended.
Previously committed as
c13dd74e311d2ac70dd3ea663d800307d1aa5b6b.
Fangrui Song [Fri, 5 Jun 2020 22:59:34 +0000 (15:59 -0700)]
[ELF] Don't cause assertion failure if --dynamic-list or --version-script takes an empty file
Fixes PR46184
Report line 1 of the last memory buffer.