lib: utils/irqchip: Check before initializing imsic

The current mlevel imsic check is only for the platform, which
may cause hart without imsic in the platform to trigger an
illegal instruction exception when initializing imsic. For
example, the platform contains a management hart that only
supports wired interrupts.

This patch will check if each hart supports Smaia extension
before doing imsic initialization to avoid triggering illegal
instruction exceptions.

Signed-off-by: Cheng Yang <yangcheng.work@foxmail.com>
Reviewed-by: Anup Patel <anup@brainfault.org>

platform: generic: thead: add Sophgo CV18XX/SG200X series

The Sophgo CV18XX/SG200X series SoCs have a standard C906
core. Add support for it.

Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
Reviewed-by: Anup Patel <anup@brainfault.org>

lib: sbi: Put event after use in sbi_sse_exit() loop

Currently, the sbi_sse_exit() gets event in a loop but does not put
it back after use. This results in global events remaining locked
causing hangs on sub-sequent calls to sse_event_get() for global
events.

Fixes: c8cdf01d8f3a ("lib: sbi: Add support for Supervisor Software Events extension")
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Himanshu Chauhan <hchauhan@ventanamicro.com>

utils/reset: Add SG2042 hwmon MCU support.

SG2042 uses an onboard MCU to provide reset function.
Add reset driver to support this onboard MCU.

Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
Reviewed-by: Anup Patel <anup@brainfault.org>

lib: sbi: simplify inline function in sbi_dtbr.c

The inline function can simplify the code by setting some call
restrictions. This ensures logical smoothness

Signed-off-by: Xiang W <wxjstz@126.com>
Reviewed-by: Anup Patel <anup@brainfault.org>

lib: sbi: fix return type of sbi_dbtr_shmem_disabled

Modify the return value of the sbi_dbtr_shmem_disabled function to
bool to make the semantics clearer.

Signed-off-by: Xiang W <wxjstz@126.com>
Reviewed-by: Anup Patel <anup@brainfault.org>

lib: sbi: Fixed memory permission check in sbi_dbtr_setup_shmem

The previous code detected shmem_phys_hi and shmem_phys_lo as two
addresses. fix this bug

Signed-off-by: Xiang W <wxjstz@126.com>
Reviewed-by: Himanshu Chauhan <hchauhan@ventanamicro.com>

lib: sbi: fix DBTR_SHMEM_MAKE_PHYS for RV64

Obtaining a 64-bit address under rv64 does not require combining
32-bit registers

Signed-off-by: Xiang W <wxjstz@126.com>
Reviewed-by: Himanshu Chauhan <hchauhan@ventanamicro.com>

lib: sbi: Removal unnecessary check dbtr_thishart_state_ptr

After getting hart_shmem_base, dbtr_thishart_state_ptr cannot be
empty. So remove check code.

Signed-off-by: Xiang W <wxjstz@126.com>
Reviewed-by: Himanshu Chauhan <hchauhan@ventanamicro.com>

lib: sbi: fix hart_shmem_base

When only phys_hi is equal to SBI_DBTR_SHMEM_INVALID_ADDR, it may be
a legal address. The old code would modify the legal address.

Signed-off-by: Xiang W <wxjstz@126.com>
Reviewed-by: Himanshu Chauhan <hchauhan@ventanamicro.com>

platform: generic: thead: add Canaan Kendryte K230

Canaan Kendryte K230 SoC has T-Head C908 cores inside. The dt-binding has
been merged into the linux kernel [1]. However, it has early version of
C908 core which does not have Sscofpmf and need to use T-Head PMU
extension. Thus, we add a K230 compatible string to thead_generic_match
and set quirk for T-Head PMU.

[1] https://lore.kernel.org/linux-riscv/tencent_4D85743622F39109466913393EE2F6C5980A@qq.com/

Signed-off-by: Yangyu Chen <cyy@cyyself.name>
Reviewed-by: Inochi Amaoto <inochiama@outlook.com>
Reviewed-by: Anup Patel <anup@brainfault.org>

platform: generic: thead: separate T-Head PMU Errata

As Guo Ren said from the kernel mailing list [1], future T-Head CPUs,
including the newer versions of T-Head C908, will feature standard
Sscofpmf extension. For these CPUs, T-Head's implementation of PMU
Overflow Interrupts may not needed anymore. In this case, we shouldn't
apply T-Head PMU for all T-Head CPUs. Thus, this patch separated T-Head PMU
errata.

[1] https://lore.kernel.org/linux-riscv/Zh9sUUUT09LZb0MO@gmail.com/

Signed-off-by: Yangyu Chen <cyy@cyyself.name>
Reviewed-by: Inochi Amaoto <inochiama@outlook.com>
Reviewed-by: Anup Patel <anup@brainfault.org>

platform: andes: Change all occurrences of andes45 to andes

To make the framework suit all Andes CPUs, change all occurrences of
andes45 to andes.

In addition, we fix some coding style problems and remove an unused
macro in andes.h.

Signed-off-by: Ben Zong-You Xie <ben717@andestech.com>
Reviewed-by: Anup Patel <anup@brainfault.org>

platform: andes: Rename files with the prefix andes45

Rename files with the prefix andes45 to andes.

Signed-off-by: Ben Zong-You Xie <ben717@andestech.com>
Reviewed-by: Anup Patel <anup@brainfault.org>

sbi: sbi_domain_context: Add spinlock for updating domain assigned_harts

Add spinlock protection to avoid race condition on assigned_harts
during domain context switching. Also, rename/add variables for
accessing the corresponding domain of target/current context.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Anup Patel <anup@brainfault.org>

lib: sbi: Refine the settings for switching to Virtual Supervisor Mode.

Although Mstatus.MPV is set, before executing mret, access to VS mode
registers should use the actual register addresses, not the pseudonyms
of S registers.

Signed-off-by: Pope B.Lei <popeblei@gmail.com>
Reviewed-by: Anup Patel <anup@brainfault.org>

lib: sbi: sse: check handler entry to belong to supervisor mode

When registering an SSE event, check for the handler_entry_pc to belong
to supervisor mode domain using sbi_domain_check_addr_range().

Signed-off-by: Clément Léger <cleger@rivosinc.com>
Reported-by: Samuel Holland <samuel.holland@sifive.com>
Reviewed-by: Anup Patel <anup@brainfault.org>

lib: sbi: sse: use PRV_S instead of hardcoded value for mode

Rather then passing 1 to sbi_domain_check_addr_range() for supervisor
mode, use PRV_S.

Signed-off-by: Clément Léger <cleger@rivosinc.com>
Reviewed-by: Anup Patel <anup@brainfault.org>

lib: sbi: sse: call enable callback before sending IPI

Move the enable callback call before sending the IPI. Even though the
event is locked and no race condition can happen, this is more logical.

Signed-off-by: Clément Léger <cleger@rivosinc.com>
Reported-by: Samuel Holland <samuel.holland@sifive.com>
Reviewed-by: Anup Patel <anup@brainfault.org>

lib: sbi: sse: remove superfluous sbi_list_empty() check

The list loop below that check is actually not looping if the list is
empty so there was no need for this check.

Signed-off-by: Clément Léger <cleger@rivosinc.com>
Reported-by: Samuel Holland <samuel.holland@sifive.com>
Reviewed-by: Anup Patel <anup@brainfault.org>

lib: sbi: sse: simplify 32bits overflow check

Rather than checking 32bits overflow with some absolute value, check the
value to be different from the cast itself.

Signed-off-by: Clément Léger <cleger@rivosinc.com>
Reported-by: Samuel Holland <samuel.holland@sifive.com>
Reviewed-by: Anup Patel <anup@brainfault.org>

lib: sbi: sse: rename sse_hart_unlock() to sse_enabled_event_unlock()

There was a naming incoherency between enabled events list lock/unlock.
Rename sse_hart_unlock() to sse_enabled_event_unlock() to be coherent
and reword comments above lock()/unlock() functions.

Signed-off-by: Clément Léger <cleger@rivosinc.com>
Reviewed-by: Anup Patel <anup@brainfault.org>

lib: sbi: sse: fix typos, comments and spacing errors

Fix some errors spotted by Samuel while reviewing the SSE implementation.

Signed-off-by: Clément Léger <cleger@rivosinc.com>
Reported-by: Samuel Holland <samuel.holland@sifive.com>
Reviewed-by: Anup Patel <anup@brainfault.org>

lib: tests: Add test for spinlocks

Implement the test which covers some of the functions from the
`riscv_locks.h` file. This test consists of 3 test cases:

1) For lock/unlock functions
2) Unsuccessful trylock (the lock was previously taken)
3) Successful trylock (the lock is free and can be taken)

Signed-off-by: Ivan Orlov <ivan.orlov0322@gmail.com>
Reviewed-by: Anup Patel <anup@brainfault.org>

lib: tests: Add test for atomic_t

Implement the test which covers some of the functions from the
`riscv_atomic.h` header file. The test contains 9 test cases:

1) atomic read/write test
2) add/return test
3) sub/return test
4) cmpxchg test
5) atomic_xchg test
6) atomic_raw_set_bit test
7) atomic_raw_clear_bit test
8) atomic_set_bit test
9) atomic_clear_bit test

Some of the test cases operate on the `test_atomic` variable. It gets
initialized in the suite init function.

Signed-off-by: Ivan Orlov <ivan.orlov0322@gmail.com>
Reviewed-by: Anup Patel <anup@brainfault.org>

lib: tests: Add test suite init function

Allow to define an init function for the test suite. It could help us
to initialize global variable once, and use them in multiple test cases
after the initialization.

For instance, if multiple test cases use the same atomic_t var, it
could be helpful to call ATOMIC_INIT once during the suite
initialization.

Signed-off-by: Ivan Orlov <ivan.orlov0322@gmail.com>
Reviewed-by: Anup Patel <anup@brainfault.org>

firmware: remove FW_TEXT_START

Now opensbi can run at any address via dynamic relocation. We can
remove FW_TEXT_START.

Signed-off-by: Xiang W <wxjstz@126.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Tested-by: Anup Patel <anup@brainfault.org>

lib: utils: check correct value in fdt_node_offset_by_compatible

After calling fdt_node_offset_by_compatible() we must check its return
value and not an unrelated value.

Addresses-Coverity-ID: 1584993 Logically dead code
Fixes: 67ce5a763cfb ("platform: generic: Add support for specify coldboot harts in DT")
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Anup Patel <anup@brainfault.org>

lib: sbi: sse_event_get() may return NULL

sse_event_get() may return NULL. We should not dereference the return value
in sbi_sse_exit() without checking.

Fixes: c8cdf01d8f3a ("lib: sbi: Add support for Supervisor Software Events extension")
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Anup Patel <anup@brainfault.org>

lib: sbi: Add missing sscrind and sscfg extensions in sbi_hart_ext[]

The sbi_hart_ext[] array is missing these two extensions ids. It is
expected that this array contains all the extensions declaration at the
same index of the SBI_HART_EXT_* define. Without this, when adding a new
extension, there is a mismatch between ids and extension names and it
can even display corrupted extension names.

Addresses-Coverity-ID: 1584994 Out-of-bounds read
Fixes: 6bb6b61c27eb ("lib: sbi: Add support for smcsrind and smcdeleg")
Signed-off-by: Clément Léger <cleger@rivosinc.com>
Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Anup Patel <anup@brainfault.org>

Makefile: Remove unnecessary dependencies

The rule included from auto.conf.cmd adds a dependency on every Kconfig
file, so these two Kconfig files do not need to be specified again here.

Signed-off-by: Samuel Holland <samuel.holland@sifive.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Tested-by: Anup Patel <anup@brainfault.org>

Makefile: Respect manual changes to .config

The .config file may be manually edited or copied from another location.
Since genconfig.py is responsible for generating auto.conf (the Makefile
fragment) and autoconf.h (the C header) from .config, it must be run any
time .config changes, not just when running menuconfig.

Fixes: 662e631ccef2 ("Makefile: Add initial kconfig support for each platform")
Signed-off-by: Samuel Holland <samuel.holland@sifive.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Tested-by: Anup Patel <anup@brainfault.org>

sbi: sbi_domain_context: Check privilege spec version before accessing S-mode CSRs

SCOUNTEREN and SENVCFG may not be supported on certain RISC-V core,
so check the existence of these CSRs via privilege spec version to
prevent illegal instructions.

Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Signed-off-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Anup Patel <anup@brainfault.org>

lib: sbi: Wakeup non-coldboot HARTs early in the coldboot path

Currently, all non-coldboot HARTs busy spin in wait_for_coldboot()
until the entire coldboot init sequence is completed.

This means:
1) On QEMU, all non-coldboot HARTs will eat host CPU time and
   also slow down the coldboot HART until the entire coldboot
   init sequence is completed.
2) On real HW, all non-coldboot HARTs will consume more CPU
   power until the entire coldboot init sequence is completed.

To address this, wake up all non-coldboot HARTs as early as
possible in the coldboot init sequence.

Signed-off-by: Anup Patel <apatel@ventanamicro.com>

lib: sbi: Simplify wait_for_coldboot() implementation

On QEMU virt machine with large number of HARTs, some of the HARTs
randomly fail to come out of wait_for_coldboot() due to one of the
following race-conditions:

1) Failing HARTs are not able to acquire the coldboot_lock and
   update the coldboot_hartmask in wait_for_coldboot() before
   the coldboot HART acquires the coldboot_lock and sends IPI
   in wake_coldboot_harts() hence the failing HARTs never
   receive IPI from the coldboot HART.

2) Failing HARTs acquire the coldbood_lock and update the
   coldboot_hartmask before coldboot HART does sbi_scratch_init()
   so the sbi_hartmask_set_hartid() does not update the
   coldboot_hartmask on the failing HARTs hence they never
   receive IPI from the coldboot HART.

To address this, use a simple busy-loop in wait_for_coldboot() for
polling on coldboot_done flag.

Signed-off-by: Anup Patel <apatel@ventanamicro.com>

platform: generic: allwinner: Optimize current hart scratch access

The address of the local scratch area is stored in each hart's mscratch
CSR. It is more efficient to read the CSR than to compute the address
from the hart ID.

Signed-off-by: Samuel Holland <samuel.holland@sifive.com>
Reviewed-by: Anup Patel <anup@brainfault.org>

lib: utils/timer: Optimize current hart scratch access

The address of the local scratch area is stored in each hart's mscratch
CSR. It is more efficient to read the CSR than to compute the address
from the hart ID.

Signed-off-by: Samuel Holland <samuel.holland@sifive.com>
Reviewed-by: Anup Patel <anup@brainfault.org>

include: sbi: Support byteorder macros in assembly

Avoid using C types and casts if sbi/sbi_byteorder.h is included in
assembly code

Signed-off-by: Vivian Wang <dramforever@live.com>
Reviewed-by: Anup Patel <anup@brainfault.org>

lib: sbi: Add SSE support for PMU events

Add SSE callbacks registration to PMU driver in order to disable
interrupt delegation for PMU interrupts. When interrupts are
undelegated send the PMU SSE event upon LCOFIP IRQ.

Signed-off-by: Clément Léger <cleger@rivosinc.com>
Reviewed-by: Anup Patel <anup@brainfault.org>

lib: sbi: Implement SBI SSE extension

The SBI SSE extension defines a set of function that can be called to
register and handle supervisor sofwtare events. This patch implements
all of the functionality defined in the specification.

Signed-off-by: Clément Léger <cleger@rivosinc.com>
Reviewed-by: Himanshu Chauhan <hchauhan@ventanamicro.com>
Reviewed-by: Anup Patel <anup@brainfault.org>

lib: sbi: Add support for Supervisor Software Events extension

This extension [1] allows to deliver events from SBI to supervisor via
a software mechanism. This extension defines events (either local or
global) which are signaled by the SBI on specific signal sources (IRQ,
exceptions, etc) and are injected to be executed in supervisor mode.

[1] https://lists.riscv.org/g/tech-prs/message/798

Signed-off-by: Clément Léger <cleger@rivosinc.com>
Reviewed-by: Himanshu Chauhan <hchauhan@ventanamicro.com>
Reviewed-by: Anup Patel <anup@brainfault.org>

firmware: remove copy-base relocation

Remove copy-base relocations that are no longer needed.

Signed-off-by: Xiang W <wxjstz@126.com>
Reviewed-by: Samuel Holland <samuel.holland@sifive.com>
Tested-by: Samuel Holland <samuel.holland@sifive.com>
Reviewed-by: Anup Patel <anup@brainfault.org>

platform: generic: allwinner: sun20i-d1: Remove duplicated CSR definitions

All T-Head CSRs are already defined in thead/c9xx_encoding.h.
Let's reuse the values from there instead of redefining them with
a slightly different name.

Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
Reviewed-by: Anup Patel <anup@brainfault.org>

docs: writing_tests: Make docs correspond the latest changes

We should store test object files list in the `libsbi-objs-y` Makefile
variable, not in `libsbitests-objs-y`. Update the documentation
correspondingly.

Since we don't use the `console_dev` static variable directly in the
`sbi_console_test` unit test anymore, remove the paragraph which says
that we do.

Fixes: 86224ec36aed ("docs/writing_tests: Update tests paths")
Signed-off-by: Ivan Orlov <ivan.orlov0322@gmail.com>
Reviewed-by: Anup Patel <anup@brainfault.org>

lib: sbi: Extend sbi_trap_error() to dump state in a nested trap

The sbi_trap_error() should dump state of all in-flight traps upon
failure in a nested trap so extend it accordingly.

Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Tested-by: Samuel Holland <samuel.holland@sifive.com>

lib: sbi: Pass trap context pointer to sbi_ecall_handler()

To be consistent with other trap handlers, pass trap context pointer
to sbi_ecall_handler().

Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Samuel Holland <samuel.holland@sifive.com>
Tested-by: Samuel Holland <samuel.holland@sifive.com>
Reviewed-by: Clément Léger <cleger@rivosinc.com>

lib: sbi: Remove regs parameter from trap irq handling functions

The trap irq handling functions no longer require regs parameter
so remove it.

Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Samuel Holland <samuel.holland@sifive.com>
Tested-by: Samuel Holland <samuel.holland@sifive.com>

lib: sbi: Remove regs paramter of sbi_irqchip_process()

The irqchip handlers will typically not need pointer to trap registers
so remove regs parameter of sbi_irqchip_process().

Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Samuel Holland <samuel.holland@sifive.com>
Tested-by: Samuel Holland <samuel.holland@sifive.com>
Reviewed-by: Clément Léger <cleger@rivosinc.com>

lib: sbi: Simplify parameters of sbi_illegal_insn_handler()

The struct sbi_trap_context already has the information needed by
sbi_illegal_insn_handler() so directly pass struct sbi_trap_context
pointer to this function.

Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Samuel Holland <samuel.holland@sifive.com>
Tested-by: Samuel Holland <samuel.holland@sifive.com>

lib: sbi: Simplify parameters of misaligned and access fault handlers

The struct sbi_trap_context already has the information needed by
misaligned load/store and access fault load/store handlers so directly
pass struct sbi_trap_context pointer to these functions.

Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Samuel Holland <samuel.holland@sifive.com>
Tested-by: Samuel Holland <samuel.holland@sifive.com>
Reviewed-by: Clément Léger <cleger@rivosinc.com>

lib: sbi: Introduce trap context

Club the struct sbi_trap_regs and struct sbi_trap_info a new
struct sbi_trap_context (aka trap context) which must be saved
by low-level trap handler before calling sbi_trap_handler().

To track nested traps, the struct sbi_scratch points to the current
trap context and the trap context has pointer to pervious context
of previous trap.

Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Samuel Holland <samuel.holland@sifive.com>
Tested-by: Samuel Holland <samuel.holland@sifive.com>

include: sbi: Add trap_context pointer in struct sbi_scratch

To track nested traps, the struct sbi_scratch needs a pointer the
current trap context so add trap_context pointer in struct sbi_context.

Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Samuel Holland <samuel.holland@sifive.com>
Tested-by: Samuel Holland <samuel.holland@sifive.com>

lib: sbi: Remove sbi_trap_exit() and related code

Over the years, no uses of sbi_trap_exit() have been found so remove
it and also remove related code from fw_base.S and sbi_scratch.h.

Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Samuel Holland <samuel.holland@sifive.com>
Tested-by: Samuel Holland <samuel.holland@sifive.com>

lib: sbi: Remove epc from struct sbi_trap_info

In the only places this value is used, it duplicates mepc from
struct sbi_trap_regs.

Signed-off-by: Samuel Holland <samuel.holland@sifive.com>
Reviewed-by: Anup Patel <anup@brainfault.org>

docs/writing_tests: Update tests paths

Since the tests should be moved to the lib/sbi/tests directory, the
documentation should be updated correspondingly. So, update the paths
where they have to be changed.

Signed-off-by: Ivan Orlov <ivan.orlov0322@gmail.com>
Reviewed-by: Anup Patel <anup@brainfault.org>

lib: tests: Move tests to a separate directory

Move all of the SBIUnit-related code into the lib/sbi/tests directory.
Update 'Makefile' to index objects from the tests subdirectory.

I don't think creating the full separate list of Makefile variables
(libsbitests-objs-path-y, libsbitests-object-mks, etc. as it is done for
libsbiutils) is necessary for the tests because:

1) `lib/sbi/tests/objects.mk` is already indexed into
'libsbi-objects-mks' since the find expression for the libsbi-object-mks
variable looks for objects.mk files in the nested directories as well).

2) Tests are tightly coupled with the `lib/sbi/` sources, therefore it
may be reasonable to store the list of lib/sbi and lib/sbi/tests object
files together in the libsbi-objs-path-y variable.

Additionally, update relative paths in the tests where necessary.

Signed-off-by: Ivan Orlov <ivan.orlov0322@gmail.com>
Reviewed-by: Anup Patel <anup@brainfault.org>

lib: sbi: call platform load/store emulators

sbi_load/store_access_handler now tries to call platform emulators
if defined. Otherwise, redirects the fault. If the platform code
returns failure, this means the H/S/U has accessed the emulated
devices in an unexpected manner, which is very likely caused by
buggy code in H/S/U. We redirect the fault, so lower privileged
level can get notified, and act accordingly. (E.g., oops in Linux)

We let the handler truly fail if the trap was originated from M mode.
In this case, something must be very wrong and we should just fail.

Signed-off-by: Bo Gan <ganboing@gmail.com>
Reviewed-by: Anup Patel <anup@brainfault.org>

include: sbi: add emulate_load/store handler to platform ops

This patch allows the platform to define load/store emulators. This
enables a platform to trap-and-emulate special devices or filter
access to existing physical devices.

Signed-off-by: Bo Gan <ganboing@gmail.com>
Reviewed-by: Anup Patel <anup@brainfault.org>

lib: sbi: abstract out insn decoding to unify mem fault handlers

This patch abstracts out the instruction decoding part of misaligned ld/st
fault handlers, so it can be reused by ld/st access fault handlers.
Also Added lb/lbu/sb decoding. (previously unreachable by misaligned fault)

sbi_trap_emulate_load/store is now the common handler which takes a `emu`
parameter that is responsible for emulating the misaligned or access fault.
The `emu` callback is expected to fixup the fault, and based on the return
code of `emu`, sbi_trap_emulate_load/store will:

  r/wlen => the fixup is successful and regs/mepc needs to be updated.
  0      => the fixup is successful, but regs/mepc should be left untouched
            (this is usually used if `emu` does `sbi_trap_redirect`)
  -err   => failed, sbi_trap_error will be called

For now, load/store access faults are blindly redirected. It will be
enhanced in the following patches.

Signed-off-by: Bo Gan <ganboing@gmail.com>
Reviewed-by: Anup Patel <anup@brainfault.org>

lib: sbi: change prototype of sbi_misaligned_load/store_handler

This simplifies both handlers such that when the handler needs to
redirect the original trap, it's readily available.

Signed-off-by: Bo Gan <ganboing@gmail.com>
Reviewed-by: Anup Patel <anup@brainfault.org>

lib: sbi: change prototype of sbi_trap_redirect

sbi_trap_redirect now uses const pointer to `trap`.
This ensures the caller that we never change `trap` in sbi_trap_redirect.

Signed-off-by: Bo Gan <ganboing@gmail.com>
Reviewed-by: Anup Patel <anup@brainfault.org>

include: sbi: rename sbi_misaligned_ldst.h to sbi_trap_ldst.h

Signed-off-by: Bo Gan <ganboing@gmail.com>
Reviewed-by: Anup Patel <anup@brainfault.org>

lib: sbi: rename sbi_misaligned_ldst.c to sbi_trap_ldst.c

Signed-off-by: Bo Gan <ganboing@gmail.com>
Reviewed-by: Anup Patel <anup@brainfault.org>

lib: sbi: Add initial domain context management support

The domain context management component in OpenSBI provides basic CPU
context management routines for existing OpenSBI domain. As domain
extension, it was initially designed to facilitate the suspension
and resumption of domains, enabling secure domains to efficiently
share CPU resources.

The patch also provides an addition to the OpenSBI domain to provide
updates on hart-domain assignment and declarations of contexts within
the domain.

Signed-off-by: Qingyu Shang <2931013282@sjtu.edu.cn>
Reviewed-by: Yu Chien Peter Lin <peterlin@andestech.com>
Tested-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Anup Patel <anup@brainfault.org>

lib: tests: Add sbi_console test

Add the test suite covering some of the functions from
lib/sbi/sbi_console.c: putc, puts and printf. The test covers a variety
of format specifiers for printf and different strings and characters for
putc and puts.

In order to do that, the test "mocks" the sbi_console_device structure
by setting the 'console_dev' variable to the virtual console.

Signed-off-by: Ivan Orlov <ivan.orlov0322@gmail.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>

lib: tests: Add a test for sbi_bitmap

Add test suite covering all of the functions from lib/sbi/sbi_bitmap.c:
__bitmap_and, __bitmap_or and __bitmap_xor.

Signed-off-by: Ivan Orlov <ivan.orlov0322@gmail.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>

lib: Add SBIUnit testing macros and functions

This patch introduces all of the SBIUnit macros and functions which
can be used during the test development process. Also, it defines
the 'run_all_tests' function, which is being called during the
'init_coldboot' right after printing the boot hart information.

Also, add the CONFIG_SBIUNIT Kconfig entry in order to be able to
turn the tests on and off. When the CONFIG_SBIUNIT is disabled,
the tests and all related code is excluded completely on the
compilation stage.

Signed-off-by: Ivan Orlov <ivan.orlov0322@gmail.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>

docs: Add documentation about tests and SBIUnit

This patch contains the documentation for SBIUnit. It describes:

- What is SBIUnit
- Simple test writing scenario
- How we can cover static functions
- How we can "mock" structures in order to test the functions which
operate on them
- SBIUnit API Reference

Signed-off-by: Ivan Orlov <ivan.orlov0322@gmail.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>

firmware: fw_base.S: fix _reset_regs

a3 and a4 cannot be reset because used in fw_platform_init.

Signed-off-by: Xiang W <wxjstz@126.com>
Reviewed-by: Anup Patel <anup@brainfault.org>

firmware: fw_base.S: Remove _relocate_lottery

Remove _relocate_lottery and use _boot_status instead.

Signed-off-by: Xiang W <wxjstz@126.com>
Reviewed-by: Anup Patel <anup@brainfault.org>

firmware: fw_dynamic.S: Remove _bad_dynamic_info

_bad_dynamic_info is same as _start_hang, so remove it.

Signed-off-by: Xiang W <wxjstz@126.com>
Reviewed-by: Anup Patel <anup@brainfault.org>

firmware: fw_base: Simplified setup trap handler

The same detection was done twice when setting mtvec and trap_exit.
Merging can reduce code size.

Signed-off-by: Xiang W <wxjstz@126.com>
Reviewed-by: Anup Patel <anup@brainfault.org>

firmware: fw_base.S: Simplify address get

Simplify address get and remove _link_start _link_end _load_start.

Signed-off-by: Xiang W <wxjstz@126.com>
Reviewed-by: Anup Patel <anup@brainfault.org>

lib: sbi_misaligned_ldst: Add handling of C.LHU/C.LH and C.SH

Added exception handling for compressed instructions C.LHU, C.LH, and
C.SH from the zcb extension to the sbi_misaligned_ldst library.

Signed-off-by: Nylon Chen <nylon.chen@sifive.com>
Reviewed-by: Anup Patel <anup@brainfault.org>

platform: andes: Drop andes_pmu_setup()

andes_pmu_setup() [1] was intended to populate event mapping from
hardcoded arrays, however, this increases firmware size and we should
just use PMU DT node [2] instead.

Link: https://lists.infradead.org/pipermail/opensbi/2023-November/006032.html
Link: https://github.com/riscv-software-src/opensbi/blob/v1.4/docs/pmu_support.md#example-3
Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Anup Patel <anup@brainfault.org>

lib: sbi: Add support for smcsrind and smcdeleg

Smcsrind allows generic indirect CSR access mechanism while
Smcdeleg allows delegating hpmcounters in Supervisor mode.

Enable both extensions and set the appropriate bits in mstateen
and menvcfg.

Co-developed-by: Kaiwen Xue <kaiwenxue1@gmail.com>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
Reviewed-by: Anup Patel <anup@brainfault.org>

lib: sbi_hsm: Restor hart state to stop when fails to start

Hart state should change back to hart stop when hsm_device_hart_start()
or sbi_ipi_raw_send() fails to perform hart start.

Signed-off-by: Joshua Yeong <joshua.yeong@starfivetech.com>
Reviewed-by: Xiang W <wxjstz@126.com>
Reviewed-by: Anup Patel <anup@brainfault.org>

docs/firmware: document new options for jump and payload firmwares

Adding relocatable address brings new configuration options for jump
and payload firmwares. Describe these new options in documentation.

Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
Reviewed-by: Anup Patel <anup@brainfault.org>

platform: Apply relocatable address

Since jump and payload firmware support relocatable address, make
general platform use runtime relocatable address.

Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
Reviewed-by: Anup Patel <anup@brainfault.org>

firmware: Add relocatable FW_PAYLOAD_FDT_ADDR

The fw_payload.bin has the same issue as described in previous patch.
But only FW_PAYLOAD_FDT_ADDR is affected.

Add FW_PAYLOAD_FDT_OFFSET to identify relocatable payload fdt address.

Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
Reviewed-by: Anup Patel <anup@brainfault.org>

firmware: Add relocatable FW_JUMP_ADDR and FW_JUMP_FDT_ADDR

If FW_PIC=y is defined, the fw_jump.bin will be broken if
FW_TEXT_START is wrong. This is not the desired behavior.

Add two new variables to identify relocatable jump address:
FW_JUMP_OFFSET and FW_JUMP_FDT_ADDR. To keep the existing
ABI, FW_JUMP_ADDR and FW_JUMP_FDT_ADDR is prefered if they
are defined.

Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
Reviewed-by: Anup Patel <anup@brainfault.org>

platform: starfive: call starfive_jh7110_inst_init() in pm_reset_init()

The function starfive_jh7110_inst_init() initialize some power
management unit address and clock addresses, needed for the reset
driver. It doesn't do anything else, and also the reset driver doesn't
work without calling this function. Thus, it does not make much sense
that this function is independent from pm_reset_init().

Delete the separate call to starfive_jh7110_inst_init(), and instead
just call this function inside pm_reset_init().

Doing this also fixes another problem: if starfive_jh7110_inst_init()
returns an error code, it gets propagated to final_init() and OpenSBI
hangs. This hang is not necessary, because failures within
starfive_jh7110_inst_init() only mean OpenSBI cannot perform reboot or
shutdown, but the system can still function normally.

Signed-off-by: Nam Cao <namcao@linutronix.de>
Tested-by: Minda Chen <minda.chen@starfivetech.com>
Reviewed-by: Anup Patel <anup@brainfault.org>

platform: starfive: return error if needed devices are not present

Jh7110's reset driver needs power management device and clock controller
device to work. Currently, the driver proceed anyway without these
devices, and invalid addresses (jh7110_inst.pmu_reg_base and
jh7110_inst.clk_reg_base) are used during reboot, which causes
unpredictable broken behaviors.

If these devices are not present, return -SBI_ENODEV.

Signed-off-by: Nam Cao <namcao@linutronix.de>
Tested-by: Minda Chen <minda.chen@starfivetech.com>
Reviewed-by: Anup Patel <anup@brainfault.org>

platform: starfive: rename "stf,axp15060-regulator" -> "x-powers,axp15060"

OpenSBI uses the device tree compatible string "stf,axp15060-regulator"
for the regulator node. However, the string used by U-Boot (and Linux)
is actually "x-powers,axp15060". As OpenSBI gets the device tree from
U-Boot, this causes the regulator device to be undetected, and OpenSBI
does not use this device to perform board reset/shutdown.

Rename this device tree compatible string to match U-Boot (and Linux).

Signed-off-by: Nam Cao <namcao@linutronix.de>
Acked-by: Minda Chen <minda.chen@starfivetech.com>
Tested-by: Minda Chen <minda.chen@starfivetech.com>
Reviewed-by: Anup Patel <anup@brainfault.org>

platform: starfive: remove redundant compatibility check in pmic_ops

pmic_ops() is only called if a compatible device is found in device
tree. It is redundant for this function to check the compability again.
Remove this check.

Signed-off-by: Nam Cao <namcao@linutronix.de>
Tested-by: Minda Chen <minda.chen@starfivetech.com>
Reviewed-by: Anup Patel <anup@brainfault.org>

platform: starfive: get I2C offset address from clocks property

The current code gets the I2C offset address using the device tree node
name: it get the I2C device index from the 4th character in the node
name (for example, "i2c5" -> i2c device 5). However, the device tree
node's name in U-Boot is actually just "i2c" without the number, so the
current code cannot be used with the device tree from U-Boot.

Get the I2C offset address from the "clocks" property instead.

Signed-off-by: Nam Cao <namcao@linutronix.de>
Reviewed-by: Minda Chen <minda.chen@starfivetech.com>
Tested-by: Minda Chen <minda.chen@starfivetech.com>
Reviewed-by: Anup Patel <anup@brainfault.org>

platform: starfive: correct system clock device tree node

Starfive names the system clock device tree node "starfive,jh7110-clkgen"
in all their git repositories. However, a different name is used in
upstream U-Boot (and also Linux): "starfive,jh7110-syscrg". Since
OpenSBI gets the device tree from U-Boot, this inconsistency leads the
problem that OpenSBI doesn't know the system clock device exists.

Correct this name to keep the consistency.

Signed-off-by: Nam Cao <namcao@linutronix.de>
Acked-by: Minda Chen <minda.chen@starfivetech.com>
Tested-by: Minda Chen <minda.chen@starfivetech.com>
Reviewed-by: Anup Patel <anup@brainfault.org>

lib: sbi_pmu: Before using we should ensure PMU init done

If trap earlier before sbi_pmu_init done, some path would call
sbi_pmu_ctr_incr_fw, then it would go wrong:
1. if phs_ptr_offset is zero, then it get a wrong pmu state ptr
2. if phs_ptr_offset is ok, but we didn't call pmu_set_hart_state_ptr
it would be NULL POINT

Of course, the above situation will not occur at present, but it is
reasonable to check before using.

Signed-off-by: yang.zhang <yang.zhang@hexintek.com>
Reviewed-by: Anup Patel <anup@brainfault.org>

docs: move documentation of system suspend test.

This patch move documentation of "system-suspend-test" from
docs/domain_support.md to docs/opensbi_config.md

Signed-off-by: Cheng Yang <yangcheng.work@foxmail.com>
Reviewed-by: Anup Patel <anup@brainfault.org>

platform: generic: Parse system suspend test from config node.

This patch update generic_domains_init() so that "system-suspend-test"
is parsed from "/chosen/opensbi-config" DT node.

Signed-off-by: Cheng Yang <yangcheng.work@foxmail.com>
Reviewed-by: Anup Patel <anup@brainfault.org>

docs: Add OpenSBI DT configuration guide.

This patch add docs/opensbi_config.md which describes the
"/chosen/opensbi-config" DT node and properties

Signed-off-by: Cheng Yang <yangcheng.work@foxmail.com>
Reviewed-by: Anup Patel <anup@brainfault.org>

platform: generic: Add support for specify coldboot harts in DT

Added support for the generic platform to specify the set of coldboot
hart in DT. If not specified in DT, all harts are allowed to coldboot
as before.

The functions related to sbi_hartmask are not available before coldboot,
so I used bitmap, and added a new bitmap_test() function to test whether
a certain bit of the bitmap is set.

Signed-off-by: Cheng Yang <yangcheng.work@foxmail.com>
Reviewed-by: Anup Patel <anup@brainfault.org>

firmware: fw_base.S: remove _runtime_offset

_runtime_offset is a variable not used elsewhere, so remove it.

Signed-off-by: Xiang W <wxjstz@126.com>
Reviewed-by: Anup Patel <anup@brainfault.org>

firmware: fw_base.S: Improve loading u32

lwu exists under the current rv64 and should also exist under the rv128
in the future, so I modified the conditions of conditional compilation
so that it can adapt to the future situation

Signed-off-by: Xiang W <wxjstz@126.com>
Reviewed-by: Anup Patel <anup@brainfault.org>

firmware: always create dynsym section

With a bare-metal linkers (e.g. riscv64-elf-ld), there exists no
dynsym section. The dynsym section is not used by OpenSBI but
discarding it makes linkers with dynamic library support unhappy.

Signed-off-by: Leon M. Busch-George <leon@georgemail.eu>
Reviewed-by: Anup Patel <anup@brainfault.org>

Makefile: check for --exclude-libs

While writing to the dynsym is futile, the --exclude-libs options is not
recognized by all linkers (e.g. riscv64-elf-ld.bfd).

Signed-off-by: Leon M. Busch-George <leon@georgemail.eu>
Reviewed-by: Anup Patel <anup@brainfault.org>

Makefile: don't pass -mstrict-align if not supported

Support for that option will be added in LLVM 18:
https://github.com/llvm/llvm-project/commit/23ce5368409c760f3dd49d0f17f34772b0b869d8

Clang 17.0.6, however, will error when passed the
`-mstrict-align` flag.
We should only use the flag if it is supported.

Signed-off-by: Kalle Wachsmuth <kalle.wachsmuth@gmail.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Xiang W <wxjstz@126.com>

fw_base.S: Fix comment errors

When calling '_reset_regs', it'll reset all registers except some
specific registers (ra, a0, a1, and a2).

Both boot HART and non-boot HARTs will execute the '_start_warm'
function. Therefore, when '_reset_regs' is called in '_start_warm', it
will reset all registers except some specific registers (ra, a0, a1 and
a2) for both boot HART and non-boot HARTs.

Signed-off-by: Zhang Runmin <fmrt19zrmin@163.com>
Reviewed-by: Anup Patel <anup@brainfault.org>

lib: sbi: Use mask to check the free bit during trigger allocation

The trigger allocation function uses bit shift instead of mask to check the
mapped status of the triggers. This causes index 0 to be return always. As a
result, the older triggers are overwritten.

Use the mask for MAPPED field in state word to check if the trigger is mapped.

Fixes: 97f234f15 ("lib: sbi: Introduce the SBI debug triggers extension support")
Signed-off-by: Himanshu Chauhan <hchauhan@ventanamicro.com>
Reviewed-by: Anup Patel <anup@brainfault.org>

lib: sbi: Print number of debug triggers found

Print the total number of triggers found on the boot hart.

Signed-off-by: Himanshu Chauhan <hchauhan@ventanamicro.com>
Reviewed-by: Anup Patel <anup@brainfault.org>