review.tizen.org Git - platform/upstream/mesa.git/log

anv/image: Rework YCbCr image aspects

The Vulkan 1.2.184 spec says:

    "When creating a VkImageView, if sampler Y′CBCR conversion is
    enabled in the sampler, the aspectMask of a subresourceRange used by
    the VkImageView must be VK_IMAGE_ASPECT_COLOR_BIT.

    When creating a VkImageView, if sampler Y′CBCR conversion is not
    enabled in the sampler and the image format is multi-planar, the
    image must have been created with
    VK_IMAGE_CREATE_MUTABLE_FORMAT_BIT, and the aspectMask of the
    VkImageView’s subresourceRange must be VK_IMAGE_ASPECT_PLANE_0_BIT,
    VK_IMAGE_ASPECT_PLANE_1_BIT or VK_IMAGE_ASPECT_PLANE_2_BIT."

Previously, for YCbCr images, we were flipping this around.  For single-
plane views where VK_IMAGE_ASPECT_PLANE_N_BIT would be passed in by the
app, we would store VK_IMAGE_ASPECT_COLOR_BIT.  For multi-plane views
where the client says VK_IMAGE_ASPECT_COLOR_BIT, we would store a all of
the planes.  (There was also an extra bit of remapping that would
compact the planes in the non-existent case of a format with a non-
contiguous set of planes.)  The idea behind this was that for things
like rendering or single-plane sampling, storage, or compute, we want it
to look as much like a single-plane image as possible but we wanted the
multi-plane case to be the awkward one.

This commit changes it around so that iview->aspects is always exactly
the subset of image->vk.aspects represented by the view.  This is
identical to how aspects work for depth/stencil so it gains us some
consistency.

This commit also changes anv_image_view::aspect_mask to aspects to force
a full audit of the field.  As can be seen, there are only a few uses of
this field and they're all mostly fine:

- A bunch of them are used to check for depth/stencil.  That hasn't
   changed.

- Most of the checks for color already used ANY_COLOR_BIT, only one
   needed fixing.

- There's a check that both src/depth are color for MSAA resolves.
   However, we don't support MSAA on YCbCr so there's no point in
   checking for ANY_COLOR_BIT.

There is a hidden usage of planes in anv_descriptor_set_write_image_view
that's not as obvious.  However, this function simply looks at
anv_image_view::n_planes and blindly fills out the descriptor
accordingly.  As long as image views with a single plane continue to
claim n_planes == 1, this will be fine.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12141>

anv: Stop assuming planes are in aspect-bit-order

Previously, we initialized vplane in anv_CreateImageView to 0 and
incremented it every iteration of the aspect loop. This only works
because planes are guaranteed to be in aspect-bit-order which wasn't
documented anywhere. Instead, drop this assumption and burn a couple
CPU cycles properly calculating vplane.

While we're here, make iplane const as well.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12141>

anv: Use anv_get_format_plane for color image view setup

When creating a single-plane view of a multi-plane image, we were
relying on vplane_aspect to be VK_IMAGE_ASPECT_COLOR_BIT so that
anv_get_format_plane of the single-plane view format would work.
Instead of relying on this quirk, we can drop vplane_aspect and rely
entirely on vplane to only be 0 in this case. In the case of depth or
stencil images, we still need to grab the format aspect but we can use
the actual aspect and don't need the vplane_aspect trickery.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12141>

anv: Use anv_get_format_plane in anv_get_image_format_features

Once we get past depth/stencil, what we really want is plane 0 not the
color aspect. A bunch of those formats don't have a single color
aspect.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12141>

anv: Add a get_format_plane helper and use it in image setup

Unlike anv_get_format_aspect, this takes a plane number which is
relative to the set of aspects on the format. There are a number of
cases where we already have the plane and so re-fetching it is useless.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12141>

anv: Rework depth/stencil early return in anv_get_format_plane

The comment about modifiers is bogus because we check the modifier
before this check and return early. Also, there's no reason why we need
to check the requested aspect when we could check the format itself.
anv_image_aspect_to_plane will ensure that the requested aspect is one
that actually exists.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12141>

anv: Rename anv_get_format_plane to anv_get_format_aspect

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12141>

anv/blorp: Use the isl_surf for computing level_width/height in anv_image_ccs_op

Don't manually monkey around with the denominator scales.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12141>

anv/blorp: Drop some can_ycbcr checks

Vulkan allows us to, in theory, support ycbcr on single-plane formats if
the client really wants it. Also, these functions should work on a
multi-plane color image as long as the client specifies the right
aspect. This gets rid of our usage of can_ycbcr outside of anv_image.c.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12141>

nouveau: Use nir_lower_tex for projectors

Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11826>

nir: add imm_vec3 to round these out

Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12253>

radv: Allocate space for inline push constants.

In the compute dispatch path we do not allocate a huge amount
of space to cover everything so the individual functions have to
allocate. This was missing here, causing a hang in Cyberpunk when
accessing the system menu at some locations with thread tracing
enabled.

Fixes: bd1186572f6 ("radv: add support for push constants inlining when possible")
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12271>

radv: Use correct signedness in misalign test.

Lots of the MAX2 args end up subtracting two unsigned numbers, which
blows up when the result is negative.

Fixes: 4c99d6ff54b ("radv: flush L2 for images affected by the pipe misaligned issue on GFX10+")
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12272>

panfrost: Fix pan_blitter_emit_bifrost_blend()

If we return inside a pan_pack() the descriptor packing doesn't happen.

Cc: mesa-stable
Fixes: 8ba2f9f69858 ("panfrost: Create a blitter library to replace the existing preload helpers")
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12239>

v3d: print error on perfmon destroy error

Print an error in case destroying the kernel perfmon fails.

Fixes CID 1489964: Error handling issues (CHECKED_RETURN).

v2:
- Wrap line (Iago).

Fixes: 685281278eb ("v3d: implement performance counter queries")
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12280>

broadcom/compiler: change current block on setting spill base

The spill base setting instructions (which includes some uniforms) are
added in the entry block, not in the current block. When ldunif
optimization is applied, the cursor is pointing to instructions in the
entry block, but the current block is a different one. This leads to a
heap-buffer-overflow when going through the list of instructions
(detected by the address sanitizer).

Thus change the current block to entry block, and restore it after the
setup is done.

This fixes
dEQP-VK.ssbo.readonly.layout.single_struct.single_buffer.std430_instance_array_comp_access_store_cols
with address sanitizer enabled.

v2:
- Set current block instead of disabling ldunif optimization (Iago)

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12221>

gallium/noop: implement a lot of missing context functions

Acked-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12255>

gallium/noop: implement a lot of missing screen functions

Acked-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12255>

gallium/noop: update pipe_screen::num_contexts

Acked-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12255>

gallium/noop: enable threaded_context to test TC overhead without a driver

Acked-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12255>

gallium/noop: use threaded_transfer

to enable threaded_context later

Acked-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12255>

gallium/noop: use threaded_resource

to enable threaded_context later

Acked-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12255>

gallium/noop: use threaded_query

to enable threaded_context later

Acked-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12255>

gallium/noop: implement shader buffers and shader images

Acked-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12255>

gallium/noop: implement fences

Acked-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12255>

gallium: simplify VRAM uploads by adding PIPE_RESOURCE_FLAG_DONT_MAP_DIRECTLY

When this flag is set, u_threaded_context will try not to map it directly
for better buffer placement. It's set by drivers when visible VRAM is too
small.

Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12257>

radeonsi: improve viewperf snx performance by forcing staging for VRAM buffers

Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12257>

radv: remove unnecessary FIXME about custom sample locations

VK_EXT_sample_locations is disabled on GFX10+.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12247>

nir/tests: add tests for umod/imod/irem optimizations

Both nir_opt_algebraic and nir_opt_idiv_const have optimizations for
umod/imod/irem by constants.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12039>

nir: fix signed overflow for iadd constant folding

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12039>

nir/idiv_const: optimize imod/irem

fossil-db changes (Sienna Cichlid):
Totals from 223 (0.15% of 150170) affected shaders:
CodeSize: 384564 -> 370824 (-3.57%)
Instrs: 74518 -> 71961 (-3.43%)
Latency: 351620 -> 344640 (-1.99%)
InvThroughput: 80122 -> 74846 (-6.58%)
VClause: 919 -> 920 (+0.11%)
SClause: 2879 -> 2877 (-0.07%); split: -0.10%, +0.03%
Copies: 3099 -> 3103 (+0.13%)

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12039>

nir/idiv_const: improve idiv(n, INT_MIN)

This lowering is smaller and -INT64_MIN is probably UB (signed overflow).

No fossil-db changes.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12039>

nir/algebraic: improve irem by power-of-two optimization

Requires one less instruction.

No fossil-db changes.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12039>

nir/search: don't consider INT_MIN a negative power-of-two

ineg(INT_MIN)/iabs(INT_MIN) won't work as expected.

No fossil-db changes.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12039>

nir/algebraic: add optimizations for imul(a, INT_MIN)

is_pos_power_of_two would catch this, but nir_op_imul has signed sources,
so is_neg_power_of_two catches it instead, which creates a useless
nir_op_ineg.

fossil-db (Sienna Cichlid):
Totals from 1014 (0.68% of 150170) affected shaders:
CodeSize: 3592296 -> 3592288 (-0.00%); split: -0.00%, +0.00%
Instrs: 671211 -> 670426 (-0.12%)
Latency: 5268917 -> 5268479 (-0.01%); split: -0.01%, +0.00%
InvThroughput: 2187349 -> 2187343 (-0.00%); split: -0.00%, +0.00%
VClause: 8634 -> 8636 (+0.02%)
Copies: 97585 -> 97604 (+0.02%)

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12039>

nir/algebraic: don't optimize umod/imod/irem if lower_bitops=true

Match the udiv/idiv/imul by power-of-two optimizations.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12039>

nir/algebraic: fix imod by negative power-of-two

If "a" is a multiple of "b", then the result would have been "b" instead
of 0.

No fossil-db changes.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Fixes: 0ef5f3552f6 ("nir: add strength reduction pattern for imod/irem with pow2 divisor.")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12039>

radv: fix initializing the DS clear metadata value for separate aspects

We shouldn't overwrite the clear value of the other aspect (in case
separate depth/stencil layouts are used).

Found by inspection.

Cc: 21.2 mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12222>

radeonsi: don't create an infinite number of variants

If a shader has code like this:

   uniform float timestamp;
   ...
   if (timestamp > 0.0)
      do_something()

And timestamp is modified each frame, we'll end up generating a new
variant per frame.

This commit introduces a hard limit on the number of variants we generate
for a single shader.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5121
Fixes: b7501184b90 ("radeonsi: implement inlinable uniforms")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12138>

radeonsi: add -t option to the test script

This allows to easily run a subset of the tests without having
to figure out which test suite(s) they belong to.

dEQP cannot use this option because currently "deqp-runner suite"
don't have it.

Acked-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12215>

radeonsi: fix test script's output

This line was dropped in the last refactoring. We need
to clearly state to the user if the new results are
different to the expected ones.

Acked-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12215>

radv: allow DCC MSAA fast clears if a FCE is needed

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12180>

radv: perform a FCE for MSAA images that might have been fast-cleared

FMASK_DECOMPRESS can't eliminate DCC fast clears. This will allow to
enable DCC MSAA fast clears that require a FCE.

Only supported on GFX10+.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12180>

radv: rework DCC, FMASK and FCE decompress path

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12180>

gallivm: remove code to force nearest s/t interpolation

These two bits were added in 2012, but never got wired up. Let's cut our
losses, and remove them again. 9 years unused seems sufficient.

While we're at it, remove reduction_mode from the hacks-section, because
this isn't a hack at all, rather normal state.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12240>

lavapipe: lower mipmapPrecisionBits to 4

Through some exhaustive searching, I've found that our log2 approximation
is precise to around 3.5 bits. And the squaring step should increase the
result with one bit, leaving us with 4.5 bits of precision.

Reporting the right mipmap precision fixes a few CTS-tests.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12238>

anv: allow stencil memory export

This commit reverts 58e93711412 as now iris driver can import stencil.
This makes ext_external_objects-vk-stencil-display pass and X-Plane 11
vulkan rendering backend to work with anv + iris.

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Eleni Maria Stea <elene.mst@gmail.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10609>

anv: disable aux for exportable images without modifiers

This makes import easier on different gfx generations and we don't
have to lock down on a certain aux layout just yet.

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10609>

iris: handle depth-stencil import with a wrapper function

This is similar to u_transfer_helper wrap but implemented in
the driver as the layout between drivers can vary.

v2: remove else, simplify (Rohan, Eleni)
v3: add hiz surface support when importing depth buffer
v4: use iris_resource_configure_aux_offsets for setting
aux offsets for depth
v5: introduce helper for configuring imported memobj aux
offsets and utilize that
v6: simplify, remove aux support for now
v7: cleanups, fix offset calculation (Nanley)

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10609>

crocus: disable depth and d+s formats with memory objects

This is similar to i965 commit ba11f673a24, we set depth and
d+s formats unsupported for now.

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10609>

crocus: take a reference to memobj bo in crocus_resource_from_memobj

This is the same fix as commit 2d87ea31665 for iris driver.

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10609>

i915g: Reapply clang-format.

Missed this in 2008ec8a432c ("i915g: Fix writemasking of SEQ/SNE/SSG.")

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12250>

i915g: Use the devmaster quadratic approximation for sin/cos.

11 instructions, but now processes up to 4 channels at once (since TGSI
splits to scalar for these math ops) while being higher accuracy.
Previously we used 6 instructions per channel, but it didn't look like a
sine wave. i915c managed it in 9 instructions per scalar channel, thanks
to avoiding an extra mov we do for the fabs (should be fixable), and
avoiding an extra MUL (maybe just needs reassociation of our immediates?).
But, the ALU count win from doing 4 channels at once will be way more
important for making sure that programs compile than those 2 ALU ops, plus
now we do it in NIR instead of assembly.

Closes: #4981
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12250>

freedreno/regs: add bit to control continuous clock with 7nm PHYs

7nm PHYs need another special bit set in DSI_LANE_CTRL to enable
continuous DSI clock. Document this bit.

Signed-off-by: Dmitry Baryshkov <dbaryshkov@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11219>

docs: make most important part of bugs.rst easier to find

Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12124>

pps: Restore documentation

Restore part of the perfetto documentation deleted by mistake.

Signed-off-by: Antonio Caggiano <antonio.caggiano@collabora.com>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11846>

frontends/va/postproc: Keep track of deinterlacing method being used

When transcoding a video, the context used by decode/postproc process
might be different from that of the encoder, but we encoder needs to
know if deinterlacing was used.

Fixes: c5088b49729 ("gallium: Fix VAAPI postproc blit")
Signed-off-by: Thong Thai <thong.thai@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12251>

gallium/util: add half texel offset param to util_compute_blit

Fixes an issue where the video image is blurry after blitting.

Fixes: c5088b49729 ("gallium: Fix VAAPI postproc blit")
Signed-off-by: Thong Thai <thong.thai@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12251>

gallium/auxiliary/vl: Add additional deinterlace enum and tracking

Add additional deinterlace enums and a deinterlace field to the
vl_compositor struct, so we can keep track of which deinterlacing
algorithm is currently being used, if any.

Signed-off-by: Thong Thai <thong.thai@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12251>

util/fossilize_db: Add extra flock mutex.

The flock is per-fd, not per thread, and we do it outside of the main mutex. This was
done to avoid having to wait in the mutex, but we can get a case where one ends up running
the body with the flock unlocked.

Fix this by adding a mutex that doesn't need to be locked for reads.

Fixes: 4f0f8133a35 "util/fossilize_db: Do not lock the fossilize db permanently."
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12266>

util/fossilize_db: Unlock the cache file if the entry already exists.

Fixes: 4f0f8133a35 "util/fossilize_db: Do not lock the fossilize db permanently."
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12266>

util/fossilize_db: Use uint64_t for file size.

For those 32-bit systems with 4G of cache.

Fixes: 2ec1bff0f3a "util/fossilize_db: Split out reading the index."
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12266>

util/fossilize_db: Only allocate entries after full read.

Should void leaking entries on read failure.

Fixes: 2ec1bff0f3a "util/fossilize_db: Split out reading the index."
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12204>

util/fossilize_db: Be conservative about header length check for locking.

Don't anticipate seeing any partial written headers but just in case we
should probably wait on the lock to make sure whatever header was being
written is finished being written.

Fixes: 4f0f8133a35 "util/fossilize_db: Do not lock the fossilize db permanently."
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12204>

util/fossilize_db: Flush files after header write.

We should probably flush before we unlock the file again.

Fixes: 4f0f8133a35 "util/fossilize_db: Do not lock the fossilize db permanently."
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12204>

util/fossilize_db: Reset file position to parsed_offset on cache_offset read failure.

Otherwise we might restart reading from the middle of the entry.

Fixes: 2ec1bff0f3a "util/fossilize_db: Split out reading the index."
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12204>

util/fossilize_db: Update parsed_offset correctly.

If things went perfectly parsed_offset was never updated for the
final entry and we'd seek_set to the start of the last entry. Is
fun when appending to the file next.

Fixes: 2ec1bff0f3a "util/fossilize_db: Split out reading the index."
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12204>

spirv_to_dxil: Fix missing-prototypes build error.

../src/microsoft/spirv_to_dxil/spirv_to_dxil.c: At top level:
../src/microsoft/spirv_to_dxil/spirv_to_dxil.c:200:1: error: no previous prototype for ‘spirv_to_dxil_get_version’ [-Werror=missing-prototypes]
200 | spirv_to_dxil_get_version()
| ^~~~~~~~~~~~~~~~~~~~~~~~~

Fixes: 92b0cf8e773 ("spirv_to_dxil: expose version number")
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12264>

ci/freedreno: Add jobs to manually do a full VK on freedreno.

Building toward scheduled nightly runs, add a button to do a full VK run
when you think you're changing test expectations.

Be gentle with the play button on this, 4 people doing this at once
would block marge for everyone else for a while.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12150>

ci/freedreno: Skip the slow dEQP-VK.ubo.random.all_shared_buffer.48 in CI.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12150>

ci/freedreno: Clean up and fill out the tess timeout annotations.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12150>

ci/freedreno: Generalize the spirv_ids_abuse skips.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12150>

ci/freedreno: Organize, fill out, and document our VK xfails.

This is the full set of xfails for 1.2.7.0 currently.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12150>

venus: free queues after vkDestroyDevice is emitted

Otherwise, another thread might reuse their object ids for other
objects.  For example,

  T1: free queue with object id X
  T2: reuse id X
  T2: emit vkCreateFoo with id X
  T1: emit vkDestroyDevice

virglrenderer happily accepts that which leads to double frees of the
queue: once when X is updated to point to another object and once when
vkDestroyDevice is executed.  virglrenderer should be fixed to catch
such invalid object id reuse as well.

Fixes
dEQP-VK.api.object_management.multithreaded_shared_resources.device_group.

Fixes: ddd75330559 ("venus: initial support for queue/fence/semaphore")
Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-by: Ryan Neph <ryanneph@google.com>
Reviewed-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12252>

freedreno: Device matching based on chip_id

Add support for device matching based on chip_id instead of gpu_id, to
handle newer GPUs

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12159>

freedreno: Make chip_id 64b

In the UABI it is already 64b, but userspace ignored the upper 32b. But
it looks like we will start needing the upper 32b. So before we start
actually *using* chip_id, lets make sure everything is treating it as
64b.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12159>

freedreno/all: Introduce fd_dev_id

Move away from using gpu_id as the primary means to identify which
adreno we are running on, as future GPUs (starting with 7c3) stop
providing a gpu_id as a new naming scheme is introduced.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12159>

freedreno/ir3/lower_io_offsets: Drop gpu_id param

It was unused.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12159>

freedreno/ir3: Reduce use of compiler->gpu_id

For the same reason as previous patch. Mostly we only care about the
generation, so convert things to use compiler->gen instead.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12159>

freedreno: Reduce use of screen->gpu_id

Newer GPU's are moving away from using gpu_id, including the code
landing upstream for "7c Gen 3". But most of the places in the gallium
driver where we were looking at gpu_id, we only cared about the major
generation. So convert those to use screen->gen instead.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12159>

freedreno: Drop device_id

This wasn't actually used for anything.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12159>

freedreno: Move generated device table to .h

We only need it in a single .c file, so we can make the device table
static. Also rename the struct for device table entries, as I want
to re-use the name 'fd_dev_id'

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12159>

nine: enable tc

Acked-by: <Axel Davy davyaxel0@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11866>

nine: track bound sampler count to optimize unbinds

Acked-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: <Axel Davy davyaxel0@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11865>

nine: update bound sampler mask directly during texture updates

Reviewed-by: <Axel Davy davyaxel0@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11865>

nine: split enabled/dummy texture binds into separate iterators

this removes a conditional from the loops

Reviewed-by: <Axel Davy davyaxel0@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11865>

nine: optimize texture binds a bit

this can just iterate over the mask of active textures instead of always
iterating over and rebinding all textures

Acked-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: <Axel Davy davyaxel0@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11865>

tu: Raise maxDescriptorSetUpdateAfterBindUniformBuffersDynamic to 16

... and reduce maxDescriptorSetUpdateAfterBindStorageBuffersDynamic from 12 to
8.

MAX_DYNAMIC_BUFFERS is MAX_DYNAMIC_UNIFORM_BUFFERS +
MAX_DYNAMIC_STORAGE_BUFFERS. We set

maxDescriptorSetUniformBuffersDynamic = MAX_DYNAMIC_UNIFORM_BUFFERS
maxDescriptorSetStorageBuffersDynamic = MAX_DYNAMIC_STORAGE_BUFFERS
maxDescriptorSetUpdateAfterBindUniformBuffersDynamic = MAX_DYNAMIC_BUFFERS / 2
maxDescriptorSetUpdateAfterBindStorageBuffersDynamic = MAX_DYNAMIC_BUFFERS / 2

The CTS test checks that

maxDescriptorSetUpdateAfterBindUniformBuffersDynamic
- is at least 8; and
- is at least maxDescriptorSetUniformBuffersDynamic
maxDescriptorSetUpdateAfterBindStorageBuffersDynamic
- is at least 4; and
- and is at least maxDescriptorSetStorageBuffersDynamic

Prior to this patch maxDescriptorSetUpdateAfterBindUniformBuffersDynamic was 12
but maxDescriptorSetUniformBuffersDynamic was 16, thus causing the CTS failure
in
dEQP-VK.api.info.vulkan1p2_limits_validation.ext_descriptor_indexing

By raising maxDescriptorSetUpdateAfterBindUniformBuffersDynamic to the same
value as maxDescriptorSetUniformBuffersDynamic, we bring the limits into the
appropriate ranges. We do the same thing for
maxDescriptorSetUpdateAfterBindStorageBuffersDynamic by assigning it the same
value as maxDescriptorSetStorageBuffersDynamic.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12193>

mesa: Add EXT_texture_mirror_clamp_to_edge to extension table

This is the OpenGL ES version of ARB_texture_mirror_clamp_to_edge.

v2: fix TexParameter validation (Erik)
v3: Use modernized extension test (Erik)

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10325>

mesa: Add support for EXT_clear_texture

This extension implements a subset of ARB_clear_texture (i.e.
only the features that are not available in OpenGL ES have been
dropped).

v2: Move call declarations from function to offsets (Emil)

v3: Update llvmpipe and softpipe expectations

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10325>

lavapipe: remove duplicate xfail with typo

Seems there's a rogue "time" in here, causing it to look like a new
failure. But if we remove that and resort the list, we'll see that this
failure was already listed.

Fixes: dfccbdff981 ("ci: update to VK-GL-CTS 1.2.7.0")
Acked-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12233>

nine: set CSO_NO_USER_VERTEX_BUFFERS for main cso context

this skips vbuf for radeonsi and saves some cpu

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Axel Davy <davyaxel0@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11884>

nine: don't memset sampler state during conversion

this ends up having pretty huge overhead

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Axel Davy <davyaxel0@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11887>

ir3: Document RA-related register flags better

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12216>

gbm: add GBM_FORMAT_R16

Signed-off-by: Simon Zeni <simon@bl4ckb0ne.ca>
Reviewed-by: Simon Ser <contact@emersion.fr>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12101>

radv: Write RSRC2_GS for NGGC when pipeline is dirty but not emitted.

The radv_emit_ngg_culling_state function won't write the
SPI_SHADER_PGM_RSRC2_GS register when it knows in advance that
radv_emit_graphics_pipeline will overwrite it anyway.

However, there is an unhandled case:

radv_emit_graphics_pipeline will not emit anything (including this
register) when the pipeline is already emitted. Hence, improve
the check in radv_emit_ngg_culling_state to consider this.

Fixes: 9a95f5487f5ab83fa44bea12afa30cf1a25fc9db
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12237>

st/pbo: add a fast pbo download code-path

Based on the glReadPixels code.

pbobench piglit benchmark reports identical/similar results on about 50% of
the test cases. The other test cases get a 2x-50x speedup.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5084
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/1030
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12096>

st/pbo: set nir_tex_instr::is_array field

Otherwise the layer argument won't be used.

Fixes: a01ad311 ("st/mesa: Add NIR versions of the PBO upload/download shaders. ")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12096>

st/pbo: only use x coord when reading a PIPE_TEXTURE_1D

This fixes the following NIR validation error in the
st/pbo download FS:

vec2 32 ssa_14 = mov ssa_4.xy
vec2 32 ssa_15 = f2i32 ssa_14
vec1 32 ssa_16 = deref_var &tex (uniform sampler1D)
vec4 32 ssa_17 = (float32)txf ssa_16 (texture_deref), ssa_16 (sampler_deref), ssa_15 (coord)
error: nir_src_num_components(instr->src[i].src) == instr->coord_components (../src/compiler/nir/nir_validate.c:839)

With this change, the FS becomes:

vec4 32 ssa_2 = intrinsic load_frag_coord () ()
vec1 32 ssa_3 = f2i32 ssa_2.x
[...]
vec1 32 ssa_9 = deref_var &tex (uniform sampler1D)
vec4 32 ssa_10 = (float32)txf ssa_9 (texture_deref), ssa_9 (sampler_deref), ssa_3 (coord), ssa_0 (lod)

Fixes: a01ad311 ("st/mesa: Add NIR versions of the PBO upload/download shaders. ")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12096>