Michal Simek [Thu, 21 Jan 2021 13:02:30 +0000 (14:02 +0100)]
xilinx: zynqmp: Enable gpio-key/button driver
Enable button uclass and also gpio-key driver by default.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Fri, 4 Dec 2020 09:37:38 +0000 (10:37 +0100)]
arm64: zynqmp: Enable sha1sum command
Enable it for TPM usage.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Ashok Reddy Soma [Tue, 10 Aug 2021 06:16:12 +0000 (00:16 -0600)]
watchdog: versal: Include header file needed for dev_ functions
dev_dbg, dev_err and dev_warn seems to be moved to different header file.
Include dm/device_compat.h file to compile properly.
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Wed, 28 Jul 2021 10:25:49 +0000 (12:25 +0200)]
xilinx: zynqmp: Add debug messages for boot mode
Add debug messages to see HW boot mode and also alternative boot mode in
logs directly.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Wed, 11 Aug 2021 10:01:25 +0000 (12:01 +0200)]
cmd: boot: Update reset usage message
The commit
573a3811edc8 ("sysreset: psci: support system reset in a generic
way with PSCI") has added support for warm reset via PSCI but this hasn't
been reflected in usage message and user has to look at the code how to run
it. That's why update usage text to make this clear.
Here is full help with updated usage:
ZynqMP> help reset
reset - Perform RESET of the CPU
Usage:
reset - cold boot without level specifier
reset -w - warm reset if implemented
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Igor Opaniuk <igor.opaniuk@foundries.io>
Michal Simek [Thu, 1 Jul 2021 09:44:51 +0000 (11:44 +0200)]
cmd: pwm: Remove additional pwm description
The first name is taken from command name that's why shouldn't be listed in
help. And commands shouldn't be listed with <> which means value but value
itself is command name.
Also add description for commands to make it clear what it does.
Before
pwm pwm <invert> <pwm_dev_num> <channel> <polarity>
pwm <config> <pwm_dev_num> <channel> <period_ns> <duty_ns>
...
After:
pwm invert <pwm_dev_num> <channel> <polarity> - invert polarity
pwm config <pwm_dev_num> <channel> <period_ns> <duty_ns> - config PWM
pwm enable <pwm_dev_num> <channel> - enable PWM output
pwm disable <pwm_dev_num> <channel> - disable PWM output
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
T Karthik Reddy [Tue, 10 Aug 2021 12:50:21 +0000 (06:50 -0600)]
xilinx: Enable config to display cpuinfo
Enable CONFIG_DISPLAY_CPUINFO to display SoC family & revision.
Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Reviewed-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
T Karthik Reddy [Tue, 10 Aug 2021 12:50:20 +0000 (06:50 -0600)]
xilinx: common: Add function to print SoC info
Add print_cpuinfo() to print SoC info like family & revision.
This function depends on CONFIG_DISPLAY_CPUINFO config.
Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Reviewed-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
T Karthik Reddy [Tue, 10 Aug 2021 12:50:19 +0000 (06:50 -0600)]
soc: xilinx: versal: Add soc_xilinx_versal driver
soc_xilinx_versal driver allows identification of family & revision
of versal SoC. This driver is selected by CONFIG_SOC_XILINX_VERSAL.
Probe this driver using platdata U_BOOT_DEVICE structure which is
defined at mach-versal/cpu.c.
Add this config to xilinx_versal_virt_defconfig &
xilinx_versal_mini_ospi_defconfig file to select this driver.
Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Reviewed-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
T Karthik Reddy [Tue, 10 Aug 2021 12:50:18 +0000 (06:50 -0600)]
soc: xilinx: zynqmp: Add soc_xilinx_zynqmp driver
soc_xilinx_zynqmp driver allows identification of family & revision
of zynqmp SoC. This driver is selected by CONFIG_SOC_XILINX_ZYNQMP.
Add this config to xilinx_zynqmp_virt_defconfig file.
Probe this driver using platdata U_BOOT_DEVICE structure which is
specified in mach-zynqmp/cpu.c.
Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Reviewed-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Tue, 10 Aug 2021 07:21:54 +0000 (09:21 +0200)]
fdt_support: Add kernel-doc for fdt_fixup_memory_banks()
Add kernel-doc description for fdt_fixup_memory_banks() because it is
implemented in one specific way and this information should be available
for others to decide if their SoC conforms to it.
If you don't want U-Boot to update your memory DT layout please disable
CONFIG_ARCH_FIXUP_FDT_MEMORY.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Michal Simek [Fri, 6 Aug 2021 12:09:32 +0000 (14:09 +0200)]
xilinx: Disable ARCH_FIXUP_FDT_MEMORY
Based on DT spec you can have one memory node which multiple ranges or
multiple nodes.
fdt_fixup_memory_banks() is not implemented in a correct way when multiple
memory nodes are present because all ranges are put it to the first memory
node found. And next memory nodes are kept in DT which ends up in the same
range specification in the same DT.
Here is what it is happening.
Origin DT.
memory@0 {
device_type = "memory";
reg = <0x0 0x0 0x0 0x80000000>;
};
memory@
800000000 {
device_type = "memory";
reg = <0x8 0x00000000 0x0 0x80000000>;
};
After fdt_fixup_memory_banks()
memory@0 {
device_type = "memory";
reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
};
memory@
800000000 {
device_type = "memory";
reg = <0x8 0x00000000 0x0 0x80000000>;
};
As is visible memory@0 node got second range but there is still
memory@
800000000 node present and 2G range is listed twice.
The solution can't be that second node is removed because it can be
referenced already that's why it is better for us to disable this option
for now.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Fri, 6 Aug 2021 11:30:11 +0000 (13:30 +0200)]
ARM: zynq: Enable smcc and nor for zc770-xm012
Enable cfi flash on zc770-xm012 configuration.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Fri, 6 Aug 2021 11:30:19 +0000 (13:30 +0200)]
ARM: zynq: Wire single qspi on couple of boards
Single configuration is working fine and no issue to enable it.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Sai Krishna Potthuri [Fri, 6 Aug 2021 07:41:46 +0000 (01:41 -0600)]
ARM: zynq: Replace 'io-standard' with 'power-source' property
Replace 'io-standard' property with 'power-source' property in all
zynq dts files to be in sync with Zynq Pinctrl driver.
Signed-off-by: Sai Krishna Potthuri <lakshmi.sai.krishna.potthuri@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Raju Kumar Pothuraju [Thu, 1 Jul 2021 08:45:11 +0000 (14:15 +0530)]
xilinx: Add jedec compatible string for QSPI (Zynq/ZynqMP)
Add missing "jedec, spi-nor" compatible string for QSPI flash node.
Spi-nor framework uses this compatibility string to probe &
initialize flash. With missing compatibility string we are observing
below error:
Zynq> sf probe 0 0 0
jedec_spi_nor spi_flash@0:0: unrecognized JEDEC id bytes:
00, 00, 00 Failed to initialize SPI flash at 0:0 (error -2)
Signed-off-by: Raju Kumar Pothuraju <raju.kumar-pothuraju@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Thu, 5 Aug 2021 06:28:46 +0000 (08:28 +0200)]
arm64: zynqmp: Update comment style sm-k26
Trivial style patch.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Fri, 6 Aug 2021 09:12:29 +0000 (11:12 +0200)]
arm64: zynqmp: Fix header alignment on kv260 boards
Fix header alignment.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Fri, 6 Aug 2021 09:12:56 +0000 (11:12 +0200)]
arm64: zynqmp: Fix node name for ds35/36 leds
By dt-binding specs led nodes should have -led suffix that's why add it.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Thu, 29 Jul 2021 12:22:05 +0000 (14:22 +0200)]
xilinx: zynqmp: Initialize usb and scsi via preboot
Based on thread
https://lists.denx.de/pipermail/u-boot/2021-June/451828.html
especially
"Overall we have a deficiency in the UEFI implementation in that we
cannot deal with block devices added or removed after initialization."
there is a need to deal with removable media as usb/scsi/sata.
That's why bridge this gap in EFI implementation by resetting usb and
scsi resets to get all disks before efi_init_obj_list() is called.
In our standard boot flow, where we use distro boot, order is fixed as
"jtag mmc0 mmc1 qspi0 nand0 usb0 usb1 scsi0 pxe dhcp" with prioritizing
boot device added by commit
2882b39d564b ("arm64: zynqmp: Setup the first
boot_target at run time").
When device has ESP partition all devices should be detected because then
efi_disk_register() in efi_init_obj_list() is called only once.
The first such a device is sd/emmc(mmc0/mmc1) and then disks on usb/sata
are not handled at all.
The commit
6bb577dbb30f ("arm64: zynqmp: Disable
EFI_CAPSULE_ON_DISK_EARLY") also pointed out on this issue but detection of
removable media wasn't solved that's why do it now via preboot command.
I have tested cases without usb and scsi and there is no problem with
calling resets without devices itself.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Fri, 6 Aug 2021 07:18:17 +0000 (09:18 +0200)]
arm64: zynqmp: Disable WDT_CDNS driver by default
Do not enable watchdog driver in default zynqmp configuration. The reason
is that not all distributions are handling watchdog properly and then
expires and system resets. If someone needs watchdog in their design please
enable it by hand.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Ashok Reddy Soma [Tue, 3 Aug 2021 05:20:46 +0000 (23:20 -0600)]
mmc: zynq_sdhci: Use set_control_reg from sdhci.c
Since set_control_reg is available in sdhci.c, use it and remove
arasan_sdhci_set_control_reg().
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
T Karthik Reddy [Tue, 3 Aug 2021 05:20:45 +0000 (23:20 -0600)]
mmc: zynq_sdhci: Wait till sd card detect state is stable
As per SD spec when SD host controller is reset, it takes 1000msec
to detect the card state. In case, if we enable the sd bus voltage &
card detect state is not stable, then host controller will disable
the sd bus voltage.
In case of warm/subsystem reboot, due to unstable card detect state
host controller is disabling the sd bus voltage to sd card causing
sd card timeout error. So we wait for a maximum of 1000msec to get
the card detect state stable before we enable the sd bus voltage.
This current fix is workaround for now, this needs to be analysed
further. Zynqmp platform should behave the same as Versal, but we
did not encounter this issue as of now. So we are fixing it for
Versal only.
Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Ashok Reddy Soma [Tue, 3 Aug 2021 05:20:44 +0000 (23:20 -0600)]
mmc: zynq_sdhci: Move setting tapdelay code to driver
Move tapdelay function calls to zynq_sdhci.c and make them static
inline. zynqmp_tap_delay.h has function prototypes for the functions
defined in tap_delays.c, which will not be needed anymore.
Remove tap_delays.c and zynqmp_tap_delay.h files.
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Ashok Reddy Soma [Tue, 3 Aug 2021 05:20:43 +0000 (23:20 -0600)]
mmc: zynq_sdhci: Add xilinx_pm_request() method to set tapdelays
Currently xilinx sdhci driver is using zynqmp_mmio_write() to set
tapdelay values and DLL resets. Continue to use this for SPL and mini
U-Boot where U-Boot will be executed at EL3 level.
Use firmware call xilinx_pm_request() using appropriate arguments to
set input/output tapdelays and also for DLL resets in regular flow(EL2).
Host driver should explicitly request DLL reset before ITAP (assert DLL)
and after OTAP (release DLL) to avoid issues in some cases. Also handle
error return where possible.
Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Tom Rini [Wed, 25 Aug 2021 11:48:06 +0000 (07:48 -0400)]
Merge branch 'next-socfpga' of https://github.com/tienfong/uboot_mainline
Siew Chin Lim [Tue, 10 Aug 2021 03:26:42 +0000 (11:26 +0800)]
arm: socfpga: Enable Intel N5X device build
Add defconfig for N5X to support legacy, ATF and VAB boot flow.
Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Siew Chin Lim [Tue, 10 Aug 2021 03:26:41 +0000 (11:26 +0800)]
include: configs: Add Intel N5X device CONFIGs
Add CONFIGs for N5X.
Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Siew Chin Lim [Tue, 10 Aug 2021 03:26:40 +0000 (11:26 +0800)]
arm: dts: Add base dtsi and devkit dts for Intel N5X device
Add device tree for N5X.
Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
Reviewed-by: Ley Foon Tan <lftan.linux@gmail.com>
Siew Chin Lim [Tue, 10 Aug 2021 03:26:39 +0000 (11:26 +0800)]
board: intel: Add socdk board support for Intel N5X device
Add N5X SoC devkit board.
Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Siew Chin Lim [Tue, 10 Aug 2021 03:26:38 +0000 (11:26 +0800)]
arm: socfpga: Add SPL for Intel N5X device
Add SPL for N5X.
Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Tien Fong Chee [Tue, 10 Aug 2021 03:26:37 +0000 (11:26 +0800)]
ddr: altera: Add SDRAM driver for Intel N5X device
The DDR subsystem in Diamond Mesa is consisted of controller, PHY,
memory reset manager and memory clock manager.
Configuration settings of controller, PHY and memory reset manager
is come from DDR handoff data in bitstream, which contain the register
base addresses and user settings from tool.
Configuration settings of memory clock manager is come from the HPS
handoff data in bitstream, however the register base address is defined
in device tree.
The calibration is fully done in HPS, which requires IMEM and DMEM
binaries loading to PHY SRAM for running this calibration, both
IMEM and DMEM binaries are also part of bitstream, this bitstream
would be loaded to OCRAM by SDM, and configured by DDR driver.
Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
Tien Fong Chee [Tue, 10 Aug 2021 03:26:36 +0000 (11:26 +0800)]
ddr: socfpga: Enable memory test on memory size less than 1GB
Minimum 1GB memory size is required in current memory test, so this patch
improves the memory test for processing memory size less than 1GB, and
the size in power of two.
Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
Siew Chin Lim [Tue, 10 Aug 2021 03:26:35 +0000 (11:26 +0800)]
arm: socfpga: Changed misc_s10.c to misc_soc64.c
Rename to common file name to used by all SOC64 devices.
No functionality change.
Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Siew Chin Lim [Tue, 10 Aug 2021 03:26:34 +0000 (11:26 +0800)]
arm: socfpga: Add clock manager for Intel N5X device
Add clock manager for N5X.
Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Siew Chin Lim [Tue, 10 Aug 2021 03:26:33 +0000 (11:26 +0800)]
arm: socfpga: Move cm_get_mpu_clk_hz function declaration to clock_manager.h
Move cm_get_mpu_clk_hz function declaration from individual device's
clock manager header file to common clock_manager.h.
Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Siew Chin Lim [Tue, 10 Aug 2021 03:26:32 +0000 (11:26 +0800)]
drivers: clk: Add memory clock driver for Intel N5X device
Add memory clock manager driver for N5X. Provides memory clock
initialization and enable functions.
Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Siew Chin Lim [Tue, 10 Aug 2021 03:26:31 +0000 (11:26 +0800)]
arm: socfpga: Get clock manager base address for Intel N5X device
Add N5X clock manager to socfpga_get_managers_addr function.
Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Siew Chin Lim [Tue, 10 Aug 2021 03:26:30 +0000 (11:26 +0800)]
drivers: clk: Add clock driver for Intel N5X device
Add clock manager driver for N5X. Provides clock initialization
and get_rate functions.
Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Tien Fong Chee [Tue, 10 Aug 2021 03:26:29 +0000 (11:26 +0800)]
arm: socfpga: Add handoff data support for Intel N5X device
N5X support both HPS handoff data and DDR handoff data.
Existing HPS handoff functions are restructured to support both existing
devices and N5X device.
Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
Siew Chin Lim [Tue, 10 Aug 2021 03:26:28 +0000 (11:26 +0800)]
arm: socfpga: Add base address for Intel N5X device
Reuse base_addr_soc64.h for Intel N5X device, the address is the
same as Agilex.
Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Siew Chin Lim [Tue, 10 Aug 2021 03:26:27 +0000 (11:26 +0800)]
arm: socfpga: Changed base_addr_s10.h to base_addr_soc64.h
Rename to common file name to used by all SOC64 devices and change
"_S10_" to "_SOC64_" in base_addr_soc64.h.
Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Siew Chin Lim [Tue, 10 Aug 2021 03:26:26 +0000 (11:26 +0800)]
arm: socfpga: Move linux_qspi_enable from bootcommand to board_prep_linux function
Move 'linux_qspi_enable' from bootcommand to board_prep_linux function when
OS booted from FIT image for Stratix 10 and Agilex. This flow is common for
all Intel SOC64 devices.
U-Boot will update 'fdt_addr' environment value based on FIT image in
board_prep_linux function, and 'linux_qspi_enable' will refer to 'fdt_addr'
environment value to retrieve the device tree node.
Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Tom Rini [Mon, 23 Aug 2021 16:44:12 +0000 (12:44 -0400)]
Merge tag 'efi-2021-10-rc3' of https://source.denx.de/u-boot/custodians/u-boot-efi
Pull request for efi-2021-10-rc3
Documentation:
* Rename Freescale to NXP
* Document structures used for the UEFI TCG2 protocol
UEFI:
* Device paths must use EfiBootServicesData
Tom Rini [Mon, 23 Aug 2021 13:17:32 +0000 (09:17 -0400)]
Merge https://gitlab.denx.de/u-boot/custodians/u-boot-fsl-qoriq
fsl-qoriq: Fixes related to env, spi, usb, crypto, configs, distro-boot
for Layerscape Boards like lx2, sl28, ls2088ardb.
powerpc: Fixes for t208xrdb revd board and cortina related configs
update for T208xRDB, T4240RDB.
Tom Rini [Mon, 23 Aug 2021 13:17:07 +0000 (09:17 -0400)]
Merge tag 'for-v2021.10-rc3' of https://source.denx.de/u-boot/custodians/u-boot-i2c
i2c changes for for-v2021.10-rc3
new driver:
- Introduce mcp230xx support
from Sebastian Reichel
new feature:
- i2c-gpio: add support for "sda-gpios" + "scl-gpios" i2c-gpio bindings.
from Samuel Holland
- bootcount: add a new driver with syscon as backend
from Nandor Han
Tom Rini [Sun, 22 Aug 2021 19:44:53 +0000 (15:44 -0400)]
Merge branch '2021-08-21-assorted-changes'
Nandor Han [Thu, 10 Jun 2021 12:40:38 +0000 (15:40 +0300)]
bootcount: add a new driver with syscon as backend
The driver will use a syscon regmap as backend and supports both
16 and 32 size value. The value will be stored in the CPU's endianness.
Signed-off-by: Nandor Han <nandor.han@vaisala.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Samuel Holland [Sun, 22 Aug 2021 00:25:43 +0000 (19:25 -0500)]
i2c: i2c-gpio: Support the named GPIO binding
To avoid confusion about the order of the GPIOs, the i2c-gpio binding
was updated to use a separate property for each GPIO instead of an
array. However, the driver only supports the old binding. Add support
for the new binding as well, so the driver continues to work as device
trees are updated.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
Sebastian Reichel [Thu, 15 Jul 2021 15:40:00 +0000 (17:40 +0200)]
gpio: mcp230xx: Introduce new driver
Introduce driver for I2C based MCP230xx GPIO chips, which are
quite common and already well supported by the Linux kernel.
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Sebastian Reichel [Thu, 15 Jul 2021 15:39:59 +0000 (17:39 +0200)]
i2c: add dm_i2c_reg_clrset
Add function to apply a bitmask to an i2c register, so
that specific bits can be cleared and/or set.
Suggested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Matwey V. Kornilov [Thu, 5 Aug 2021 21:22:58 +0000 (00:22 +0300)]
display_options: Do not use %llu in print_size
tiny-printf variant doesn't know how to handle %llu format string, but both
tiny-printf and print_size can meet in SPL when TFTP is used to obtain main
u-boot image. This is known to lead to critical boot issue at AM335x platform
when printf is catched in infinite loop.
To avoid such issues and make print_size function tiny-printf friendly, use %u
instead of %luu. Note, that the size value is guaranteed to be less than 1024
in this conditional branch, so the cast to unsigned int is safe.
Signed-off-by: Matwey V. Kornilov <matwey.kornilov@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Matwey V. Kornilov [Thu, 5 Aug 2021 19:06:05 +0000 (22:06 +0300)]
tiny-printf: Handle %pM format when CONFIG_SPL_NET_SUPPORT is enabled
%pM format string is used to print MAC-address and this is required while SPL
network boot.
This patch fixes the SPL boot issues like the following:
Trying to boot from USB eth
## Error: flags type check failure for "ethaddr" <= "40309614M" (type: m)
## Error inserting "ethaddr" variable, errno=1
eth0: eth_cpsw## Error: flags type check failure for "eth1addr" <=
"81f01114M" (type: m)
## Error inserting "eth1addr" variable, errno=1
, eth1: usb_ether
eth_cpsw Waiting for PHY auto negotiation to complete......... TIMEOUT !
Problem booting with BOOTP
SPL: failed to boot from all boot devices
### ERROR ### Please RESET the board ###
Signed-off-by: Matwey V. Kornilov <matwey.kornilov@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Oleh Kravchenko [Wed, 19 May 2021 10:31:31 +0000 (13:31 +0300)]
Fix flashing of eMMC user area with Fastboot
'gpt' and 'mmc0' fastboot partitions have been treated as the same device,
but it is wrong.
Fill disk_partition structure with eMMC user partition info
to properly flash data.
Signed-off-by: Oleh Kravchenko <oleg@kaa.org.ua>
Cc: Pantelis Antoniou <panto@antoniou-consulting.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Sean Anderson <sean.anderson@seco.com>
Cc: Tom Rini <trini@konsulko.com>
Reviewed-by: Sean Anderson <sean.anderson@seco.com>
Oleh Kravchenko [Fri, 14 May 2021 21:06:21 +0000 (00:06 +0300)]
Fix flash and erase of eMMC Boot2 with Fastboot
The current U-Boot version has the next matches for boot partitions:
> mmc0boot0 to EMMC_BOOT1
> mmc0boot1 to EMMC_BOOT1 (should be EMMC_BOOT2)
This patch fixes a typo for the boot partition number.
Signed-off-by: Oleh Kravchenko <oleg@kaa.org.ua>
Cc: Pantelis Antoniou <panto@antoniou-consulting.com>
Cc: Marek Vasut <marex@denx.de>
Reviewed-by: Sean Anderson <sean.anderson@seco.com>
Adam Ford [Fri, 4 Jun 2021 17:26:06 +0000 (12:26 -0500)]
clk: clk_versaclock: Add support for versaclock driver
The driver is based on the Versaclock driver from the Linux code, but
due differences in the clock API between them, some pieces had to be
changed.
This driver creates a mux, pfd, pll, and a series of fod ouputs.
Rate Usecnt Name
------------------------------------------
25000000 0 `-- x304-clock
25000000 0 `-- clock-controller@6a.mux
25000000 0 |-- clock-controller@6a.pfd
2800000000 0 | `-- clock-controller@6a.pll
33333333 0 | |-- clock-controller@6a.fod0
33333333 0 | | `-- clock-controller@6a.out1
33333333 0 | |-- clock-controller@6a.fod1
33333333 0 | | `-- clock-controller@6a.out2
50000000 0 | |-- clock-controller@6a.fod2
50000000 0 | | `-- clock-controller@6a.out3
125000000 0 | `-- clock-controller@6a.fod3
125000000 0 | `-- clock-controller@6a.out4
25000000 0 `-- clock-controller@6a.out0_sel_i2cb
A translation function is added so the references to <&versaclock X> get routed
to the corresponding clock-controller@6a.outX.
Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Sean Anderson <sean.anderson@seco.com>
Priyanka Jain [Wed, 18 Aug 2021 07:07:03 +0000 (12:37 +0530)]
configs: lx2160a: load device-tree in RAM for distro boot
Update boot-commands to load device-tree from
boot-device at 'fdt_addr_r' address in DDR
during distro-boot.
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Tom Rini [Thu, 19 Aug 2021 12:23:01 +0000 (08:23 -0400)]
Merge https://source.denx.de/u-boot/custodians/u-boot-riscv
Horia Geantă [Tue, 10 Aug 2021 14:12:19 +0000 (17:12 +0300)]
crypto/fsl: fix missed dma_addr_t -> caam_dma_addr_t conversion
One of the "dma_addr_t" instances was left out when
converting to "caam_dma_addr_t".
Fixes:
2ff17d2f74c5 ("crypto: fsl: refactor for 32 bit version CAAM support on ARM64")
Signed-off-by: Horia Geantă <horia.geanta@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Kuldeep Singh [Tue, 10 Aug 2021 05:50:11 +0000 (11:20 +0530)]
board: T4240rdb: Extend cs4340_get_fw_addr() functionality
T4240RDB supports booting from 2 nor banks(default and altbank). The
corresponding defconfig can only have one entry defined and therefore,
extend cs4340_get_fw_addr() function to overwrite firmware address which
will be later used in cortina firmware.
Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Kuldeep Singh [Tue, 10 Aug 2021 05:50:10 +0000 (11:20 +0530)]
board: t208x: Extend cs4340_get_fw_addr() functionality
T2080RDB supports booting from 2 nor banks(default and altbank). The
corresponding defconfig can only have one entry defined and therefore,
extend cs4340_get_fw_addr() function to overwrite firmware address which
will be later used in cortina firmware.
Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Kuldeep Singh [Tue, 10 Aug 2021 05:50:09 +0000 (11:20 +0530)]
board: ls2088ardb: Extend cs4340_get_fw_addr() functionality
LS2088A-RDB supports TFA boot source and has 2 nor banks(default and
altbank) and QSPI as boot source. The corresponding defconfig can only
have one entry defined and therefore, extend cs4340_get_fw_addr()
function to overwrite firmware address which will be later used in
cortina firmware.
Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Kuldeep Singh [Tue, 10 Aug 2021 05:50:08 +0000 (11:20 +0530)]
net: cortina: Add support for tfa boot in cortina firmware
Add support for boards supporting TFA boot separately in cortina
firmware. Please note, a weak function is defined to retrieve firmware
address values as CONFIG_CORTINA_FW_ADDR is now defined in defconfig and
can only have one possible value defined. This weak function will help
in overwrting the values to get proper addresses as per boot source.
Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Kuldeep Singh [Tue, 10 Aug 2021 05:50:07 +0000 (11:20 +0530)]
configs: Migrate CORTINA_FW_ADDR and CORTINA_FW_LENGTH to Kconfig
Use moveconfig.py script to convert below defines to Kconfig and move
these entries to defconfigs.
CONFIG_CORTINA_FW_ADDR
CONFIG_CORTINA_FW_LENGTH
Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Kuldeep Singh [Tue, 10 Aug 2021 05:50:06 +0000 (11:20 +0530)]
env: Kconfig: Add default option for PHY_CORTINA
Add PHY_CORTINA as default option in SYS_MMC_ENV_DEV Kconfig entry as
PHY_CORTINA require SYS_MMC_ENV_DEV value similar to FMAN_ENET or QE.
This helps in resolving compilation failure.
Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Wasim Khan [Mon, 2 Aug 2021 08:34:52 +0000 (10:34 +0200)]
armv8: fsl : create bootcmd and mcinitcmd as per boot source
NXP platforms expect custom bootcmd and mcinitcmd to be
updated as per boot source with default environment.
Check env variable fsl_bootcmd_mcinitcmd_set to prepare
bootcmd and mcinitcmd
Fixes:
cbf77d201870 (armv8: fsl-layerscape: Fix automatic
setting of bootmcd with TF-A)
Signed-off-by: Wasim Khan <wasim.khan@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Kshitiz Varshney [Sun, 1 Aug 2021 12:31:45 +0000 (14:31 +0200)]
board: fsl_validate: Fix resource leak issue
Free dynamically allocated memory before every return statement
in calc_img_key_hash() and calc_esbchdr_esbc_hash() function.
Verified the secure boot changes using ls1046afrwy board.
Signed-off-by: Kshitiz Varshney <kshitiz.varshney@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Camelia Groza [Thu, 29 Jul 2021 16:31:20 +0000 (19:31 +0300)]
board: freescale: t208xrdb: enable Power-On Reset for rev D boards
Starting with board revision D, the MISCCSR CPLD register needs to be
configured to enable Power-on Reset for software reset commands.
Signed-off-by: Camelia Groza <camelia.groza@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Kuldeep Singh [Wed, 28 Jul 2021 08:35:59 +0000 (14:05 +0530)]
lx2160a: Enable CONFIG_SPI_FLASH_MT35XU for lx2160a-rdb/qds
LX2160A-RDB/QDS has micron mt35xu512aba flash which requires flag
CONFIG_SPI_FLASH_MT35XU on to probe flash successfully.
Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Michael Walle [Mon, 26 Jul 2021 20:08:44 +0000 (22:08 +0200)]
board: sl28: drop unneeded and outdated flash partitions
This board doesn't use the MTD subsystem in u-boot, thus there is no
need to specify the partitions. They are outdated anyway. Just drop
them.
Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Tom Rini [Wed, 21 Jul 2021 22:53:20 +0000 (18:53 -0400)]
arm: Finish migration of HAS_FSL_XHCI_USB
This symbol was largely migrated, except for one case. Update it.
Cc: Priyanka Jain <priyanka.jain@nxp.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Michael Walle [Mon, 26 Jul 2021 19:35:28 +0000 (21:35 +0200)]
spi: nxp_fspi: Ensure width is respected in spi-mem operations
Import linux commit
007773e16a6f ("spi: nxp-fspi: Ensure width is
respected in spi-mem operations") to fix SPI access on boards which
don't have all SPI I/O lines connected to the flash.
Since commit
71025f013ccb ("mtd: spi-nor-core: Rework hwcaps selection")
u-boot figures out the capabilities by looking at spi_mem_supports_op().
The FlexSPI driver doesn't take the board layout into account. Fix that.
Fixes:
383fded70c4f ("spi: nxp_fspi: new driver for the FlexSPI controller")
Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Pratyush Yadav <p.yadav@ti.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Heinrich Schuchardt [Tue, 17 Aug 2021 14:15:34 +0000 (16:15 +0200)]
efi_loader: use EfiBootServicesData for DP to text
Memory allocated in the implementation of the
EFI_DEVICE_PATH_TO_TEXT_PROTOCOL must be of type EfiBootServicesData.
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Heinrich Schuchardt [Tue, 17 Aug 2021 13:15:23 +0000 (15:15 +0200)]
efi_loader: use EfiBootServicesData for device path
dp_alloc() was using a constant from the wrong enum resulting in creating
device paths in EfiReservedMemory.
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Heinrich Schuchardt [Tue, 17 Aug 2021 13:05:31 +0000 (15:05 +0200)]
efi_loader: use correct type for AllocatePages, AllocatePool
Use enum efi_memory_type and enum_allocate_type in the definitions of the
efi_allocate_pages(), efi_allocate_pool().
In the external UEFI API leave the type as int as the UEFI specification
explicitely requires that enums use a 32bit type.
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Heinrich Schuchardt [Tue, 17 Aug 2021 13:02:23 +0000 (15:02 +0200)]
efi_loader rename enum efi_mem_type to efi_memory_type
Use the same name as in the UEFI specification to avoid confusion.
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Heinrich Schuchardt [Tue, 17 Aug 2021 12:52:16 +0000 (14:52 +0200)]
efi_loader: use an enum for the memory allocation types
For type checking we need an enum.
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Masahisa Kojima [Fri, 13 Aug 2021 07:12:43 +0000 (16:12 +0900)]
efi_loader: add comment for efi_tcg2.h
This commit adds the comment of the TCG Specification
efi_tcg2.h file refers, and comment for the structure.
Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Heinrich Schuchardt [Mon, 16 Aug 2021 17:46:38 +0000 (19:46 +0200)]
doc: move doc/board/st/st.rst
'make htmldocs' does not use file doc/board/st/st.rst because the name
matches the directory name. Let's rename it to st-dt.rst.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Heinrich Schuchardt [Mon, 16 Aug 2021 06:18:37 +0000 (08:18 +0200)]
doc: rename Freescale to NXP
Freescale Semiconductor, Inc. was merged into NXP Semiconductors in 2015.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Heinrich Schuchardt [Mon, 16 Aug 2021 05:54:10 +0000 (07:54 +0200)]
doc: move i.MX7D/i.MX8MM A/B booting to board specific
Having "i.MX7D/i.MX8MM SRC_GPR10 PERSIST_SECONDARY_BOOT for bootloader A/B
switching" at the top level of the documentation tree does not make sense.
Move it to board specific information.
Fixes:
59e3d1bd4992 ("doc: imx: psb: Document usage of SRC_GPR10 PERSIST_SECONDARY_BOOT for A/B switching")
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Tom Rini [Tue, 17 Aug 2021 13:39:22 +0000 (09:39 -0400)]
Merge https://source.denx.de/u-boot/custodians/u-boot-tegra
Zong Li [Tue, 27 Jul 2021 09:06:59 +0000 (17:06 +0800)]
board: sifive: overwrite board_fdt_blob_setup in u-boot proper
Add board_fdt_blob_setup to return the device tree location which is
passed by prior stage in u-boot proper. The generic board_fdt_blob_setup
always returns _end, it mignt be ok because u-boot SPL would currently
put the dtb there, but it would be broken if we put the dtb to another
place and assigned the location into a1 register for u-boot proper. Use
the location passed by prior stage would make more sence, because we
actually pass the location to u-boot proper and want to use that one,
rather than the dtb which in _end.
We can't use CONFIG_OF_PRIOR_STAGE because it doens't distinguish the
implementation of u-boot SPL and u-boot proper, so u-boot SPL need to
reply on the prior stage to pass device tree location as well, but we
don't pass the DT from boot rom now. In addition, when
CONFIG_OF_PRIOR_STAGE is enabled, the u-boot-spl.bin and u-boot.itb won't
include the device tree.
Signed-off-by: Zong Li <zong.li@sifive.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Zong Li [Tue, 27 Jul 2021 09:06:58 +0000 (17:06 +0800)]
board: sifive: compile stuff only related to SPL in SPL build
As (
3581811dc26f "riscv: sifive/fu540: Move SPL related functions to spl.c"),
we put the SPL stuff in spl.c, we don't need to compile unleashed.c and
unmatched.c in SPL build.
Signed-off-by: Zong Li <zong.li@sifive.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Zong Li [Mon, 2 Aug 2021 07:34:14 +0000 (15:34 +0800)]
riscv: cpu: fu740: Fix typo of date
Fixed the typo of date of copyright declaration.
Signed-off-by: Zong Li <zong.li@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Dimitri John Ledkov [Mon, 26 Jul 2021 10:20:17 +0000 (11:20 +0100)]
qemu-riscv64_smode: fix extlinux (define preboot)
Commit
37304aaf60bf ("Convert CONFIG_USE_PREBOOT and CONFIG_PREBOOT to
Kconfig") removed preboot commands in RISC-V targets and broke
extlinux support as reported by Fu Wei <wefu@redhat.com>.
The patch finishes migration of CONFIG_USE_PREBOOT and CONFIG_REBOOT
to Kconfig.
Fixes:
37304aaf60bf ("Convert CONFIG_USE_PREBOOT and CONFIG_PREBOOT to Kconfig")
Reported-By: Fu Wei <wefu@redhat.com>
Signed-off-by: David Abdurachmanov <david.abdurachmanov@sifive.com>
Signed-off-by: Dimitri John Ledkov <dimitri.ledkov@canonical.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Marcel Ziswiler [Wed, 11 Aug 2021 13:12:56 +0000 (15:12 +0200)]
board: apalis-tk1: launch toradex easy installer in usb recovery
The USB recovery mode is used by Toradex to load the Toradex Easy
Installer image which supports further system images installation.
Prepare for loading and launching the Toradex Easy Installer if the
USB Recovery mode is activated.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Signed-off-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Tom Rini [Mon, 16 Aug 2021 18:18:45 +0000 (14:18 -0400)]
Prepare v2021.10-rc2
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Mon, 16 Aug 2021 13:35:24 +0000 (09:35 -0400)]
configs: Resync with savedefconfig
Rsync all defconfig files using moveconfig.py
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Mon, 16 Aug 2021 13:31:00 +0000 (09:31 -0400)]
Merge https://source.denx.de/u-boot/custodians/u-boot-stm
Highlights:
- Handle TF-A boot with FIP for STM32MP1
- Fix board_get_usable_ram_top(0) for STM32MP1
- DT alignement with kernel v5.14 for STM32MP1
- SPI-NOR DT update for DHSOM
- Add UCLASS API for ECDSA singnature and implement it for STM32MP1
Alexandru Gagniuc [Thu, 29 Jul 2021 16:47:19 +0000 (11:47 -0500)]
test: dm: Add test for ECDSA UCLASS support
This test verifies that ECDSA_UCLASS is implemented, and that
ecdsa_verify() works as expected. The definition of "expected" is
"does not find a device, and returns -ENODEV".
The lack of a hardware-independent ECDSA implementation prevents us
from having one in the sandbox, for now.
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Alexandru Gagniuc [Thu, 29 Jul 2021 16:47:18 +0000 (11:47 -0500)]
Kconfig: FIT_SIGNATURE should not select RSA_VERIFY
FIT signatures can now be implemented with ECDSA. The assumption that
all FIT images are signed with RSA is no longer valid. Thus, instead
of 'select'ing RSA, only 'imply' it. This doesn't change the defaults,
but allows one to explicitly disable RSA support.
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Igor Opaniuk <igor.opaniuk@foundries.io>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Alexandru Gagniuc [Thu, 29 Jul 2021 16:47:17 +0000 (11:47 -0500)]
arm: stm32mp1: Implement ECDSA signature verification
The STM32MP ROM provides several service. One of them is the ability
to verify ecdsa256 signatures. Hook the ROM API into the ECDSA uclass.
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Alexandru Gagniuc [Thu, 29 Jul 2021 16:47:16 +0000 (11:47 -0500)]
lib: ecdsa: Implement UCLASS_ECDSA verification on target
Implement the crypto_algo .verify() function for ecdsa256. Because
it backends on UCLASS_ECDSA, this change is focused on parsing the
keys from devicetree and passing this information to the specific
UCLASS driver.
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Alexandru Gagniuc [Thu, 29 Jul 2021 16:47:15 +0000 (11:47 -0500)]
dm: crypto: Define UCLASS API for ECDSA signature verification
Define a UCLASS API for verifying ECDSA signatures. Unlike
UCLASS_MOD_EXP, which focuses strictly on modular exponentiation,
the ECDSA class focuses on verification. This is done so that it
better aligns with mach-specific implementations, such as stm32mp.
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Marek Vasut [Mon, 9 Aug 2021 12:06:04 +0000 (14:06 +0200)]
ARM: dts: stm32: Reduce DHCOR SPI NOR frequency to 50 MHz
The SPI NOR is a bit further away from the SoC on DHCOR than on DHCOM,
which causes additional signal delay. At 108 MHz, this delay triggers
a sporadic issue where the first bit of RX data is not received by the
QSPI controller.
There are two options of addressing this problem, either by using the
DLYB block to compensate the extra delay, or by reducing the QSPI bus
clock frequency. The former requires calibration and that is overly
complex for SPL, so opt for the second option. This incurs 20ms delay
during boot, when SPL loads U-Boot to DRAM.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrice Chotard <patrice.chotard@foss.st.com>
Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Marek Vasut [Mon, 9 Aug 2021 12:08:11 +0000 (14:08 +0200)]
ARM: stm32: Set environment sector size to 4k on DHSOM
The DHSOM SPI NOR is using 4k erase blocks, make use of it
and define the default environment sector size to 4k.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrice Chotard <patrice.chotard@foss.st.com>
Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Patrick Delaunay [Tue, 27 Jul 2021 10:15:12 +0000 (12:15 +0200)]
arm: dts: stm32mp15: alignment with v5.14
Device tree alignment with Linux kernel v5.14-rc3
- ARM: dts: stm32: move stmmac axi config in ethernet node on stm32mp15
- ARM: dts: stm32: Configure qspi's mdma transfer to block for stm32mp151
- ARM: dts: stm32: add a new DCMI pins group on stm32mp15
- ARM: dts: stm32: fix ltdc pinctrl on microdev2.0-of7
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Patrick Delaunay [Mon, 26 Jul 2021 09:55:27 +0000 (11:55 +0200)]
stm32mp: correctly handle board_get_usable_ram_top(0)
The function board_get_usable_ram_top can be called after relocation
with total_size = 0 to get the uppermost pointer that is valid to access
in U-Boot.
When total_size = 0, the reserved memory should be not take in account
with lmb library and 'gd->ram_base + gd->ram_size' can be used.
It is the case today in lib/efi_loader/efi_memory.c:efi_add_known_memory()
and this patch avoids that the reserved memory for OP-TEE is not part of
the EFI available memory regions.
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Patrick Delaunay [Mon, 26 Jul 2021 09:21:38 +0000 (11:21 +0200)]
stm32mp1: stm32prog: remove stm32prog_get_tee_partitions with FIP
The MTD tee partitions used to save the OP-TEE binary are needed when
TF-A doesn't use the FIP container to load binaries.
This patch puts under CONFIG_STM32MP15x_STM32IMAGE flag the associated
code in U-Boot binary and prepare the code cleanup when
CONFIG_STM32MP15x_STM32IMAGE support will be removed after TF-A migration
to FIP support.
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>