mesa: fix typo from adding glGetObjectLabelEXT

Fixes:  675bcbb7a1c0 ("mesa: add EXT_debug_label support")

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19607>

docs: update calendar for 22.3.0-rc2

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19631>

ci/iris: Add some flakes from the new testing on JSL.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19628>

intel/fs: Enable nir_op_imul_32x16 and nir_op_umul_32x16 on pre-Gfx7

Even though Intel's CI doesn't test these old platforms anymore, the
validation added in "intel/eu/validate: Validate integer multiplication
source size restrictions" combined with full shader-db runs gives me
confidence in the changes.

Sandy Bridge
total instructions in shared programs: 13902341 -> 13902167 (<.01%)
instructions in affected programs: 30771 -> 30597 (-0.57%)
helped: 66 / HURT: 0

total cycles in shared programs: 741795500 -> 741791931 (<.01%)
cycles in affected programs: 987602 -> 984033 (-0.36%)
helped: 28 / HURT: 5

Iron Lake
total instructions in shared programs: 8365806 -> 8365754 (<.01%)
instructions in affected programs: 1766 -> 1714 (-2.94%)
helped: 10 / HURT: 0

total cycles in shared programs: 248542694 -> 248542378 (<.01%)
cycles in affected programs: 29836 -> 29520 (-1.06%)
helped: 9 / HURT: 0

GM45
total instructions in shared programs: 5187127 -> 5187101 (<.01%)
instructions in affected programs: 891 -> 865 (-2.92%)
helped: 5 / HURT: 0

total cycles in shared programs: 163643914 -> 163643750 (<.01%)
cycles in affected programs: 22206 -> 22042 (-0.74%)
helped: 5 / HURT: 0

Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19602>

intel/fs: Slightly restructure emitting nir_op_imul_32x16 and nir_op_umul_32x16

There are no immediate values at this point, so all of this code was
bunk. :face_palm:

Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19602>

intel/eu/validate: Validate integer multiplication source size restrictions

v2: Expect correct result on BDW in test_eu.

v3: Fix SNB type-size check. Noticed by Marcin.

Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19602>

intel/compiler: Fix signed integer range analysis of imax and imin

Some review feedback of an earlier commit caused me to rearrange some
code quite a bit. I wasn't paying enough attention while applying the
later commits, and these breaks should have been returns. As it is, the
result of the imin or imax analysis is overwritten by the default case
handling... effectively the original commit does nothing. :(

Tiger Lake and Ice Lake had similar results. (Ice Lake shown)
total instructions in shared programs: 19914090 -> 19904772 (-0.05%)
instructions in affected programs: 121258 -> 111940 (-7.68%)
helped: 445 / HURT: 0

total cycles in shared programs: 855291535 -> 855266659 (<.01%)
cycles in affected programs: 2737005 -> 2712129 (-0.91%)
helped: 426 / HURT: 17

LOST:   0
GAINED: 3

Skylake and Broadwell had similar results. (Skylake shown)
total cycles in shared programs: 842395356 -> 842338259 (<.01%)
cycles in affected programs: 5460985 -> 5403888 (-1.05%)
helped: 458 / HURT: 0

Haswell and Ivy Bridge had similar results. (Haswell shown)
total instructions in shared programs: 16710449 -> 16708449 (-0.01%)
instructions in affected programs: 44101 -> 42101 (-4.54%)
helped: 75 / HURT: 0

total cycles in shared programs: 882760230 -> 882727923 (<.01%)
cycles in affected programs: 2867797 -> 2835490 (-1.13%)
helped: 62 / HURT: 10

No shader-db change on any other Intel platform.

No fossil-db changes on any Intel platform.

Fixes: 5ec75ca10d3 ("intel/compiler: Teach signed integer range analysis about imax and imin")
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19602>

drm-shim/nouveau: fix the shim to work with nvif ioctl.

The new nouveau code asks the kernel for supported class,
this needs the new nvif interface, so stub it up using
the old code.

unfortunately this also needs a clang warning turned off
so the gnu extension this code needs is enabled in meson

Reviewed-by: M Henning <drawoc@darkrefraction.com>
Acked-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17633>

gv100/ir: noop OP_BAR for now

Let's get stuff rolling and deal with figuring this out later.

Acked-by: M Henning <drawoc@darkrefraction.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17633>

nvc0: fix ga10x compute launch

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Acked-by: M Henning <drawoc@darkrefraction.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17633>

nvc0: no tex cb mthd on ga10x

I somewhat expect this isn't necessary on Volta and newer too, as the
index is coded into shaders now, but, HW doesn't complain, so leave it.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Acked-by: M Henning <drawoc@darkrefraction.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17633>

nvc0: recognise ga10x chipsets

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Acked-by: M Henning <drawoc@darkrefraction.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17633>

nvc0: properly allocate copy engine class before using it

Important for upcoming kernel changes to more correctly manage the CE
context on Volta and newer, or the channel will be killed in response
to a CTXNOTVALID error from the GPU.

The kernel will have a workaround for Volta and Turing GPUs to preserve
ABI, but will require userspace to behave correctly on Ampere and newer.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Acked-by: M Henning <drawoc@darkrefraction.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17633>

nvc0: lookup supported classes instead of determining from chipset

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Acked-by: M Henning <drawoc@darkrefraction.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17633>

broadcom/compiler: avoid using ldvary sequence to hide latency of branching

This can cause us to stomp the contents of r5 before we have a chance to read
it, like this:

0x3d103186bb800000 nop                           ; nop                         ; ldvary.r0
0x3d105686bbf40000 nop                           ; mov rf26, r5                ; ldvary.r1
0x020000ef0000d000 bu.allna  232, r:unif (0x0000001c / 0.000000)
0x3d1096c6bbf40000 nop                           ; mov rf27, r5                ; ldvary.r2

Here, the MOV in the last instruction is supposed to read r5 produced from
ldvary.r0, but because we have inserted the bu instruction in between now
that read happens at the same time that ldvary.r1 updates r5, stomping the
value we were supposed to read.

Fix this by disallowing injection of a branch instruction in between an ldvary
instruction and its write to the r5 register 2 instructions later.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7062
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
cc: mesa-stable

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19616>

nir/lower_io_to_vector: Demote the old scalar vars to globals.

This prevents nir_lower_io_to_temporaries from emitting new writes to the
old globals that we meant to have disappear through
DCE/remove_unused_variables.  If you don't do this, then unless you call
nir_opt_undef() and it successfully catches io_to_temps' new writes of
undefs to the scalar components, the scalar vars will stick around and
have stores that conflict with the real vector vars.

This hasn't been a problem for the end result of codegen because
nir_opt_undef() did succeed.  However, things went south with vars_to_ssa
mediump lowering, which obscured the result from opt_undef.  And, it's
really mind-bending to see undef writes to the outputs for a chunk of the
shader compiler pipeline anyway.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18218>

intel: Don't cross DWORD boundaries with byte scratch load/store

The back-end swizzles dwords so that our indirect scratch messages match
the memory layout of spill/fill messages for better cache coherency.
The swizzle happens at a DWORD granularity.  If a read or write crosses
a DWORD boundary, the first bit will get correctly swizzled but whatever
piece lands in the next dword will not because the scatter instructions
assume sequential addresses for all bytes.  For DWORD writes, this is
handled naturally as part of scalarizing.  For smaller writes, we need
to be sure that a single write never escapes a dword.

Fixes: fd04f858b0aa ("intel/nir: Don't try to emit vector load_scratch instructions")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7364
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19580>

intel/lower_mem_access_bit_sizes: Compute alignments automatically

Because dup_mem_intrinsic() retains the SSA offset from the original
intrinsic and only modifies it by adding a constant, we can compute the
alignment based on the original alignment and the constant offset.  This
is both easier and more accurate.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19580>

vulkan/wsi/display: Reset connector state in vkReleaseDisplay().

If an application was transitioning out of fullscreen exclusive
display mode, the wsi_display_connector->active state was not
reset in vkReleaseDisplay() from fullscreen. When the app then
later tried to go to fullscreen display mode again on the same
display output with the same video mode, this caused
_wsi_display_queue_next() to skip a required drmModeSetCrtc()
during the first vkQueuePresent() after entering direct display
mode.

While this often worked by pure luck on a single-display setup,
it goes sideways on a multi-display setup where the viewport
of the associated crtc does not have a (x,y) offset of (0,0).
E.g., XOrg/X11 RandR output leasing of an output whose viewport
starts at x = 1920:

1. X-Server has RandR outputs viewport at x = 1920, in a shared
   framebuffer, shared across all crtc's on a X-Screen.

2. Application leases that output for direct display mode,
   1st vkQueuePresent() triggers drmModeSetCrtc() of output
   to (x,y) = 0,0, as required for Vulkan/wsi/direct framebuffer
   setup.

3. Application does rendering and presenting.

4. Application vkReleaseDisplay() the output, terminates the
   RandR lease. X-Server takes over again.

5. X-Server modesets to reconfigure output back to viewport
   with (x,y) = 1920, 0.

6. Application leases same output again later on, and tries
   vkQueuePresent() again. Because of the bug fixed in this
   commit, the required drmModeSetCrtc() to (x,y) = 0,0 is
   erroneously skipped due to the stale cached connector state.

7. drmModePageflip() fails due to the wrong crtc viewport
   (x,y) = 1920, 0, mismatched for the need of the Vulkan
   framebuffer of (x,y) = 0,0. Kernel returns -ENOSPACE,
   Swapchain goes into permanent VK_ERROR_SURFACE_LOST state.
   Destroying and recreating the swapchain, as recommended
   by the Vulkan spec for error handling won't help. Game over!

Resetting wsi_display_connector->active = false; fixes the
problem of wrong / stale connector state and Vulkan/wsi/display
clients are happy on multi-display setups again, as tested
in various single- and multi-display configurations.

This bug affects all Mesa releases with Vulkan/WSI/Display
support and should therefore be backported.

Signed-off-by: Mario Kleiner <mario.kleiner.de@gmail.com>
Fixes: 352d320a0745 ("vulkan: Add EXT_direct_mode_display [v2]")
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19484>

rusticl/nir: copy alignment info when lowering kernel input loads

Signed-off-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19614>

docs: use ext-role for GL / VK extensions

This makes sure that we generate proper links to all of these
extensions.

Reviewed-by: Eric Engestrom <eric@igalia.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19594>

docs: add ext-role for spec extension links

This is a custom Sphinx role that generates links to GL and VK
extensions.

Reviewed-by: Eric Engestrom <eric@igalia.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19594>

docs: drop rogue backtick

Reviewed-by: Eric Engestrom <eric@igalia.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19594>

docs: NV_gpu_shader4 -> NV_gpu_program4

There's no GL_NV_gpu_shader4 extension, and the TEX opcode is defined in
NV_gpu_program4. Correct the mistake.

Reviewed-by: Eric Engestrom <eric@igalia.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19594>

docs: feeddback -> feedback

Reviewed-by: Eric Engestrom <eric@igalia.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19594>

panfrost: DRY buffer range special case

Pattern from iris.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19576>

panfrost: Remove out-of-band CRC support

Without additional signalling of modifiers, CRCs cannot possibly in a correct
way work across process boundaries. Since we don't do that signalling, we should
not be allocating private CRCs for imported resources, and we should not be
using our own private CRCs for internal resources.

The entire out-of-bands CRC infrastructure is a hack to let us do CRCs even for
imported/exported BOs, but that can't possibly work. Remove it, and remove a
pile of special cases across the driver.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19576>

panfrost: Copy resources when necessary

If the map doesn't set MAP_DISCARD_RANGE, we do have to copy the existing
contents over. MAP_WRITE on its only gives permission to replace the contents,
unfortunately it does not require that the application actually do so.

Closes: #7640
Fixes: 0b26a9f7739 ("panfrost: Don't copy resources if replaced")
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reported-by: Roman Elshin
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19576>

radv: use radv_max_descriptor_set_size() for Vulkan 1.2 properties

Instead of copying this limit entirely.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19598>

panfrost: Fix build with Perfetto (again)

Sync UAPI for the upstream fix.

Upstream commit: https://cgit.freedesktop.org/drm-misc/commit/?h=drm-misc-fixes&id=c4299907c09a638c0a30f029338d07941c049d73

Closes: #7195
Fixes: 6a4532cbabf ("panfrost: Sync panfrost_drm.h from drm-misc-next")
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Tested-by: Chris Healy <healych@amazon.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19581>

ci: Fixes macos.yml

Stick to macos-11 to prevent accident broken
always install meson with pip to prevent pull new version of python

Cc: mesa-stable
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Acked-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19615>

meson: -DVK_ENABLE_BETA_EXTENSIONS at a single place

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19549>

radv/ci: add more subtests to VanGogh's flakes list

Signed-off-by: Martin Roukala (né Peres) <martin.roukala@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19591>

docs: use c:expr role shorthand

Reviewed-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19575>

docs: remove needless c:expr roles

Reviewed-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19575>

docs: make c:expr the default-role

Mesa is a C-project, so c:expr is a really handy role to default to.
This means that `foo` is a short-hand for :c:expr:`foo`.

Reviewed-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19575>

radv/rra: Fix node type validation

Silly mistake...

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19584>

nir: Don't reorder volatile intrinsics

Fixes issue with "is helper invocation" that in recent SPIR-V is mapped to
a volatile Load.  The CSE was catching the loads before they were transformed
in the new is_helper_invocation intrinsic (that is not reorderable).

Fixes: 729df14e452 ("nir: Handle volatile semantics for loading HelperInvocation builtin")
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: M Henning <drawoc@darkrefraction.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19432>

freedreno/a6xx: set chroma offsets to MIDPOINT

Vulkan has VkChromaLocation and all drivers suggest
VK_CHROMA_LOCATION_MIDPOINT on Android.  The blob also uses MIDPOINT.
Based on my limited tests, the image quality is higher with MIDPOINT.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19514>

freedreno/a6xx: set CHROMA_LINEAR

This seems to have no effect on a618, but restores linear filtering on
a635 when the texture is yuv.  The blob sets it on a635 as well (but not
on a618).

Fixed android.media.cts.DecodeAccuracyTest#* on a635.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19514>

c11: Remove _MTX_INITIALIZER_NP for windows

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Acked-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18493>

egl: Remove the need of _MTX_INITIALIZER_NP by using simple_mtx_t/SIMPLE_MTX_INITIALIZER in egllog.c

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Acked-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18493>

nir: Remove the need of _MTX_INITIALIZER_NP by using simple_mtx_t/SIMPLE_MTX_INITIALIZER in nir/nir_validate.c

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Acked-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18493>

glsl: Remove the need of _MTX_INITIALIZER_NP by using simple_mtx_t/SIMPLE_MTX_INITIALIZER

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Acked-by: Jesse Natalie <jenatali@microsoft.com>
Acked-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18493>

llvmpipe: Remove the need of _MTX_INITIALIZER_NP by using simple_mtx_t/SIMPLE_MTX_INITIALIZER in lp_texture.c

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Acked-by: Jesse Natalie <jenatali@microsoft.com>
Acked-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18493>

vulkan/device-select-layer: Remove the need of call_once by using simple_mtx_t instead mtx_t

Function device_select_once_init are removed in-favor of SIMPLE_MTX_INITIALIZER

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Acked-by: Jesse Natalie <jenatali@microsoft.com>
Acked-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18493>

freedreno/a6xx: Switch to global bcolor buffer

Since we expect a limited # of unique border-color entry states, we can
use a global table of border-color entries, rather than constructing the
state at draw time.  This shifts all the border-color overhead from draw
time to sampler state CSO creation time.  And it's less code!

A hashtable is used to map unique border-color table value to entry so
multiple usages of what maps to the same table entry all re-use a single
slot in the table.  This puts an upper bound on the # of unique border-
color plus format value.  In practice this shouldn't be a problem, we'll
just size the table to be large enough to not run into problems with
CTS.  Note that the border-color table entry is not completely format
dependent (mostly just integer vs float dependent), so for example a
single color with different float formats can map to a single table
entry.

This also fixes the problem that we completely ignored border-color for
GS/tess stages.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7518
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19561>

freedreno/a6xx: Rename tex cache key/equals fxns

We'll need different functions for border-color cache.  Prep for next
patch.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19561>

freedreno/a6xx: Move bcolor entry setup

Just code motion, in prep for a following patch.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19561>

freedreno/ci: Update a5xx expectations

These seem to have not been updated in a while.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19561>

freedreno: Use our border-color quirk

This will let us remove our assumption that samplers and views map 1:1,
and generally simplify our border-color handling.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19561>

ci/bare-metal: remove consolidations leftovers

All defined in the baremetal-test-arm*

Reviewed-by: Eric Engestrom <eric@igalia.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19548>

freedreno/ir3: Reduce compiler thread pool size

With the current scheme, looking at game startup which should be the
worst case (most heavily loaded) time for the compiler threads, and they
seem to be ~10% busy.  Furthermore we typically have a mix of "big" and
"LITTLE" cores.. with about half being "big".  So sizing the thread pool
to the half the # of CPU cores seems reasonable.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19387>

util/disk_cache: Add some blob cache traces

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19387>

util/disk_cache: Add compression in blob cb path

Android's implementation of the blob-cache get/put funcs do not
implement any compression.  And the default cache size is rather small,
at 2MB (!!) per app (although I assume everyone patches android to
increase the size limit).

We don't bother compressing the has_key/put_key path, since that path is
only storing a uint32_t.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19387>

vulkan/wsi/wayland: return VK_ERROR_NATIVE_WINDOW_IN_USE_KHR

If the surface is already in use by another swapchain, return
VK_ERROR_NATIVE_WINDOW_IN_USE_KHR. The spec states:

> If pCreateInfo->oldSwapchain is VK_NULL_HANDLE, and the native
> window referred to by pCreateInfo->surface is already associated
> with a Vulkan swapchain, VK_ERROR_NATIVE_WINDOW_IN_USE_KHR must
> be returned.

Signed-off-by: Simon Ser <contact@emersion.fr>
Reviewed-by: Leandro Ribeiro <leandro.ribeiro@collabora.com>
Acked-by: Daniel Stone <daniels@collabora.com>
References: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7467
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19229>

ci: run shaderdb on vc4 as well

Signed-off-by: Eric Engestrom <eric@igalia.com>
Acked-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19305>

vc4: add DRM_VC4_CREATE_SHADER_BO support to drm-shim

Signed-off-by: Eric Engestrom <eric@igalia.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19305>

nv50/ir: Support fmulz and ffmaz

Signed-off-by: Yusuf Khan <yusisamerican@gmail.com>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19333>

nv50/ir: add prefer_nir flag for getting compiler options

So that we dont expose certain options for nir_to_tgsi

Signed-off-by: Yusuf Khan <yusiamerican@gmail.com>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19333>

tu: Support GMEM with layered rendering and multiview

It turns out that this actually is supported. GMEM can hold multiple
layers which are cleared, loaded, and resolved separately. The stride
between layers seems to be implicitly calculated based on the tile size,
and we have to match it when blitting to/from GMEM. One tricky thing is
that now we may realize that we don't have enough space for GMEM only
when computing the tiling config, because we may not know the number of
framebuffer layers until we have the framebuffer and too many
framebuffer layers will exhaust GMEM.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19505>

radv: stop emulating number of generated primitives by GS on GFX11

According to RadeonSI, only GFX10 and GFX10.3 need to emulate.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19319>

anv: fix missing VkPhysicalDeviceExtendedDynamicState3PropertiesEXT handling

Fixes: 13c422e1b2ed ("anv: toggle on EXT_extended_dynamic_state3")
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19573>

crocus: enable NV_alpha_to_coverage_dither_control

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19463>

iris: enable NV_alpha_to_coverage_dither_control

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19463>

radv: advertise extendedDynamicState3ColorWriteMask

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19589>

radv: add support for dynamic color write mask

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19589>

intel/compiler: Remove unused fs_visitor::emit_percomp()

Since 7ef7738a61d ("i965: Write gl_FragCoord directly to the destination.") this
is not used.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19586>

intel/compiler: Remove various unused function declarations

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19586>

intel/compiler: Remove unused data members

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19586>

util: Remove os/os_thread.h and replace #include "os/os_thread.h" with #include "util/u_thread.h"

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19557>

util: cleanup os_thread.h

__pipe_mutex_assert_locked is not used anymore so remove it from os_thread.h
The remove of "pipe/p_compiler.h" caused compiling failure also fixed

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19557>

util: Move pipe_semaphore to u_thread.h and rename it to util_semaphore

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19557>

gallium/util: Remove the EMBEDDED_DEVICE macro because nobody use it

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7641

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Acked-by: Jose Fonseca <jfonseca@vmware.com>
Acked-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19552>

intel/fs: Optimize integer multiplication of large constants by factoring

Many Intel platforms can only perform 32x16 bit multiplication.  The
straightforward way to implement 32x32 bit multiplications is by
splitting one of the operands into high and low parts called H and L,
repsectively.  The full multiplication can be implemented as:

         ((A * H) << 16) + (A * L)

On Intel platforms, special register accesses can be used to eliminate
the shift operation.  This results in three instructions and a temporary
register for most values.

If H or L is 1, then one (or both) of the multiplications will later be
eliminated.  On some platforms it may be possible to eliminate the
multiplication when H is 256.

If L is zero (note that H cannot be zero), one of the multiplications
will also be eliminated.

Instead of splitting the operand into high and low parts, it may
possible to factor the operand into two 16-bit factors X and Y.  The
original multiplication can be replaced with (A * (X * Y)) = ((A * X) *
Y).  This requires two instructions without a temporary register.

I may have gone a bit overboard with optimizing the factorization
routine.  It was a fun brainteaser, and I couldn't put it down. :) On my
1.3GHz Ice Lake, a standalone test could chug through 1,000,000 randomly
selected values in about 5.7 seconds.  This is about 9x the performance
of the obvious, straightforward implementation that I started with.

v2: Drop an unnecessary return.  Rearrange logic slightly and rename
variables in factor_uint32 to better match the names used in the large
comment.  Both suggested by Caio. Rearrange logic to avoid possibly
using `a` uninitialized. Noticed by Marcin.

v3: Use DIV_ROUND_UP instead of open coding it. Noticed by Caio.

Tiger Lake, Ice Lake, Haswell, and Ivy Bridge had similar results. (Ice Lake shown)
total instructions in shared programs: 19912558 -> 19912526 (<.01%)
instructions in affected programs: 3432 -> 3400 (-0.93%)
helped: 10 / HURT: 0

total cycles in shared programs: 856413218 -> 856412810 (<.01%)
cycles in affected programs: 122032 -> 121624 (-0.33%)
helped: 9 / HURT: 0

No shader-db changes on any other Intel platforms.

Tiger Lake and Ice Lake had similar results. (Ice Lake shown)
Instructions in all programs: 141997227 -> 141996923 (-0.0%)
Instructions helped: 71

Cycles in all programs: 9162524757 -> 9162523886 (-0.0%)
Cycles helped: 63
Cycles hurt: 5

No fossil-db changes on any other Intel platforms.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17718>

intel/compiler: Teach signed integer range analysis about imax and imin

This is especially helpful for a*isign(a) generated by idiv_by_const
optimization.  On many GPUs, isign(a) is lowered to imax(imin(a, 1),
-1).

There are no changes on fossil-db because ANV uses a different
optimization path for idiv with a constant denominator.  A future MR
will change this.

NOTE: This commit used to help a few hundred shader-db shaders, but
now none are affected.  I suspect this is due to some change in the
idiv_by_const optimization.  This could possibly be dropped.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17718>

intel/compiler: Signed integer range analysis for imul_32x16 generation

Only iabs and ineg are treated specially.  Everything else just uses
nir_unsigned_upper_bound.  The special treatment of source modifiers is
because they cause problems for nir_unsigned_upper_bound.  Once those
are peeled off, nir_unsigned_upper_bound can generally produce a
tighter bound.

Future commits will add more opcodes.  This mostly introduces the
basic framework.

v2: Add a bunch of comments to signed_integer_range_analysis. Re-arrange
the code a little to reduce duplication.  Both suggested by
Caio. Rearrange some logic to simplify things. Suggested by Marcin.

Tiger Lake, Ice Lake, Haswell, and Ivy Bridge had similar results. (Ice Lake shown)
total instructions in shared programs: 19912894 -> 19912558 (<.01%)
instructions in affected programs: 109275 -> 108939 (-0.31%)
helped: 74 / HURT: 0

total cycles in shared programs: 856422769 -> 856413218 (<.01%)
cycles in affected programs: 15268102 -> 15258551 (-0.06%)
helped: 65 / HURT: 4

total fills in shared programs: 8218 -> 8217 (-0.01%)
fills in affected programs: 1171 -> 1170 (-0.09%)
helped: 1 / HURT: 0

Skylake and Broadwell had similar results. (Skylake shown)
total cycles in shared programs: 845145547 -> 845142263 (<.01%)
cycles in affected programs: 15261465 -> 15258181 (-0.02%)
helped: 65 / HURT: 0

Tiger Lake
Tiger Lake
Instructions in all programs: 157580768 -> 157579730 (-0.0%)
Instructions helped: 312
Instructions hurt: 28

Cycles in all programs: 7566977172 -> 7566967746 (-0.0%)
Cycles helped: 288
Cycles hurt: 53

Spills in all programs: 19701 -> 19700 (-0.0%)
Spills helped: 2
Spills hurt: 4

Fills in all programs: 33311 -> 33335 (+0.1%)
Fills helped: 5
Fills hurt: 4

Ice Lake
Instructions in all programs: 141998667 -> 141997227 (-0.0%)
Instructions helped: 420
Instructions hurt: 3

Cycles in all programs: 9162565297 -> 9162524757 (-0.0%)
Cycles helped: 389
Cycles hurt: 29

Spills in all programs: 19918 -> 19916 (-0.0%)
Spills helped: 2
Spills hurt: 3

Fills in all programs: 32795 -> 32814 (+0.1%)
Fills helped: 6
Fills hurt: 3

Skylake
Instructions in all programs: 132567691 -> 132567745 (+0.0%)
Instructions hurt: 24

Cycles in all programs: 8828897462 -> 8828889517 (-0.0%)
Cycles helped: 405
Cycles hurt: 6

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17718>

intel/compiler: Add and use a pass to generate imul_32x16 instructions

Gfx8 and Gfx9 platforms are helped for cycles because now many
instructions like

    mul(8)          g12<1>D         g10<8,8,1>D     6D

become

    mul(8)          g12<1>D         g10<8,8,1>D     6W

It is the same number of instructions, but the 32x16 multiply is a
little faster.

v2: Fix transposed hi and lo in "(hi >= INT16_MIN && lo <= INT16_MAX)".
Noticed by Caio.  Use nir_src_is_const instead of open coding it.
Suggested by Caio.

Broadwell and Skylake had similar results. (Skylake shown)
total cycles in shared programs: 845748380 -> 845145547 (-0.07%)
cycles in affected programs: 446346348 -> 445743515 (-0.14%)
helped: 6017
HURT: 0
helped stats (abs) min: 2 max: 7380 x̄: 100.19 x̃: 8
helped stats (rel) min: <.01% max: 3.72% x̄: 0.41% x̃: 0.39%
95% mean confidence interval for cycles value: -113.37 -87.00
95% mean confidence interval for cycles %-change: -0.42% -0.41%
Cycles are helped.

Skylake
Cycles in all programs: 8844820715 -> 8828897462 (-0.2%)
Cycles helped: 47914
Cycles hurt: 1

No shader-db or fossil-db changes on any other Intel platform.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17718>

intel/fs: Allow constant copy prop from DW to W

This enables copy propagation of

    mov(8)          g5<1>UD         0x00000180UD
    mul(8)          g10<1>D         g2.3<0,1,0>D    g5<16,8,2>W

into

    mul(8)          g10<1>D         g2.3<0,1,0>D    180W

This is necessary for any optimization passes that generate imul_32x16
instructions.

No fossil-db or shader-db changes on any Intel platform.

v2: Fix type size check to (src size != 2) || (dest size != 4).  It was
previously &&. :( This allowed copying constants into UB sources, and
that is invalid.

v3: Fix incorrect extraction of upper 16-bits of immediate value when
subnr=2. Noticed by Caio.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17718>

intel/fs: Fix bounds checking for integer multiplication lowering

The previous bounds checking would cause

    mul(8)          g121<1>D        g120<8,8,1>D    0xec4dD

to be lowered to

    mul(8)          g121<1>D        g120<8,8,1>D    0xec4dUW
    mul(8)          g41<1>D         g120<8,8,1>D    0x0000UW
    add(8)          g121.1<2>UW     g121.1<16,8,2>UW g41<16,8,2>UW

Instead of picking the bounds (and the new type) based on the old type,
pick the new type based on the value only.

This helps a few fossil-db shaders in Witcher 3 and Geekbench5.  No
changes on any other Intel platforms.

Tiger Lake
Instructions in all programs: 157581069 -> 157580768 (-0.0%)
Instructions helped: 24

Cycles in all programs: 7566979620 -> 7566977172 (-0.0%)
Cycles helped: 22
Cycles hurt: 4

Ice Lake
Instructions in all programs: 141998965 -> 141998667 (-0.0%)
Instructions helped: 26

Cycles in all programs: 9162568666 -> 9162565297 (-0.0%)
Cycles helped: 24
Cycles hurt: 2

Skylake
No changes.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17718>

intel/fs: Fix constant propagation into 32x16 integer multiplication

Don't copy propagate the constant in situations like

    mov(8)          g8<1>D          0x7fffffffD
    mul(8)          g16<1>D         g8<8,8,1>D      g15<16,8,2>W

On platforms that only have a 32x16 multiplier, this will result in
lowering the multiply to

    mul(8)          g15<1>D         g14<8,8,1>D     0xffffUW
    mul(8)          g16<1>D         g14<8,8,1>D     0x7fffUW
    add(8)          g15.1<2>UW      g15.1<16,8,2>UW g16<16,8,2>UW

On Gfx8 and Gfx9, which have the full 32x32 multiplier, it results in

    mul(8)          g16<1>D         g15<16,8,2>W    0x7fffffffD

Volume 2a of the Skylake PRM says:

    When multiplying a DW and any lower precision integer, the
    DW operand must on src0.

See also https://gitlab.freedesktop.org/mesa/crucible/-/merge_requests/104.

Previous to INTEL_shader_integer_functions2 (in Vulkan or OpenGL), I
don't think it would be possible to create a situation where this could
occur.  I discovered this via some optimizations that can determine that
the non-constant source must be able to fit in 16-bits.  The case listed
above came from piglit's "ext_transform_feedback-order arrays points"
with those optimizations in place.

No shader-db or fossil-db changes on any Intel platform.

Fixes: de6c0f84879 ("intel/fs: Implement support for NIR opcodes for INTEL_shader_integer_functions2")
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17718>

wgl: fix reference to wgl(Create|Delete)Context function pointers

Currently in wglCreateContextAttribsARB(), we get and save the
pointers to OPENGL32.DLL's wglCreate/DeleteContext() functions.
But these function pointers might be invalid after opengl32.dll is
unloaded and reloaded again and possibly in a different address space.
This patch, provided by Jose Fonseca, uses GetModuleHandle and gets
the proc address of wglCreate/DeleteContext functions every time the
function is called.

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19478>

r600: Fix some border color swizzles on Evergreen

Note: (u)int32 is broken on this hardware.

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19532>

r600: fix some border color swizzles on CAYMAN

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19532>

docs: update calendar and link releases notes for 22.2.3

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19585>

docs: Add sha256 sum for 22.2.3

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19585>

docs: add release notes for 22.2.3

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19585>

Android.mk: Fix gnu++14 related build failures

This patch filters-out '-std=gnu++14' from the cflags obtained
from AOSP/KATI dummy target output to avoid the following building errors:

FAILED: src/gallium/drivers/r600/45f68e3@@r600@sta/sfn_sfn_assembler.cpp.o
...
clang++ ... -std=c++17 ... -std=gnu++14
...
In file included from ../src/gallium/drivers/r600/sfn/sfn_assembler.cpp:27:
In file included from ../src/gallium/drivers/r600/sfn/sfn_assembler.h:32:
In file included from ../src/gallium/drivers/r600/sfn/sfn_shader.h:31:
../src/gallium/drivers/r600/sfn/sfn_instr.h:369:56: error: no template named 'is_base_of_v' in namespace 'std'; did you mean 'is_base_of'?
template <typename T, typename = std::enable_if_t<std::is_base_of_v<Instr, T>>>
                                                  ~~~~~^~~~~~~~~~~~
                                                       is_base_of
/home/utente/pie-x86_kernel/external/libcxx/include/type_traits:1412:29: note: 'is_base_of' declared here
struct _LIBCPP_TEMPLATE_VIS is_base_of
                            ^
In file included from ../src/gallium/drivers/r600/sfn/sfn_assembler.cpp:27:
In file included from ../src/gallium/drivers/r600/sfn/sfn_assembler.h:32:
In file included from ../src/gallium/drivers/r600/sfn/sfn_shader.h:31:
../src/gallium/drivers/r600/sfn/sfn_instr.h:369:51: error: template argument for non-type template parameter must be an expression
template <typename T, typename = std::enable_if_t<std::is_base_of_v<Instr, T>>>
                                                  ^~~~~~~~~~~~~~~~~~~~~~~~~~~~
/home/utente/pie-x86_kernel/external/libcxx/include/type_traits:439:16: note: template parameter is declared here
template <bool _Bp, class _Tp = void> using enable_if_t = typename enable_if<_Bp, _Tp>::type;
               ^
2 errors generated.

Cc: "22.2" "22.3" mesa-stable
Reviewed-by: Roman Stratiienko <r.stratiienko@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19563>

intel: Add and use intel_gem_can_render_on_fd()

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19425>

intel: Add has_context_isolation to intel_device_info

Iris, hasvk and anv were fetching the same information, better do it
on one place.

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19425>

intel: Add has_userptr_probe to intel_device_info

Iris, hasvk and anv were fetching the same information, better do it
on one place.

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19425>

intel: Add has_mmap_offset to intel_device_info

All 4 drivers were fetching the same information, better do it on one
place.

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19425>

intel: Add and use intel_gem_get_param()

Again sharing the same function across all Intel drivers.

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19425>

docs/asahi: Document drm-shim

Explain how to build drm-shim and how to use it for shader-db.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19540>

asahi: Add drm-shim implementation

Forked off from v3d's. This gets us a render node which is good enough for
shader-db.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19540>

radv/ci: add another test to the navi21 flakes list

Add dEQP-VK.memory.pipeline_barrier.host_read_host_write.1048576 to
the list of flakes of navi21. Found after 80 runs.

Signed-off-by: Martin Roukala (né Peres) <martin.roukala@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19569>

ac/nir,radv: rework and fix NGG queries enables for VS/TES

XFB queries need to be enabled with NGG streamout and VS/TES.
Previously, the NGG lowering code relied on has_prim_query for XFB.

This fixes failures with RADV_PERFTEST=ngg_streamout on GFX10.3 with
the vkd3d-proton testsuite. Vulkan CTS is missing TES tests with XFB
queries apparently.

Cc: 22.3 mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19493>

radv: move computing the binning state to the cmdbuf

With dynamic color write mask and rasterization samples, the binning
state will have to be re-computed dynamically. This shouldn't hurt
anything right now because it's only done at pipeline bind time.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19164>

radv: always set FLUSH_ON_BINNING_TRANSITION

The hardware can detect binning transitions apparently, so it can be
hardcoded. This matches RadeonSI and PAL.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19164>

radv: cleanup setting disabled binning state for GFX9

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19164>