zink: fix line smooth lowering

Fixes: 80285db9efe1 ("zink: lower smooth-lines if not supported")
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21731>

docs: update calendar for 22.3.7

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21795>

docs/relnotes: add sha256sum for 22.3.7

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21795>

docs: add release notes for 22.3.7

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21795>

docs/relnotes: add 23.0.0 to relnotes.rst

I used an old version of the script to generate the notes, which didn't
generate this. It is being kept separate instead of being squashed so
that the commits on the 23.0 branch and those on main match

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21500>

docs: Add sha256 sum for 23.0.0

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21500>

docs: add release notes for 23.0.0

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21500>

docs: Add calendar entries for 23.0 release.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21500>

osmesa: add exported symbols check

Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/1308>

anv+hasvk: Use driconf to disable 16-bit for zink.

The HW can technically execute 16-bit operations, but the restrictions on
16-bit ALU ops are so great that it ends up not being a win for
GLES-on-Vulkan to lower mediump to 16-bit operations, at least with the
current state of the Intel compiler.  This brings zink-on-anv in line with
iris and angle-on-anv for mediump behavior (ANGLE uses RelaxedPrecision,
which we ignore).

Perf on some angle traces on my brya (ADL) and i9-9900K (CFL):

ADL zink pubg_mobile_battle_royale:  +13.4574% +/- 5.2046% (n=5)
CFL zink pubg_mobile_battle_royale:  +29.5332% +/- 0.646585% (n=6)
ADL zink aztec_ruins_high:           +5.78027% +/- 4.80645% (n=4)
CFL zink aztec_ruins_high:           -1.10641% +/- 0.140562% (n=12)
ADL zink trex_200:                   +5.86956% +/- 2.09633% (n=10)
CFL zink trex_200:                   +9.72136% +/- 0.749261% (n=10)

Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21775>

intel/isl: Don't scream FINISHME into logs for 3D vs. CCS

This would probably be a nice optimisation to have, but it really does
make the CTS logs awful:
    https://gitlab.freedesktop.org/mesa/mesa/-/jobs/37692447

Just demote this isl_finishme() to a comment; given it's been unfinished
since 2019, we can probably live without it.

Fixes: 126c9562d98b ("isl: Redefine the CCS layout for Gen12")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21788>

ci/anv: Temporarily halve TGL testing load

Our TGL machines are currently slightly oversubscribed (max. 17 jobs in
a pipeline on 15 DUTs). They're also currently suffering from
thermally-induced GPU throttling (being investigated), and a
thundering-herd network load effect: as all 15 jobs start at once, we
end up saturating one of our network links.

The combination of all three of these things means that TGL is often our
long pole in CI runs. Until we can ameliorate the two issues
constraining throughput (and a third where an unreliable hardware UART
sometimes kills jobs when it shouldn't), halve the workload so we at
least have some breathing room to absorb them.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21790>

util: allow align64() to do alignments >= 4Gb

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21757>

radv: use 1ull for alignment computations

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21757>

anv: force MEDIA_INTERFACE_DESCRIPTOR_LOAD reemit after 3D->GPGPU switch

Seems to fix a hang in the following titles :
   - Age of Empire 4
   - Monster Hunter Rise

where the HW is hung on a PIPE_CONTROL after a GPGPU_WALKER but no
MEDIA_INTERFACE_DESCRIPTOR_LOAD was emitted since the switch from 3D
to GPGPU.

This would happen in the following case :

   vkCmdBindPipeline(COMPUTE, cs_pipeline);
   vkCmdDispatch(...);
   vkCmdBindPipeline(GRAPHICS, gfx_pipeline);
   vkCmdDraw(...);
   vkCmdDispatch(...);

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17247>

radv/rt: Fix updating stack_size if the shader uses scratch

src_vars contains the stack_size of the shader that is about to get inlined.

Fixes: 7fadee9b70c9d1d7229c7bbc9811a858297b193c ('radv/rt: only reserve stack_sizes after rt_case insertion')
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21768>

ci/radv: Skip vkCreateInstance memory-fail test

This has been failing a bit ever since CTS 1.3.5.0. Skip it for now.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21789>

aco: don't reallocate fma{mk,ak,_mix} instruction

Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21762>

aco/optimizer: don't reallocate instruction when converting to VOP3

Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21762>

lavapipe: break out main shader lowering into separate function

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21778>

lavapipe: move uniform inline functions to shader struct

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21778>

lavapipe: rename inline uniform function params

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21778>

lavapipe: move xfb init to shader struct

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21778>

lavapipe: more small shader struct usage tweaks

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21778>

lavapipe: pass shader struct and layout to scan_pipeline_info()

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21778>

lavapipe: split out shader struct members into their own struct

kinda gross but simplifies some code

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21778>

lavapipe: split out spirv compile of shaders

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21778>

vulkan/wsi: fix crash in failed swapchain creation for wayland

this otherwise calls wsi_wl_swapchain_chain_free() before the wsi
pointer has been set

ref #6578

cc: mesa-stable

Acked-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21563>

radv/rt: use terminate() when returning from raygen shaders

Q2RTX stats:
Totals from 7 (0.01% of 134913) affected shaders:

CodeSize: 204712 -> 204744 (+0.02%); split: -0.06%, +0.07%
Instrs: 37526 -> 37522 (-0.01%); split: -0.07%, +0.06%
Latency: 950563 -> 956024 (+0.57%)
InvThroughput: 187915 -> 188977 (+0.57%)
Copies: 4829 -> 4763 (-1.37%)
Branches: 1570 -> 1583 (+0.83%)
PreSGPRs: 407 -> 400 (-1.72%)
PreVGPRs: 614 -> 617 (+0.49%)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21736>

aco: fix NIR infinite loops

The previous solution breaks potential loop header phis.
Move the dummy-break to the bottom of the loop.

Fixes: dEQP-VK.reconvergence.subgroup_uniform_control_flow_ballot.*
Fixes: a9c4a31d8d8a955711d6f49869090caf87846f1b ('aco: handle NIR loops without breaks')
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21736>

nir/gather_info: allow terminate() in non-PS

RADV will use terminate() to end ray-tracing shaders.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21736>

radv: move device memory related code to radv_device_memory.c

radv_device.c is getting too big.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21767>

radv: move buffer related code to radv_buffer.c

radv_device.c is getting too big and this follows the Vulkan common
runtime infrastructure.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21767>

radv: move event related code to radv_event.c

radv_device.c is getting too big.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21767>

radv: move sampler related code to radv_sampler.c

radv_device.c is getting too big and this follows the Vulkan common
runtime infrastructure.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21767>

radv: move queue related code to radv_queue.c

radv_device.c is getting too big and this follows the Vulkan common
runtime infrastructure.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21767>

radv: move physical device related code to radv_physical_device.c

radv_device.c is getting too big and this follows the Vulkan common
runtime infrastructure.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21767>

radv: move instance related code to radv_instance.c

radv_device.c is getting too big and this follows the Vulkan common
runtime infrastructure.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21767>

nir: add nir_lower_alu_width_test.fdot_order

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20812>

nir: make fdph lowering match fdot

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20812>

nir: use xyzw order for precise fdot

Fixes flickering grass in Immortals Fenyx Rising.

fossil-db (gfx1100):
Totals from 13969 (10.38% of 134574) affected shaders:
MaxWaves: 442794 -> 442878 (+0.02%)
Instrs: 4861105 -> 4901408 (+0.83%); split: -0.02%, +0.85%
CodeSize: 24316100 -> 24396272 (+0.33%); split: -0.03%, +0.35%
VGPRs: 446256 -> 445572 (-0.15%); split: -0.20%, +0.05%
Latency: 28122456 -> 28162233 (+0.14%); split: -0.10%, +0.24%
InvThroughput: 2899673 -> 2904323 (+0.16%); split: -0.07%, +0.23%
VClause: 119599 -> 119631 (+0.03%); split: -0.07%, +0.09%
SClause: 186636 -> 186265 (-0.20%); split: -0.23%, +0.03%
Copies: 301370 -> 300386 (-0.33%); split: -0.75%, +0.42%
Branches: 85066 -> 85047 (-0.02%); split: -0.02%, +0.00%
PreSGPRs: 436167 -> 436137 (-0.01%)
PreVGPRs: 329715 -> 329809 (+0.03%); split: -0.01%, +0.04%

fossil-db (gfx1100, RADV_DEBUG=invariantgeom):
Totals from 43116 (32.04% of 134574) affected shaders:
MaxWaves: 1332938 -> 1333012 (+0.01%); split: +0.01%, -0.00%
Instrs: 16424513 -> 16658021 (+1.42%); split: -0.06%, +1.48%
CodeSize: 81258868 -> 81827860 (+0.70%); split: -0.07%, +0.77%
VGPRs: 1720368 -> 1719648 (-0.04%); split: -0.19%, +0.15%
SpillSGPRs: 1670 -> 1600 (-4.19%); split: -5.27%, +1.08%
Latency: 82063766 -> 82425418 (+0.44%); split: -0.23%, +0.67%
InvThroughput: 9665803 -> 9727810 (+0.64%); split: -0.09%, +0.73%
VClause: 449662 -> 451099 (+0.32%); split: -0.32%, +0.64%
SClause: 498841 -> 498639 (-0.04%); split: -0.24%, +0.20%
Copies: 1001020 -> 1000770 (-0.02%); split: -1.20%, +1.17%
Branches: 237580 -> 239637 (+0.87%); split: -0.01%, +0.88%
PreSGPRs: 1198167 -> 1198024 (-0.01%); split: -0.01%, +0.00%
PreVGPRs: 1225202 -> 1225035 (-0.01%); split: -0.06%, +0.05%

fossil-db (navi10):
Totals from 13969 (10.38% of 134563) affected shaders:
MaxWaves: 474386 -> 474508 (+0.03%); split: +0.05%, -0.03%
Instrs: 3740895 -> 3771566 (+0.82%); split: -0.00%, +0.82%
CodeSize: 19426592 -> 19459916 (+0.17%); split: -0.00%, +0.18%
VGPRs: 389916 -> 389852 (-0.02%); split: -0.09%, +0.07%
Latency: 25452927 -> 25502482 (+0.19%); split: -0.14%, +0.34%
InvThroughput: 3880807 -> 3923144 (+1.09%); split: -0.07%, +1.16%
VClause: 66835 -> 66712 (-0.18%); split: -0.38%, +0.20%
SClause: 178805 -> 178802 (-0.00%); split: -0.01%, +0.01%
Copies: 167601 -> 167625 (+0.01%); split: -0.54%, +0.56%
Branches: 83788 -> 83784 (-0.00%)
PreSGPRs: 388229 -> 388216 (-0.00%)
PreVGPRs: 342984 -> 343062 (+0.02%); split: -0.01%, +0.03%

fossil-db (navi10, RADV_DEBUG=invariantgeom):
Totals from 43116 (32.04% of 134563) affected shaders:
MaxWaves: 1260184 -> 1256414 (-0.30%); split: +0.10%, -0.40%
Instrs: 12804951 -> 12983628 (+1.40%); split: -0.01%, +1.41%
CodeSize: 65813224 -> 66137852 (+0.49%); split: -0.03%, +0.52%
VGPRs: 1556396 -> 1561340 (+0.32%); split: -0.09%, +0.41%
SpillSGPRs: 1377 -> 1395 (+1.31%)
Latency: 76095867 -> 76355111 (+0.34%); split: -0.32%, +0.66%
InvThroughput: 13546863 -> 13788789 (+1.79%); split: -0.05%, +1.84%
VClause: 310910 -> 311283 (+0.12%); split: -0.63%, +0.75%
SClause: 474878 -> 474941 (+0.01%); split: -0.09%, +0.10%
Copies: 639367 -> 637610 (-0.27%); split: -1.03%, +0.76%
Branches: 240178 -> 240185 (+0.00%); split: -0.00%, +0.00%
PreSGPRs: 1056594 -> 1056590 (-0.00%); split: -0.00%, +0.00%
PreVGPRs: 1247950 -> 1247798 (-0.01%); split: -0.05%, +0.04%

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7920
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20812>

aux/tc: fix rp info resizing clobbering current info

the recording rp_info may be a pointer to a member of the array being
reallocated, so test for this and re-set it to avoid invalid memory
access

found with this caselist:
KHR-GL46.texture_gather.offset-gather-unorm-2darray
KHR-GL46.texture_view.view_sampling

cc: mesa-stable

Acked-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21729>

anv: report max register pressure in pipeline properties

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21756>

intel/fs: report max register pressure in shader stats

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21756>

anv/iris: report counter symbols with debug option

v2: rename to INTEL_DEBUG=perf-symbol-names

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17672>

radv: disable DCC with signedness reinterpretation on GFX11

All formats should be compatible on GFX11 but for some weird reasons
DCC with signedness reinterpretation doesn't work as expected, like
R8_UINT<->R8_SINT. Note that RadeonSI also has issues with this.

This might be a hardware bug on RDNA3.

This fixes DCC issues with Cyberpunk and A Plague Tale: Requiem.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8020
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8371
Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21755>

radeonsi: fix fast depth_clear_value/stencil_clear_value

We need to update the when promoting from non-TC-compatible to
TC-compatible or we'll get incorrect values in the buffer.

Fixes: 9defe8aca95 ("radeonsi: implement fast Z/S clears using clear_buffer on HTILE")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8418
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21726>

radeonsi: don't use PKT3_SET_SH_REG_INDEX on gfx9 and older

Fixes: ccaaf8fe04c ("amd: massively simplify how info->spi_cu_en is applied")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8464
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21726>

radeonsi/test: update test results

Depends on https://gitlab.freedesktop.org/mesa/piglit/-/merge_requests/779
to fix glx-make-current GLX errors.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21726>

radeonsi/test: use gbm-skips.txt

Use shared skips file to avoid running tests that can't pass on gbm.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21726>

radv: enable VK_KHR_fragment_shading_rate on GFX11

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20333>

radv: advertise attachmentFragmentShadingRate on GFX11

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20333>

radv: do not emit PA_SC_VRS_OVERRIDE_CNTL from the pipeline on GFX11

PA_SC_VRS_OVERRIDE_CNTL is emitted when a framebuffer is bound because
it controls the VRS surface enable bit. Though, if a pipeline is bound
after the framebuffer is emitted, it can override the state. Remove it
completely since VRS for flat shading and RADV_FORCE_VRS are disabled.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20333>

radv: add support for VRS attachment on GFX11

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20333>

ac/surface: add RADEON_SURF_VRS_RATE for selecting swizzle mode on GFX11

On GFX11, VRS rate images can't use linear tiling and the swizzle mode
must be either SW_Z or SW_R.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20333>

radv: move disabling DCC for VRS rate images in radv_get_surface_flags()

On GFX11, the VRS rate image needs a specific swizzle mode and a new
flag will be added here.

gned-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20333>

anv: enable VK_EXT_pipeline_library_group_handles

A noop for us.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20929>

radeonsi: increase NGG workgroup size to 256 for VS/TES with streamout and GS

NGG streamout performance is limited by the workgroup size, so make it as
large as possible.

Since this uses si_get_max_workgroup_size() to set the NGG workgroup size,
the side effect is that all GS is also getting an increase to 256, which
is OK.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21403>

radeonsi: allow using 64K LDS for NGG to allow larger workgroups

This should help with NGG streamout performance, which is limited by
the workgroup size (it should be as large as possible).

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21403>

radeonsi: other cosmetic changes in si_state_shaders.cpp

VS_W32_EN has no effect on Gfx11, but we better not set it.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21403>

radeonsi: reorganize si_shader_ps

To make branching based on gfx_level nicer and the code in a logical order.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21403>

radeonsi: reorganize si_shader_ngg

To make branching based on gfx_level nicer and the code in a logical order.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21403>

radeonsi: reorganize si_shader_hs

To make branching based on gfx_level nicer and the code in a logical order.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21403>

radeonsi: reindent si_shader_ls, si_shader_es, si_shader_gs, si_shader_vs

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21403>

radeonsi: set pm4.atom.emit in si_get_shader_pm4_state

except gfx10_shader_ngg, which isn't as trivial

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21403>

radeonsi: lower nir_texop_sampler_descriptor_amd

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21403>

radeonsi: separate nir_texop_descriptor_amd lowering

This moves the code to a separate branch to make it less intertwined
with the rest to allow sampler descriptor lowering later.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21403>

radeonsi: merge si_emit_initial_compute_regs with si_init_cs_preamble_state

It's better to set all immutable registers in one place.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21403>

radeonsi: emulate VGT_ESGS_RING_ITEMSIZE in the shader on gfx9-11

The hardware uses the register to premultiply GS vertex indices
in input VGPRs.

This changes the behavior as follows:
- VGT_ESGS_RING_ITEMSIZE is always 1 on gfx9-11, set in the preamble.
- The value is passed to the shader via current_gs_state (vs_state_bits).
- The shader does the multiplication.

The reason is that VGT_ESGS_RING_ITEMSIZE will be removed in the future.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21403>

ac/nir: clear nir_var_shader_out from TCS barriers

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21403>

aco: Don't include headers from radv.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21696>

aco, radv: Don't use radv_shader_args in aco.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21696>

aco, radv: Move PS epilog and VS prolog args to their info structs.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21696>

aco, radv: Rename aco_*_key to aco_*_info.

The naming of aco_*_key didn't make sense because they
were never actually used as cache keys, only radv_*_key
are used as cache keys.

Rename the aco structs to aco_*_info instead.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21696>

aco, radv: Move is_trap_handler_shader to aco info.

v2 by Timur Kristóf:
- Rebase this patch on latest main.

Signed-off-by: Qiang Yu <yuq825@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21696>

aco, radv: Add load_grid_size_from_user_sgpr to aco options.

v2 by Timur Kristóf:
- Rebase this patch.

Signed-off-by: Qiang Yu <yuq825@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21696>

aco: Generalize vs_inputs to args_pending_vmem.

Handle arguments that need a waitcnt without relying on
RADV specific VS input information.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21696>

radv: Set pending_vmem on dynamic VS input args.

These are loaded from VMEM and need a waitcnt before use.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21696>

ac: Add pending_vmem field to args.

This is to indicate when an argument was loaded from VMEM
and needs a waitcnt before it can be used.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21696>

freedreno: Promote non-drawing batches to sysmem

Sometimes we can end up with a sequence where we need to flush a batch
with no clears and no draws (for ex, to get a fence).  Promote these to
sysmem.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21747>

zink: hook up buffer TRANSFER_DST barrier optimizing

this should massively optimize e.g., incremental index buffer overwrites

ref #8358

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21779>

zink: add a driver workaround to disable copy box optimizations

turnip is nonconformant regarding cache access (see noted issue),
meaning that any attempt to omit barriers breaks things

qcom proprietary may also be affected

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21779>

zink: add a mechanism to trigger copy box resets from batch state reset

the resource isn't available during batch state reset, so a new flag
is needed to force a reset the next time the copy boxes would be used

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21779>

zink: add a mechanism for managing TRANSFER_DST buffer barriers

this enables successive or unrelated transfer writes to avoid triggering
barriers, and ensuing reads of those writes should trigger their own
barriers

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21779>

zink: track the last write access for resources

this enables some optimization

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21779>

radeonsi: Add support for DPB resize

This patch will add support for dpb resize when low to high resolution
change/ svc use-cases.

With DPB tier1 type,vp9 svc decoder use cases are failed. This
Change will fix this[VCN1/VCN2].

Signed-off-by: SureshGuttula <suresh.guttula@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Boyuan Zhang <boyuan.zhang@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21548>

asahi: disable disk cache in debug runs

With debug flags enabled, shaders might get compiled differently and
running compilation might be desired e.g. for logging, so don't try to
cache them.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21776>

agx: isolate compiler debug flags

The gallium disk cache is about to depend on these, and I don't want to
create a dependency on agx_opcodes.h.py for that. So, make a new header
for them that doesn't have build dependencies.
Rename them to agx_compiler_* too, to avoid collisions with the other
driver debug flags.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21776>

intel/ci: Remove skipped float_controls tests from hasvk xfails

These tests are skipped now because preserving denorms isn't supported.

Acked-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21719>

intel/ci: Remove hasvk xfails missing from the CTS

These broken tests no longer exist in the CTS and all dynamic rendering
tests pass now.

Acked-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21719>

intel/ci: Remove outdated hasvk copy_and_blit xfails

These were fixed by commit e509afac.

Acked-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21719>

mesa/program: fix memory leak triggered by arb alias

The function _mesa_symbol_table_add_symbol() copies the string with strdup(),
the original string should be freed.

For instance, with "piglit/fp-fragment-position -auto -fbo":
Direct leak of 7 byte(s) in 1 object(s) allocated from:
    #0 0xffff99c59050 in __interceptor_strdup (/usr/lib64/libasan.so.6+0x59050)
    #1 0xffff8f53d24c in handle_ident ../src/mesa/program/program_lexer.l:129
    #2 0xffff8f53d24c in _mesa_program_lexer_lex ../src/mesa/program/program_lexer.l:312
    #3 0xffff8f529d10 in yylex ../src/mesa/program/program_parse.y:289
    #4 0xffff8f529d10 in yyparse src/mesa/program/program_parse.tab.c:2140
    #5 0xffff8f5341a4 in _mesa_parse_arb_program ../src/mesa/program/program_parse.y:2589
    #6 0xffff8f51e96c in _mesa_parse_arb_fragment_program ../src/mesa/program/arbprogparse.c:82
    #7 0xffff8f4d867c in set_program_string ../src/mesa/main/arbprogram.c:402

Signed-off-by: Patrick Lerda <patrick9876@free.fr>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21728>

mesa/program: fix memory leak triggered by multiple targets used on one texture image unit

For instance, with "piglit-2000/bin/asmparsertest ARBfp1.0 tests/asmparsertest/shaders/ARBfp1.0/shadow-02.txt":
Direct leak of 192 byte(s) in 2 object(s) allocated from:
    #0 0x7f6e8378f987 in calloc (/usr/lib64/libasan.so.6+0xb1987)
    #1 0x7f6e7769d620 in asm_instruction_copy_ctor ../src/mesa/program/program_parse.y:2146
    #2 0x7f6e7769d620 in yyparse ../src/mesa/program/program_parse.y:439
    #3 0x7f6e776a6725 in _mesa_parse_arb_program ../src/mesa/program/program_parse.y:2590
    #4 0x7f6e77687f69 in _mesa_parse_arb_fragment_program ../src/mesa/program/arbprogparse.c:82
    #5 0x7f6e77630765 in set_program_string ../src/mesa/main/arbprogram.c:402
    #6 0x7f6e76ec3e8a in _mesa_unmarshal_ProgramStringARB src/mapi/glapi/gen/marshal_generated2.c:4152
    #7 0x7f6e76a0e585 in glthread_unmarshal_batch ../src/mesa/main/glthread.c:122
    #8 0x7f6e76a1031d in _mesa_glthread_finish ../src/mesa/main/glthread.c:383
    #9 0x7f6e76a1031d in _mesa_glthread_finish ../src/mesa/main/glthread.c:348
    #10 0x7f6e76e6a062 in _mesa_marshal_GetError src/mapi/glapi/gen/marshal_generated1.c:1809

Signed-off-by: Patrick Lerda <patrick9876@free.fr>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21728>

mesa/program: fix memory leak triggered by invalid extended swizzle selector

For instance, with "piglit/bin/asmparsertest ARBfp1.0 tests/asmparsertest/shaders/ARBfp1.0/swz-04.txt":
Direct leak of 18 byte(s) in 2 object(s) allocated from:
    #0 0x7f97e99050 in __interceptor_strdup (/usr/lib64/libasan.so.6+0x59050)
    #1 0x7f8d4160ac in handle_ident ../src/mesa/program/program_lexer.l:129
    #2 0x7f8d4160ac in _mesa_program_lexer_lex ../src/mesa/program/program_lexer.l:312
    #3 0x7f8d402b50 in yylex ../src/mesa/program/program_parse.y:289
    #4 0x7f8d402b50 in yyparse src/mesa/program/program_parse.tab.c:2140
    #5 0x7f8d40d01c in _mesa_parse_arb_program ../src/mesa/program/program_parse.y:2590
    #6 0x7f8d3f77ac in _mesa_parse_arb_fragment_program ../src/mesa/program/arbprogparse.c:82
    #7 0x7f8d3ad468 in set_program_string ../src/mesa/main/arbprogram.c:402

Signed-off-by: Patrick Lerda <patrick9876@free.fr>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21728>

aco/assembler/gfx11: simplify 16bit VOP12C promotion to VOP3

With the shared struct for modifies, this is can be a lot cleaner now.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21761>

radeonsi/gfx11: only allocate GDS OA for streamout, GDS memory is not needed

Reviewed-by: Qiang Yu <yuq825@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21584>

amd/llvm,radeonsi/gfx11: switch to using GDS_STRMOUT registers

This is required by register shadowing (required by the new PAIRS packets),
preemption, user queues, and we only have to wait for VS after streamout,
not PS. This is how gfx11 streamout should have been done.

Reviewed-by: Qiang Yu <yuq825@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21584>

amd: add nir_intrinsic_xfb_counter_sub_amd and fix overflowed streamout offsets

Fixes: 5ec79f989988ba - ac/nir/ngg: nogs support streamout

Reviewed-by: Qiang Yu <yuq825@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21584>

intel/fs: use generated workaround helpers for Wa_14017989577

Wa_14017989577 is a clone of Wa_14015360517, which applies to several
platforms beyond INTEL_PLATFORM_DG2_G10.

Update references to Wa_14017989577, and use the generated workaround
helper to ensure application to the proper platforms.

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21744>

ci/etnaviv: Drop the dEQP-GLES2.functional.uniform_api.random.94 xfail.

This has been consistently passing.  I think I just missed it in my
previous update.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21769>