Weijie Gao [Fri, 5 Mar 2021 02:24:58 +0000 (10:24 +0800)]
configs: mt7622: use ARMv8 Generic Timer instead of mtk_timer
It's better to use the generic timer which is correctly initialized by
the ATF. The generic timer has higher resolution than the mtk_timer.
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
Weijie Gao [Fri, 5 Mar 2021 02:22:31 +0000 (10:22 +0800)]
pinctrl: mt7629: add jtag function and pin group
The EPHY LEDs of mt7629 can be used as JTAG. This patch adds the jtag pin
group to the pinctrl driver.
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
Weijie Gao [Fri, 5 Mar 2021 02:22:26 +0000 (10:22 +0800)]
pinctrl: mediatek: do not probe gpio driver if not enabled
The mtk pinctrl driver is a combination driver with support for both
pinctrl and gpio. When this driver is used in SPL, gpio support may not be
enabled, and this will result in a compilation error.
To fix this, macros are added to make sure gpio related code will only be
compiled when gpio support is enabled.
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
Sam Shih [Fri, 5 Mar 2021 02:22:19 +0000 (10:22 +0800)]
pinctrl: mediatek: add get_pin_muxing ops for mediatek pinctrl
This patch add get_pin_muxing support for mediatek pinctrl drivers
Signed-off-by: Sam Shih <sam.shih@mediatek.com>
Sam Shih [Fri, 5 Mar 2021 02:22:11 +0000 (10:22 +0800)]
pinctrl: mediatek: fix wrong assignment in mtk_get_pin_name
This is a bug fix for mtk pinctrl common part. Appearently pins should be
used instead of grps in mtk_get_pin_name().
Signed-off-by: Sam Shih <sam.shih@mediatek.com>
Fabien Parent [Mon, 15 Feb 2021 18:21:12 +0000 (19:21 +0100)]
board: Add MT8183 pumpkin board support
Add the MT8183 pumpkin board support.
Signed-off-by: Fabien Parent <fparent@baylibre.com>
Fabien Parent [Mon, 15 Feb 2021 18:21:11 +0000 (19:21 +0100)]
ARM: mediatek: Add MT8183 support
Add the MT8183 SoC support.
Signed-off-by: Fabien Parent <fparent@baylibre.com>
Fabien Parent [Mon, 15 Feb 2021 18:07:46 +0000 (19:07 +0100)]
configs: mt8516: use bootcmd from config_distro_bootcmd.h
Instead of redefining our own way to boot, let's just use
config_distro_bootcmd.h.
Signed-off-by: Fabien Parent <fparent@baylibre.com>
Fabien Parent [Mon, 15 Feb 2021 18:07:45 +0000 (19:07 +0100)]
board: mediatek: mt8516: init USB Ether for pumpkin board
Init USB Ether if CONFIG_USB_ETHER is enabled.
Signed-off-by: Fabien Parent <fparent@baylibre.com>
Fabien Parent [Mon, 15 Feb 2021 18:07:44 +0000 (19:07 +0100)]
board: mediatek: rename pumpkin board into mt8516
More than one pumpkin board has been made with different MediaTek SoCs.
Rename the pumpkin board to follow the naming convention of all
other MediaTek boards and also to not be confusing when other pumpkin
boards will be added in follow-up commits.
Signed-off-by: Fabien Parent <fparent@baylibre.com>
Tom Rini [Fri, 19 Mar 2021 12:20:34 +0000 (08:20 -0400)]
Merge branch 'next' of git://source.denx.de/u-boot-sh into next
- New platforms and related support
Lad Prabhakar [Mon, 15 Mar 2021 22:24:06 +0000 (22:24 +0000)]
board: silinux: Enable recovery SPL for EK874 board
Enable building SPL for EK874 board which is based on R8A774C0 SoC.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Lad Prabhakar [Mon, 15 Mar 2021 22:24:05 +0000 (22:24 +0000)]
arm: rmobile: Add Silicon Linux EK874 board support
The EK874 development kit from Silicon Linux is made of CAT874 (the main
board) and CAT875 (the sub board that goes on top of CAT874).
This patch adds the required board support to boot Si-Linux EK874 board
based on R8A774C0 SoC.
DTS files apart from r8a774c0-ek874-u-boot.dts and r8a774c0-u-boot.dtsi
have been imported from Linux kernel 5.11 commit
f40ddce88593
("Linux 5.11").
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Lad Prabhakar [Mon, 15 Mar 2021 22:24:04 +0000 (22:24 +0000)]
pinctrl: renesas: Add support for R8A774C0
Renesas RZ/G2E (a.k.a. r8a774c0) is pin compatible with R-Car
E3 (a.k.a. r8a77990), however it doesn't have several automotive
specific peripherals.
This patch hooks R8A774C0 SoC with the pfc driver.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Lad Prabhakar [Mon, 15 Mar 2021 22:24:03 +0000 (22:24 +0000)]
pinctrl: renesas: pfc-r8a77990: Sync PFC tables with Linux 5.11
Sync the R8A77990 SoC PFC tables with Linux 5.11 , commit
f40ddce88593.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Lad Prabhakar [Mon, 15 Mar 2021 22:24:02 +0000 (22:24 +0000)]
arm: dts: r8a774c0: Resync R8A774C0 SoC DTSI with Linux 5.11
Resync the R8A774C0 SoC DTSI with Linux kernel 5.11 commit
f40ddce88593
("Linux 5.11").
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Biju Das [Mon, 1 Mar 2021 17:08:49 +0000 (17:08 +0000)]
arm: rmobile: Add HopeRun HiHope RZ/G2H board support
The HiHope RZ/G2H board from HopeRun consists of main board
(HopeRun HiHope RZ/G2H main board) and sub board(HopeRun
HiHope RZ/G2H sub board). The HiHope RZ/G2H sub board sits
below the HiHope RZ/G2H main board.
This patch adds the required board support to boot HopeRun HiHope
RZ/G2H board.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Biju Das [Mon, 1 Mar 2021 17:08:48 +0000 (17:08 +0000)]
arm: rmobile: Add HopeRun HiHope RZ/G2N board support
The HiHope RZ/G2N board from HopeRun consists of main board
(HopeRun HiHope RZ/G2N main board) and sub board(HopeRun
HiHope RZ/G2N sub board). The HiHope RZ/G2N sub board sits
below the HiHope RZ/G2N main board.
This patch adds the required board support to boot HopeRun HiHope
RZ/G2N board.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Biju Das [Mon, 1 Mar 2021 17:08:47 +0000 (17:08 +0000)]
arm: rmobile: Add HopeRun HiHope RZ/G2M board support
The HiHope RZ/G2M board from HopeRun consists of main board
(HopeRun HiHope RZ/G2M main board) and sub board(HopeRun
HiHope RZ/G2M sub board). The HiHope RZ/G2M sub board sits
below the HiHope RZ/G2M main board.
This patch adds the required board support to boot HopeRun HiHope
RZ/G2M board.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Biju Das [Mon, 1 Mar 2021 17:08:46 +0000 (17:08 +0000)]
arm: dts: rmobile: r8a774e1: Synchronize DTs with Linux 5.11
Synchronize r8a774e1 device trees with Linux 5.11,
commit
f40ddce88593482919 ("Linux 5.11").
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Biju Das [Mon, 1 Mar 2021 17:08:45 +0000 (17:08 +0000)]
arm: dts: rmobile: r8a774b1: Synchronize DTs with Linux 5.11
Synchronize r8a774b1 device trees with Linux 5.11,
commit
f40ddce88593482919 ("Linux 5.11")
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Tom Rini [Mon, 15 Mar 2021 16:15:38 +0000 (12:15 -0400)]
Merge tag 'v2021.04-rc4' into next
Prepare v2021.04-rc4
Tom Rini [Mon, 15 Mar 2021 16:06:41 +0000 (12:06 -0400)]
Prepare v2021.04-rc4
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Mon, 15 Mar 2021 14:50:47 +0000 (10:50 -0400)]
configs: Resync with savedefconfig
Rsync all defconfig files using moveconfig.py
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Mon, 15 Mar 2021 12:43:29 +0000 (08:43 -0400)]
Merge tag 'ti-v2021.04-rc4' of https://source.denx.de/u-boot/custodians/u-boot-ti
- Fix boot for da850-evm and omap3_logic
- Optimize SPL size for am65x boards
Tom Rini [Mon, 15 Mar 2021 12:43:19 +0000 (08:43 -0400)]
Merge tag 'u-boot-stm32-
20210312' of https://source.denx.de/u-boot/custodians/u-boot-stm
- Add WATCHDOG_RESET() in MTD framework and STM32 QSPI driver
- stm32mp1_trusted_defconfig rely on SCMI support
- Remove the nand MTD configuration for NOR boot in stm32mp1 board
- STM32programmer update
- Bsec: manage clock when present in device tree
- stm32mp15: move bootdelay configuration in defconfig
- Update for stm32 dsi and dw_mipi_dsi
- STM32 MCU's cleanup
- Fix compilation issue depending on SYS_DCACHE_OFF and SYS_ICACHE_OFF flags
- Update stm32mp1 doc
Tom Rini [Mon, 15 Mar 2021 12:41:14 +0000 (08:41 -0400)]
Merge branch '2021-03-12-assorted-improvements' into next
- More log enhancements
- A few warning fixes in some cases
- Secure Channel Protocol 03 (SCP03) support for TEEs
Lokesh Vutla [Tue, 9 Mar 2021 18:02:45 +0000 (23:32 +0530)]
configs: am65x_evm_r5: Enable checks for spl and stack sizes
Enable relevant configs that checks for the size of image and stack:
BSS: 3KB
Initial MALLOC: ~22KB
Initial Stack: 8K
SPL Image size can be: ~215KB
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Lokesh Vutla [Tue, 9 Mar 2021 18:02:44 +0000 (23:32 +0530)]
include: configs: am65x_evm: Optimize size of SPL BSS
Current BSS allocation of SPL is as below:
$ size spl/u-boot-spl
text data bss dec hex filename
132369 7852 1496 141717 22995 spl/u-boot-spl
But 20KB is allocated currently for BSS. Reduce it to 3KB and save some
space for stack.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Adam Ford [Sat, 6 Mar 2021 02:48:50 +0000 (20:48 -0600)]
ARM: da850-evm: Fix boot issues from missing SPL_PAD_TO
In a previous attempt to unify config options and remove items
from the whitelist file, SPL items were moved into a section
enabled with CONFIG_SPL_BUILD. Unfortunately, SPL_PAD_TO
is referenced at the head Makefile and uses this define
to create padding of the output file. When it was moved
to CONFIG_SPL_BUILD, it caused boot errors with devices
that are not booting from NOR. Fix the boot issues by moving
SPL_PAD_TO out so it's always.
Fixes:
7bb33e4684aa ("ARM: da850-evm: Unify config options with Kconfig")
Signed-off-by: Adam Ford <aford173@gmail.com>
Adam Ford [Thu, 4 Mar 2021 16:31:58 +0000 (10:31 -0600)]
configs: omap3_logic: Enable CONFIG_SPL_ALLOC_BD
With bd_info dropped from the data section, the Logic PD OMAP3 boards
and AM3517 fail to boot. Enabling CONFIG_SPL_ALLOC_BD restores
them.
Fixes:
38d6b7ebdaee ("spl: Drop bd_info in the data section")
Signed-off-by: Adam Ford <aford173@gmail.com>
Igor Opaniuk [Sun, 14 Feb 2021 15:27:28 +0000 (16:27 +0100)]
test: py: add initial coverage for scp03 cmd
Add initial test coverage for SCP03 command.
Signed-off-by: Igor Opaniuk <igor.opaniuk@foundries.io>
Reviewed-by: Simon Glass <sjg@chromium.org>
Igor Opaniuk [Sun, 14 Feb 2021 15:27:27 +0000 (16:27 +0100)]
sandbox: imply SCP03 and CMD_SCP03
Enable by default SCP_03/CMD_SCP03 for sandbox target.
Signed-off-by: Igor Opaniuk <igor.opaniuk@foundries.io>
Reviewed-by: Simon Glass <sjg@chromium.org>
Jorge Ramirez-Ortiz [Sun, 14 Feb 2021 15:27:26 +0000 (16:27 +0100)]
doc: describe the scp03 command
The Secure Channel Protocol 03 command sends control requests
(enable/provision) to the TEE implementing the protocol between the
processor and the secure element.
Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io>
Reviewed-by: Simon Glass <sjg@chromium.org>
Jorge Ramirez-Ortiz [Sun, 14 Feb 2021 15:27:25 +0000 (16:27 +0100)]
drivers: tee: sandbox: SCP03 control emulator
Adds support for a working SCP03 emulation. Input parameters are
validated however the commands (enable, provision) executed by the TEE
are assumed to always succeed.
Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io>
Reviewed-by: Simon Glass <sjg@chromium.org>
Jorge Ramirez-Ortiz [Sun, 14 Feb 2021 15:27:24 +0000 (16:27 +0100)]
cmd: SCP03: enable and provision command
Enable and provision the SCP03 keys on a TEE controlled secured elemt
from the U-Boot shell.
Executing this command will generate and program new SCP03 encryption
keys on the secure element NVM.
Depending on the TEE implementation, the keys would then be stored in
some persistent storage or better derived from some platform secret
(so they can't be lost).
Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Igor Opaniuk <igor.opaniuk@foundries.io>
Jorge Ramirez-Ortiz [Sun, 14 Feb 2021 15:27:23 +0000 (16:27 +0100)]
common: SCP03 control (enable and provision of keys)
This Trusted Application allows enabling SCP03 as well as provisioning
the keys on TEE controlled secure element (ie, NXP SE050).
All the information flowing on buses (ie I2C) between the processor
and the secure element must be encrypted. Secure elements are
pre-provisioned with a set of keys known to the user so that the
secure channel protocol (encryption) can be enforced on the first
boot. This situation is however unsafe since the keys are publically
available.
For example, in the case of the NXP SE050, these keys would be
available in the OP-TEE source tree [2] and of course in the
documentation corresponding to the part.
To address that, users are required to rotate/provision those keys
(ie, generate new keys and write them in the secure element's
persistent memory).
For information on SCP03, check the Global Platform HomePage and
google for that term [1]
[1] globalplatform.org
[2] https://github.com/OP-TEE/optee_os/
check:
core/drivers/crypto/se050/adaptors/utils/scp_config.c
Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io>
Reviewed-by: Simon Glass <sjg@chromium.org>
Simon Glass [Sun, 7 Feb 2021 21:27:07 +0000 (14:27 -0700)]
doc: sandbox: Update instructions on quitting
The 'reset' command now resets sandbox but does not quit it. Fix the
instructions.
Fixes:
329dccc0675 ("sandbox: implement reset")
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Sun, 7 Feb 2021 21:27:05 +0000 (14:27 -0700)]
test: acpi: Fix warnings on 32-bit build
Some format strings use the wrong type. Fix them.
Example warnings:
In file included from test/dm/acpi.c:22:
test/dm/acpi.c: In function ‘dm_test_acpi_cmd_list’:
test/dm/acpi.c:362:21: warning: format ‘%lx’ expects argument of type
‘long unsigned int’, but argument 4 has type ‘unsigned int’ [-Wformat=]
ut_assert_nextline("RSDP %08lx %06lx (v02 U-BOOT)", addr,
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
sizeof(struct acpi_rsdp));
~~~~~~~~~~~~~~~~~~~~~~~~
include/test/ut.h:282:33: note: in definition of macro ‘ut_assert_nextline’
if (ut_check_console_line(uts, fmt, ##args)) { \
^~~
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Sun, 7 Feb 2021 21:27:04 +0000 (14:27 -0700)]
tpm: Correct warning on 32-bit build
Fix the warning:
drivers/tpm/tpm2_tis_sandbox.c: In function ‘sandbox_tpm2_xfer’:
drivers/tpm/tpm2_tis_sandbox.c:288:48: warning: format ‘%ld’ expects
argument of type ‘long int’, but argument 2 has type ‘size_t’
{aka ‘unsigned int’} [-Wformat=]
printf("TPM2: Unmatching length, received: %ld, expected: %d\n",
~~^
%d
send_size, length);
~~~~~~~~~
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Simon Glass [Thu, 21 Jan 2021 03:10:56 +0000 (20:10 -0700)]
tpm: Don't select LOG
We don't need to enable logging to run this command since the output will
still appear. Drop the 'select'.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Thu, 21 Jan 2021 03:10:54 +0000 (20:10 -0700)]
log: Add return-checking macros for 0 being success
The existing log_ret() and log_msg_ret() macros consider an error to be
less than zero. But some function may return a positive number to indicate
a different kind of failure. Add macros to check for that also.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Thu, 21 Jan 2021 03:10:53 +0000 (20:10 -0700)]
log: Handle line continuation
When multiple log() calls are used which don't end in newline, the
log prefix is prepended multiple times in the same line. This makes the
output look strange.
Fix this by detecting when the previous log record did not end in newline.
In that case, setting a flag.
Drop the unused BUFFSIZE in the test while we are here.
As an example implementation, update log_console to check the flag and
produce the expected output.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Thu, 21 Jan 2021 03:10:52 +0000 (20:10 -0700)]
log: Set up a flag byte for log records
At present only a single flag (force_debug) is used in log records. Before
adding more, convert this into a bitfield, so more can be added without
using more space.
To avoid expanding the log_record struct itself (which some drivers may
wish to store in memory) reduce the line-number field to 16 bits. This
provides for up to 64K lines which should be enough for anyone.
Signed-off-by: Simon Glass <sjg@chromium.org>
Tom Rini [Fri, 12 Mar 2021 20:57:20 +0000 (15:57 -0500)]
Merge branch '2021-03-12-test-improvements' into next
- Assorted improvements to the pytest framework
Simon Glass [Mon, 8 Mar 2021 00:35:17 +0000 (17:35 -0700)]
doc: Explain briefly how to write new tests
Add a second on writing tests, covering when to use Python and C, where
to put the tests, etc. Add a link to the existing Python test
documentation.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Mon, 8 Mar 2021 00:35:16 +0000 (17:35 -0700)]
test: sandbox: Move sandbox test docs into doc/develop
At present some of the documentation about running sandbox tests is in the
sandbox docs. It makes more sense to put it in with the other testing
docs, with a link there from sandbox. Update the documentation
accordingly.
Also add a paragraph explaining why sandbox exists and the test philosophy
that it uses.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Mon, 8 Mar 2021 00:35:15 +0000 (17:35 -0700)]
spl: test: Add a test for spl_load_simple_fit()
As an example of an SPL test, add a new test for loading a FIT within
SPL. This runs on sandbox_spl. For this to work, the text base is adjusted
so that there is plenty of space available.
While we are here, document struct spl_load_info properly, since this is
currently ambiguous.
This test only verifies the logic path. It does not actually check that
the image is loaded correctly. It is not possible for sandbox's SPL to
actually run u-boot.img since it currently includes u-boot.bin rather than
u-boot. Further work could expand the test in that direction.
The need for this was noted at:
http://patchwork.ozlabs.org/project/uboot/patch/
20201216000944.2832585-3-mr.nuke.me@gmail.com/
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Mon, 8 Mar 2021 00:35:14 +0000 (17:35 -0700)]
spl: Convert spl_fit to work with sandbox
At present this casts addresses to pointers so cannot work with sandbox.
Update the code to use map_sysmem() instead.
As part of this change, the existing load_ptr is renamed to src_ptr since
it is not a pointer to load_addr. It is confusing to use a similar name
for something that is not actually related. For the alignment code,
ALIGN() is used instead of open-coded alignment. Add a comment to the line
that casts away a const.
Use a (new) load_ptr variable to access memory at address load_addr.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Mon, 8 Mar 2021 00:35:13 +0000 (17:35 -0700)]
sandbox: Update os_find_u_boot() to find the .img file
At present this function can only locate the u-boot ELF file. For SPL it
is handy to be able to locate u-boot.img since this is what would normally
be loaded by SPL.
Add another argument to allow this to be selected.
While we are here, update the function to load SPL when running in TPL,
since that is the next stage.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Mon, 8 Mar 2021 00:35:12 +0000 (17:35 -0700)]
test: Allow SPL to run any available test
At present SPL only runs driver model tests. Update it to run all
available tests, i.e. in any test suite.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Mon, 8 Mar 2021 00:35:11 +0000 (17:35 -0700)]
test: Rename all linker lists to have a ut_ prefix
At present each test suite has its own portion of the linker_list section
of the image, but other lists are interspersed. This makes it hard to
enumerate all the available tests without knowing the suites that each one
is in.
Place all tests together in a single contiguous list by giving them
common prefix not used elsewhere in U-Boot. This makes it possible to find
the start and end of all tests.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Mon, 8 Mar 2021 00:35:10 +0000 (17:35 -0700)]
test: Add a macros for finding tests in linker_lists
At present we use the linker list directly. This is not very friendly, so
add a helpful macro instead. This will also allow us to change the naming
later without updating this code.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Mon, 8 Mar 2021 00:35:09 +0000 (17:35 -0700)]
test: log: Rename log main test file to log_ut.c
The current name is the same as the main test runner file. Rename it to
avoid confusion.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Simon Glass [Mon, 8 Mar 2021 00:35:08 +0000 (17:35 -0700)]
test: Move restoring of driver model state to ut_run_list()
Add this functionality to ut_run_list() so it can be removed from
dm_test_run().
At this point all tests are run through ut_run_list().
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Mon, 8 Mar 2021 00:35:07 +0000 (17:35 -0700)]
test: Move the devicetree check into ut_run_list()
Add a check to ut_run_list() as to whether a list has driver model tests.
Move the logic for the test devicetree into that function, in an effort
to eventually remove all logic from dm_test_run().
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Mon, 8 Mar 2021 00:35:06 +0000 (17:35 -0700)]
test: Use return values in dm_test_run()
Update this function to use the return value of ut_run_list() to check for
success/failure, so that they are in sync. Also return a command success
code so that the caller gets what it expects.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Mon, 8 Mar 2021 00:35:05 +0000 (17:35 -0700)]
test: Run driver-model tests using ut_run_list()
Use this function instead of implementing it separately for driver model.
Make ut_run_tests() private since it is only used in test-main.c
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Mon, 8 Mar 2021 00:35:04 +0000 (17:35 -0700)]
test: Use a local variable for test state
At present we use a global test state for all driver-model tests. Make use
of a local struct like we do with the other tests.
To make this work, add functions to get and set this state. When a test
starts, the state is set (so it can be used in the test). When a test
finishes, the state is unset, so it cannot be used by mistake.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Mon, 8 Mar 2021 00:35:03 +0000 (17:35 -0700)]
test: Add ut_run_test_live_flat() to run tests twice
Driver model tests are generally run twice, once with livetree enable and
again with it disabled. Add a function to handle this and call it from the
driver model test runner.
Make ut_run_test() private since it is not used outside test-main.c now.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Mon, 8 Mar 2021 00:35:02 +0000 (17:35 -0700)]
test: Drop dm_do_test()
In an effort to make use of a common test runner, use ut_run_test()
directly to run driver model tests.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Mon, 8 Mar 2021 00:35:01 +0000 (17:35 -0700)]
test: Use ut_run_test() to run driver model tests
Instead of having a separate function for running driver model tests, use
the common one. Make the pre/post-run functions private since we don't
need these outside of test-main.c
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Mon, 8 Mar 2021 00:35:00 +0000 (17:35 -0700)]
test: Move test running into a separate function
Add a function to handle the preparation for running a test and the
post-test clean-up.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Mon, 8 Mar 2021 00:34:59 +0000 (17:34 -0700)]
test: Move dm_test_destroy() into test-main.c
Move this function into the common test runner and rename it to
dm_test_post_run() so that its purpose is clear.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Mon, 8 Mar 2021 00:34:58 +0000 (17:34 -0700)]
test: Move dm_test_init() into test-main.c
Move this function into test-main so that all the init is in one place.
Rename it so that its purpose is clearer.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Mon, 8 Mar 2021 00:34:57 +0000 (17:34 -0700)]
test: Drop struct dm_test_state
Driver model is a core part of U-Boot. We don't really need to have a
separate test structure for the driver model tests and it makes it harder
to write a test if you have to think about which type of test it is.
Subsume the fields from struct dm_test_state into struct unit_test_state
and delete the former.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Mon, 8 Mar 2021 00:34:56 +0000 (17:34 -0700)]
test: Handle driver model reinit in test_pre_run()
For driver model tests we want to reinit the data structures so that
everything is in a known state before the test runs. This avoids one test
changing something that breaks a subsequent tests.
Move the call for this into test_pre_run().
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Mon, 8 Mar 2021 00:34:55 +0000 (17:34 -0700)]
test: Move delay skipping to test_pre_run()
This allows delays to be skipped in sandbox tests. Move it to the
common pre-init function.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Mon, 8 Mar 2021 00:34:54 +0000 (17:34 -0700)]
test: Move console silencing to test_pre_run()
We already have a function for silencing the console during tests. Use
this from test_pre_run() and drop this code from the driver model tests.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Mon, 8 Mar 2021 00:34:53 +0000 (17:34 -0700)]
test: Drop mallinfo() work-around
This is not needed now. Drop it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Mon, 8 Mar 2021 00:34:52 +0000 (17:34 -0700)]
test: Move dm_scan_plat() to test_pre_run()
Move this step over to the pre-run function.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Mon, 8 Mar 2021 00:34:51 +0000 (17:34 -0700)]
test: Move do_autoprobe() to test_pre_run()
Move this step over to the pre-run function.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Mon, 8 Mar 2021 00:34:50 +0000 (17:34 -0700)]
test: Move dm_extended_scan() to test_pre_run()
Move this step over to the pre-run function.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Mon, 8 Mar 2021 00:34:49 +0000 (17:34 -0700)]
test: Call test_pre/post_run() from driver model tests
Ultimately we want to get rid of the special driver model test init and
use test_pre_run() and test_post_run() for all tests. As a first step,
use those function to handle console recording.
For now we need a special case for setting uts->start, but that wil go
away once all init is in one place.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Mon, 8 Mar 2021 00:34:48 +0000 (17:34 -0700)]
test: Create pre/post-run functions
Split out the test preparation into a separation function before
expanding it. Add a post-run function as well, currently empty.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Mon, 8 Mar 2021 00:34:47 +0000 (17:34 -0700)]
test: Add an overall test runner
Add a new test runner that will eventually be able to run any test. For
now, have it run the 'command' unit tests, so that the functionality in
cmd_ut_category() moves into it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Mon, 8 Mar 2021 00:34:46 +0000 (17:34 -0700)]
test: Rename test-main.c to test-dm.c
This is the main test function for driver model but not for other tests.
Rename the file and the function so this is clear.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Mon, 8 Mar 2021 00:34:45 +0000 (17:34 -0700)]
test: Mark all driver model tests with a flag
Add a flag for driver model tests, so we can do special processing for
them.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Mon, 8 Mar 2021 00:34:44 +0000 (17:34 -0700)]
test: Correct setexpr test prefix
This prefix should be for setexpr, not mem. This means that trying to
select just these tests to run does not work. Fix it.
For some reason this provokes an assertion failure due to memory not
being freed. Move the env_set() in setexpr_test_str() to before the
malloc() heap size size is recorded and disable the rest in
setexpr_test_str_oper().
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Mon, 8 Mar 2021 00:34:43 +0000 (17:34 -0700)]
doc: Document how sandbox_spl_tests are run
Add a few notes about the sandbox_spl tests, since they are special.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Pratyush Yadav <p.yadav@ti.com>
Simon Glass [Mon, 8 Mar 2021 00:34:42 +0000 (17:34 -0700)]
doc: Explain how to run tests without pytest
Add details about how to run a sandbox test directly, without using
pytest. This is more convenient for rapid development, since it is faster
and allows easier use of a debugger. Also mention sandbox_flattree as an
example of the different sandbox builds available.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Mon, 8 Mar 2021 00:34:41 +0000 (17:34 -0700)]
test: Re-enable test_ofplatdata
This was inadvertently disabled after a recent change. Re-enable it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Mon, 8 Mar 2021 00:34:40 +0000 (17:34 -0700)]
sandbox: Drop the 'starting...' message
This message is annoying since it is only useful for testing. Drop it and
update the test to cope.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Mon, 8 Mar 2021 00:34:39 +0000 (17:34 -0700)]
doc: Document make tcheck
Add a comment about this option in the documentation. Also mention the
script that runs these combinations.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Simon Glass [Mon, 8 Mar 2021 00:34:38 +0000 (17:34 -0700)]
doc: Tidy up testing section
Tweak this so the output looks a little better.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Simon Glass [Mon, 8 Mar 2021 00:34:37 +0000 (17:34 -0700)]
dm: core: Fix allocation of empty of-platdata
With of-platdata we always have a dtv struct that holds the platform data
provided by the driver_info record. However, this struct can be empty if
there are no actual devicetree properties provided.
The upshot of empty platform data is that it will end up as a zero-size
member in the BSS section, which is fine. But if the driver specifies
plat_auto then it expects the correct amount of space to be allocated.
At present this does not happen, since device_bind() assumes that the
platform-data size will always be >0. As a result we end up not
allocating the space and just use the BSS region, overwriting whatever
other contents are present.
Fix this by removing the condition that platform data be non-empty, always
allocating space if requested.
This fixes a strange bug that has been lurking since of-platdata was
implemented. It has likely never been noticed since devices normally have
at least some devicetree properties, BSS is seldom used on SPL, the dtv
structs are normally at the end of bss and the overwriting only happens
if a driver changes its platform data.
It was discovered using sandbox_spl, which exercises more features than
a normal board might, and the critical global_data variable 'gd' happened
to be at the end of BSS.
Fixes:
9fa28190091 ("dm: core: Expand platdata for of-platdata devices")
Signed-off-by: Simon Glass <sjg@chromium.org>
Marek Vasut [Sat, 6 Mar 2021 20:44:17 +0000 (21:44 +0100)]
doc: stm32mp1: Use u-boot.itb if CONFIG_SPL_LOAD_FIT=y
For systems where SPL loads fitImage, i.e. CONFIG_SPL_LOAD_FIT=y, use
u-boot.itb in the relevant documentation parts. Otherwise use u-boot.img.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrice Chotard <patrice.chotard@foss.st.com>
Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Tom Rini [Fri, 12 Mar 2021 13:00:39 +0000 (08:00 -0500)]
Merge https://source.denx.de/u-boot/custodians/u-boot-marvell
- Some more updates/sync's to A38x DDR3 code (Marek & Pali)
- marvell/ddr/AXP: Some type fixes found in the LTO work (Marek)
- Espressobin: Enable more options (Pali)
- pci-aardvark: Implement workaround for the readback value of
VEND_ID (Paili)
Patrice Chotard [Wed, 24 Feb 2021 12:53:27 +0000 (13:53 +0100)]
arm: stm32mp: Fix compilation issue when SYS_DCACHE_OFF and/or SYS_DCACHE_SYS are enabled
Fix following compilation issue when SYS_DCACHE_OFF and/or SYS_DCACHE_SYS
are enabled :
arch/arm/mach-stm32mp/cpu.c: In function ‘early_enable_caches’:
arch/arm/mach-stm32mp/cpu.c:223:10: error: ‘volatile struct arch_global_data’ has no member named ‘tlb_size’
223 | gd->arch.tlb_size = PGTABLE_SIZE;
| ^
arch/arm/mach-stm32mp/cpu.c:224:10: error: ‘volatile struct arch_global_data’ has no member named ‘tlb_addr’
224 | gd->arch.tlb_addr = (unsigned long)&early_tlb;
| ^
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Patrice Chotard [Wed, 24 Feb 2021 12:38:20 +0000 (13:38 +0100)]
board: st: Remove board_early_init_f and board_late_init callbacks for stm32 boards
Remove board_early_init_f() and board_late_init() callbacks for stm32
boards as the corresponding flags (CONFIG_BOARD_LATE_INIT and
CONFIG_BOARD_EARLY_INIT_R) are now disabled.
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Patrice Chotard [Wed, 24 Feb 2021 12:38:19 +0000 (13:38 +0100)]
configs: stm32: Remove BOARD_EARLY_INIT_F and BOARD_LATE_INIT for stm32 boards
These flags was defined and callbacks linked to these flags are empty
and only returning 0.
Remove BOARD_EARLY_INIT_F and BOARD_LATE_INIT flags for these stm32 boards.
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Pali Rohár [Fri, 5 Mar 2021 14:52:42 +0000 (15:52 +0100)]
arm: mvebu: a38x: Remove dead code ARMADA_39X
Config option ARMADA_39X is never set so remove all dead code hidden under
ifdef CONFIG_ARMADA_39X blocks.
Also remove useless checks for CONFIG_ARMADA_38X define as this macro is
always defined for a38x code path.
Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
Pali Rohár [Wed, 3 Mar 2021 13:37:59 +0000 (14:37 +0100)]
arm: a37xx: pci: Implement workaround for the readback value of VEND_ID
Marvell Armada 3720 Functional Errata, Guidelines, and Restrictions
document describes in erratum 4.1 PCIe value of vendor ID (Ref #: 243):
The readback value of VEND_ID (RD0070000h [15:0]) is 1B4Bh, while it
should read 11ABh.
The firmware can write the correct value, 11ABh, through VEND_ID
(RD0076044h [15:0]).
Implement this workaround in U-Boot PCIe controller driver aardvark for
both PCI vendor id and PCI subsystem vendor id.
This change affects PCI vendor id of PCIe root bridge emulated by Linux
kernel. With this change Linux kernel reports correct vendor id 11AB.
Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
Pali Rohár [Wed, 3 Mar 2021 10:34:53 +0000 (11:34 +0100)]
arm: mvebu: Espressobin: Enable additional options
Enable support for NVMe disks which can be connected to mPCIe slot via M.2
reduction. Enable btrfs and squashfs filesystems which are used by more
Linux distributions. And enable fsuuid and setexpr commands which can be
useful in scripting.
Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
Marek Behún [Sat, 6 Mar 2021 23:00:34 +0000 (00:00 +0100)]
ddr: marvell: axp: fix array types have different bounds warning
The arrays `pbs_dq_mapping`, `div_ratio1to1` and `div_ratio2to1` have
different bounds declared in header files where these variables are also
defined from the ones declared in source files.
This causes the compiler to complain (when building with LTO):
ddr3_sdram.c:24:12: warning: type of ‘pbs_dq_mapping’ does not match
original declaration
[-Wlto-type-mismatch]
ddr3_patterns_64bit.h:911:5: note: array types have different bounds
ddr3_patterns_64bit.h:911:5: note: ‘pbs_dq_mapping’ was previously
declared here
ddr3_dfs.c:45:11: warning: type of ‘div_ratio1to1’ does not match
original declaration [-Wlto-type-mismatch]
ddr3_axp_vars.h:167:4: note: array types have different bounds
ddr3_axp_vars.h:167:4: note: ‘div_ratio1to1’ was previously declared
here
ddr3_dfs.c:46:11: warning: type of ‘div_ratio2to1’ does not match
original declaration [-Wlto-type-mismatch]
ddr3_axp_vars.h:196:4: note: array types have different bounds
ddr3_axp_vars.h:196:4: note: ‘div_ratio2to1’ was previously declared
here
CI managed to trigger this as an error when compiling with LTO for AXP.
Fix this by using values from the header files, which seem to be the
correct ones.
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Marek Behún [Thu, 4 Mar 2021 10:23:14 +0000 (11:23 +0100)]
ddr: marvell: axp: align signature of mv_xor_mem_init() with a38x
In arch/arm/mach-mvebu/dram.c we always include axp's xor.h for common
XOR definitions, regardless whether we compile for axp or a38x.
But the declaration of this function has a different signature in axp's
xor.h from the one used in a38x' implementation - one parameter is u64
instead of u32. This can result in wrong argument's being passed to that
function on a38x with no one the wiser.
I discovered this when building U-Boot for Turris Omnia with LTO. The
compiler complains about the different signatures being thrown into the
same linking process:
axp/xor.h:67:5: warning: type of ‘mv_xor_mem_init’ does not match
original declaration [-Wlto-type-mismatch]
67 | int mv_xor_mem_init(u32 chan, u32 start_ptr, u32 block_size,
| ^
a38x/xor.c:165:5: note: type mismatch in parameter 3
165 | int mv_xor_mem_init(u32 chan, u32 start_ptr, unsigned long long
| ^
a38x/xor.c:165:5: note: type ‘long long unsigned int’ should match
type ‘u32’
Fix this by changing the type of the block_size argument in the axp's
implementation and header file to the one used in a38x (and upstream
mv-ddr-marvell).
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
Pali Rohár [Tue, 2 Mar 2021 10:17:41 +0000 (11:17 +0100)]
ddr: marvell: a38x: Sync code with Marvell mv-ddr-marvell repository
This syncs drivers/ddr/marvell/a38x/ with the master branch of repository
https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell.git up to the
commit
7c351731d196 ("Merge pull request #29 from pali/sync-a38x-uboot").
This patch was created by following steps:
1. Replace all a38x files in U-Boot tree by files from upstream github
Marvell mv-ddr-marvell repository.
2. Run following command to omit portions not relevant for a38x and ddr3:
files=drivers/ddr/marvell/a38x/*
sed 's/#if defined(CONFIG_ARMADA_38X) || defined(CONFIG_ARMADA_39X)/#ifdef TRUE/' -i $files
unifdef -m -UMV_DDR -UMV_DDR_ATF -UCONFIG_DDR4 -UCONFIG_APN806 \
-UCONFIG_MC_STATIC -UCONFIG_MC_STATIC_PRINT -UCONFIG_PHY_STATIC \
-UCONFIG_PHY_STATIC_PRINT -UCONFIG_CUSTOMER_BOARD_SUPPORT \
-UCONFIG_A3700 -UA3900 -UA80X0 -UA70X0 -DTRUE $files
3. Manually omit SPDX-License-Identifier changes from this patch as
upstream license in upstream github repository contains long license
texts and U-Boot is using just SPDX-License-Identifier.
After applying this patch, a38x ddr3 code in upstream Marvell github
repository and in U-Boot would be fully identical. So in future applying
above steps could be used to sync code again.
The only change in this patch is removal of dead code and some fixes with
include files.
Signed-off-by: Pali Rohár <pali@kernel.org>
Tested-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Sujeet Baranwal [Fri, 26 Feb 2021 10:56:59 +0000 (11:56 +0100)]
ddr: marvell: a38x: Add more space for additional info from SPD
commit
258be123226f8f5cd516b7813fe201fb7d7416e9 upstream.
At this moment, only page 0 of SPD is being read but to support
smbios, we need to read page 1 also which has more info. In order
to do that, we need to allocate more space.
Signed-off-by: Sujeet Baranwal <sujeet.baranwal@cavium.com>
Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com>
Reviewed-by: Sujeet Kumar Baranwal <Sujeet.Baranwal@cavium.com>
Reviewed-by: Nadav Haklai <nadavh@marvell.com>
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Tested-by: Chris Packham <judge.packham@gmail.com>
Patrick Delaunay [Mon, 1 Mar 2021 12:17:56 +0000 (13:17 +0100)]
board: stm32mp1: use CONFIG_SYS_MMC_ENV_DEV when available
Check whether user has explicitly defined the mmc device to use
in mmc_get_env_dev() with CONFIG_SYS_MMC_ENV_DEV.
On STMicroelectronics boards the used mmc device for environment is
the instance of boot device provided by the ROM code; the mmc instance
is configured by alias in device tree. The used partition is defined in
device tree with u-boot,mmc-env-partition = "ssbl".
This patch allows to override this selection for the support of customer
boards without alias; for example when SDMMC1 is not used and ENV in
mmc0=SDMMC2, user can force the value: CONFIG_SYS_MMC_ENV_DEV = 0.
On STMicroelectronics boards, the current behavior is kept with
CONFIG_SYS_MMC_ENV_DEV = -1.
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Yannick Fertre [Thu, 4 Mar 2021 12:14:36 +0000 (13:14 +0100)]
video: dw_mipi_dsi: update log of dphy_enable
The DSI phy can be turned on from the DSI digital interface in
the dphy_enable() function or from a dedicated DSI phy "wrapper"
in phy_ops->init() function. If the STM32MP1 case, the wrapper
is used then the dphy_enable() "warning" traces are not relevant.
This patch moves these "warning" traces to "debug" traces so
they are still available for DSI phy based on the digital
interface in debug logging mode, but not there in normal mode
for both cases.
Note: The related Linux kernel driver uses a "debug"
message too.
Signed-off-by: Yannick Fertre <yannick.fertre@foss.st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Acked-by: Yannick Fertre <yannick.fertre@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>