Peter Smith [Fri, 7 Jun 2019 13:00:17 +0000 (13:00 +0000)]
[ELF][AArch64] Support for BTI and PAC
Branch Target Identification (BTI) and Pointer Authentication (PAC) are
architecture features introduced in v8.5a and 8.3a respectively. The new
instructions have been added in the hint space so that binaries take
advantage of support where it exists yet still run on older hardware. The
impact of each feature is:
BTI: For executable pages that have been guarded, all indirect branches
must have a destination that is a BTI instruction of the appropriate type.
For the static linker, this means that PLT entries must have a "BTI c" as
the first instruction in the sequence. BTI is an all or nothing
property for a link unit, any indirect branch not landing on a valid
destination will cause a Branch Target Exception.
PAC: The dynamic loader encodes with PACIA the address of the destination
that the PLT entry will load from the .plt.got, placing the result in a
subset of the top-bits that are not valid virtual addresses. The PLT entry
may authenticate these top-bits using the AUTIA instruction before
branching to the destination. Use of PAC in PLT sequences is a contract
between the dynamic loader and the static linker, it is independent of
whether the relocatable objects use PAC.
BTI and PAC are independent features that can be combined. So we can have
several combinations of PLT:
- Standard with no BTI or PAC
- BTI PLT with "BTI c" as first instruction.
- PAC PLT with "AUTIA1716" before the indirect branch to X17.
- BTIPAC PLT with "BTI c" as first instruction and "AUTIA1716" before the
first indirect branch to X17.
The use of BTI and PAC in relocatable object files are encoded by feature
bits in the .note.gnu.property section in a similar way to Intel CET. There
is one AArch64 specific program property GNU_PROPERTY_AARCH64_FEATURE_1_AND
and two target feature bits defined:
- GNU_PROPERTY_AARCH64_FEATURE_1_BTI
-- All executable sections are compatible with BTI.
- GNU_PROPERTY_AARCH64_FEATURE_1_PAC
-- All executable sections have return address signing enabled.
Due to the properties of FEATURE_1_AND the static linker can tell when all
input relocatable objects have the BTI and PAC feature bits set. The static
linker uses this to enable the appropriate PLT sequence.
Neither -> standard PLT
GNU_PROPERTY_AARCH64_FEATURE_1_BTI -> BTI PLT
GNU_PROPERTY_AARCH64_FEATURE_1_PAC -> PAC PLT
Both properties -> BTIPAC PLT
In addition to the .note.gnu.properties there are two new command line
options:
--force-bti : Act as if all relocatable inputs had
GNU_PROPERTY_AARCH64_FEATURE_1_BTI and warn for every relocatable object
that does not.
--pac-plt : Act as if all relocatable inputs had
GNU_PROPERTY_AARCH64_FEATURE_1_PAC. As PAC is a contract between the loader
and static linker no warning is given if it is not present in an input.
Two processor specific dynamic tags are used to communicate that a non
standard PLT sequence is being used.
DTI_AARCH64_BTI_PLT and DTI_AARCH64_BTI_PAC.
Differential Revision: https://reviews.llvm.org/D62609
llvm-svn: 362793
Anton Afanasyev [Fri, 7 Jun 2019 12:59:32 +0000 (12:59 +0000)]
[Support][Test] Time profiler: add regression test
Summary:
Add output to `llvm::errs()` when `-ftime-trace` option is enabled,
add regression test checking this option works as expected.
Reviewers: thakis, aganea
Subscribers: cfe-commits, llvm-commits
Tags: #clang, #llvm
Differential Revision: https://reviews.llvm.org/D61914
llvm-svn: 362792
Simon Tatham [Fri, 7 Jun 2019 12:42:54 +0000 (12:42 +0000)]
[ARM] Fix bugs introduced by the fp64/d32 rework.
Change D60691 caused some knock-on failures that weren't caught by the
existing tests. Firstly, selecting a CPU that should have had a
restricted FPU (e.g. `-mcpu=cortex-m4`, which should have 16 d-regs
and no double precision) could give the unrestricted version, because
`ARM::getFPUFeatures` returned a list of features including subtracted
ones (here `-fp64`,`-d32`), but `ARMTargetInfo::initFeatureMap` threw
away all the ones that didn't start with `+`. Secondly, the
preprocessor macros didn't reliably match the actual compilation
settings: for example, `-mfpu=softvfp` could still set `__ARM_FP` as
if hardware FP was available, because the list of features on the cc1
command line would include things like `+vfp4`,`-vfp4d16` and clang
didn't realise that one of those cancelled out the other.
I've fixed both of these issues by rewriting `ARM::getFPUFeatures` so
that it returns a list that enables every FP-related feature
compatible with the selected FPU and disables every feature not
compatible, which is more verbose but means clang doesn't have to
understand the dependency relationships between the backend features.
Meanwhile, `ARMTargetInfo::handleTargetFeatures` is testing for all
the various forms of the FP feature names, so that it won't miss cases
where it should have set `HW_FP` to feed into feature test macros.
That in turn caused an ordering problem when handling `-mcpu=foo+bar`
together with `-mfpu=something_that_turns_off_bar`. To fix that, I've
arranged that the `+bar` suffixes on the end of `-mcpu` and `-march`
cause feature names to be put into a separate vector which is
concatenated after the output of `getFPUFeatures`.
Another side effect of all this is to fix a bug where `clang -target
armv8-eabi` by itself would fail to set `__ARM_FEATURE_FMA`, even
though `armv8` (aka Arm v8-A) implies FP-Armv8 which has FMA. That was
because `HW_FP` was being set to a value including only the `FPARMV8`
bit, but that feature test macro was testing only the `VFP4FPU` bit.
Now `HW_FP` ends up with all the bits set, so it gives the right
answer.
Changes to tests included in this patch:
* `arm-target-features.c`: I had to change basically all the expected
results. (The Cortex-M4 test in there should function as a
regression test for the accidental double-precision bug.)
* `arm-mfpu.c`, `armv8.1m.main.c`: switched to using `CHECK-DAG`
everywhere so that those tests are no longer sensitive to the order
of cc1 feature options on the command line.
* `arm-acle-6.5.c`: been updated to expect the right answer to that
FMA test.
* `Preprocessor/arm-target-features.c`: added a regression test for
the `mfpu=softvfp` issue.
Reviewers: SjoerdMeijer, dmgreen, ostannard, samparker, JamesNagurne
Reviewed By: ostannard
Subscribers: srhines, javed.absar, kristof.beyls, hiraditya, cfe-commits, llvm-commits
Tags: #clang, #llvm
Differential Revision: https://reviews.llvm.org/D62998
llvm-svn: 362791
Sam Elliott [Fri, 7 Jun 2019 12:20:14 +0000 (12:20 +0000)]
[RISCV] Support Bit-Preserving FP in F/D Extensions
Summary:
This allows some integer bitwise operations to instead be performed by
hardware fp instructions. This is correct because the RISC-V spec
requires the F and D extensions to use the IEEE-754 standard
representation, and fp register loads and stores to be bit-preserving.
This is tested against the soft-float ABI, but with hardware float
extensions enabled, so that the tests also ensure the optimisation also
fires in this case.
Reviewers: asb, luismarques
Reviewed By: asb
Subscribers: hiraditya, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, jrtc27, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, Jim, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D62900
llvm-svn: 362790
Valery Pykhtin [Fri, 7 Jun 2019 12:16:46 +0000 (12:16 +0000)]
[AMDGPU] Constrain the AMDGPU inliner on maximum number of basic blocks in a caller function (compile time performance)
Differential revision: https://reviews.llvm.org/D62917
llvm-svn: 362789
Fangrui Song [Fri, 7 Jun 2019 11:09:33 +0000 (11:09 +0000)]
[ELF] Delete R_PPC64_CALL_PLT from isRelExpr()
It was added by D46654 but is actually never used.
R_PPC64_CALL_PLT (was: R_PPC_CALL_PLT) is a static link-time constant.
Reviewed By: ruiu
Differential Revision: https://reviews.llvm.org/D62994
llvm-svn: 362788
Russell Gallop [Fri, 7 Jun 2019 09:51:44 +0000 (09:51 +0000)]
[X86][test] Add test cases using immediates to builtins-x86.c
These builtins should work with immediate or variable shift operand for
gcc compatibility.
Differential Revision: https://reviews.llvm.org/D62850
llvm-svn: 362786
Sam McCall [Fri, 7 Jun 2019 09:45:17 +0000 (09:45 +0000)]
[CodeComplete] Improve overload handling for C++ qualified and ref-qualified methods.
Summary:
- when a method is not available because of the target value kind (e.g. an &&
method on a Foo& variable), then don't offer it.
- when a method is effectively shadowed by another method from the same class
with a) an identical argument list and b) superior qualifiers, then don't
offer it.
Reviewers: ilya-biryukov
Subscribers: cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D62582
llvm-svn: 362785
Pavel Labath [Fri, 7 Jun 2019 09:43:53 +0000 (09:43 +0000)]
Fix some signed/unsigned comparison warnings
llvm-svn: 362784
Pavel Labath [Fri, 7 Jun 2019 09:43:47 +0000 (09:43 +0000)]
DWARF: Simplify SymbolFileDWARF::GetDWARFCompileUnit
Summary:
The DWARFCompileUnit is set as the "user data" of the lldb compile unit
directly in the constructor (see ParseCompileUnit).
This means that instead of going through unit indexes, we can just fetch
the DWARF unit directly from there.
Reviewers: clayborg, JDevlieghere
Subscribers: aprantl, jdoerfert, lldb-commits
Differential Revision: https://reviews.llvm.org/D62943
llvm-svn: 362783
Dmitri Gribenko [Fri, 7 Jun 2019 09:28:19 +0000 (09:28 +0000)]
Work around a circular dependency between IR and MC introduced in r362735
I replaced the circular library dependency with a forward declaration,
but it is only a workaround, not a real fix.
llvm-svn: 362782
Pengfei Wang [Fri, 7 Jun 2019 08:53:37 +0000 (08:53 +0000)]
[X86] -march=cooperlake (clang)
Support intel -march=cooperlake in clang
Patch by Shengchen Kan (skan)
Differential Revision: https://reviews.llvm.org/D62835
llvm-svn: 362781
Cullen Rhodes [Fri, 7 Jun 2019 08:46:56 +0000 (08:46 +0000)]
[AArch64][AsmParser] error on unexpected SVE predicate type suffix
Summary:
This patch fixes a bug in the assembler that permitted a type suffix on
predicate registers when not expected. For instance, the following was
previously valid:
faddv h0, p0.q, z1.h
This bug was present in all SVE instructions containing predicates with
no type suffix and no predication form qualifier, i.e. /z or /m. The
latter instructions are already caught with an appropiate error message
by the assembler, e.g.:
.text
<stdin>:1:13: error: not expecting size suffix
cmpne p1.s, p0.b/z, z2.s, 0
^
A similar issue for SVE vector registers was fixed in:
https://reviews.llvm.org/D59636
Reviewed By: SjoerdMeijer
Differential Revision: https://reviews.llvm.org/D62942
llvm-svn: 362780
Cullen Rhodes [Fri, 7 Jun 2019 08:37:00 +0000 (08:37 +0000)]
[AArch64][AsmParser] Provide better diagnostics for SVE predicates
Patch by Sander de Smalen (sdesmalen)
Reviewed By: SjoerdMeijer
Differential Revision: https://reviews.llvm.org/D62941
llvm-svn: 362779
George Rimar [Fri, 7 Jun 2019 08:34:18 +0000 (08:34 +0000)]
[llvm-objcopy] - Emit error and don't crash if program header reaches past end of file.
This is https://bugs.llvm.org/show_bug.cgi?id=42122.
If an object file has a size less than program header's file [offset + size]
(i.e. if we have overflow), llvm-objcopy crashes instead of reporting a
error.
The patch fixes this issue.
Differential revision: https://reviews.llvm.org/D62898
llvm-svn: 362778
George Rimar [Fri, 7 Jun 2019 08:31:36 +0000 (08:31 +0000)]
[yaml2elf] - Refactoring followup for D62809
This is a refactoring follow-up for D62809
"Change how we handle implicit sections.".
It allows to simplify the code.
Differential revision: https://reviews.llvm.org/D62912
llvm-svn: 362777
Pengfei Wang [Fri, 7 Jun 2019 08:31:35 +0000 (08:31 +0000)]
[X86] -march=cooperlake (llvm)
Support intel -march=cooperlake in llvm
Patch by Shengchen Kan (skan)
Differential Revision: https://reviews.llvm.org/D62836
llvm-svn: 362776
Sam Parker [Fri, 7 Jun 2019 08:04:18 +0000 (08:04 +0000)]
Fix for lld buildbot
Removed unused (in non-debug builds) variable.
llvm-svn: 362775
Sam Parker [Fri, 7 Jun 2019 07:35:30 +0000 (07:35 +0000)]
[CodeGen] Generic Hardware Loop Support
Patch which introduces a target-independent framework for generating
hardware loops at the IR level. Most of the code has been taken from
PowerPC CTRLoops and PowerPC has been ported over to use this generic
pass. The target dependent parts have been moved into
TargetTransformInfo, via isHardwareLoopProfitable, with
HardwareLoopInfo introduced to transfer information from the backend.
Three generic intrinsics have been introduced:
- void @llvm.set_loop_iterations
Takes as a single operand, the number of iterations to be executed.
- i1 @llvm.loop_decrement(anyint)
Takes the maximum number of elements processed in an iteration of
the loop body and subtracts this from the total count. Returns
false when the loop should exit.
- anyint @llvm.loop_decrement_reg(anyint, anyint)
Takes the number of elements remaining to be processed as well as
the maximum numbe of elements processed in an iteration of the loop
body. Returns the updated number of elements remaining.
llvm-svn: 362774
Dylan McKay [Fri, 7 Jun 2019 06:55:00 +0000 (06:55 +0000)]
[AVR] Expand 16-bit rotations during the legalization stage
In r356860, the legalization logic for BSWAP was modified to ISD::ROTL,
rather than the old ISD::{SHL, SRL, OR} nodes.
This works fine on AVR for 8-bit rotations, but 16-bit rotations are
currently unimplemented - they always trigger an assertion error in the
AVRExpandPseudoInsts pass ("RORW unimplemented").
This patch instructions the legalizer to expand 16-bit rotations into
the previous SHL, SRL, OR pattern it did previously.
This fixes the 'issue-cannot-select-bswap.ll' test. Interestingly, this
test failure seems flaky - it passes successfully on the avr-build-01
buildbot, but fails locally on my Arch Linux install.
llvm-svn: 362773
Michael Pozulp [Fri, 7 Jun 2019 06:28:43 +0000 (06:28 +0000)]
[NFC] Delete trailing whitespace character.
llvm-svn: 362772
Michael Pozulp [Fri, 7 Jun 2019 06:23:54 +0000 (06:23 +0000)]
[llvm-objdump] Print source when subsequent lines in the translation unit come from the same line in two different headers.
Reviewers: grimar, rupprecht, jhenderson
Reviewed By: grimar, jhenderson
Subscribers: llvm-commits, jhenderson
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D62461
llvm-svn: 362771
Sam Clegg [Fri, 7 Jun 2019 06:05:26 +0000 (06:05 +0000)]
[lld] Allow args::getInterger to parse args larger than 2^31-1
Differential Revision: https://reviews.llvm.org/D62933
llvm-svn: 362770
Sam Clegg [Fri, 7 Jun 2019 06:00:46 +0000 (06:00 +0000)]
[WebAssembly] Fix for discarded init functions
When a function is excluded via comdat we shouldn't add it to the
final list of init functions.
Differential Revision: https://reviews.llvm.org/D62983
llvm-svn: 362769
Michael Pozulp [Fri, 7 Jun 2019 05:11:13 +0000 (05:11 +0000)]
[llvm-objdump] Add warning if --disassemble-functions specifies an unknown symbol
Summary: Fixes Bug 41904 https://bugs.llvm.org/show_bug.cgi?id=41904
Reviewers: jhenderson, rupprecht, grimar, MaskRay
Reviewed By: jhenderson, rupprecht, MaskRay
Subscribers: dexonsmith, rupprecht, kristina, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D62275
llvm-svn: 362768
Fangrui Song [Fri, 7 Jun 2019 03:47:22 +0000 (03:47 +0000)]
[MC][ELF] Don't create relocations with section symbols for STB_LOCAL ifunc
We should keep the symbol type (STT_GNU_IFUNC) for a local ifunc because
it may result in an IRELATIVE reloc that the dynamic loader will use to
resolve the address at startup time.
There is another problem that is not fixed by this patch: a PC relative
relocation should also create a relocation with the ifunc symbol.
llvm-svn: 362767
Michael Pozulp [Fri, 7 Jun 2019 03:23:00 +0000 (03:23 +0000)]
[ADT] Enable set_difference() to be used on StringSet
Subscribers: mgorny, mgrang, dexonsmith, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D62992
llvm-svn: 362766
Peter Collingbourne [Fri, 7 Jun 2019 02:30:58 +0000 (02:30 +0000)]
Set an output file name for the override-new-delete.cpp test.
The android_compile.py script requires one.
llvm-svn: 362764
Michael Pozulp [Fri, 7 Jun 2019 01:55:59 +0000 (01:55 +0000)]
[NFC] Test commit.
llvm-svn: 362763
Fangrui Song [Fri, 7 Jun 2019 01:48:26 +0000 (01:48 +0000)]
[LV] Fix -Wunused-function after r362736
llvm-svn: 362762
Matt Arsenault [Fri, 7 Jun 2019 00:14:55 +0000 (00:14 +0000)]
AMDGPU: Don't count mask branch pseudo towards skip threshold
llvm-svn: 362761
Matt Arsenault [Fri, 7 Jun 2019 00:14:45 +0000 (00:14 +0000)]
AMDGPU: Insert skips for blocks with FLAT
This already forced a skip for VMEM, so it should also be done for
flat. I'm somewhat skeptical about the benefit of this though.
llvm-svn: 362760
Nemanja Ivanovic [Thu, 6 Jun 2019 23:49:01 +0000 (23:49 +0000)]
[PowerPC] Exploit the vector min/max instructions
Use the PPC vector min/max instructions for computing the corresponding
operation as these should be faster than the compare/select sequences
we currently emit.
Differential revision: https://reviews.llvm.org/D47332
llvm-svn: 362759
Mitch Phillips [Thu, 6 Jun 2019 23:43:25 +0000 (23:43 +0000)]
Change GWP-ASan build to use '-pthread' instead of '-lpthread' in order
to try and fix android buildbot. Also make sure that the empty dummy
test contains an output file name so the android_build.py wrapper script
doesn't check fail.
llvm-svn: 362758
Richard Smith [Thu, 6 Jun 2019 23:24:18 +0000 (23:24 +0000)]
Factor out duplicated code building a MemberExpr and marking it
referenced.
This reinstates r362563, reverted in r362597.
llvm-svn: 362757
Richard Smith [Thu, 6 Jun 2019 23:24:15 +0000 (23:24 +0000)]
Convert MemberExpr creation and serialization to work the same way as
most / all other Expr subclasses.
This reinstates r362551, reverted in r362597, with a fix to a bug that
caused MemberExprs to sometimes have a null FoundDecl after a round-trip
through an AST file.
llvm-svn: 362756
Jordan Rupprecht [Thu, 6 Jun 2019 23:23:14 +0000 (23:23 +0000)]
Revert [ELF] Simplify the condition to create .interp
This reverts r362355 (git commit
c78c999a9cd7a77b9d13c610c9faebac5d560a55)
This causes some internal tests to fail; details provided offthread.
llvm-svn: 362755
Matt Arsenault [Thu, 6 Jun 2019 22:51:51 +0000 (22:51 +0000)]
AMDGPU: Insert skip branches over return blocks
SIInsertSkips really doesn't understand the control flow, and makes
very stupid assumptions about the block layout. This was able to get
away with not skipping return blocks, since usually after
structurization there is only one placed at the end of the
function. Tail duplication can break this assumption.
llvm-svn: 362754
David Tenty [Thu, 6 Jun 2019 22:07:14 +0000 (22:07 +0000)]
[NFC] Test commit, whitespace change
As per the Developer Policy, upon obtaining commit access.
llvm-svn: 362753
Cameron McInally [Thu, 6 Jun 2019 21:49:59 +0000 (21:49 +0000)]
[NFC][CodeGen] Add unary fneg tests to X86/fma4-intrinsics-x86.ll
llvm-svn: 362752
Alexey Lapshin [Thu, 6 Jun 2019 21:19:39 +0000 (21:19 +0000)]
[DebugInfo] Incorrect debug info record generated for loop counter.
Incorrect Debug Variable Range was calculated while "COMPUTING LIVE DEBUG VARIABLES" stage.
Range for Debug Variable("i") computed according to current state of instructions
inside of basic block. But Register Allocator creates new instructions which were not taken
into account when Live Debug Variables computed. In the result DBG_VALUE instruction for
the "i" variable was put after these newly inserted instructions. This is incorrect.
Debug Value for the loop counter should be inserted before any loop instruction.
Differential Revision: https://reviews.llvm.org/D62650
llvm-svn: 362750
Alexander Timofeev [Thu, 6 Jun 2019 21:13:02 +0000 (21:13 +0000)]
[AMDGPU] Partial revert for the
ba447bae7448435c9986eece0811da1423972fdd
"Divergence driven ISel. Assign register class for cross block values
according to the divergence."
that discovered the design flaw leading to several issues that
required to be solved before.
This change reverts AMDGPU specific changes and keeps common part
unaffected.
llvm-svn: 362749
Cameron McInally [Thu, 6 Jun 2019 21:12:22 +0000 (21:12 +0000)]
[NFC][CodeGen] Add unary fneg tests to X86/fma-intrinsics-x86.ll
llvm-svn: 362748
Craig Topper [Thu, 6 Jun 2019 21:00:04 +0000 (21:00 +0000)]
[X86] Make a bunch of merge masked binops commutable for loading folding.
This primarily affects add/fadd/mul/fmul/and/or/xor/pmuludq/pmuldq/max/min/fmaxc/fminc/pmaddwd/pavg.
We already commuted the unmasked and zero masked versions.
I've added 512-bit stack folding tests for most of the instructions
affected. I've tested needing commuting and not commuting across
unmasked, merged masked, and zero masked. The 128/256 bit instructions
should behave similarly.
llvm-svn: 362746
Amy Huang [Thu, 6 Jun 2019 20:23:05 +0000 (20:23 +0000)]
Add cdb test for global constants
Summary: This creates an integration test for global constants
Reviewers: rnk
Subscribers: llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D62974
llvm-svn: 362745
Sean Fertile [Thu, 6 Jun 2019 20:16:59 +0000 (20:16 +0000)]
Revert "Revert "[ELF] Suppress "STT_SECTION symbol should be defined" on .eh_frame, .debug*, .zdebug* and .gcc_except_table""
This reverts commit
f49f58527a6d8147524d8d6f2eb1feb70f856292.
llvm-svn: 362744
Sean Fertile [Thu, 6 Jun 2019 20:16:53 +0000 (20:16 +0000)]
Revert "Revert "Reland D61583 [ELF] Error on relocations to STT_SECTION symbols if the sections were discarded""
This reverts commit
729111cf1824159bb4dd331cab8a829eab30313f.
Reverting the previous commit breaks other LLD buildbots.
llvm-svn: 362743
Sanjay Patel [Thu, 6 Jun 2019 20:14:06 +0000 (20:14 +0000)]
[InstSimplify] add tests for fcmp with known-never-nan operands; NFC
llvm-svn: 362742
Cameron McInally [Thu, 6 Jun 2019 20:11:30 +0000 (20:11 +0000)]
[NFC][CodeGen] Add unary fneg tests to X86/fma-scalar-combine.ll
llvm-svn: 362741
Francois Ferrand [Thu, 6 Jun 2019 20:06:23 +0000 (20:06 +0000)]
clang-format: better handle namespace macros
Summary:
Other macros are used to declare namespaces, and should thus be handled
similarly. This is the case for crpcut's TESTSUITE macro, or for
unittest-cpp's SUITE macro:
TESTSUITE(Foo) {
TEST(MyFirstTest) {
assert(0);
}
} // TESTSUITE(Foo)
This patch deals with this cases by introducing a new option to specify
lists of namespace macros. Internally, it re-uses the system already in
place for foreach and statement macros, to ensure there is no impact on
performance.
Reviewers: krasimir, djasper, klimek
Reviewed By: klimek
Subscribers: acoomans, cfe-commits, klimek
Tags: #clang
Differential Revision: https://reviews.llvm.org/D37813
llvm-svn: 362740
Sean Fertile [Thu, 6 Jun 2019 19:34:26 +0000 (19:34 +0000)]
Revert "Reland D61583 [ELF] Error on relocations to STT_SECTION symbols if the sections were discarded"
This reverts commit
5d3b3188f722456a6470c7effcacf17656406429.
Breaks the PowerPC multi-stage buildbot.
llvm-svn: 362739
Sean Fertile [Thu, 6 Jun 2019 19:34:18 +0000 (19:34 +0000)]
Revert "[ELF] Suppress "STT_SECTION symbol should be defined" on .eh_frame, .debug*, .zdebug* and .gcc_except_table"
This reverts commit
dcba4828a9ead5f5b1fa27f0853823618075d0e0.
This commit builds on
dcba4828a9ead5f5b1fa27f0853823618075d0e0 which breaks the
multi-staged PowerPC buildbot.
llvm-svn: 362738
Craig Topper [Thu, 6 Jun 2019 19:21:23 +0000 (19:21 +0000)]
[CFLGraph] Add support for unary fneg instruction.
Differential Revision: https://reviews.llvm.org/D62791
llvm-svn: 362737
Renato Golin [Thu, 6 Jun 2019 19:15:52 +0000 (19:15 +0000)]
[LV] Wrap LV illegality reporting in a function. NFC.
A function for loop vectorization illegality reporting has been
introduced:
void LoopVectorizationLegality::reportVectorizationFailure(
const StringRef DebugMsg, const StringRef OREMsg,
const StringRef ORETag, Instruction * const I) const;
The function prints a debug message when the debug for the compilation
unit is enabled as well as invokes the optimization report emitter to
generate a message with a specified tag. The function doesn't cover any
complicated logic when a custom lambda should be passed to the emitter,
only generating a message with a tag is supported.
The function always prints the instruction `I` after the debug message
whenever the instruction is specified, otherwise the debug message
ends with a dot: 'LV: Not vectorizing: Disabled/already vectorized.'
Patch by Pavel Samolysov <samolisov@gmail.com>
llvm-svn: 362736
Jason Liu [Thu, 6 Jun 2019 19:13:36 +0000 (19:13 +0000)]
[AIX] Implement function descriptor on SDAG
Summary:
(1) Function descriptor on AIX
On AIX, a called routine may have 2 distinct symbols associated with it:
* A function descriptor (Name)
* A function entry point (.Name)
The descriptor structure on AIX is the same as those in the ELF V1 ABI:
* The address of the entry point of the function.
* The TOC base address for the function.
* The environment pointer.
The descriptor symbol uses the same name as the source level function in C.
The function entry point is analogous to the symbol we would generate for a
function in a non-descriptor-based ABI, except that it is renamed by
prepending a ".".
Which symbol gets referenced depends on the context:
* Taking the address of the function references the descriptor symbol.
* Calling the function references the entry point symbol.
(2) Speaking of implementation on AIX, for direct function call target, we
create proper MCSymbol SDNode(e.g . ".foo") while constructing SDAG to
replace original TargetGlobalAddress SDNode. Then down the path, we can
take advantage of this MCSymbol.
Patch by: Xiangling_L
Reviewed by: sfertile, hubert.reinterpretcast, jasonliu, syzaara
Differential Revision: https://reviews.llvm.org/D62532
llvm-svn: 362735
Cameron McInally [Thu, 6 Jun 2019 19:02:46 +0000 (19:02 +0000)]
[NFC][CodeGen] Add unary fneg tests to X86/fma4-fneg-combine.ll
llvm-svn: 362733
Craig Topper [Thu, 6 Jun 2019 19:02:18 +0000 (19:02 +0000)]
[InlineCost] Add support for unary fneg.
This adds support for unary fneg based on the implementation of BinaryOperator without the soft float FP cost.
Previously we would just delegate to visitUnaryInstruction. I think the only real change is that we will pass the FastMath flags to SimplifyFNeg now.
Differential Revision: https://reviews.llvm.org/D62699
llvm-svn: 362732
Kadir Cetinkaya [Thu, 6 Jun 2019 18:49:16 +0000 (18:49 +0000)]
[clang][HeaderSearch] Consider all path separators equal
Reviewers: ilya-biryukov, sammccall
Subscribers: cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D62965
llvm-svn: 362731
Cameron McInally [Thu, 6 Jun 2019 18:41:18 +0000 (18:41 +0000)]
[NFC][CodeGen] Add unary fneg tests to X86/fma_patterns.ll
llvm-svn: 362730
Puyan Lotfi [Thu, 6 Jun 2019 18:05:10 +0000 (18:05 +0000)]
Fixing ppc tests: sed -i 's/# REQUIES: ppc/# REQUIRES: ppc/g'
llvm-svn: 362728
Philip Reames [Thu, 6 Jun 2019 18:02:36 +0000 (18:02 +0000)]
[LoopPred] Fix a bug in unconditional latch bailout introduced in r362284
This is a really silly bug that even a simple test w/an unconditional latch would have caught. I tried to guard against the case, but put it in the wrong if check. Oops.
llvm-svn: 362727
Michael Kruse [Thu, 6 Jun 2019 17:15:36 +0000 (17:15 +0000)]
[ScheduleTreeTransform] Silence compiler warning. NFC.
Use size_t for position which is the return type type ArrayRef::size()
it is compared to.
llvm-svn: 362724
Simon Pilgrim [Thu, 6 Jun 2019 17:04:13 +0000 (17:04 +0000)]
[DAGCombine] MergeConsecutiveStores - improve non-temporal load\store handling (PR42123)
This patch is the first step towards ensuring MergeConsecutiveStores correctly handles non-temporal loads\stores:
1 - When merging load\stores we must ensure that they all have the same non-temporal flag. This is unlikely to occur, but can in strange cases where we're storing at the end of one page and the beginning of another.
2 - The merged load\store node must retain the non-temporal flag.
Differential Revision: https://reviews.llvm.org/D62910
llvm-svn: 362723
Fangrui Song [Thu, 6 Jun 2019 17:03:10 +0000 (17:03 +0000)]
[PPC32] Support GD/LD/IE/LE TLS models and their relaxations
Reviewed By: ruiu
Differential Revision: https://reviews.llvm.org/D62940
llvm-svn: 362722
Fangrui Song [Thu, 6 Jun 2019 17:03:00 +0000 (17:03 +0000)]
[PPC32] Improve the 32-bit PowerPC port
Many -static/-no-pie/-shared/-pie applications linked against glibc or musl
should work with this patch. This also helps FreeBSD PowerPC64 to migrate
their lib32 (PR40888).
* Fix default image base and max page size.
* Support new-style Secure PLT (see below). Old-style BSS PLT is not
implemented, so it is not suitable for FreeBSD rtld now because it doesn't
support Secure PLT yet.
* Support more initial relocation types:
R_PPC_ADDR32, R_PPC_REL16*, R_PPC_LOCAL24PC, R_PPC_PLTREL24, and R_PPC_GOT16.
The addend of R_PPC_PLTREL24 is special: it decides the call stub PLT type
but it should be ignored for the computation of target symbol VA.
* Support GNU ifunc
* Support .glink used for lazy PLT resolution in glibc
* Add a new thunk type: PPC32PltCallStub that is similar to PPC64PltCallStub.
It is used by R_PPC_REL24 and R_PPC_PLTREL24.
A PLT stub used in -fPIE/-fPIC usually loads an address relative to
.got2+0x8000 (-fpie/-fpic code uses _GLOBAL_OFFSET_TABLE_ relative
addresses).
Two .got2 sections in two object files have different addresses, thus a PLT stub
can't be shared by two object files. To handle this incompatibility,
change the parameters of Thunk::isCompatibleWith to
`const InputSection &, const Relocation &`.
PowerPC psABI specified an old-style .plt (BSS PLT) that is both
writable and executable. Linkers don't make separate RW- and RWE segments,
which causes all initially writable memory (think .data) executable.
This is a big security concern so a new PLT scheme (secure PLT) was developed to
address the security issue.
TLS will be implemented in D62940.
glibc older than ~2012 requires .rela.dyn to include .rela.plt, it can
not handle the DT_RELA+DT_RELASZ == DT_JMPREL case correctly. A hack
(not included in this patch) in LinkerScript.cpp addOrphanSections() to
work around the issue:
if (Config->EMachine == EM_PPC) {
// Older glibc assumes .rela.dyn includes .rela.plt
Add(In.RelaDyn);
if (In.RelaPlt->isLive() && !In.RelaPlt->Parent)
In.RelaDyn->getParent()->addSection(In.RelaPlt);
}
Reviewed By: ruiu
Differential Revision: https://reviews.llvm.org/D62464
llvm-svn: 362721
Cameron McInally [Thu, 6 Jun 2019 16:55:51 +0000 (16:55 +0000)]
[NFC][CodeGen] Add unary fneg tests to X86/fma_patterns_wide.ll
llvm-svn: 362720
Nico Weber [Thu, 6 Jun 2019 16:55:05 +0000 (16:55 +0000)]
gn build: Merge r362685
llvm-svn: 362719
Dmitri Gribenko [Thu, 6 Jun 2019 16:47:06 +0000 (16:47 +0000)]
Remove unused PPC.h includes under llvm/lib/Target/PowerPC.
llvm-svn: 362718
Craig Topper [Thu, 6 Jun 2019 16:39:04 +0000 (16:39 +0000)]
[X86] Make masked floating point equality/ordered compares commutable for load folding purposes.
Same as what is supported for the unmasked form.
llvm-svn: 362717
Xinliang David Li [Thu, 6 Jun 2019 16:29:44 +0000 (16:29 +0000)]
[Profile]: Add runtime interface to specify file handle for profile data (Part-II)
Test cases
Author: Sajjad Mirza
Differential Revision: http://reviews.llvm.org/D62541
llvm-svn: 362716
Cameron McInally [Thu, 6 Jun 2019 16:13:23 +0000 (16:13 +0000)]
[NFC][CodeGen] Add unary fneg tests to fmul-combines.ll fnabs.ll
llvm-svn: 362715
Fangrui Song [Thu, 6 Jun 2019 15:31:45 +0000 (15:31 +0000)]
[PowerPC] Add R_PPC_IRELATIVE
This will be used by lld's powerpc port.
llvm-svn: 362713
Cameron McInally [Thu, 6 Jun 2019 15:29:11 +0000 (15:29 +0000)]
[NFC][CodeGen] Add unary fneg tests to fp-fast.ll fp-fold.ll fp-in-intregs.ll fp-stack-compare-cmov.ll fp-stack-compare.ll fsxor-alignment.ll
llvm-svn: 362712
Whitney Tsang [Thu, 6 Jun 2019 15:12:49 +0000 (15:12 +0000)]
[DA] Add an option to control delinearization validity checks
Summary: Dependence Analysis performs static checks to confirm validity
of delinearization. These checks often fail for 64-bit targets due to
type conversions and integer wrapping that prevent simplification of the
SCEV expressions. These checks would also fail at compile-time if the
lower bound of the loops are compile-time unknown.
For example:
void foo(int n, int m, int a[][m]) {
for (int i = 0; i < n; ++i)
for (int j = 0; j < m; ++j) {
a[i][j] = a[i+1][j-2];
}
}
opt -mem2reg -instcombine -indvars -loop-simplify -loop-rotate -inline
-pass-remarks=.* -debug-pass=Arguments
-da-permissive-validity-checks=false k3.ll -analyze -da
will produce the following by default:
da analyze - anti [* *|<]!
but will produce the following expected dependence vector if the
validity checks are disabled:
da analyze - consistent anti [1 -2]!
This revision will introduce a debug option that will leave the validity
checks in place by default, but allow them to be turned off. New tests
are added for cases where it cannot be proven at compile-time that the
individual subscripts stay in-bound with respect to a particular
dimension of an array. These tests enable the option to provide user
guarantee that the subscripts do not over/under-flow into other
dimensions, thereby producing more accurate dependence vectors.
For prior discussion on this topic, leading to this change, please see
the following thread:
http://lists.llvm.org/pipermail/llvm-dev/2019-May/132372.html
Reviewers: Meinersbur, jdoerfert, kbarton, dmgreen, fhahn
Reviewed By: Meinersbur, jdoerfert, dmgreen
Subscribers: fhahn, hiraditya, javed.absar, llvm-commits, Whitney,
etiotto
Tag: LLVM
Differential Revision: https://reviews.llvm.org/D62610
llvm-svn: 362711
Cameron McInally [Thu, 6 Jun 2019 14:52:16 +0000 (14:52 +0000)]
[NFC][CodeGen] Remove duplicate test in fp-fast.ll
@test10 is the same as @test11.
llvm-svn: 362710
Ilya Biryukov [Thu, 6 Jun 2019 14:51:55 +0000 (14:51 +0000)]
gn build: Add new tidy checks to gn files
The checks were added in r362673 and r362672.
llvm-svn: 362709
Jason Liu [Thu, 6 Jun 2019 14:36:43 +0000 (14:36 +0000)]
[AIX] Implement call lowering with parameters could pass onto GPRs
Summary:
This patch implements SDAG call lowering on AIX for functions
which only have parameters that could fit into GPRs.
Reviewers: hubert.reinterpretcast, syzaara
Differential Revision: https://reviews.llvm.org/D62823
llvm-svn: 362708
Yitzhak Mandelbaum [Thu, 6 Jun 2019 14:20:29 +0000 (14:20 +0000)]
[LibTooling] Add insert/remove convenience functions for creating `ASTEdit`s.
Summary: `change()` is an all purpose function; the revision adds simple shortcuts for the specific operations of inserting (before/after) or removing source.
Reviewers: ilya-biryukov
Subscribers: cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D62621
llvm-svn: 362707
Haojian Wu [Thu, 6 Jun 2019 13:43:38 +0000 (13:43 +0000)]
[clang-tidy] Another attempt to fix misc-redundant-expression check.
Correct the fix of rL3627011, the isValueDependent guard was added in a wrong place in rL362701.
llvm-svn: 362706
Thomas Preud'homme [Thu, 6 Jun 2019 13:21:06 +0000 (13:21 +0000)]
FileCheck [6/12]: Introduce numeric variable definition
Summary:
This patch is part of a patch series to add support for FileCheck
numeric expressions. This specific patch introduces support for defining
numeric variable in a CHECK directive.
This commit introduces support for defining numeric variable from a
litteral value in the input text. Numeric expressions can then use the
variable provided it is on a later line.
Copyright:
- Linaro (changes up to diff 183612 of revision D55940)
- GraphCore (changes in later versions of revision D55940 and
in new revision created off D55940)
Reviewers: jhenderson, chandlerc, jdenny, probinson, grimar, arichardson, rnk
Subscribers: hiraditya, llvm-commits, probinson, dblaikie, grimar, arichardson, tra, rnk, kristina, hfinkel, rogfer01, JonChesterfield
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D60386
llvm-svn: 362705
Owen Reynolds [Thu, 6 Jun 2019 13:19:50 +0000 (13:19 +0000)]
[llvm-ar] Create thin archives with MRI scripts
This patch implements the "CREATE_THIN" MRI script command, allowing thin archives to be created via MRI scripts.
Differential Revision: https://reviews.llvm.org/D62919
llvm-svn: 362704
Sanjay Patel [Thu, 6 Jun 2019 13:18:20 +0000 (13:18 +0000)]
[InstCombine] add tests for loads of bitcasted vector pointer; NFC
llvm-svn: 362703
Nikolai Kosjar [Thu, 6 Jun 2019 13:13:27 +0000 (13:13 +0000)]
[clang-tidy] Make the plugin honor NOLINT
Instantiate a ClangTidyDiagnosticConsumer also for the plugin case and
let it forward the diagnostics to the external diagnostic engine that is
already in place.
One minor difference to the clang-tidy executable case is that the
compiler checks/diagnostics are referred to with their original name.
For example, for -Wunused-variable the plugin will refer to the check as
"-Wunused-variable" while the clang-tidy executable will refer to that
as "clang-diagnostic- unused-variable". This is because the compiler
diagnostics never reach ClangTidyDiagnosticConsumer.
Differential Revision: https://reviews.llvm.org/D61487
llvm-svn: 362702
Haojian Wu [Thu, 6 Jun 2019 12:58:48 +0000 (12:58 +0000)]
[clang-tidy] Fix an assertion failure in misc-redundant-expression.
Summary:
The assertion "isIntegerConstantExpr" is triggered in the
isIntegerConstantExpr(), we should not call it if the expression is value
dependent.
Reviewers: gribozavr
Subscribers: xazax.hun, cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D62947
llvm-svn: 362701
Adhemerval Zanella [Thu, 6 Jun 2019 12:38:11 +0000 (12:38 +0000)]
AArch64] Handle ISD::LRINT and ISD::LLRINT for float16
This patch is a follow up for D62018 to add lrint/llrint
support for float16.
Reviewed By: SjoerdMeijer
Differential Revision: https://reviews.llvm.org/D62863
llvm-svn: 362700
Benjamin Kramer [Thu, 6 Jun 2019 12:35:46 +0000 (12:35 +0000)]
Revert "[SCEV] Use wrap flags in InsertBinop"
This reverts commit r362687. Miscompiles llvm-profdata during selfhost.
llvm-svn: 362699
Adhemerval Zanella [Thu, 6 Jun 2019 11:53:26 +0000 (11:53 +0000)]
[AArch64] Handle ISD::LROUND and ISD::LLROUND for float16
This patch is a follow up for D61391 to add lround/llround
support for float16.
Reviewed By: SjoerdMeijer
Differential Revision: https://reviews.llvm.org/D62861
llvm-svn: 362698
Simon Pilgrim [Thu, 6 Jun 2019 11:15:36 +0000 (11:15 +0000)]
[X86][SSE] Add nonuniform constant vector test for PR42105
llvm-svn: 362697
Dmitri Gribenko [Thu, 6 Jun 2019 10:37:06 +0000 (10:37 +0000)]
Include what you use in LanaiAsmParser.cpp
llvm-svn: 362696
Simon Pilgrim [Thu, 6 Jun 2019 10:21:18 +0000 (10:21 +0000)]
[DAGCombine] Cleanup isNegatibleForFree/GetNegatedExpression. NFCI.
Prep work for PR42105 - clang-format, use auto for cast and merge nested if()s
llvm-svn: 362695
Simon Pilgrim [Thu, 6 Jun 2019 10:15:26 +0000 (10:15 +0000)]
Fix whitespace indentation. NFCI.
Tabs are not our friends.
llvm-svn: 362694
Luis Marques [Thu, 6 Jun 2019 10:12:28 +0000 (10:12 +0000)]
[RISCV] Disable test/Analysis/CostModel/RISCV tests if RISCV backend not built
Adds missing lit.local.cfg. Fixes rL362691.
llvm-svn: 362693
Petar Avramovic [Thu, 6 Jun 2019 10:00:41 +0000 (10:00 +0000)]
[MIPS GlobalISel] Select sqrt
Select G_FSQRT for MIPS32.
Differential Revision: https://reviews.llvm.org/D62905
llvm-svn: 362692
Luis Marques [Thu, 6 Jun 2019 09:47:53 +0000 (09:47 +0000)]
[RISCV] Add CostModel GEP tests
Differential Revision: https://reviews.llvm.org/D61185
llvm-svn: 362691
Petar Avramovic [Thu, 6 Jun 2019 09:22:37 +0000 (09:22 +0000)]
[MIPS GlobalISel] Select fabs
Select G_FABS for MIPS32.
Differential Revision: https://reviews.llvm.org/D62903
llvm-svn: 362690
Petar Avramovic [Thu, 6 Jun 2019 09:16:58 +0000 (09:16 +0000)]
[MIPS GlobalISel] Select fpext and fptrunc
Select G_FPEXT and G_FPTRUNC for MIPS32.
Differential Revision: https://reviews.llvm.org/D62902
llvm-svn: 362689
Petar Avramovic [Thu, 6 Jun 2019 09:02:24 +0000 (09:02 +0000)]
[MIPS GlobalISel] Select floor and ceil
Select G_FFLOOR and G_FCEIL for MIPS32.
Differential Revision: https://reviews.llvm.org/D62901
llvm-svn: 362688
Sam Parker [Thu, 6 Jun 2019 08:56:26 +0000 (08:56 +0000)]
[SCEV] Use wrap flags in InsertBinop
If the given SCEVExpr has no (un)signed flags attached to it, transfer
these to the resulting instruction or use them to find an existing
instruction.
Differential Revision: https://reviews.llvm.org/D61934
llvm-svn: 362687
Ilya Biryukov [Thu, 6 Jun 2019 08:32:25 +0000 (08:32 +0000)]
[clangd] Remove unused signature help quality signal. NFC
ContainsActiveParameter is not used anywhere, set incorrectly (see the
removed FIXME) and has no unit tests.
Removing it to simplify the code.
llvm-svn: 362686
Pengfei Wang [Thu, 6 Jun 2019 08:28:42 +0000 (08:28 +0000)]
[X86] Add ENQCMD instructions
For more details about these instructions, please refer to the latest
ISE document:
https://software.intel.com/en-us/download/intel-architecture-instruction-set-extensions-programming-reference.
Patch by Tianqing Wang (tianqing)
Differential Revision: https://reviews.llvm.org/D62282
llvm-svn: 362685