Boyuan Zhang [Wed, 16 Jun 2021 15:39:16 +0000 (11:39 -0400)]
radeon/vcn: allocate non-tmz context buffer for VCN2+
By design, context buffer should be allocated as TMZ buffer for secure playback
for VCN 1 only. For VCN 2&2+, context buffer should be moved out of TMZ.
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11388>
Boyuan Zhang [Mon, 14 Jun 2021 17:35:48 +0000 (13:35 -0400)]
radeon/vcn: move calc_dpb_size into create_decoder
Dpb buffer size calculation should based on the values provided in player's
decoder creation call. db_alignmet should be decided in decoder creation
call as well. Therefore, move db_alignment and dpb buffer size calculation
from rvcn_dec_message_decode to radeon_create_decoder function.
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11378>
Jason Ekstrand [Tue, 15 Jun 2021 21:57:25 +0000 (16:57 -0500)]
docs/isl: Add detailed documentation about CCS compression
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11366>
Jason Ekstrand [Tue, 15 Jun 2021 21:20:14 +0000 (16:20 -0500)]
docs/isl: Add detailed documentation about tiling on Intel GPUs
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11366>
Jason Ekstrand [Tue, 15 Jun 2021 04:44:05 +0000 (23:44 -0500)]
docs/isl: Add detailed documentation about isl formats
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11366>
Jason Ekstrand [Tue, 15 Jun 2021 02:33:35 +0000 (21:33 -0500)]
docs/isl: Document ISL's units
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11366>
Jason Ekstrand [Tue, 15 Jun 2021 02:33:18 +0000 (21:33 -0500)]
isl: Document more members of isl_surf
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11366>
Jason Ekstrand [Mon, 14 Jun 2021 21:55:21 +0000 (16:55 -0500)]
docs: Begin documenting ISL
This commit mostly just adds the framework required to scrape
documentation out of the ISL sources and headers. The method chosen
here is a combination of doxygen and breathe (a sphinx extension for
doxygen integration). I'll freely admit that doxygen is pretty terrible
but it seems like the best option we have available to us today.
Acked-by: Emma Anholt <emma@anholt.net>
Acked-by: Daniel Stone <daniels@collabora.com>
Acked-by: Erik Faye-Lund <erik.faye-lund@collabora.com>.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11366>
Mike Blumenkrantz [Tue, 11 May 2021 16:10:05 +0000 (12:10 -0400)]
zink: remove inlinable_uniforms_dirty_mask
this should've always just been flagging the shaders dirty directly
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11405>
Mike Blumenkrantz [Fri, 18 Jun 2021 04:17:10 +0000 (00:17 -0400)]
zink: remove duplicated bitflag filtering for inline uniforms
'bits' already does this
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11405>
Samuel Pitoiset [Wed, 9 Jun 2021 12:29:25 +0000 (14:29 +0200)]
radv: create only one pipeline for decompressing depth/stencil images
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11263>
Samuel Pitoiset [Wed, 9 Jun 2021 12:26:15 +0000 (14:26 +0200)]
radv: always decompress both aspects of a depth/stencil image
If compressed rendering is only used for the depth aspect of a
depth/stencil image, stencil might also be compressed and it needs
to be decompressed. This only happens for non-TC compatible images.
As long as the driver needs to decompress the depth aspect, I don't
think that decompressing the stencil aspect introduces extra cost.
Fixes dEQP-VK.renderpass*late_fragment_tests*.d32_sfloat_s8_uint for
chips that don't support TC-compat HTILE.
Cc: 21.1 mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11263>
Samuel Pitoiset [Thu, 17 Jun 2021 12:46:50 +0000 (14:46 +0200)]
radv: reject binding buffer/image when the device memory is too small
From the Vulkan spec 1.2.181:
"The difference of the size of memory and memoryOffset must be
greater than or equal to the size member of the
VkMemoryRequirements structure returned from a call to
vkGetImageMemoryRequirements with the same image"
This is invalid usage but adding a check in the driver is safe and
might avoid spurious failures.
This is a workaround for the inventory GPU hang with Cyberpunk 2077
which is actually a game bug. Luckily the game handles this error
gracefully.
Since the addrlib change from March, addrlib now selects a better
swizzle mode (4KB instead of 64KB) which reduces image size. Though,
the game assumes that an image with 2 mips is always smaller than the
same image but with 6 mips. This is not always true if the swizzle mode
is different. Then, it creates a D312 heap that is too small for the 2
mips image and the GPU hang with a memory violation, ugh...
Note that next vkd3d-proton release should also reject this but
fixing both sides is fine.
Cc: 21.1 mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4823
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4593
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11448>
Pierre-Eric Pelloux-Prayer [Mon, 14 Jun 2021 07:53:45 +0000 (09:53 +0200)]
radeonsi: skip instance_count==0 draws on <= GFX9
This changes seems to prevent a hang, at least on Renoir chips.
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4866
Cc: mesa-stable
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11356>
Vinson Lee [Mon, 14 Jun 2021 00:09:46 +0000 (17:09 -0700)]
nvc0/ir: Initialize Limits members in constructor.
Fix defect reported by Coverity Scan.
Uninitialized scalar field (UNINIT_CTOR)
uninit_member: Non-static class member min is not initialized in this constructor nor in any functions that it calls.
uninit_member: Non-static class member max is not initialized in this constructor nor in any functions that it calls.
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11351>
Vinson Lee [Sun, 13 Jun 2021 05:50:32 +0000 (22:50 -0700)]
intel/vec4: Add missing break statement.
Fix defect reported by Coverity Scan.
Missing break in switch (MISSING_BREAK)
unterminated_case: The case for value
VEC4_OPCODE_ZERO_OOB_PUSH_REGS is not terminated by a break
statement.
Fixes:
89fd196f6b5 ("intel/vec4: Add support for masking pushed data")
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11347>
Emma Anholt [Tue, 18 May 2021 23:04:47 +0000 (16:04 -0700)]
i915g: Switch to using nir-to-tgsi.
This fixes ~10% of the GLES2 failures thanks to having a better compiler,
though in some cases we get some new compile fails due to instr count or
uniform count. We still have to do NIR-to-TGSI because the NIR gallivm
draw path isn't ready for non-native-integer NIR code, and st/mesa treats
native-integer as a screen property instead of a stage property.
Other than the noted regressions in the xfails, for
dEQP-GLES2.functional.uniform_api.random.74: compile fail changes reasons
triggering an aassertion instead of drawing magenta.
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11329>
Emma Anholt [Sun, 13 Jun 2021 16:39:23 +0000 (09:39 -0700)]
i915g: Handle fragment depth being in OUT[1] not OUT[0].
Prevents regressions when switching to nir-to-tgsi which orders the
outputs differently.
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11329>
Emma Anholt [Sun, 13 Jun 2021 15:07:14 +0000 (08:07 -0700)]
nir_to_tgsi: Support integer sysvals on !CAP_INTEGERS hardware.
glsl_to_tgsi does the same thing, needed for the draw path on i915g.
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11329>
Emma Anholt [Thu, 3 Jun 2021 23:20:12 +0000 (16:20 -0700)]
nir_to_tgsi: Fix internal handling of NIR uints for !CAP_INTEGERS
If we called nir_lower_int_to_float(), then ALU-consumed ints got turned
into floats and we have to interpret them that way.
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11329>
Eric Anholt [Wed, 12 Aug 2020 18:17:28 +0000 (11:17 -0700)]
nir: Do peephole select on other instructions if the limit is ~0.
limit==0 is the signal for "don't peephole anything but a move that will
be optimized aways." limit > 0 is "up to N alu instructions may be moved
out." nir-to-tgsi uses ~0 as the indicator of "No, we really need to
eliminate all if instructions" on hardware like i915 that doesn't have
control flow.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11329>
Emma Anholt [Thu, 3 Jun 2021 18:10:48 +0000 (11:10 -0700)]
nir/lower_int_to_float: Make sure the cursor is in the right spot.
We need to make get it updated after we may have nir_instr_remove()d an
instruction, and when we cross blocks. This didn't really matter before
because the only builder usage was idiv, which other users of
lower_int_to_float were probably never hitting.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11329>
Emma Anholt [Mon, 7 Jun 2021 22:09:33 +0000 (15:09 -0700)]
i915g: Allow fragment coord conventions TGSI properties to be set.
The frontend lowering handles normalizing the conventions to the only
model we support, we just need to ignore the property in the TGSI.
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11329>
Emma Anholt [Mon, 7 Jun 2021 18:32:08 +0000 (11:32 -0700)]
i915: Drop assertion failure about seeing each const decled once.
nir_to_tgsi sometimes emits multiple decls currently, but we don't
actually care because we're just checking which ones are live.
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11329>
Emma Anholt [Tue, 8 Jun 2021 19:05:42 +0000 (12:05 -0700)]
i915: Disable vertex texturing and delete the code.
It's not a required feature of the GL2.1 or GLES2, and you really don't
want to be doing SW VS access of the write-combined texture data. Also,
avoids memory corruption in deqp:
Test case 'dEQP-GLES2.functional.texture.vertex.cube.filtering.linear_mipmap_nearest_linear_repeat'..
Mesa: User error: GL_INVALID_ENUM in glGetIntegerv(pname=GL_MAJOR_VERSION)
Fail (Image comparison failed)
Test case 'dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_depth_funcs.stencil_equal_depth_always'..
==559181== Invalid read of size 4
==559181== at 0x641E8D0: i915_drm_buffer_unmap (i915_drm_buffer.c:204)
==559181== by 0x64151EB: i915_cleanup_vertex_sampling (i915_state.c:449)
==559181== by 0x640AEA7: i915_draw_vbo (i915_context.c:134)
==559181== by 0x640AEA7: i915_draw_vbo (i915_context.c:55)
==559181== by 0x61367B1: cso_draw_vbo (cso_context.c:1524)
[...]
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11329>
Yiwei Zhang [Wed, 9 Jun 2021 22:23:24 +0000 (22:23 +0000)]
anv: enable multi-planar support for drm format modifier
This patch only enables the below VkFormat:
- VK_FORMAT_G8_B8R8_2PLANE_420_UNORM
This patch ensures the proper behavior of the below APIs:
- vkGetPhysicalDeviceFormatProperties2
- vkGetPhysicalDeviceImageFormatProperties2
- vkCreateImage
- vkGetImageSubresourceLayout
- vkGetImageDrmFormatModifierPropertiesEXT
- vkGetImageMemoryRequirements
- vkGetImageMemoryRequirements2
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Chad Versace <chad@kiwitree.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11281>
Yiwei Zhang [Wed, 9 Jun 2021 00:53:55 +0000 (00:53 +0000)]
anv: support multi-planar format in add_all_surfaces_explicit_layout
Add initial multi-planar format support on the images with modifiers:
- With aux usage,
- Format plane count must be 1.
- Memory plane count must be 2.
- Without aux usage,
- Each format plane must map to a distinct memory plane.
For the other cases, currently there is no way to properly map memory
planes to format planes and aux planes due to the lack of defined ABI
for external multi-planar images.
This patch doesn't include some potentially supported cases like all
format planes mapping to a single memory plane, additional refactoring
is needed to workaround explicit base offset + ANV_OFFSET_IMPLICIT.
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Chad Versace <chad@kiwitree.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11281>
Yiwei Zhang [Wed, 16 Jun 2021 20:53:47 +0000 (20:53 +0000)]
anv: fix some log formats
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Chad Versace <chad@kiwitree.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11281>
Emma Anholt [Thu, 17 Jun 2021 23:03:31 +0000 (16:03 -0700)]
freedreno: Add some cheza flakes from the last week.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11453>
Emma Anholt [Thu, 17 Jun 2021 20:24:45 +0000 (13:24 -0700)]
freedreno: Skip staging blits from uninitialized resources.
When storing depth- or stencil-only texture data that has been packed into
a depth/stencil texture, the tex store gets PIPE_MAP_READ added onto it
since the other channel will get ORed into the incoming data, but
sometimes we know that the other component is undefined because the whole
texture is either fresh or just invalidated.
Cleans up a confusing extra blit in a dEQP case I've been debugging, and
should be less work for dEQP CI.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11452>
Emma Anholt [Thu, 17 Jun 2021 19:06:25 +0000 (12:06 -0700)]
freedreno: Add more detailed blit debug in FD_MESA_DEBUG=msgs.
For debugging the batch cache, it really helps to see the blits that
happen, and which are staging blits in the transfer map process.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11452>
Emma Anholt [Thu, 17 Jun 2021 19:57:31 +0000 (12:57 -0700)]
freedreno/fdl: Give the tiling mode a nice name in debug dumps.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11452>
Emma Anholt [Thu, 17 Jun 2021 17:54:46 +0000 (10:54 -0700)]
freedreno: Move FD_MESA_DEBUG=msgs output to mesa_logi.
It didn't work unless you had a debug build, and I regularly want to use
it on non-debug builds.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11452>
Emma Anholt [Thu, 17 Jun 2021 17:46:28 +0000 (10:46 -0700)]
freedreno: Add perf_debug() for our software conditional rendering.
We could do it in hardware, and turnip does, but it hasn't bubbled up our
priorities yet. At least make it more discoverable when you stumble over
it.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11452>
Rob Clark [Thu, 17 Jun 2021 19:03:57 +0000 (12:03 -0700)]
freedreno: Defer freeing batch->key
We use the same key in autotune to track historical data about a given
framebuffer state, to inform the decision about using gmem vs sysmem
rendering. Which means we need the key to stick around during the
flush, even if the batch is removed from the batch-cache before the
flush.
Fixes:
507f701d9e8 ("freedreno: Fix batch flush race condition")
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11450>
Caio Marcelo de Oliveira Filho [Thu, 25 Feb 2021 20:31:51 +0000 (12:31 -0800)]
spirv: Fix handling of OpBranchConditional with same THEN and ELSE
When an OpBranchConditional that had two equal branches was parsed, we
were treating it as a regular OpBranch. However this doesn't work
well when there's an associated OpSelectionMerge. We ended up
skipping marking the merge block as such, and depending on what was
inside the construct we would end up trying to process the block
twice.
Fix this by keeping the vtn_if around, but when emitting NIR identify
the two equal branch case.
Fixes:
9c2a11430e1 ("spirv: Rewrite CFG construction")
Closes: #3786, #4580
Reviewed-by: Yevhenii Kolesnikov <yevhenii.kolesnikov@globallogic.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9297>
Icecream95 [Mon, 7 Jun 2021 07:33:54 +0000 (19:33 +1200)]
pan/mdg: Fix reading a spilt register in the bundle it's written
Read directly from the instruction getting spilt. Otherwise a fill
will be inserted before the spill writing the value, so the
instruction reading the spilt value gets garbage data.
Use the bundle_id to check if the instructions are in the same bundle.
Insert a move instruction, as the spill needs the value in a LD/ST
register such as AL0, while the ALU instruction reading the value
needs it in a work register such as R0.
Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4857
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11212>
Icecream95 [Mon, 7 Jun 2021 07:30:02 +0000 (19:30 +1200)]
pan/mdg: Fill from TLS before spilling non-SSA nodes
Otherwise the data already written to the node will get overwritten.
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11212>
Icecream95 [Mon, 7 Jun 2021 07:25:42 +0000 (19:25 +1200)]
pan/mdg: Reorder some code in mir_spill_register
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11212>
Icecream95 [Mon, 7 Jun 2021 07:21:41 +0000 (19:21 +1200)]
pan/mdg: Add a bundle ID to instructions
So that it is possible to check if two instructions were scheduled
into the same bundle.
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11212>
Rob Clark [Wed, 16 Jun 2021 23:36:59 +0000 (16:36 -0700)]
freedreno/a6xx: Skip nv_copy_image tests
These look pretty redundant with arb_copy_image, so skip to keep CI
runtime reasonable.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11402>
Rob Clark [Sun, 13 Jun 2021 20:38:00 +0000 (13:38 -0700)]
freedreno/a6xx: Flip on copy_image
Now that we have the rest of format "casting" sharp edges sorted, flip
on copy_image and gles32.
Unfortunately it adds back to piglit xfails (but at least that is more
than offset by my previous round of piglit fixes, and these are pretty
much all things we know had issues based on corresponding nv_copy_image
tests).
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11402>
Rob Clark [Wed, 16 Jun 2021 19:13:21 +0000 (12:13 -0700)]
freedreno: Fix for multi-draw blits
We have some logic to detect when u_blitter generated draws overwrite
the entire render-target, so we know we can discard anything previous.
But some blits (like multi-sample) do multiple draws. We don't want to
discard the earlier draws from the same blit.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11402>
Rob Clark [Tue, 15 Jun 2021 23:50:31 +0000 (16:50 -0700)]
freedreno/a6xx: Handle u/snorm vs u/sint validation
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11402>
Rob Clark [Tue, 15 Jun 2021 23:35:57 +0000 (16:35 -0700)]
freedreno/a6xx: Use UNORM for SNORM copy blits
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11402>
Rob Clark [Wed, 16 Jun 2021 17:05:45 +0000 (10:05 -0700)]
freedreno/blitter: Flush before self-blits
In paths where we are handling blits on the 3d pipe, if src==dst we need
to flush to ensure what gets sampled by the blit shader reflects the
results of any previous blits.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11402>
Rob Clark [Wed, 16 Jun 2021 17:20:05 +0000 (10:20 -0700)]
freedreno: Fix flushes with NULL batch
Sequences that pctx->set_framebuffer_state() before pctx->flush() will
see ctx->batch being NULL.. but they still need to call fd_bc_flush(ctx)
to ensure pending batches associated with the context are flushed.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11402>
Iván Briano [Wed, 16 Jun 2021 22:49:25 +0000 (15:49 -0700)]
intel/nir: Fix txs for null surfaces
Closes: #4860
Fixes:
05a37e24220 ("intel/nir: Set lower txs with non-zero LOD")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11435>
Emma Anholt [Tue, 15 Jun 2021 20:58:50 +0000 (13:58 -0700)]
freedreno: Flush batches upon destroying the ctx.
The invalidate would take it out of the bc tracking, so you could go
allocate a new batch->idx matching this one, while this one is still in
the bc using that idx.
You can't generate any new rendering with the ctx's old batches at this
point, anyway, so just flush for simplicity.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11439>
Emma Anholt [Tue, 15 Jun 2021 19:53:34 +0000 (12:53 -0700)]
freedreno: Remove broken back_blit optimization.
It wasn't checking that the transfer map would definitely overwrite all of
the data being initialized by the back blit, and if we knew that it
would then the caller would have provided PIPE_MAP_DISCARD_WHOLE_RESOURCE.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11439>
Emma Anholt [Tue, 15 Jun 2021 17:43:11 +0000 (10:43 -0700)]
freedreno: Move the !MAP_WRITE write batch refcounting to the branch.
For MAP_WRITE, we flush all the batches referencing the BO, so the write
batch will get flushed anyway. No need to take an extra ref.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11439>
Emma Anholt [Tue, 15 Jun 2021 17:38:49 +0000 (10:38 -0700)]
freedreno: Fix batch reference handling in flush_resource().
We take references under the lock, but then accessed the lock-requiring
batch_cache structure without holding the lock. The batches wouldn't get
freed and removed from their slots until the last ref goes away so it was
safe (other than the assert at the end), but writing the simple code is
shorter and requires fewer assumptions.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11439>
Iago Toral Quiroga [Thu, 17 Jun 2021 10:12:46 +0000 (12:12 +0200)]
v3dv: implement VK_EXT_index_type_uint8
Relevant CTS tests:
dEQP-VK.pipeline.input_assembly.*.index_type_uint8.*
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11444>
Charlie [Fri, 11 Jun 2021 19:02:10 +0000 (20:02 +0100)]
v3dv: enable ASTC formats
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11336>
Charlie [Fri, 11 Jun 2021 19:00:51 +0000 (20:00 +0100)]
v3dv: add ASTC formats to get_compatible_tlb_format
CTS doesn't seem to hit this, but they're all 128bit formats so this
should be right
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11336>
Charlie [Fri, 11 Jun 2021 18:58:28 +0000 (19:58 +0100)]
v3dv: divide by block size in copy_image_blit
This handles compressed formats with non-4x4 blocks, like ASTC.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11336>
Charlie [Fri, 11 Jun 2021 18:54:50 +0000 (19:54 +0100)]
v3dv: add the unswizzled RGBA4444 format
If we're supporting the R/B swapped one we might as well support the one that
isn't.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11336>
Gert Wollny [Sun, 13 Jun 2021 18:20:08 +0000 (20:20 +0200)]
r600/sfn: Clean up some ALU lowering and move code
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11348>
Gert Wollny [Sun, 13 Jun 2021 12:36:13 +0000 (14:36 +0200)]
r600/sfn: Don't read return values of atomic ops that are not used
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11348>
Gert Wollny [Sun, 13 Jun 2021 12:35:02 +0000 (14:35 +0200)]
r600/sfn: Drop method for emit_atomic_add, it is handled in generic code
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11348>
Gert Wollny [Sun, 13 Jun 2021 12:15:31 +0000 (14:15 +0200)]
r600/sfn: don't read back unused image atomic result values
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11348>
Gert Wollny [Sun, 13 Jun 2021 12:10:19 +0000 (14:10 +0200)]
r600/sfn: don't designates initializers, since they are c++20
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11348>
Kai-Heng Feng [Fri, 4 Jun 2021 04:13:04 +0000 (12:13 +0800)]
iris: Avoid abort() if kernel can't allocate memory
When the system doesn't have enough memory, GNOME Shell may be crashed
by iris:
gnome-shell[1161]: iris: Failed to submit batchbuffer: Cannot allocate memory
gnome-shell[1161]: GNOME Shell crashed with signal 6
So don't abort() when kernel can't allocate memory to avoid crashing the
entire desktop.
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11178>
Iago Toral Quiroga [Thu, 17 Jun 2021 07:18:23 +0000 (09:18 +0200)]
v3dv: expose VK_KHR_shader_non_semantic_info
This is entirely implemented in the SPIR-V frontend.
Relevant CTS tests:
dEQP-VK.spirv_assembly.instruction.compute.non_semantic_info.*
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11440>
Pierre-Eric Pelloux-Prayer [Wed, 9 Jun 2021 11:52:36 +0000 (13:52 +0200)]
disk_cache: use UTIL_QUEUE_INIT_SCALE_THREADS
Instead of spawning 4 threads when the cache is created,
spawn 1 and let u_queue grow the number of threads if
needed.
I wrote this patch because when running piglit's quick_shader
profile I had lots of samples in disk cache threads - mostly
in native_queued_spin_lock_slowpath kernel function.
Since these tests shouldn't really stress the cache, I assumed
it was caused only by thread creations.
After writing the patch and redoing the measurement, I got an
improvement but I still more hits in the same function for
shader_runner:$disk0 thread so something was wrong.
After digging more, I found out that my shader cache index was
corrupted: the on-disk size was 29MB but the index reported it
was way more than 1GB. So each disk cache thread was spending
a lot of time trying to evict files. Given that my cache had
a really low count of files, the LRU method based on randomly
generating subfolder names failed, so evicting was very slow.
Now that my cache index is fixed, the disk cache threads are
mostly idle but I still think it makes sense to grow the
number of threads instead of spawning 4 at the program start.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11296>
Pierre-Eric Pelloux-Prayer [Wed, 9 Jun 2021 11:49:23 +0000 (13:49 +0200)]
util/u_queue: add UTIL_QUEUE_INIT_SCALE_THREADS flag
This flag allow to create a single thread initially, but set
max_thread to the request thread count.
If the queue is full and num_threads is lower than max_threads,
we spawn a new thread to help process the queue faster.
This avoid creating N threads at queue creation time.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11296>
Pierre-Eric Pelloux-Prayer [Wed, 9 Jun 2021 11:48:25 +0000 (13:48 +0200)]
util/u_queue: move function definition up
Will be used by the next commit.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11296>
Pierre-Eric Pelloux-Prayer [Wed, 9 Jun 2021 08:32:41 +0000 (10:32 +0200)]
radeonsi: delay sample_pos_buffer creation until first use
And use pipe_buffer_create_with_data instead of doing it
manually.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11296>
Pierre-Eric Pelloux-Prayer [Wed, 9 Jun 2021 08:26:14 +0000 (10:26 +0200)]
vbo: delay vbo_exec_vtx_map call
Instead of doing vbo_exec_vtx_map during initialization,
defer it until the first actual user.
v2: move init to vbo_exec_wrap_upgrade_vertex (Emma Anholt)
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11296>
Vinson Lee [Sun, 13 Jun 2021 23:57:32 +0000 (16:57 -0700)]
nvc0/ir: Initialize CodeEmitterNVC0 member progType in constructor.
Fix defect reported by Coverity Scan.
Uninitialized scalar field (UNINIT_CTOR)
uninit_member: Non-static class member progType is not initialized
in this constructor nor in any functions that it calls.
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11350>
Marek Olšák [Fri, 21 May 2021 21:52:27 +0000 (17:52 -0400)]
mesa: execute glFlush asynchronously if no image has been imported/exported
This improves viewperf performance and it shouldn't break synchronization
with external clients when it's indirectly implied by glFlush.
This should not break the cases described in:
https://gitlab.freedesktop.org/mesa/mesa/-/issues/4903
Acked-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11341>
Marek Olšák [Mon, 14 Jun 2021 20:56:57 +0000 (16:56 -0400)]
mesa: move _mesa_notifySwapBuffers into the x11 swrast driver
It has no other use and no relevance to DRI drivers despite the name.
Acked-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11341>
Marek Olšák [Sat, 12 Jun 2021 16:20:06 +0000 (12:20 -0400)]
mesa: add gallium flush_flags param into ctx->Driver.Flush
Acked-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11341>
Marek Olšák [Sat, 12 Jun 2021 16:28:41 +0000 (12:28 -0400)]
st/mesa: move the st_flush_bitmap_cache call into st_flush
Acked-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11341>
Marek Olšák [Sat, 12 Jun 2021 16:27:21 +0000 (12:27 -0400)]
st/mesa: fix an incorrect comment in st_context_flush
Acked-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11341>
Marek Olšák [Sat, 12 Jun 2021 16:31:28 +0000 (12:31 -0400)]
glthread: change when glFlush flushes asynchronously
This fixes the flushing with external textures.
We don't know if we need to flush synchronously with multiple contexts,
so I removed that.
Acked-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11341>
Kenneth Graunke [Wed, 16 Jun 2021 22:58:28 +0000 (15:58 -0700)]
anv: Fix dynamic primitive topology for tess on Gfx7.x too
Commit
24342e499bc58348b257716f629dccca3c1b0833 changed how primitive
topology is handled on Gfx8+ but missed updating the Gfx7.x code.
As a result, tests which previously used topologies like PATCHLIST_3
instead started using bogus ones like LINESTRIP_ADJ. This caused a
GPU hangs in a bunch of Vulkan conformance tests involving tessellation.
This fixes those hangs.
Fixes:
24342e499bc ("anv: fix dynamic primitive topology for tess")
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11434>
Zhaofeng Li [Sun, 13 Jun 2021 03:37:16 +0000 (20:37 -0700)]
Add default driver selections for RISC-V
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11346>
Mike Blumenkrantz [Wed, 7 Apr 2021 14:55:49 +0000 (10:55 -0400)]
zink: always defer image descriptor barriers
this is simpler and guaranteed to be accurate
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11393>
Mike Blumenkrantz [Wed, 7 Apr 2021 14:49:39 +0000 (10:49 -0400)]
zink: use fake buffer barriers for descriptors
GL requires explicit glMemoryBarrier calls for shader synchronization
and only calls that map/copy buffers get implicit sync, so we don't actually
need barriers for any of these cases, only the state needs to be updated
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11393>
Mike Blumenkrantz [Thu, 6 May 2021 16:55:07 +0000 (12:55 -0400)]
zink: check actual mem props to determine if resource object is coherent
this was correct for what it has been used for until now, but it will no
longer be correct going forward
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11397>
Mike Blumenkrantz [Thu, 6 May 2021 14:59:50 +0000 (10:59 -0400)]
zink: key alloc cache on heap index, not heap flags
this is a bit more sane
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11397>
Mike Blumenkrantz [Thu, 6 May 2021 13:52:08 +0000 (09:52 -0400)]
zink: avoid caching visible vram allocations
the visible vram heap is potentially going to be limited in size, so avoid
caching these allocations since that locks them to a given allocation size
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11397>
Mike Blumenkrantz [Thu, 6 May 2021 13:51:02 +0000 (09:51 -0400)]
zink: change a bunch of sparse buffer resource checks to host-visible checks
(sparse buffer) is a subset of !host-visible, and !host-visible is actually the
more correct check to be using
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11397>
Mike Blumenkrantz [Thu, 6 May 2021 13:48:55 +0000 (09:48 -0400)]
zink: collapse host_visible and non-coherent alignment alloc cases
* buffers can use normal mem prop checking to determine host_visible setting
* sparse buffers are never coherent, so this case can be dropped from the conditional
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11397>
Martin Krastev [Tue, 15 Jun 2021 19:18:31 +0000 (12:18 -0700)]
compiler/glsl: Use mutex lock while freeing up mem_ctx
builtin_builder::~builtin_builder() and builtin_builder::release()
are running into race condition. This leads lightsmark to crash at
the end because both calls ralloc_free which mutates the arguments state
This patch fixes lightsmark2008 crash
Fixes:
e4da8b9c331cc3a ("mesa/compiler: rework tear down of builtin/types")
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Reviewed-by: Neha Bhende <bhenden@vmware.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Tested-by: Neha Bhende <bhenden@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11385>
Mike Blumenkrantz [Thu, 15 Apr 2021 12:59:16 +0000 (08:59 -0400)]
zink: mark some functions inline
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11429>
Connor Abbott [Wed, 16 Jun 2021 13:55:30 +0000 (15:55 +0200)]
ir3/ra: Fix array parallelcopy confusion
With array registers, there are two num's we care about:
1. The base num that the whole array starts at (->array.base)
2. The num that the instruction uses, plus possibly an indirect offset
(->num or ->array.offset)
For parallel copies we always copy the whole array, so (2) is irrelevant
here. For phis and parallel copies inserted for phis, we used
assign_reg() which assigned ->array.base, but we forgot about this when
constructing our own parallel copies for live range splitting, just
setting ->num instead. The parallel copy lowering was also inconsistent
here, using ra_reg_get_num() (which looks at ->array.base for arrays)
for sources but looking at ->num directly for destinations. This makes
everything use ->array.base consistently.
While we're here, make sure to remove IR3_REG_SSA from liveout copies to
make sure printing works correctly.
Fixes: 0ffcb19 ("ir3: Rewrite register allocation")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11422>
Connor Abbott [Wed, 16 Jun 2021 13:50:56 +0000 (15:50 +0200)]
ir3: Improve printing of array parallelcopies/phis
Normally something with IR3_REG_ARRAY doesn't have a register assigned,
but we keep IR3_REG_ARRAY for parallel copies after RA because we need
to know the appropriate size. We want to see the register assigned for
these when printing the RA result before parallel copies are lowered.
The register is in ->array.base in this case, so initialize it to
INVALID_REG and print ->array.base if it's been assigned to something,
similar to ->num in the normal case.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11422>
Marek Olšák [Tue, 25 May 2021 20:27:30 +0000 (16:27 -0400)]
shader_enums: change VERT_BIT back to the 32-bit shift
This reverts
0e2566a8. The warning is fixed differently.
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10993>
Marek Olšák [Tue, 25 May 2021 20:28:47 +0000 (16:28 -0400)]
gallium/pb: change alignment to 32 bits
This partially reverts
4a3f0444. The warning is fixed differently.
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10993>
Marek Olšák [Wed, 16 Jun 2021 17:16:23 +0000 (13:16 -0400)]
radeonsi: remove -Wstrict-overflow=0 since it doesn't seem to be needed
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11384>
Marek Olšák [Mon, 14 Jun 2021 01:13:39 +0000 (21:13 -0400)]
radeonsi: remove the chip_class dimension from the draw_vbo array
We don't use/initialize draw_vbo callbacks for other generations anymore.
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11384>
Marek Olšák [Mon, 14 Jun 2021 01:12:22 +0000 (21:12 -0400)]
radeonsi: compile si_state_draw.cpp for each gfx generation separately
It makes compilating faster.
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11384>
Marek Olšák [Mon, 14 Jun 2021 01:04:42 +0000 (21:04 -0400)]
radeonsi: move a few functions from si_state_draw.cpp into si_gfx_cs.c
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11384>
Yiwei Zhang [Wed, 9 Jun 2021 23:05:50 +0000 (23:05 +0000)]
venus: remove workarounds for multi-planar format interop
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Chia-I Wu <olvaffe@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11282>
Yiwei Zhang [Tue, 15 Jun 2021 05:39:39 +0000 (05:39 +0000)]
anv: fix build errors after commit 8b7ff78
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Roman Stratiienko <r.stratiienko@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11373>
Yiwei Zhang [Tue, 15 Jun 2021 05:34:15 +0000 (05:34 +0000)]
radv: fix build errors after commit
8b7ff784
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Roman Stratiienko <r.stratiienko@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11373>
Mike Blumenkrantz [Wed, 16 Jun 2021 17:54:23 +0000 (13:54 -0400)]
zink: ci updates
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11391>
Mike Blumenkrantz [Fri, 2 Apr 2021 15:59:20 +0000 (11:59 -0400)]
zink: support more RGBX formats
the base formats are supported, so these should fall into place naturally
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11391>