r600: fix typo that could lead to a possible crash

For instance, with "piglit/bin/arb_shader_image_load_store-host-mem-barrier --quick -auto -fbo":
==18549==ERROR: AddressSanitizer: heap-buffer-overflow on address 0x61200000a059 at pc 0x7f65d8937b80 bp 0x7fff6ed19a00 sp 0x7fff6ed199f8
READ of size 1 at 0x61200000a059 thread T0
    #0 0x7f65d8937b7f in evergreen_set_shader_images ../src/gallium/drivers/r600/evergreen_state.c:4277
    #1 0x7f65d6b471b8 in st_bind_images ../src/mesa/state_tracker/st_atom_image.c:172
    #2 0x7f65d6b76b26 in st_validate_state ../src/mesa/state_tracker/st_util.h:129
    #3 0x7f65d6b76b26 in prepare_draw ../src/mesa/state_tracker/st_draw.c:88
    #4 0x7f65d6b77c8a in st_draw_gallium ../src/mesa/state_tracker/st_draw.c:141
    #5 0x7f65d72698a2 in _mesa_draw_arrays ../src/mesa/main/draw.c:1202

Fixes: a6b379284365 ("r600: add core pieces of image support.")
Signed-off-by: Patrick Lerda <patrick9876@free.fr>
Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22273>

vc4/ci: add arm64 failure to flakes as it works on armhf

Signed-off-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22297>

gallium/pipe: change PIPE_DEFAULT_DECODER_FEEDBACK_TIMEOUT_NS to 1 second

Fixes: 5e1bd07a ("radeonsi: vcn: implement the get_decoder_fence vfunc")
The commit [5e1bd07a] puts a timeout on fence_wait which causes a 8k AV1
decoding regression on gfx940. By adding DECODER_FEEDBACK_TIMEOUT to
add fence wait time.

Signed-off-by: Sonny Jiang <sonny.jiang@amd.com>
Reviewed-by: Boyuan Zhang <Boyuan.Zhang@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22268>

docs: Claim less functionality for glsl_compiler.

It doesn't generate GPU code, just GLSL IR code.  Also, clarify where to
find the built tool, and what the options do.

Closes: #8674
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22271>

ci: Add missing dependency on doxygen sources for docs-generation jobs.

!22191 broke docs generation and marge didn't notice because of missing
 deps.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22271>

docs: Update Vulkan renderpass docs for !22191

Fixes: 6ad5f885afef ("vulkan: Drop VkRenderingSelfDependencyInfoMESA")
Closes: #8773
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22271>

i915: hook new get_fd proc for drm winsys

Fixes: 853b4801f27 ("i915: Add support for `get_screen_fd`")
Signed-off-by: Ryan Neph <ryanneph@google.com>
Reviewed-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22294>

virgl: hook new get_fd proc for drm winsys

Fixes: 2ade6917dacb ("virgl: Add support for `get_screen_fd`")
Signed-off-by: Ryan Neph <ryanneph@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22292>

radv: update PS num_vgprs in case of epilogs rather than overallocating VGPRs

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22267>

aco: don't use shared VGPRs for shaders consisting of multiple binaries

When using multiple binaries, we don't know the required number of VGPRs beforehand,
which means we either have to over-allocate VGPRs or avoid shared VGPRs.
As bpermute is the only instructions needing shared VGPRs, we decide for the latter.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22267>

aco/ra: adjust_max_used_regs() for fixed Operands

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22267>

aco: split ps_epilog args before exporting them

This avoids some unnecessary copies from extracting from the input vectors.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22267>

anv: Drop dead code that sets the L3BypassDisable field

These helper functions will only get invoked for GFX < 11 and the
L3BypassDisable field is present starting from GFX12+.

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22275>

anv: Drop unused param from add_surface_reloc

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22275>

ci/zink: Disable godot-tps-gles3 on a630.

This trace used too much memory to be run in parallel with our other
traces.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22279>

Uprev Piglit to 2391a83d1639a7ab7bbea02853b922878687b0e5

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22279>

radv: enable shaders cache for libraries with GPL

This was the last missing feature for GPL. The main problem is that
the on-disk shaders cache size will increase a lot because we don't
deduplicate shaders but there is on-going work to improve that.

We also can't use the shaders cache for libraries created with the
RETAIN_LINK_TIME_OPTIMIZATION flag and module identifiers because we
don't know the SPIR-V and thus can't retain NIR shaders for linking.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22264>

radv: ensure to retain NIR shaders for GPL libs found in the cache

Even if we are able to get the assembly from the shaders cache for
graphics pipeline libraries, we still need to retain NIR shaders in
case the LTO pipelines won't be find in the cache.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22264>

radv: add VkGraphicsPipelineLibraryFlag to the graphics pipeline key

This is to generate a different key for a library created with
FRAGMENT_SHADER_BIT and no FS (ie. it would generate a noop FS) and
a library created with FRAGMENT_OUTPUT_INTERFACE with no CB attachments.

Otherwise, the same key would be generated and this would corrupt
the cache.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22264>

radv: remove dead code in radv_pipeline_get_nir()

We either import the NIR or the assembly, so this was never reached.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22264>

radv: allow to create/insert PS epilogs from/to the cache for libs

To cache PS epilogs compiled inside graphics pipeline libraries.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22264>

radv: rely on non-NULL binaries when inserting shaders to the cache

With GPL, a stage can be imported from a library which means that the
binary is NULL (it's freed right after compilation) but the shader is
non-NULL. To avoid crashing, rely on non-NULL binaries because this
implies that the shader is non-NULL as well.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22264>

radv: only copy non-NULL shaders when loaded from the cache

With GPL, we don't necessarily load all stages from the same cache
entry and other stages might have been imported from libraries, so
don't overwrite them.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22264>

nir, spirv: Add support for VK_EXT_fragment_density_map

This involves two new system values.

Reviewed-by: Faith Ekstrand <faith@gfxstrand.net>
Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20303>

ci/zink: Drop validation exception for leaks at device destroy.

Between the recent glthread and zink fixes, we should be good to go.

Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22237>

radeonsi: update test results

This test was fixed by bf910c94e06 ("glsl: fix gl_CullDistance lowering
from float[8] to vec4[2]").

Acked-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22237>

util/vbuf: fix index_bo leak

When indices are unrolled we still have to release the index_bo
references passed to us.

Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8272
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22237>

util/vbuf: clarify indirect draws handling

It wasn't obvious from the u_vbuf code alone that num_draws
is guaranteed to be 1 in the indirect case.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22237>

mesa: fix invalid index_bo refcounting

If take_index_buffer_ownership is true, then we should reserve
enough references of index_bo or we'll get an underflow later.

Fixes: 819627041e7 ("mesa: set pipe_draw_info::index::resource directly and remove gl_bo")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8747
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22237>

zink: be explicit about separate shader dsl indexing during creation

this fixes a minor issue where a fs without a vs dsl would have the wrong
index

Fixes: e3b746e3a31 ("zink: use GPL to handle (simple) separate shader objects")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22269>

anv: check for MESA_SHADER_TESS_CTRL with get_tcs_prog_data

Fixes: 86d931724db ("anv: Implement Wa_14015297576")
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22282>

anv: take primitive ID override to account Wa_14015297576

Commit ca4ec49b0e0 took primitive ID override fields in to use, this
has to be checked as part of Wa_14015297576.

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22282>

zink: always store nir serialized

this saves a ton of memory and has minimal, if any cpu impact

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22266>

zink: store num_inlinable_uniforms separately for cs programs

compute is a special case because the zink_shader itself is created
in a thread, which means it cannot be accessed directly at bind time
since it may not have finished creating itself yet

to avoid prematurely waiting on an async fence, the one value needed
at bind time can instead be stored separately

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22266>

zink: move nir cloning out to callers of zink_shader_compile

this will make more sense with future changes

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22266>

zink: break out nir blob deserializing

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22266>

zink: simplify assign_io() further

no functional changes

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22266>

zink: store nir as serialized on zink_shader structs

nir_shader objects are hefty, and they really add up when there's a lot
of them. there's also not much use in keeping them around, as any time
they'll be used, they're always cloned first, and deserializing isn't
likely to be any slower than a clone

cuts driver memory usage by ~40% for tomb raider

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22266>

zink: streamline nir cloning for assign_io

more relics from the time of pipe_shader_type

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22266>

zink: directly return nir from zink_shader_tcs_create

not currently used but will be

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22266>

zink: swap nir pointers when compiling compute shaders

these are the same pointer, just use a different one

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22266>

zink: pass nir directly to zink_shader_tcs_create()

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22266>

zink: simplify fbfetch output detection from fs

this should be identical to the previous code, except it also
handles depth/stencil (not yet supported)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22266>

zink: use zink_shader::info instead of zink_shader::nir::info

no functional changes

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22266>

zink: generate flat_flags during shader creation

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22266>

zink: pass nir_shader to update_so_info()

no functional changes

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22266>

zink: add and populate a shader_info struct to zink_shader

this avoids the need to use the nir pointer to access shader info

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22266>

zink: delete shader reordering in assign_io()

this is a relic of when pipe_shader_type was different than gl_shader_stage

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22266>

v3dv/pipeline: use pipeline depth bias enabled to fill up CFG packet

Even if the VkPipelineRasterizationStateCreateInfo sets
depthBiasEnable, internally we comput if it is really makes sense, and
use that to decide for example if we emit the Depth Offset packet.

But we were not using this to enable Depth Bias through the depth
offset enable field on the CFG packet.

So in some tests we were enabling depth bias, but not emitting the
packet to configure it, that seemed somewhat inconsistent.

This didn't cause any issue so far, but let's be conservative.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22252>

intel/perf: fix OA format selection on MTL

Anything Gfx12.5+ has a different format.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 90c86fe63e ("intel: add MTL performance metrics")
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22257>

intel/dev: set a default valid kmd_type

src/intel/perf/intel_perf_query_layout.c needs a valid kmd type to
look at the metrics

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 757e2dd692 ("intel/perf: Disable it for Xe KMD")
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22257>

intel/fs: Rework the loop of opt_combine_constants that collects constants

This is a bit more wordy, but it will greatly simplify some future
changes.

v2: Rebase on ADD3 changes.

Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Tested-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22274>

intel/fs: Refactor part of opt_combine_constants to a separate function

Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Tested-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22274>

intel/fs: Output opt_combine_constants debug to stderr

It's a lot more useful to have it in the same stream with the
INTEL_DEBUG=fs output.

Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Tested-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22274>

vulkan/wsi/display: do not dereference a NULL pointer

Fixes dEQP-VK.wsi.direct_drm.swapchain.simulate_oom.*

Cc: mesa-stable
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19025>

vulkan: Drop VkRenderingSelfDependencyInfoMESA

It's no longer needed as VK_EXT_attachment_feedback_loop_layout provides
everything we need.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22191>

vulkan: Drop vk_render_pass_state::*self_dependenc*

ANV was the only driver using them and now it's on feedback loop flags.
Other drivers should convert instead of depending on the old version.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22191>

hasvk/pipeline: Use feedback loop flags for self-dependencies

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22191>

anv/pipeline: Use feedback loop flags for self-dependencies

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22191>

vulkan: Plumb rendering flags through vk_graphics_pipeline_state

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22191>

vk/render_pass: Support VK_EXT_fragment_density_map

Support emulating "classic" FDM with dynamic rendering.

Reviewed-by: Faith Ekstrand <faith@gfxstrand.net>
Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22191>

tu: Use vk_pipeline_get_renderpass_flags()

With this we can remove usage of VkSelfDependencyInfoMESA.

Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22191>

vulkan: Record pipeline flags in the render pass

This records any rendering pipeline flags in the render pass.  This
provides much-needed information for the VK_KHR_fragment_shading_rate
and VK_EXT_fragment_density_map extensions as well as provides an
alternative to VkRenderingSelfDependencyInfoMESA which is based on
VK_EXT_attachment_feedback_loop_layout.

v2 (Connor): Name something more general
v3 (Faith): Also add the FSR flag

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22191>

radv/ci: add one more flake

This one is randomly failing.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22258>

zink/ci: remove primitive-id-no-gs-quads from the NAVI10 fail list

It has been fixed too.

Fixes: 5fb8ba0eb8b ("zink/ci: remove `primitive-id-no-gs-quads` from radv-vangogh-fails")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22258>

radv/gfx11: improve RT scratch allocation

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Friedrich Vock <friedrich.vock@gmx.de>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22232>

radv: Use linear_dispatch info in GFX11 task/mesh draw packet.

This helps the CP (command processor) optimize mesh shader
dispatch when Y = Z = 1.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22222>

nir: Gather compile time constant task->mesh dispatch size.

Some GPUs such as AMD RDNA3 can use this information
to optimize mesh shader dispatches.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22222>

aco: Better phi lowering for merge block when else-side is const.

Add a new special case for binary merge blocks to boolean
phi lowerig. This special case benefits shaders that
have divergent branches with an empty else block,
for example all NGG culling shaders.

Fossil DB stats on Rembrandt (NGG culling enabled):

Totals from 61778 (45.79% of 134913) affected shaders:
SpillVGPRs: 2268 -> 2284 (+0.71%); split: -1.10%, +1.81%
CodeSize: 164317952 -> 162962772 (-0.82%); split: -0.83%, +0.00%
Instrs: 31249824 -> 30910686 (-1.09%); split: -1.09%, +0.00%
Latency: 154948555 -> 154781097 (-0.11%); split: -0.12%, +0.02%
InvThroughput: 30397664 -> 30370872 (-0.09%); split: -0.13%, +0.04%
VClause: 529239 -> 529229 (-0.00%); split: -0.00%, +0.00%
SClause: 783417 -> 783430 (+0.00%)
Copies: 2627570 -> 2595161 (-1.23%); split: -1.25%, +0.02%
Branches: 976506 -> 976508 (+0.00%); split: -0.00%, +0.00%

Fossil DB stats on GFX11 (NGG culling disabled):

Totals from 895 (0.66% of 134913) affected shaders:
SpillVGPRs: 2258 -> 2322 (+2.83%); split: -0.44%, +3.28%
CodeSize: 6229152 -> 6215880 (-0.21%); split: -0.37%, +0.16%
Scratch: 216576 -> 215808 (-0.35%); split: -0.47%, +0.12%
Instrs: 1202077 -> 1198396 (-0.31%); split: -0.43%, +0.13%
Latency: 15921336 -> 16000561 (+0.50%); split: -0.74%, +1.24%
InvThroughput: 7425765 -> 7474891 (+0.66%); split: -0.67%, +1.33%
VClause: 22976 -> 23008 (+0.14%); split: -0.03%, +0.17%
SClause: 38269 -> 38271 (+0.01%)
Copies: 123244 -> 123896 (+0.53%); split: -0.30%, +0.83%
Branches: 47570 -> 47574 (+0.01%); split: -0.00%, +0.01%

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21493>

aco: Call dominator_tree before lower_phis.

This just makes it possible to use the dominator
tree information during phi lowering.

No Fossil DB changes on GFX11.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21493>

aco: Pop branch operands when targets are same in SSA elimination.

The branch instruction is no longer conditional when the targets are the
same, so the operand is not necessary and can be removed.

Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21493>

aco: Don't verify branch exec read when eliminating exec writes.

Verifying that the branch instruction reads exec is not actually
necessary because the pattern that we look for already implies that.

This prepares for the next commit which will remove the exec operand
from branches that have the same target. These branches will no
longer read exec, but they should still get the same optimization.

Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21493>

aco: Simplify get_phi_operand using Operand::c32_or_c64.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21493>

aco: Don't remove exec writes that also write other registers.

Don't eliminate an instruction that writes registers other than exec and scc.
It is possible that this is eg. an s_and_saveexec and the saved value is
used by a later branch.

Fixes: bc130497472cb4ec4ec60695ed99b169d6681118
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21493>

aco: Consider p_cbranch_nz as divergent branch too.

A p_cbranch_nz instruction that reads exec is divergent too.

Fixes: f030b75b7d2c359b90c18ee4ed83fa05265c12e0
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21493>

ci: disable lima farm, currently out-of-space, needs to be fixed

Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22265>

radv: Pre-compute descriptor set layout hash.

While analyzing cache loading performance, hashing the pipeline layout was
surprisingly consuming around 4% of time, sometimes close to the cost of
hashing shader modules.

Turns out we were hashing the pipeline layout on every pipeline creation.
Considering that pipeline layouts are usually deduplicated by the
application, this was amplifying the hashing cost by a big margin.

With Graphics Pipeline Library, we do need to rebuild the pipeline layout
by combining those from each library, but we can memoize the hash of the
descriptor set layout. The cost of re-hashing hashes is negligible since
each descriptor set layout can amount to 1–2KB in size.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22254>

anv: Bump VkDeviceMemory objects limit to 4GB

Android CTS 13_r4 tests dEQP-VK.memory.allocation.random* fail
with VK_ERROR_OUT_OF_DEVICE_MEMORY on ADL boards with 32GB memory
as memory allocation requests from DEQP are much larger(~2.9GB+)
based on device heap size/8.

Increase the limit to unsigned 32bit max(~4GB) which helps to
fix the dEQP-VK.memory.allocation.random* tests.

v1: Bound allocation by the largest memory heap size (Lionel Landwerlin)

v2: Clean up comments to reflect the code change (Ivan Briano)
    Update the value of MAX_MEMORY_ALLOCATION_SIZE (Lionel Landwerlin)

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22066>

isl: update max buffer size for SKL+

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22066>

anv: take care of maxStorageBufferRange being uint32_t

Not fixing anything, but required for another fix.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22066>

ac/llvm: remove ac_build_opencoded_load_format

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22045>

ac/llvm,radeonsi: remove abi->load_inputs implementation

No nir_load_input in VS now.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22045>

radeonsi: monolithic VS emit prolog in nir directly

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22045>

ac/llvm: move ac_fixup_ls_hs_input_vgprs to amd common

To be shared with radeonsi.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22045>

ac/llvm: vs_rel_patch_id can also be fixed up

It's currently used when LS store output to LDS.
The LS/HS bug fix seems does not affect this case.
But we'd better treat it as other fixed args.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22045>

radeonsi: add si_nir_lower_vs_inputs

Ported from llvm:
* si_load_vs_input
* ac_build_opencoded_load_format
* ac_ufN_to_float
* get_vertex_index
* ac_build_fast_udiv_nuw

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22045>

ac/nir: add ac_nir_load_arg_at_offset

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22045>

radeonsi: expose si_nir_load_internal_binding

PS polygon stippling is going to use it too.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22045>

hasvk: include "vk_android.h" header in anv_android.c

Fixes the following building errors:

../src/intel/vulkan_hasvk/anv_android.c:387:34: error: implicit declaration of function 'vk_alloc_ahardware_buffer' is invalid in C99 [-Werror,-
Wimplicit-function-declaration]
   struct AHardwareBuffer *ahw = vk_alloc_ahardware_buffer(pAllocateInfo);
                                 ^
../src/intel/vulkan_hasvk/anv_android.c:387:28: error: incompatible integer to pointer conversion initializing 'struct AHardwareBuffer *' with an expression of type 'int' [-Werror,-Wint-conversion]
   struct AHardwareBuffer *ahw = vk_alloc_ahardware_buffer(pAllocateInfo);
                           ^     ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2 errors generated.

Fixes: b16cfe23 ("vulkan,anv,hasvk,radv: Unify Android hardware buffer creation")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22251>

ac/nir: When task->mesh dispatch Y or Z are 0, also set X to 0.

AMD recommends doing this to speed up the CP when it processes
the draw ring entries. LLPC also does this.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22211>

ac/nir: Store only lowest 8 bits for task draw ring DWORD3.

When writing the draw ready bit, don't write the high 24 bits
of DWORD3, because that is used by the HW for something else
according to LLPC.

Cc: mesa-stable
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22211>

aco: fix nir_var_shader_out barriers for task shaders

These will be used in a future commit.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22211>

freedreno: Support the disable_throttling=true driconf option

At this point, mostly just to make it easier to disable throttling for
performance debugging.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22224>

freedreno: Move driconf settings into sub-struct

Organize all one of them in a single place before adding more.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22224>

freedreno: Avoid looping shader stages if nothing dirty

We have corresponding global dirty bits for each of the per-stage dirty
bits.  We can use this to skip iterating over shader stages when there
is no per-stage dirty state to handle.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22224>

freedreno: Re-work dirty-resource tracking

If a resource is dirty but already tracked by the current batch, no need
to process it at draw time.

Note that the batch could change (ie. new fb state bound, etc) after the
check if we need resource dirty tracking, but in these cases all the
dirty-resource state is marked dirty.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22224>

freedreno: Inline single-use helpers

bind_sampler_states() / set_sampler_views() have just a single caller.
So inline them.  Needed for next commit.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22224>

freedreno: Extract out a helper

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22224>

freedreno: Hoist dirty vars

Prep to re-work how we track dirty-resource.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22224>

freedreno: Stop being too clever by half

This wasn't taking into account a change in corresponding bit in
writeable_bitmask, causing problem if an SSBO was first bound for
read, and then rebound for write, we wouldn't update the buffers
valid range.  Instead just drop the premature optimization.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22224>