Jiawei [Thu, 20 Oct 2022 09:32:32 +0000 (17:32 +0800)]
RISC-V: Minimal support of z*inx extension.
Minimal support of z*inx extension, include 'zfinx', 'zdinx' and 'zhinx/zhinxmin'
corresponding to 'f', 'd' and 'zfh/zfhmin', the 'zdinx' will imply 'zfinx'
same as 'd' imply 'f', 'zhinx' will aslo imply 'zfinx', all zfinx extension imply 'zicsr'.
Co-Authored-By: Sinan Lin <sinan@isrc.iscas.ac.cn>
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc: New extensions.
* config/riscv/arch-canonicalize: New imply relations.
* config/riscv/riscv-opts.h (MASK_ZFINX): New mask.
(MASK_ZDINX): Ditto.
(MASK_ZHINX): Ditto.
(MASK_ZHINXMIN): Ditto.
(TARGET_ZFINX): New target.
(TARGET_ZDINX): Ditto.
(TARGET_ZHINX): Ditto.
(TARGET_ZHINXMIN): Ditto.
* config/riscv/riscv.opt: New target variable.
GCC Administrator [Thu, 27 Oct 2022 00:18:35 +0000 (00:18 +0000)]
Daily bump.
David Malcolm [Wed, 26 Oct 2022 20:45:17 +0000 (16:45 -0400)]
analyzer: fixes to file-descriptor handling
gcc/analyzer/ChangeLog:
* sm-fd.cc (fd_state_machine::on_open): Transition to "unchecked"
when the mode is symbolic, rather than just on integer constants.
(fd_state_machine::check_for_open_fd): Don't complain about
unchecked values in the start state.
gcc/testsuite/ChangeLog:
* gcc.dg/analyzer/fd-3.c (test_5): Expect "opened here" message
even when flags are symbolic.
(test_read_from_symbolic_fd): New.
(test_write_to_symbolic_fd): New.
Signed-off-by: David Malcolm <dmalcolm@redhat.com>
David Malcolm [Wed, 26 Oct 2022 20:44:23 +0000 (16:44 -0400)]
analyzer: add sm-fd.dot
Add a .dot file to document the file descriptor state machine.
gcc/analyzer/ChangeLog:
* sm-fd.dot: New file.
Signed-off-by: David Malcolm <dmalcolm@redhat.com>
Harald Anlauf [Wed, 26 Oct 2022 19:00:44 +0000 (21:00 +0200)]
Fortran: BOZ literal constants are not compatible to any type [PR103413]
gcc/fortran/ChangeLog:
PR fortran/103413
* symbol.cc (gfc_type_compatible): A boz-literal-constant has no type
and thus is not considered compatible to any type.
gcc/testsuite/ChangeLog:
PR fortran/103413
* gfortran.dg/illegal_boz_arg_4.f90: New test.
David Faust [Mon, 24 Oct 2022 20:59:39 +0000 (13:59 -0700)]
bpf: add preserve_field_info builtin
Add BPF __builtin_preserve_field_info. This builtin is used to extract
information to facilitate struct and union relocations performed by the
BPF loader, especially for bitfields.
The builtin has the following signature:
unsigned int __builtin_preserve_field_info (EXPR, unsigned int KIND);
Where EXPR is an expression accessing a field of a struct or union.
Depending on KIND, different information is returned to the program. The
supported values for KIND are as follows:
enum {
FIELD_BYTE_OFFSET = 0,
FIELD_BYTE_SIZE,
FIELD_EXISTENCE,
FIELD_SIGNEDNESS,
FIELD_LSHIFT_U64,
FIELD_RSHIFT_U64
};
If -mco-re is in effect (explicitly or implicitly specified), a CO-RE
relocation is added for the access in EXPR recording the relevant
information according to KIND.
gcc/
* config/bpf/bpf.cc: Support __builtin_preserve_field_info.
(enum bpf_builtins): Add new builtin.
(bpf_init_builtins): Likewise.
(bpf_core_field_info): New function.
(bpf_expand_builtin): Accomodate new builtin. Refactor adding new
relocation to...
(maybe_make_core_relo): ... here. New function.
(bpf_resolve_overloaded_builtin): Accomodate new builtin.
(bpf_core_newdecl): Likewise.
(bpf_core_walk): Likewise.
(bpf_core_is_maybe_aggregate_access): Improve logic.
(struct core_walk_data): New.
* config/bpf/coreout.cc (bpf_core_reloc_add): Allow adding different
relocation kinds.
* config/bpf/coreout.h: Analogous change.
* doc/extend.texi: Document BPF __builtin_preserve_field_info.
gcc/testsuite/
* gcc.target/bpf/core-builtin-fieldinfo-errors-1.c: New test.
* gcc.target/bpf/core-builtin-fieldinfo-errors-2.c: New test.
* gcc.target/bpf/core-builtin-fieldinfo-existence-1.c: New test.
* gcc.target/bpf/core-builtin-fieldinfo-lshift-1-be.c: New test.
* gcc.target/bpf/core-builtin-fieldinfo-lshift-1-le.c: New test.
* gcc.target/bpf/core-builtin-fieldinfo-lshift-2.c: New test.
* gcc.target/bpf/core-builtin-fieldinfo-offset-1.c: New test.
* gcc.target/bpf/core-builtin-fieldinfo-rshift-1.c: New test.
* gcc.target/bpf/core-builtin-fieldinfo-rshift-2.c: New test.
* gcc.target/bpf/core-builtin-fieldinfo-sign-1.c: New test.
* gcc.target/bpf/core-builtin-fieldinfo-sign-2.c: New test.
* gcc.target/bpf/core-builtin-fieldinfo-size-1.c: New test.
Marek Polacek [Fri, 14 Oct 2022 14:05:57 +0000 (10:05 -0400)]
c++: Implement -Wdangling-reference [PR106393]
This patch implements a new experimental warning (enabled by -Wall) to
detect references bound to temporaries whose lifetime has ended. The
primary motivation is the Note in
<https://en.cppreference.com/w/cpp/algorithm/max>:
Capturing the result of std::max by reference produces a dangling reference
if one of the parameters is a temporary and that parameter is returned:
int n = 1;
const int& r = std::max(n-1, n+1); // r is dangling
That's because both temporaries for n-1 and n+1 are destroyed at the end
of the full expression. With this warning enabled, you'll get:
g.C:3:12: warning: possibly dangling reference to a temporary [-Wdangling-reference]
3 | const int& r = std::max(n-1, n+1);
| ^
g.C:3:24: note: the temporary was destroyed at the end of the full expression 'std::max<int>((n - 1), (n + 1))'
3 | const int& r = std::max(n-1, n+1);
| ~~~~~~~~^~~~~~~~~~
The warning works by checking if a reference is initialized with a function
that returns a reference, and at least one parameter of the function is
a reference that is bound to a temporary. It assumes that such a function
actually returns one of its arguments! (I added code to check_return_expr
to suppress the warning when we've seen the definition of the function
and we can say that it can return a variable with static storage
duration.)
It warns when the function in question is a member function, but only if
the function is invoked on a temporary object, otherwise the warning
would emit loads of warnings for valid code like obj.emplace<T>({0}, 0).
It does detect the dangling reference in:
struct S {
const S& self () { return *this; }
};
const S& s = S().self();
It warns in member initializer lists as well:
const int& f(const int& i) { return i; }
struct S {
const int &r;
S() : r(f(10)) { }
};
I've run the testsuite/bootstrap with the warning enabled by default.
There were just a few FAILs, all of which look like genuine bugs.
A bootstrap with the warning enabled by default passed as well.
When testing a previous version of the patch, there were many FAILs in
libstdc++'s 22_locale/; all of them because the warning triggered on
const test_type& obj = std::use_facet<test_type>(std::locale());
but this code looks valid -- std::use_facet doesn't return a reference
to its parameter. Therefore I added a #pragma and code to suppress the
warning.
PR c++/106393
gcc/c-family/ChangeLog:
* c.opt (Wdangling-reference): New.
gcc/cp/ChangeLog:
* call.cc (expr_represents_temporary_p): New, factored out of...
(conv_binds_ref_to_temporary): ...here. Don't return false just
because a ck_base is missing. Use expr_represents_temporary_p.
(do_warn_dangling_reference): New.
(maybe_warn_dangling_reference): New.
(extend_ref_init_temps): Call maybe_warn_dangling_reference.
* cp-tree.h: Adjust comment.
* typeck.cc (check_return_expr): Suppress -Wdangling-reference
warnings.
gcc/ChangeLog:
* doc/invoke.texi: Document -Wdangling-reference.
libstdc++-v3/ChangeLog:
* include/bits/locale_classes.tcc: Add #pragma to disable
-Wdangling-reference with std::use_facet.
gcc/testsuite/ChangeLog:
* g++.dg/cpp23/elision4.C: Use -Wdangling-reference, add dg-warning.
* g++.dg/cpp23/elision7.C: Likewise.
* g++.dg/warn/Wdangling-pointer-2.C: Use -Wno-dangling-reference.
* g++.dg/warn/Wdangling-reference1.C: New test.
* g++.dg/warn/Wdangling-reference2.C: New test.
* g++.dg/warn/Wdangling-reference3.C: New test.
Takayuki 'January June' Suwa [Wed, 26 Oct 2022 06:27:51 +0000 (15:27 +0900)]
xtensa: Fix out-of-bounds array access in the movdi pattern
The following new warnings were introduced in the commit
4f3f0296acbb ("xtensa: Prepare the transition from Reload to LRA"):
gcc/config/xtensa/xtensa.md:945:26: error: array subscript 3 is above
array bounds of 'rtx_def* [2]' [-Werror=array-bounds]
945 | emit_move_insn (operands[2], operands[3]);
gcc/config/xtensa/xtensa.md:945:26: error: array subscript 2 is above
array bounds of 'rtx_def* [2]' [-Werror=array-bounds]
945 | emit_move_insn (operands[2], operands[3]);
From gcc/insn-emit.cc (generated by building):
> /* ../../gcc/config/xtensa/xtensa.md:932 */
> rtx
> gen_movdi (rtx operand0,
> rtx operand1)
> {
> rtx_insn *_val = 0;
> start_sequence ();
> {
> rtx operands[2]; // only 2 elements
> operands[0] = operand0;
> operands[1] = operand1;
> #define FAIL return (end_sequence (), _val)
> #define DONE return (_val = get_insns (), end_sequence (), _val)
> #line 936 "../../gcc/config/xtensa/xtensa.md"
> {
> if (CONSTANT_P (operands[1]))
> {
> /* Split in halves if 64-bit Const-to-Reg moves
> because of offering further optimization opportunities. */
> if (register_operand (operands[0], DImode))
> {
> xtensa_split_DI_reg_imm (operands); // out-of-bounds!
> emit_move_insn (operands[0], operands[1]);
> emit_move_insn (operands[2], operands[3]); // out-of-bounds!
> DONE;
> }
gcc/ChangeLog:
* config/xtensa/xtensa.md (movdi):
Copy operands[0...1] to ops[0...3] and then use the latter before
calling xtensa_split_DI_reg_imm() and emitting insns.
Alexander Monakov [Wed, 26 Oct 2022 13:37:34 +0000 (16:37 +0300)]
ipa-visibility: remove assert in TLS optimization [PR107353]
When upgrading TLS access model based on optimized symbol visibility
status, we attempted to assert that recomputing the model would not
weaken it. It turns out that C, C++, and Fortran front-ends all can
(unintentionally) assign a stronger model than what can be derived
from the declaration.
Let's act conservatively instead of asserting, at least as long as
such pre-existing issues remain.
gcc/ChangeLog:
PR other/107353
* ipa-visibility.cc (function_and_variable_visibility):
Conditionally upgrade TLS model instead of asserting.
Andrew MacLeod [Tue, 25 Oct 2022 19:16:47 +0000 (15:16 -0400)]
Check if varying may also be non-negative.
When using strict enums, we can sometimes turn varying into a better
range.
* gimple-range-fold.cc (fold_using_range::fold_stmt): Check if
stmt is non-negative and adjust the range.
Martin Liska [Tue, 25 Oct 2022 04:28:44 +0000 (06:28 +0200)]
i386: add reset_cpu_feature
gcc/ChangeLog:
* common/config/i386/cpuinfo.h (has_cpu_feature): Add comment.
(reset_cpu_feature): New.
(get_zhaoxin_cpu): Use reset_cpu_feature.
Ju-Zhe Zhong [Tue, 25 Oct 2022 13:53:23 +0000 (21:53 +0800)]
RISC-V: Fix epilogue generation for barrier.
I noticed that I have made a mistake in previous patch:
https://patchwork.sourceware.org/project/gcc/patch/
20220817071950.271762-1-juzhe.zhong@rivai.ai/
The previous statement before this patch:
bool need_barrier_p = (get_frame_size () + cfun->machine->frame.arg_pointer_offset) != 0;
However, I changed it in the previous patch:
bool need_barrier_p = known_ne (get_frame_size (), cfun->machine->frame.arg_pointer_offset);
This is incorrect.
Now, I correct this statement in this patch.
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_expand_epilogue): Fix statement.
Ju-Zhe Zhong [Tue, 25 Oct 2022 03:22:38 +0000 (11:22 +0800)]
RISC-V: ADJUST_NUNITS according to -march.
This patch fixed PR107357: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=107357
gcc/ChangeLog:
PR target/107357
* config/riscv/riscv-modes.def (VECTOR_BOOL_MODE): Set to minimum size.
(ADJUST_NUNITS): Adjust according to -march.
(ADJUST_BYTESIZE): Ditto.
* config/riscv/riscv-protos.h (riscv_v_ext_enabled_vector_mode_p):
Remove.
(riscv_v_ext_vector_mode_p): Change function implementation.
* config/riscv/riscv-vector-builtins.cc (rvv_switcher::rvv_switcher):
Change to riscv_v_ext_vector_mode_p.
(register_builtin_type): Ditto.
* config/riscv/riscv.cc (riscv_v_ext_vector_mode_p): Change to enabled
modes.
(ENTRY): Ditto.
(riscv_v_ext_enabled_vector_mode_p): Remove.
(riscv_v_adjust_nunits): New function.
(riscv_vector_mode_supported_p): Use riscv_v_ext_vector_mode_p instead.
* config/riscv/riscv.h (riscv_v_adjust_nunits): New function.
Ju-Zhe Zhong [Mon, 24 Oct 2022 02:08:53 +0000 (10:08 +0800)]
RISC-V: Support load/store in mov<mode> pattern for RVV modes.
gcc/ChangeLog:
* config.gcc (riscv*): Add riscv-v.o to extra_objs.
* config/riscv/constraints.md (vu): New constraint.
(vi): Ditto.
(Wc0): Ditto.
(Wc1): Ditto.
* config/riscv/predicates.md (vector_length_operand): New.
(reg_or_mem_operand): Ditto.
(vector_move_operand): Ditto.
(vector_mask_operand): Ditto.
(vector_merge_operand): Ditto.
* config/riscv/riscv-protos.h (riscv_regmode_natural_size) New.
(riscv_vector::const_vec_all_same_in_range_p): Ditto.
(riscv_vector::legitimize_move): Ditto.
(tail_policy): Ditto.
(mask_policy): Ditto.
* config/riscv/riscv-v.cc: New.
* config/riscv/riscv-vector-builtins-bases.cc
(vsetvl::expand): Refactor how LMUL encoding.
* config/riscv/riscv.cc (riscv_print_operand): Update how LMUL
print and mask operand print.
(riscv_regmode_natural_size): New.
* config/riscv/riscv.h (REGMODE_NATURAL_SIZE): New.
* config/riscv/riscv.md (mode): Add vector modes.
* config/riscv/t-riscv (riscv-v.o) New.
* config/riscv/vector-iterators.md: New.
* config/riscv/vector.md (vundefined<mode>): New.
(mov<mode>): New.
(*mov<mode>): New.
(@vsetvl<mode>_no_side_effects): New.
(@pred_mov<mode>): New.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/mov-1.c: New.
* gcc.target/riscv/rvv/base/mov-10.c: New.
* gcc.target/riscv/rvv/base/mov-11.c: New.
* gcc.target/riscv/rvv/base/mov-12.c: New.
* gcc.target/riscv/rvv/base/mov-13.c: New.
* gcc.target/riscv/rvv/base/mov-2.c: New.
* gcc.target/riscv/rvv/base/mov-3.c: New.
* gcc.target/riscv/rvv/base/mov-4.c: New.
* gcc.target/riscv/rvv/base/mov-5.c: New.
* gcc.target/riscv/rvv/base/mov-6.c: New.
* gcc.target/riscv/rvv/base/mov-7.c: New.
* gcc.target/riscv/rvv/base/mov-8.c: New.
* gcc.target/riscv/rvv/base/mov-9.c: New.
Monk Chiang [Tue, 25 Oct 2022 06:17:33 +0000 (14:17 +0800)]
RISC-V: Recognized Svinval and Svnapot extensions
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc (riscv_ext_version_table):
Add svinval and svnapot extension.
(riscv_ext_flag_table): Ditto.
* config/riscv/riscv-opts.h (MASK_SVINVAL): New.
(MASK_SVNAPOT): Ditto.
(TARGET_SVINVAL): Ditto.
(TARGET_SVNAPOT): Ditto.
* config/riscv/riscv.opt (riscv_sv_subext): New.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/predef-24.c:New.
* gcc.target/riscv/predef-25.c:New.
Ju-Zhe Zhong [Mon, 24 Oct 2022 14:24:14 +0000 (22:24 +0800)]
RISC-V: Adjust table indentation in commnet for riscv-modes.def
gcc/ChangeLog:
* config/riscv/riscv-modes.def: Adjust table indentation in commnet.
Martin Liska [Wed, 26 Oct 2022 06:39:49 +0000 (08:39 +0200)]
gcc/configure: regenerate
gcc/ChangeLog:
* configure: Regenerate.
Aldy Hernandez [Tue, 25 Oct 2022 20:22:56 +0000 (22:22 +0200)]
Convert flag_finite_math_only uses in frange to HONOR_*.
As mentioned earlier, we should be using HONOR_* on types rather than
flag_finite_math_only.
gcc/ChangeLog:
* value-range.cc (frange::set): Use HONOR_*.
(frange::verify_range): Same.
* value-range.h (frange_val_min): Same.
(frange_val_max): Same.
Jiufu Guo [Tue, 19 Jul 2022 10:30:58 +0000 (18:30 +0800)]
rs6000: cannot_force_const_mem for HIGH code rtx[PR106460]
As the issue in PR106460, a rtx 'high:DI (symbol_ref:DI ("var_48")' is tried
to store into constant pool and ICE occur. But actually, this rtx represents
partial incomplete address and can not be put into a .rodata section.
This patch updates rs6000_cannot_force_const_mem to return true for rtx(s) with
HIGH code, because these rtx(s) indicate part of address and are not ok for
constant pool.
Below are some examples:
(high:DI (const:DI (plus:DI (symbol_ref:DI ("xx") (const_int 12 [0xc])))))
(high:DI (symbol_ref:DI ("var_1")..)))
PR target/106460
gcc/ChangeLog:
* config/rs6000/rs6000.cc (rs6000_cannot_force_const_mem): Return true
for HIGH code rtx.
gcc/testsuite/ChangeLog:
* gcc.target/powerpc/pr106460.c: New test.
Kito Cheng [Fri, 14 Oct 2022 09:34:02 +0000 (17:34 +0800)]
RISC-V: Add h extension support
`h` was the prefix of multi-letter extension name, but it become a
extension in later RISC-V isa spec.
Fortunately we don't have any extension really defined is prefixed
with `h`, so we can just change that.
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc (riscv_ext_version_table):
Add `h`.
(riscv_supported_std_ext): Ditto.
(multi_letter_subset_rank): Remove `h`.
(riscv_subset_list::parse_std_ext): Handle `h` as single letter
extension.
(riscv_subset_list::parse): Ditto.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/arch-18.c: New.
* gcc.target/riscv/arch-5.c: Remove test for prefixed
with `h`.
* gcc.target/riscv/predef-23.c: New.
Eugene Rozenfeld [Wed, 26 Oct 2022 00:17:05 +0000 (17:17 -0700)]
Don't force DWARF4 for AutoFDO tests
Support for DWARF5 was added to create_gcov in
https://github.com/google/autofdo so we no longer need
to force DWARF4 for AutoFDO tests.
Tested on x86_64-pc-linux-gnu.
gcc/testsuite/ChangeLog:
* lib/profopt.exp: Don't force DWARF4 for AutoFDO tests
GCC Administrator [Wed, 26 Oct 2022 00:17:15 +0000 (00:17 +0000)]
Daily bump.
Eugene Rozenfeld [Mon, 25 Apr 2022 18:45:43 +0000 (11:45 -0700)]
Start using discriminators in AutoFDO.
Tested on x86_64-pc-linux-gnu.
gcc/ChangeLog:
* auto-profile.cc (get_combined_location): Include discriminator in the
returned combined location.
(read_function_instance): Read discriminators from profiles.
Nathan Sidwell [Tue, 25 Oct 2022 13:39:00 +0000 (09:39 -0400)]
c++: Adjust synthetic template parm creation
We intend to mark synthetic template parameters (coming from use of auto
parms), as DECL_VIRTUAL_P. The API of process_template_parm is
awkwardly confusing, and we were marking the previous template parm
(unless this was the first parm). process_template_parm returns the list
of parms, when most (all?) users really want the newly-added final node.
That's a bigger change, so let's not do it right now. With this, we
correctly mark such synthetic parms DECL_VIRTUAL_P.
gcc/cp/
* parser.cc (synthesize_implicit_template_parm): Fix thinko about
mark the new parm DECL_VIRTUAL_P. Avoid unneccessary tree_last call.
Patrick Palka [Tue, 25 Oct 2022 18:14:29 +0000 (14:14 -0400)]
c++: remove use_default_args parm of coerce_template_parms
The parameter use_default_args of coerce_template_parms, introduced way
back in r110693, is effectively unused ever since r7-5536-g3c75aaa3d884ef
removed the last 'coerce_template_parms (..., true, false)' call. So
this patch aims to simplify this function's API by getting rid of this
parameter.
In passing, I noticed we currently define wrapper overloads of
coerce_template_parms that act as defacto default arguments for complain
and require_all_args. It seems cleaner however to just specify real
default arguments for the main overload instead. And I suppose we
should also give c_innermost_t_p the same defaults.
But I'm not sure about defaulting complain to tf_none, which is
inconsistent with how we default it in other places to either tf_error
or tf_warning_or_error (as a convenience for non-SFINAE callers). And
since in general it's probably better to not default complain as that's
a source of SFINAE bugs, and only a handful of callers use this defacto
complain=tf_none default, this patch gets rid of this complain default
(but keeps the require_all_args default).
gcc/cp/ChangeLog:
* constraint.cc (resolve_function_concept_overload): Explicitly
pass complain=tf_none to coerce_template_parms.
(resolve_concept_check): Likewise.
(normalize_concept_check): Likewise.
* cp-tree.h (coerce_template_parms): Declare the main overload
and default its last parameter to true. Remove wrapper overloads.
* pt.cc (determine_specialization): Adjust calls to
coerce_template_parms and coerce_innermost_template_parms after
removing their last parameter.
(coerce_template_args_for_ttp): Likewise.
(coerce_ttp_args_for_tta): Likewise.
(coerce_template_template_parms): Likewise.
(coerce_template_parms): Remove use_default_args parameter and
adjust function comment. Document default argument. Remove
wrapper overloads. No longer static.
(coerce_innermost_template_parms): Remove use_default_args
parameter. Default require_all_args to true.
(lookup_template_class): As with determine_specialization.
(finish_template_variable): Likewise.
(tsubst_decl): Likewise.
(instantiate_alias_template): Likewise.
(fn_type_unification): Likewise.
(resolve_overloaded_unification): Likewise.
(resolve_nondeduced_context): Likewise.
(get_partial_spec_bindings): Likewise.
Jason Merrill [Tue, 25 Oct 2022 17:54:12 +0000 (13:54 -0400)]
c++: correct fold_operand change
Still want the conversion to bool.
gcc/cp/ChangeLog:
* constexpr.cc (find_failing_clause_r): Re-add the call to
contextual_conv_bool.
Patrick Palka [Tue, 25 Oct 2022 17:41:18 +0000 (13:41 -0400)]
c++ modules: enum TYPE_MIN/MAX_VALUE streaming [PR106848]
In the frontend, the TYPE_MIN/MAX_VALUE of ENUMERAL_TYPE is the same as
that of the enum's underlying type (see start_enum). And the underlying
type of an enum is always known, even for an opaque enum that lacks a
definition.
But currently, we stream TYPE_MIN/MAX_VALUE of an enum only as part of
its definition. So if the enum is declared but never defined, the
ENUMERAL_TYPE we stream in will have empty TYPE_MIN/MAX_VALUE fields
despite these fields being non-empty on stream out.
And even if the enum is defined, read_enum_def updates these fields only
on the main variant of the enum type, so for other variants (that we may
have streamed in earlier) these fields remain empty. That these fields
are unexpectedly empty for some ENUMERAL_TYPEs is ultimately the cause
of the below two PRs.
This patch fixes this by making us stream TYPE_MIN/MAX_VALUE directly
for each ENUMERAL_TYPE rather than as part of the enum's definition, so
that we naturally also stream these fields for opaque enums (and each
enum type variant).
PR c++/106848
PR c++/102600
gcc/cp/ChangeLog:
* module.cc (trees_out::core_vals): Stream TYPE_MAX_VALUE and
TYPE_MIN_VALUE of ENUMERAL_TYPE.
(trees_in::core_vals): Likewise.
(trees_out::write_enum_def): Don't stream them here.
(trees_in::read_enum_def): Likewise.
gcc/testsuite/ChangeLog:
* g++.dg/modules/enum-9_a.H: New test.
* g++.dg/modules/enum-9_b.C: New test.
* g++.dg/modules/enum-10_a.H: New test.
* g++.dg/modules/enum-10_b.C: New test.
* g++.dg/modules/enum-11_a.H: New test.
* g++.dg/modules/enum-11_b.C: New test.
H.J. Lu [Wed, 19 Oct 2022 19:53:35 +0000 (12:53 -0700)]
Always use TYPE_MODE instead of DECL_MODE for vector field
e034c5c8957 re PR target/78643 (ICE in convert_move, at expr.c:230)
fixed the case where DECL_MODE of a vector field is BLKmode and its
TYPE_MODE is a vector mode because of target attribute. Remove the
BLKmode check for the case where DECL_MODE of a vector field is a vector
mode and its TYPE_MODE isn't a vector mode because of target attribute.
gcc/
PR target/107304
* expr.cc (get_inner_reference): Always use TYPE_MODE for vector
field with vector raw mode.
gcc/testsuite/
PR target/107304
* gcc.target/i386/pr107304.c: New test.
Jason Merrill [Tue, 25 Oct 2022 00:36:32 +0000 (20:36 -0400)]
c++: constexpr-evaluate more assumes
The initial [[assume]] support avoided evaluating assumes with
TREE_SIDE_EFFECTS set, such as calls, because we don't want any side-effects
that change the constexpr state. This patch allows us to evaluate
expressions with that flag set by tracking which variables the evaluation is
allowed to modify, and giving up if it tries to touch any others.
I considered allowing changes to other variables and then rolling them back,
but that seems like a rare enough situation that it doesn't seem worth
working to handle nicely at this point.
gcc/cp/ChangeLog:
* constexpr.cc (class constexpr_global_ctx): Add modifiable field,
get_value, get_value_ptr, put_value, remove_value, flush_modifiable
member functions.
(class modifiable_tracker): New.
(cxx_eval_internal_function): Use it.
(diagnose_failing_condition): Strip CLEANUP_POINT_EXPR.
gcc/testsuite/ChangeLog:
* g++.dg/cpp23/attr-assume9.C: New test.
* g++.dg/cpp23/attr-assume10.C: New test.
Jason Merrill [Mon, 24 Oct 2022 21:17:24 +0000 (17:17 -0400)]
c++: improve failed constexpr assume diagnostic
I noticed that we were printing "the comparison reduces to (x == 42)" when
we should be able to give the value of x. Fixed by doing the same
evaluation in diagnose_failing_condition that we already do in
find_failing_clause.
gcc/cp/ChangeLog:
* constexpr.cc (fold_operand): New function.
(find_failing_clause_r): Add const.
(find_failing_clause): Add const.
(diagnose_failing_condition): Add ctx parameter.
(cxx_eval_internal_function): Pass it.
* semantics.cc (diagnose_failing_condition): Move to constexpr.cc.
* cp-tree.h: Adjust.
gcc/testsuite/ChangeLog:
* g++.dg/cpp23/attr-assume2.C: Expect constant values.
Segher Boessenkool [Mon, 24 Oct 2022 18:17:24 +0000 (18:17 +0000)]
rs6000: Add CCANY; replace <un>signed by <mode:CCANY>
This is in preparation for adding CCFP, and maybe CCEQ, and whatever
other CC mode we may want later. CCANY is used for CC mode consumers
that actually can take any of the four CR field bits.
2022-10-25 Segher Boessenkool <segher@kernel.crashing.org>
* config/rs6000/rs6000.md (CCEITHER): Delete.
(CCANY): New.
(un): Delete.
(isel_<un>signed_<GPR:mode>): Rename to...
(isel_<CCANY:mode>_<GPR:mode>): ... this. Adjust.
(*isel_reversed_<un>signed_<GPR:mode>): Rename to...
(*isel_reversed_<CCANY:mode>_<GPR:mode>): ... this. Adjust.
(setbc_<un>signed_<GPR:mode>): Rename to...
(setbc_<CCANY:mode>_<GPR:mode>C): ... this. Adjust."
(*setbcr_<un>signed_<GPR:mode>): Rename to ...
(*setbcr_<CCANY:mode>_<GPR:mode>): ... this. Adjust.
(*setnbc_<un>signed_<GPR:mode>): Rename to ...
(*setnbc_<CCANY:mode>_<GPR:mode>): ... this. Adjust.
(*setnbcr_<un>signed_<GPR:mode>): Rename to ...
(*setnbcr_<CCANY:mode>_<GPR:mode>): ... this. Adjust.
(eq<mode>3 for GPR): Adjust.
(ne<mode>3 for GPR): Adjust.
* config/rs6000/rs6000-string.cc (do_isel): Adjust.
* config/rs6000/rs6000.cc (rs6000_emit_int_cmove): Adjust.
Richard Biener [Mon, 24 Oct 2022 06:52:12 +0000 (08:52 +0200)]
tree-optimization/107176 - SCEV analysis association issue
The following fixes a wrong-code issue caused by SCEV analysis
associating an addition due trying to use tail-recursion in
follow_ssa_edge_expr. That causes us to apply a conversion at
the wrong point and thus miscompute the scalar evolution of
an induction variable. This reverts the PR66375 fix and
revisits the PR42512 fix by keeping the evolution symbolic
up to the point we process the first linear function when
we then can check for the supported cases and substitute the
whole symbolic expression with the built chrec substituting
the proper initial value.
To simplify passing around things and to clarify scoping of
the involved functions this change wraps the SCEV DFS walking
code into a class.
PR tree-optimization/107176
PR tree-optimization/66375
PR tree-optimization/42512
* tree-scalar-evolution.cc (follow_ssa_edge_expr): Revert
the PR66375 fix, do not not associate PLUS_EXPR to be able
to use tail-recursion.
(follow_ssa_edge_binary): Likewise.
(interpret_loop_phi): Revert PR42512 fix, do not throw
away analyze_evolution_in_loop result after the fact.
(follow_ssa_edge_expr): When reaching halting_phi initalize
the evolution to the symbolic value of the PHI result.
(add_to_evolution_1): When adding the first evolution verify
we can handle the expression wrapping the symbolic evolution
and replace that in full using the initial condition.
(class scev_dfs): New, contains ...
(follow_ssa_edge_expr, follow_ssa_edge_binary,
follow_ssa_edge_in_condition_phi_branch,
follow_ssa_edge_in_condition_phi,
follow_ssa_edge_inner_loop_phi,
add_to_evolution, add_to_evolution_1): ... these with
loop and halting_phi arguments in class data.
(scev_dfs::get_ev): New toplevel DFS entry, start with
a chrec_dont_know evolution.
(analyze_evolution_in_loop): Use scev_dfs.
* gcc.dg/torture/pr107176.c: New testcase.
Eric Botcazou [Tue, 25 Oct 2022 10:20:33 +0000 (12:20 +0200)]
Relax assertion in profiler
This assertion in branch_prob:
if (bb == ENTRY_BLOCK_PTR_FOR_FN (cfun)->next_bb)
{
location_t loc = DECL_SOURCE_LOCATION (current_function_decl);
gcc_checking_assert (!RESERVED_LOCATION_P (loc));
had been correct until the fix for PR debug/101598 was installed.
gcc/
* profile.cc (branch_prob): Be prepared for ignored functions with
DECL_SOURCE_LOCATION set to UNKNOWN_LOCATION.
gcc/testsuite:
* gnat.dg/specs/coverage1.ads: New test.
* gnat.dg/specs/variant_part.ads: Minor tweak.
* gnat.dg/specs/weak1.ads: Add dg directive.
Richard Biener [Tue, 25 Oct 2022 08:04:56 +0000 (10:04 +0200)]
Move NOP stripping in SCEV analysis
The following moves a pair of STRIP_USELESS_TYPE_CONVERSIONS to
where it belongs and adds a comment on why we handle GENERIC
there at all.
* tree-scalar-evolution.cc (follow_ssa_edge_expr): Move
STRIP_USELESS_TYPE_CONVERSIONS to where it matters.
Tejas Joshi [Fri, 21 Oct 2022 15:35:39 +0000 (21:05 +0530)]
Remove znver4 instruction reservations
This reverts the changes made to znver.md in:
commit
bf3b532b524ecacb3202ab2c8af419ffaaab7cff
2022-10-21 Tejas Joshi <TejasSanjay.Joshi@amd.com>
gcc/ChangeLog:
* common/config/i386/i386-common.cc (processor_alias_table): Use
CPU_ZNVER3 for znver4.
* config/i386/znver.md: Remove znver4 reservations.
Jakub Jelinek [Tue, 25 Oct 2022 08:45:29 +0000 (10:45 +0200)]
gimplify: Fix comment typos
While looking at gimple_boolify for PR107368, I've noticed 2 comment
typos.
2022-10-25 Jakub Jelinek <jakub@redhat.com>
* gimplify.cc (gimple_boolify): Fix comment typos, prduce -> produce
and There -> These.
Jakub Jelinek [Tue, 25 Oct 2022 08:42:59 +0000 (10:42 +0200)]
gimplify: Call gimple_boolify on IFN_ASSUME argument [PR107368]
The following testcase ICEs in C, because assume attribute condition
has int type rather than bool and the gimplification into GIMPLE_ASSUME
assigns it into a bool variable.
Fixed by calling gimple_boolify.
2022-10-25 Jakub Jelinek <jakub@redhat.com>
PR tree-optimization/107368
* gimplify.cc (gimplify_call_expr): For complex IFN_ASSUME
conditions call gimple_boolify on the condition.
* gcc.dg/attr-assume-5.c: New test.
YunQiang Su [Sat, 8 May 2021 09:45:54 +0000 (05:45 -0400)]
MIPS: add builtime option for -mcompact-branches
For R6+ target, it allows to configure gcc to use compact branches only
if avaiable.
gcc/ChangeLog:
* config.gcc: add -with-compact-branches=policy build option.
* doc/install.texi: Likewise.
* config/mips/mips.h: Likewise.
YunQiang Su [Sat, 8 May 2021 09:45:53 +0000 (05:45 -0400)]
MIPS: Not trigger error for pre-R6 and -mcompact-branches=always
For MIPSr6, we may wish to use compact-branches only.
Currently, we have to use `always' option, while it is mark as conflict
with pre-R6.
cc1: error: unsupported combination: ‘mips32r2’ -mcompact-branches=always
Just ignore -mcompact-branches=always for pre-R6.
This patch also defines
__mips_compact_branches_never
__mips_compact_branches_always
__mips_compact_branches_optimal
predefined macros
gcc/ChangeLog:
* config/mips/mips.cc (mips_option_override): not trigger error
for compact-branches=always for pre-R6.
* config/mips/mips.h (TARGET_RTP_PIC): not trigger error for
compact-branches=always for pre-R6.
(TARGET_CB_NEVER): Likewise.
(TARGET_CB_ALWAYS): Likewise.
(struct mips_cpu_info): define macros for compact branch policy.
* doc/invoke.texi: Document "always" with pre-R6.
gcc/testsuite/ChangeLog:
* gcc.target/mips/compact-branches-1.c: add isa_rev>=6.
* gcc.target/mips/mips.exp: don't add -mipsXXr6 option for
-mcompact-branches=always. It is usable for pre-R6 now.
* gcc.target/mips/compact-branches-8.c: New test.
* gcc.target/mips/compact-branches-9.c: New test.
Jakub Jelinek [Tue, 25 Oct 2022 08:39:20 +0000 (10:39 +0200)]
gimplify: Don't add GIMPLE_ASSUME if errors were seen [PR107369]
The FEs emit errors about jumps into assume attribute conditions,
but when we add GIMPLE_ASSUME for the condition which is reachable
through those jumps, we can run into cfg verification diagnostics.
Fixed by throwing the IFN_ASSUME away during gimplification if
seen_error () - like we already do for -O0. GIMPLE_ASSUME in the middle-end
is a pure optimization thing and if errors were reported, the optimizations
will not be beneficial for anything.
2022-10-25 Jakub Jelinek <jakub@redhat.com>
PR tree-optimization/107369
* gimplify.cc (gimplify_call_expr): If seen_error, handle complex
IFN_ASSUME the same as for -O0.
* gcc.dg/attr-assume-4.c: New test.
* g++.dg/cpp23/attr-assume8.C: New test.
YunQiang Su [Wed, 21 Sep 2022 11:13:03 +0000 (11:13 +0000)]
MIPS: fix building on multiarch platform
On platforms that support multiarch, such as Debian,
the filesystem hierarchy doesn't fellow the old Irix style:
lib & lib/<multiarch> for native
lib64 for N64 on N32/O32 systems
lib32 for N32 on N64/O32 systems
libo32 for O32 on N64/N32 systems
Thus we cannot
#define STANDARD_STARTFILE_PREFIX_1
#define STANDARD_STARTFILE_PREFIX_2
on N32 or N64 systems, else collect2 won't look for libraries
on /lib/<multiarch>.
gcc/ChangeLog:
* configure.ac: AC_DEFINE(ENABLE_MULTIARCH, 1)
* configure: Regenerated.
* config.in: Regenerated.
* config/mips/mips.h: don't define STANDARD_STARTFILE_PREFIX_1
if ENABLE_MULTIARCH is defined.
* config/mips/t-linux64: define correct multiarch path when
multiarch is enabled.
Richard Biener [Mon, 24 Oct 2022 07:51:32 +0000 (09:51 +0200)]
tree-optimization/100756 - niter analysis and folding
niter analysis, specifically the part trying to simplify the computed
maybe_zero condition against the loop header copying condition, is
confused by us now simplifying
_15 = n_8(D) * 4;
if (_15 > 0)
to
_15 = n_8(D) * 4;
if (n_8(D) > 0)
which is perfectly sound at the point we do this transform. One
solution might be to involve ranger in this simplification, another
is to be more aggressive when expanding expressions - the condition
we try to simplify is _15 > 0, so all we need is expanding that
to n_8(D) * 4 > 0.
The following does just that.
PR tree-optimization/100756
* tree-ssa-loop-niter.cc (expand_simple_operations): Also
expand multiplications by invariants.
* gcc.dg/vect/pr100756.c: New testcase.
Kewen Lin [Tue, 25 Oct 2022 05:18:45 +0000 (00:18 -0500)]
rs6000/test: Support vect_long_long effective target
Currently effective target vect_long_long doesn't have
power specific check, I think it's an oversight. This
is to add the support which checks for has_arch_pwr8,
since we set rs6000_vector_unit[V2DImode] as:
(TARGET_P8_VECTOR) ? VECTOR_P8_VECTOR : VECTOR_NONE;
it means its full support starts from ISA 2.07.
Although ISA 2.06 has some instructions like lxvd2x
and stxvd2x etc., it's used for testing, checking for
ISA 2.07 is more sensitive.
gcc/testsuite/ChangeLog:
* lib/target-supports.exp (check_effective_target_vect_long_long): Add
support for powerpc*-*-*.
Kewen Lin [Tue, 25 Oct 2022 05:18:08 +0000 (00:18 -0500)]
vect: Fix wrong shift_n after widening on BE [PR107338]
As PR107338 shows, with the use of widening loads, the
container_type can become a wider type, it causes us to
get wrong shift_n since the BIT_FIELD_REF offset actually
becomes bigger on BE. Taking the case in PR107338 as
example, at the beginning the container type is short and
BIT_FIELD_REF offset is 8 and size is 4, with unpacking to
wider type int, the high 16 bits are zero, by viewing it
as type int, its offset actually becomes to 24. So the
shift_n should be 4 (32 - 24 - 4) instead of 20 (32 - 8
- 4).
I noticed that if we move shift_n calculation early
before the adjustments for widening loads (container type
change), it's based on all the stuffs of the original
container, the shfit_n calculated there is exactly what
we want, it can be independent of widening. Besides, I
add prec adjustment together with the current adjustments
for widening loads, although prec's subsequent uses don't
require this change for now, since the container type gets
changed, we should keep the corresponding prec consistent.
PR tree-optimization/107338
gcc/ChangeLog:
* tree-vect-patterns.cc (vect_recog_bitfield_ref_pattern): Move
shfit_n calculation before the adjustments for widening loads.
Martin Liska [Tue, 25 Oct 2022 04:58:17 +0000 (06:58 +0200)]
riscv: fix cross compiler
Move riscv_get_valid_option_values out of
Fixes:
riscv/riscv-common.cc:1748:40: error: ‘riscv_get_valid_option_values’ was not declared in this scope
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc
(riscv_get_valid_option_values): Get out of ifdef.
Martin Liska [Tue, 25 Oct 2022 04:16:03 +0000 (06:16 +0200)]
i386: fix pedantic warning
PR target/107364
gcc/ChangeLog:
* common/config/i386/i386-cpuinfo.h (enum processor_vendor):
Fix pedantic warning.
GCC Administrator [Tue, 25 Oct 2022 00:17:33 +0000 (00:17 +0000)]
Daily bump.
David Malcolm [Mon, 24 Oct 2022 20:41:09 +0000 (16:41 -0400)]
analyzer: fix ICE on va_copy [PR107349]
gcc/analyzer/ChangeLog:
PR analyzer/107349
* varargs.cc (get_va_copy_arg): Fix the non-pointer case.
gcc/testsuite/ChangeLog:
PR analyzer/107349
* gcc.dg/analyzer/stdarg-1-ms_abi.c (pr107349): New.
* gcc.dg/analyzer/stdarg-1-sysv_abi.c (pr107349): New.
* gcc.dg/analyzer/stdarg-1.c (pr107349): New.
Signed-off-by: David Malcolm <dmalcolm@redhat.com>
Martin Liska [Mon, 24 Oct 2022 20:40:00 +0000 (16:40 -0400)]
diagnostics: fix ICE in sarif output with NULL filename [PR107366]
gcc/ChangeLog:
PR analyzer/107366
* diagnostic-format-sarif.cc
(sarif_builder::maybe_make_physical_location_object): Gracefully
reject locations with NULL filename.
gcc/testsuite/ChangeLog:
PR analyzer/107366
* gcc.dg/analyzer/sarif-pr107366.c: New test.
Signed-off-by: David Malcolm <dmalcolm@redhat.com>
David Malcolm [Mon, 24 Oct 2022 20:38:23 +0000 (16:38 -0400)]
analyzer: handle (NULL == &VAR) [PR107345]
gcc/analyzer/ChangeLog:
PR analyzer/107345
* region-model.cc (region_model::eval_condition_without_cm):
Ensure that constants are on the right-hand side before checking
for them.
gcc/testsuite/ChangeLog:
PR analyzer/107345
* gcc.dg/analyzer/pr107345.c: New test.
Signed-off-by: David Malcolm <dmalcolm@redhat.com>
David Malcolm [Mon, 24 Oct 2022 20:38:23 +0000 (16:38 -0400)]
analyzer: simplify sm_state_map lookup
gcc/analyzer/ChangeLog:
* engine.cc (impl_region_model_context::get_malloc_map): Replace
with...
(impl_region_model_context::get_state_map_by_name): ...this.
(impl_region_model_context::get_fd_map): Delete.
(impl_region_model_context::get_taint_map): Delete.
* exploded-graph.h (impl_region_model_context::get_fd_map):
Delete.
(impl_region_model_context::get_malloc_map): Delete.
(impl_region_model_context::get_taint_map): Delete.
(impl_region_model_context::get_state_map_by_name): New.
* region-model.h (region_model_context::get_state_map_by_name):
New vfunc.
(region_model_context::get_fd_map): Convert from vfunc to
function.
(region_model_context::get_malloc_map): Likewise.
(region_model_context::get_taint_map): Likewise.
(noop_region_model_context::get_state_map_by_name): New.
(noop_region_model_context::get_fd_map): Delete.
(noop_region_model_context::get_malloc_map): Delete.
(noop_region_model_context::get_taint_map): Delete.
(region_model_context_decorator::get_state_map_by_name): New.
(region_model_context_decorator::get_fd_map): Delete.
(region_model_context_decorator::get_malloc_map): Delete.
(region_model_context_decorator::get_taint_map): Delete.
Signed-off-by: David Malcolm <dmalcolm@redhat.com>
David Malcolm [Mon, 24 Oct 2022 20:38:22 +0000 (16:38 -0400)]
analyzer: handle "pipe" and "pipe2" [PR106300]
gcc/analyzer/ChangeLog:
PR analyzer/106300
* engine.cc (impl_region_model_context::get_fd_map): New.
* exploded-graph.h (impl_region_model_context::get_fd_map): New
decl.
* region-model-impl-calls.cc (region_model::impl_call_pipe): New.
* region-model.cc (region_model::update_for_int_cst_return): New,
based on...
(region_model::update_for_zero_return): ...this. Reimplement in
terms of the former.
(region_model::on_call_pre): Handle "pipe" and "pipe2".
(region_model::on_call_post): Likewise.
* region-model.h (region_model::impl_call_pipe): New decl.
(region_model::update_for_int_cst_return): New decl.
(region_model::mark_as_valid_fd): New decl.
(region_model_context::get_fd_map): New pure virtual fn.
(noop_region_model_context::get_fd_map): New.
(region_model_context_decorator::get_fd_map): New.
* sm-fd.cc: Include "analyzer/program-state.h".
(fd_state_machine::describe_state_change): Handle transitions from
start state to valid states.
(fd_state_machine::mark_as_valid_fd): New.
(fd_state_machine::on_stmt): Add missing return for "creat".
(region_model::mark_as_valid_fd): New.
gcc/ChangeLog:
PR analyzer/106300
* doc/invoke.texi (Static Analyzer Options): Add "pipe" and
"pipe2" to the list of functions the analyzer has hardcoded
knowledge of.
gcc/testsuite/ChangeLog:
PR analyzer/106300
* gcc.dg/analyzer/pipe-1.c: New test.
* gcc.dg/analyzer/pipe-glibc.c: New test.
* gcc.dg/analyzer/pipe-manpages.c: New test.
* gcc.dg/analyzer/pipe2-1.c: New test.
Signed-off-by: David Malcolm <dmalcolm@redhat.com>
Jason Merrill [Thu, 20 Oct 2022 17:51:37 +0000 (13:51 -0400)]
tree: add build_string_literal overloads
Simplify several calls to build_string_literal by not requiring redundant
strlen or IDENTIFIER_* in the caller.
I also corrected a wrong comment on IDENTIFIER_LENGTH.
gcc/ChangeLog:
* tree.h (build_string_literal): New one-argument overloads that
take tree (identifier) and const char *.
* builtins.cc (fold_builtin_FILE)
(fold_builtin_FUNCTION)
* gimplify.cc (gimple_add_init_for_auto_var)
* vtable-verify.cc (verify_bb_vtables): Simplify calls.
gcc/cp/ChangeLog:
* cp-gimplify.cc (fold_builtin_source_location)
* vtable-class-hierarchy.cc (register_all_pairs): Simplify calls to
build_string_literal.
(build_string_from_id): Remove.
Thomas Schwinge [Mon, 24 Oct 2022 19:11:47 +0000 (21:11 +0200)]
libgomp/nvptx: Prepare for reverse-offload callback handling, resolve spurious SIGSEGVs
Per commit r13-3460-g131d18e928a3ea1ab2d3bf61aa92d68a8a254609
"libgomp/nvptx: Prepare for reverse-offload callback handling",
I'm seeing a lot of libgomp execution test regressions. Random
example, 'libgomp.c-c++-common/error-1.c':
[...]
GOMP_OFFLOAD_run: kernel main$_omp_fn$0: launch [(teams: 1), 1, 1] [(lanes: 32), (threads: 8), 1]
Thread 1 "a.out" received signal SIGSEGV, Segmentation fault.
0x00007ffff793b87d in GOMP_OFFLOAD_run (ord=<optimized out>, tgt_fn=<optimized out>, tgt_vars=<optimized out>, args=<optimized out>) at [...]/source-gcc/libgomp/plugin/plugin-nvptx.c:2127
2127 if (__atomic_load_n (&ptx_dev->rev_data->fn, __ATOMIC_ACQUIRE) != 0)
(gdb) print ptx_dev
$1 = (struct ptx_device *) 0x6a55a0
(gdb) print ptx_dev->rev_data
$2 = (struct rev_offload *) 0xffffffff00000000
(gdb) print ptx_dev->rev_data->fn
Cannot access memory at address 0xffffffff00000000
libgomp/
* plugin/plugin-nvptx.c (nvptx_open_device): Initialize
'ptx_dev->rev_data'.
Martin Liska [Mon, 24 Oct 2022 13:34:39 +0000 (15:34 +0200)]
x86: fix VENDOR_MAX enum value
PR target/107364
gcc/ChangeLog:
* common/config/i386/i386-cpuinfo.h (enum processor_vendor):
Reorder enum values as BUILTIN_VENDOR_MAX should not point
in the middle of the valid enum values.
Marek Polacek [Thu, 20 Oct 2022 19:55:28 +0000 (15:55 -0400)]
c++: ICE with invalid structured bindings [PR107276]
This test ICEs in C++23 because we reach the new code in do_auto_deduction:
30468 if (cxx_dialect >= cxx23
30469 && context == adc_return_type
30470 && (!AUTO_IS_DECLTYPE (auto_node)
30471 || !unparenthesized_id_or_class_member_access_p (init))
30472 && (r = treat_lvalue_as_rvalue_p (maybe_undo_parenthesized_ref (init),
30473 /*return*/true)))
where 'init' is "VIEW_CONVERT_EXPR<<<< error >>>>(y)", and then the move
in treat_lvalue_as_rvalue_p returns error_mark_node whereupon
set_implicit_rvalue_p crashes.
I don't think such V_C_Es are useful so let's not create them. But that
won't fix the ICE so I'm checking the return value of move. A structured
bindings decl can have an error type, that is set in cp_finish_decomp:
8908 TREE_TYPE (first) = error_mark_node;
therefore I think treat_lvalue_as_rvalue_p just needs to cope.
PR c++/107276
gcc/cp/ChangeLog:
* typeck.cc (treat_lvalue_as_rvalue_p): Check the return value of move.
gcc/ChangeLog:
* tree.cc (maybe_wrap_with_location): Don't create a location wrapper
when the type is erroneous.
gcc/testsuite/ChangeLog:
* g++.dg/cpp2a/decomp4.C: New test.
Jakub Jelinek [Mon, 24 Oct 2022 15:53:16 +0000 (17:53 +0200)]
c, c++: Fix up excess precision handling of scalar_to_vector conversion [PR107358]
As mentioned earlier in the C++ excess precision support mail, the following
testcase is broken with excess precision both in C and C++ (though just in C++
it was triggered in real-world code).
scalar_to_vector is called in both FEs after the excess precision promotions
(or stripping of EXCESS_PRECISION_EXPR), so we can then get invalid
diagnostics that say float vector + float involves truncation (on ia32
from long double to float).
The following patch fixes that by calling scalar_to_vector on the operands
before the excess precision promotions, let scalar_to_vector just do the
diagnostics (it does e.g. fold_for_warn so it will fold
EXCESS_PRECISION_EXPR around REAL_CST to constants etc.) but will then
do the actual conversions using the excess precision promoted operands
(so say if we have vector double + (float + float) we don't actually do
vector double + (float) ((long double) float + (long double) float)
but
vector double + (double) ((long double) float + (long double) float)
2022-10-24 Jakub Jelinek <jakub@redhat.com>
PR c++/107358
gcc/c/
* c-typeck.cc (build_binary_op): Pass operands before excess precision
promotions to scalar_to_vector call.
gcc/cp/
* typeck.cc (cp_build_binary_op): Pass operands before excess precision
promotions to scalar_to_vector call.
gcc/testsuite/
* c-c++-common/pr107358.c: New test.
* g++.dg/cpp1y/pr68180.C: Remove -fexcess-precision=fast from
dg-options.
Tobias Burnus [Mon, 24 Oct 2022 14:58:43 +0000 (16:58 +0200)]
libgomp/nvptx: Prepare for reverse-offload callback handling
This patch adds a stub 'gomp_target_rev' in the host's target.c, which will
later handle the reverse offload.
For nvptx, it adds support for forwarding the offload gomp_target_ext call
to the host by setting values in a struct on the device and querying it on
the host - invoking gomp_target_rev on the result.
include/ChangeLog:
* cuda/cuda.h (enum CUdevice_attribute): Add
CU_DEVICE_ATTRIBUTE_UNIFIED_ADDRESSING.
(CU_MEMHOSTALLOC_DEVICEMAP): Define.
(cuMemHostAlloc): Add prototype.
libgomp/ChangeLog:
* config/nvptx/icv-device.c (GOMP_DEVICE_NUM_VAR): Remove
'static' for this variable.
* config/nvptx/libgomp-nvptx.h: New file.
* config/nvptx/target.c: Include it.
(GOMP_ADDITIONAL_ICVS): Declare extern var.
(GOMP_REV_OFFLOAD_VAR): Declare var.
(GOMP_target_ext): Handle reverse offload.
* libgomp-plugin.h (GOMP_PLUGIN_target_rev): New prototype.
* libgomp-plugin.c (GOMP_PLUGIN_target_rev): New, call ...
* target.c (gomp_target_rev): ... this new stub function.
* libgomp.h (gomp_target_rev): Declare.
* libgomp.map (GOMP_PLUGIN_1.4): New; add GOMP_PLUGIN_target_rev.
* plugin/cuda-lib.def (cuMemHostAlloc): Add.
* plugin/plugin-nvptx.c: Include libgomp-nvptx.h.
(struct ptx_device): Add rev_data member.
(nvptx_open_device): Remove async_engines query, last used in
r10-304-g1f4c5b9b; add unified-address assert check.
(GOMP_OFFLOAD_get_num_devices): Claim unified address
support.
(GOMP_OFFLOAD_load_image): Free rev_fn_table if no
offload functions exist. Make offload var available
on host and device.
(rev_off_dev_to_host_cpy, rev_off_host_to_dev_cpy): New.
(GOMP_OFFLOAD_run): Handle reverse offload.
Wilco Dijkstra [Mon, 24 Oct 2022 14:14:14 +0000 (15:14 +0100)]
[AArch64] Improve immediate expansion [PR106583]
Improve immediate expansion of immediates which can be created from a
bitmask immediate and 2 MOVKs. Simplify, refactor and improve efficiency
of bitmask checks. Move various immediate handling functions together
to avoid forward declarations.
This reduces the number of 4-instruction immediates in SPECINT/FP by 10-15%.
gcc/
PR target/106583
* config/aarch64/aarch64.cc (aarch64_internal_mov_immediate)
Add support for a bitmask immediate with 2 MOVKs.
(aarch64_check_bitmask): New function after refactorization.
(aarch64_bitmask_imm): Simplify replication of small modes.
Split function into 64-bit only version for efficiency.
(aarch64_move_imm): Move near other immediate functions.
(aarch64_uimm12_shift): Likewise.
(aarch64_clamp_to_uimm12_shift): Likewise.
(aarch64_movk_shift): Likewise.
(aarch64_replicate_bitmask_imm): Likewise.
(aarch64_and_split_imm1): Likewise.
(aarch64_and_split_imm2): Likewise.
(aarch64_and_bitmask_imm): Likewise.
(aarch64_movw_imm): Likewise.
gcc/testsuite/
PR target/106583
* gcc.target/aarch64/pr106583.c: Add new test.
Jakub Jelinek [Mon, 24 Oct 2022 14:25:29 +0000 (16:25 +0200)]
c++: Fix up constexpr handling of char/signed char/short pre/post inc/decrement [PR105774]
signed char, char or short int pre/post inc/decrement are represented by
normal {PRE,POST}_{INC,DEC}REMENT_EXPRs in the FE and only gimplification
ensures that the {PLUS,MINUS}_EXPR is done in unsigned version of those
types:
case PREINCREMENT_EXPR:
case PREDECREMENT_EXPR:
case POSTINCREMENT_EXPR:
case POSTDECREMENT_EXPR:
{
tree type = TREE_TYPE (TREE_OPERAND (*expr_p, 0));
if (INTEGRAL_TYPE_P (type) && c_promoting_integer_type_p (type))
{
if (!TYPE_OVERFLOW_WRAPS (type))
type = unsigned_type_for (type);
return gimplify_self_mod_expr (expr_p, pre_p, post_p, 1, type);
}
break;
}
This means during constant evaluation we need to do it similarly (either
using unsigned_type_for or using widening to integer_type_node).
The following patch does the latter.
2022-10-24 Jakub Jelinek <jakub@redhat.com>
PR c++/105774
* constexpr.cc (cxx_eval_increment_expression): For signed types
that promote to int, evaluate PLUS_EXPR or MINUS_EXPR in int type.
* g++.dg/cpp1y/constexpr-105774.C: New test.
Arsen Arsenović [Fri, 14 Oct 2022 10:04:51 +0000 (12:04 +0200)]
c-family: Implicitly return zero from main even on freestanding
... unless marked noreturn.
This should not get in anyone's way, but should permit the use of main()
in freestanding more easily, especially for writing test cases that
should work both in freestanding and hosted modes.
gcc/c/ChangeLog:
* c-decl.cc (finish_function): Ignore hosted when deciding
whether to implicitly return zero, but check noreturn.
* c-objc-common.cc (c_missing_noreturn_ok_p): Loosen the
requirements to just MAIN_NAME_P when hosted, or `int main'
otherwise.
gcc/cp/ChangeLog:
* cp-tree.h (DECL_MAIN_P): Move most logic, besides the hosted
check, from here...
(DECL_MAIN_ANY_P): ... to here, so that it can be reused ...
(DECL_MAIN_FREESTANDING_P): ... here, with an additional
constraint on (hosted OR return type == int)
* decl.cc (finish_function): Use DECL_MAIN_FREESTANDING_P
instead of DECL_MAIN_P, to loosen the hosted requirement, but
check noreturn, before adding implicit returns.
gcc/testsuite/ChangeLog:
* gcc.dg/noreturn-4.c: Removed.
* g++.dg/freestanding-main.C: New test.
* g++.dg/freestanding-nonint-main.C: New test.
* gcc.dg/freestanding-main.c: New test.
* gcc.dg/freestanding-nonint-main.c: New test.
Aldy Hernandez [Mon, 24 Oct 2022 10:37:25 +0000 (12:37 +0200)]
[PR tree-optimization/107355] Handle NANs in abs range-op entry.
The problem here is that the threader is coming up with a path where
the only valid result is a NAN. When the abs op1_range entry is
trying to add the negative posibility, it attempts to get the bounds
of the working range. NANs don't have bounds so they need to be
special cased.
PR tree-optimization/107355
gcc/ChangeLog:
* range-op-float.cc (foperator_abs::op1_range): Handle NAN.
gcc/testsuite/ChangeLog:
* gcc.dg/tree-ssa/pr107355.c: New test.
Tobias Burnus [Mon, 24 Oct 2022 13:19:00 +0000 (15:19 +0200)]
OpenMP: Fix reverse offload GOMP_TARGET_REV IFN corner cases [PR107236]
For 'target parallel' and similarly nested directives, cgraph_node's
calls_declare_variant_alt was not set in the parent region node but in
cfun->decl. Hence, pass_omp_device_lower did not process handle the
internal function GOMP_TARGET_REV. - Solution is to set it to the
DECL_CONTEXT, which is set in adjust_context_and_scope.
The cgraph_node::create_clone issue is exposed with -O2 for the existing
libgomp.fortran/reverse-offload-1.f90.
PR middle-end/107236
gcc/ChangeLog:
* omp-expand.cc (expand_omp_target): Set calls_declare_variant_alt
in DECL_CONTEXT and not to cfun->decl.
* cgraphclones.cc (cgraph_node::create_clone): Copy also the
node's calls_declare_variant_alt value.
gcc/testsuite/ChangeLog:
* gfortran.dg/gomp/target-device-ancestor-6.f90: New test.
Kito Cheng [Fri, 30 Sep 2022 02:05:23 +0000 (10:05 +0800)]
RISC-V: Support --target-help for -mcpu/-mtune
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc (riscv_tunes): New.
(riscv_get_valid_option_values): New.
(TARGET_GET_VALID_OPTION_VALUES): New.
* config/riscv/riscv-cores.def (RISCV_TUNE): New, define options
for tune here.
(RISCV_CORE): Fix comment.
* config/riscv/riscv.cc (riscv_tune_info_table): Move definition to
riscv-cores.def.
Aldy Hernandez [Sun, 23 Oct 2022 14:51:17 +0000 (16:51 +0200)]
Check HONOR_NANS instead of flag_finite_math_only in frange:verify_range.
[Jakub and other FP experts, would this be OK, or am I missing
something?]
Vax does not seem to have !flag_finite_math_only, but float_type_node
does not HONOR_NANS. The check in frange::verify_range dependend on
flag_finite_math_only, which is technically not correct since
frange::set_varying() checks HONOR_NANS instead of
flag_finite_math_only.
I'm actually getting tired of flag_finite_math_only and
!flag_finite_math_only discrepancies in the selftests (Vax and rx-elf
come to mind). I think we should just test both alternatives in the
selftests as in this patch.
We could also check flag_finite_math_only=0 with a float_type_node
that does not HONOR_NANs, but I have no idea how to twiddle
FLOAT_MODE_FORMAT temporarily, and that may be over thinking it.
PR tree-optimization/107365
gcc/ChangeLog:
* value-range.cc (frange::verify_range): Predicate NAN check in
VARYING range on HONOR_NANS instead of flag_finite_math_only.
(range_tests_floats): Same.
(range_tests_floats_various): New.
(range_tests): Call range_tests_floats_various.
Torbjörn SVENSSON [Fri, 21 Oct 2022 10:29:13 +0000 (12:29 +0200)]
lto: Always quote path to touch
When generating the makefile, make sure that the paths are quoted so
that a native Windows path works within Cygwin.
Without this patch, this error is reported by the DejaGNU test suite:
make: [T:\ccMf0kI3.mk:3: T:\ccGEvdDp.ltrans0.ltrans.o] Error 1 (ignored)
The generated makefile fragment without the patch:
T:\ccGEvdDp.ltrans0.ltrans.o:
@T:\build\bin\arm-none-eabi-g++.exe '-xlto' ... '-o' 'T:\ccGEvdDp.ltrans0.ltrans.o' 'T:\ccGEvdDp.ltrans0.o'
@-touch -r T:\ccGEvdDp.ltrans0.o T:\ccGEvdDp.ltrans0.o.tem > /dev/null 2>&1 && mv T:\ccGEvdDp.ltrans0.o.tem T:\ccGEvdDp.ltrans0.o
.PHONY: all
all: \
T:\ccGEvdDp.ltrans0.ltrans.o
With the patch, the touch line would be replace with:
@-touch -r "T:\ccGEvdDp.ltrans0.o" "T:\ccGEvdDp.ltrans0.o.tem" > /dev/null 2>&1 && mv "T:\ccGEvdDp.ltrans0.o.tem" "T:\ccGEvdDp.ltrans0.o"
gcc/ChangeLog:
* lto-wrapper.cc: Quote paths in makefile.
Co-Authored-By: Yvan ROUX <yvan.roux@foss.st.com>
Signed-off-by: Torbjörn SVENSSON <torbjorn.svensson@foss.st.com>
Ju-Zhe Zhong [Mon, 24 Oct 2022 02:03:12 +0000 (10:03 +0800)]
RISC-V: Support (set (mem) (const_poly_int))
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_legitimize_move): Support (set (mem) (const_poly_int)).
Ju-Zhe Zhong [Mon, 24 Oct 2022 02:20:28 +0000 (10:20 +0800)]
RISC-V: Replace CONSTEXPR with constexpr
Move away from the pre-C++11 compatibility macro CONSTEXPR.
This patch is inspired by aarch64:
https://gcc.gnu.org/pipermail/gcc-patches/2022-October/603974.html.
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-bases.cc: Replace CONSTEXPR
with constexpr throughout.
* config/riscv/riscv-vector-builtins-shapes.cc (SHAPE): Likewise.
* config/riscv/riscv-vector-builtins.cc
(struct registered_function_hasher): Likewise.
* config/riscv/riscv-vector-builtins.h (struct rvv_arg_type_info):
Likewise.
Ju-Zhe Zhong [Mon, 24 Oct 2022 02:05:24 +0000 (10:05 +0800)]
RISC-V: Remove unused TI/TF vector modes.
gcc/ChangeLog:
* config/riscv/riscv-vector-switch.def (ENTRY): Remove unused TI/TF vector modes.
Ju-Zhe Zhong [Mon, 24 Oct 2022 01:39:16 +0000 (09:39 +0800)]
RISC-V: Fix REG_CLASS_CONTENTS.
Include V_REGS for ALL_REGS.
gcc/ChangeLog:
* config/riscv/riscv.h (REG_CLASS_CONTENTS): Fix ALL_REGS.
GCC Administrator [Mon, 24 Oct 2022 00:16:31 +0000 (00:16 +0000)]
Daily bump.
LIU Hao [Sat, 22 Oct 2022 09:31:46 +0000 (17:31 +0800)]
libgcc: Update 'gthr-mcf.h' to include a dedicated header for libobjc
'libobjc/thr.c' includes 'gthr.h'. While all the other gthread headers
have `#ifdef _LIBOBJC` checks, and provide a different set of inline
functions, I think having one header provide two completely unrelated
set of APIs is unsatisfactory, complicates maintenance, and hinders
further development.
This commit references a new header for libobjc, and adds a copyright
notice, as in other headers.
libgcc/ChangeLog:
* config/i386/gthr-mcf.h: Include 'gthr_libobjc.h' when building
libobjc, instead of 'gthr.h'
GCC Administrator [Sun, 23 Oct 2022 00:16:38 +0000 (00:16 +0000)]
Daily bump.
Michael Eager [Sat, 22 Oct 2022 23:23:16 +0000 (16:23 -0700)]
Fix uninitialized variable warnings.
Check for use of previously uninitialized variables; call gcc_unreachable().
Replace abort() with gcc_unreachable().
2022-10-22 Michael Eager <eager@eagercon.com>
gcc/
* config/microblaze/microblaze.cc
(microblaze_legitimize_address): Initialize 'reg' to NULL, check for NULL.
(microblaze_address_insns): Replace abort() with gcc_unreachable().
(print_operand_address): Same.
(microblaze_expand_move): Initialize 'p1' to NULL, check for NULL.
(get_branch_target): Replace abort() with gcc_unreachable().
Aldy Hernandez [Sat, 22 Oct 2022 14:22:50 +0000 (16:22 +0200)]
Update selftest such that [-Inf, +Inf] is always VARYING for -ffinite-math-only.
[-Inf, +Inf] +-NAN gets normalized as VARYING. There is a test that
drops the NAN possibility, and tests that the range is no longer
VARYING but [-Inf, +Inf]. However, for -ffinite-math-only targets
(Vax, RX, etc) the range would still be VARYING because the VARYING
range never had a NAN to begin with. This fixes the test.
I have a precommit hook that does self-tests with
-fno-finite-math-only, -ffinite-math-only, and -ffast-math as a sanity
check, but my precommit hook last week was disabled because there was
a tree-ssa.exp in mainline failing which was throwing off my scripts.
My apologies.
gcc/ChangeLog:
* value-range.cc (range_tests_floats): Predicate [-Inf, +Inf] test
with !flag_finite_math_only.
Takayuki 'January June' Suwa [Fri, 21 Oct 2022 22:46:13 +0000 (07:46 +0900)]
xtensa: Make register A0 allocable for the CALL0 ABI
This patch offers an additional allocable register by RA for the CALL0
ABI.
> Register a0 holds the return address upon entry to a function, but
> unlike the windowed register ABI, it is not reserved for this purpose
> and may hold other values after the return address has been saved.
- Xtensa ISA Reference Manual,
8.1.2 "CALL0 Register Usage and Stack Layout" [p.589]
gcc/ChangeLog:
* config/xtensa/xtensa.cc (xtensa_conditional_register_usage):
Remove register A0 from FIXED_REGS if the CALL0 ABI.
(xtensa_expand_epilogue): Change to emit '(use (reg:SI A0_REG))'
unconditionally after restoring callee-saved registers for
sibling-call functions, in order to prevent misleading that
register A0 is free to use.
GCC Administrator [Sat, 22 Oct 2022 00:17:11 +0000 (00:17 +0000)]
Daily bump.
José Rui Faustino de Sousa [Tue, 18 Oct 2022 20:29:59 +0000 (22:29 +0200)]
Fortran: Add missing TKR initialization to class variables [PR100097, PR100098]
gcc/fortran/ChangeLog:
PR fortran/100097
PR fortran/100098
* trans-array.cc (gfc_trans_class_array): New function to
initialize class descriptor's TKR information.
* trans-array.h (gfc_trans_class_array): Add function prototype.
* trans-decl.cc (gfc_trans_deferred_vars): Add calls to the new
function for both pointers and allocatables.
gcc/testsuite/ChangeLog:
PR fortran/100097
PR fortran/100098
* gfortran.dg/PR100097.f90: New test.
* gfortran.dg/PR100098.f90: New test.
Jakub Jelinek [Fri, 21 Oct 2022 16:34:37 +0000 (18:34 +0200)]
i386: Fix up BFmode comparisons in conditional moves [PR107322]
As the testcase shows, when cbranchbf4/cstorebf4 patterns are defined,
we can get ICEs for conditional moves.
The problem is that the generic conditional move expansion just calls
prepare_cmp_insn which just checks that such a cbranch<mode>4 exists
and returns directly such comparison and passes it down to the conditional
move optabs.
The following patch fixes it by punting if the comparisons aren't
ix86_fp_comparison_operator (to tell the generic code it should separately
compare) and to handle the promotion of BFmode comparison operands to
SFmode such that comparison is performed in SFmode.
2022-10-21 Jakub Jelinek <jakub@redhat.com>
PR target/107322
* config/i386/i386-expand.cc (ix86_prepare_fp_compare_args): For
BFmode comparisons promote arguments to SFmode and recurse.
(ix86_expand_int_movcc, ix86_expand_fp_movcc): Return false early
if comparison operands are BFmode and operands[1] is not
ix86_fp_comparison_operator.
* gcc.target/i386/pr107322.c: New test.
Jakub Jelinek [Fri, 21 Oct 2022 16:04:54 +0000 (18:04 +0200)]
c++: Don't shortcut TREE_CONSTANT vector type CONSTRUCTORs in cxx_eval_constant_expression [PR107295]
The excess precision support broke building skia (dependency of firefox)
on ia32 (it has something like the a constexpr variable), but as the other
cases show, it is actually a preexisting problem if one uses casts from
constants with wider floating point types.
The problem is that cxx_eval_constant_expression tries to short-cut
processing of TREE_CONSTANT CONSTRUCTORs if they satisfy
reduced_constant_expression_p - instead of calling cxx_eval_bare_aggregate
on them it just verifies flags and if they are TREE_CONSTANT even after
that, just fold.
Now, on the testcase we have a TREE_CONSTANT CONSTRUCTOR containing
TREE_CONSTANT NOP_EXPR of REAL_CST. And, fold, which isn't recursive,
doesn't optimize that into VECTOR_CST, while later on we are only able
to optimize VECTOR_CST arithmetics, not arithmetics with vector
CONSTRUCTORs.
The following patch fixes that by rejecting CONSTRUCTORs with vector type
in reduced_constant_expression_p regardless of whether they have
CONSTRUCTOR_NO_CLEARING set or not, folding result in cxx_eval_bare_aggregate
even if nothing has changed but it wasn't non-constant and removing folding
from the TREE_CONSTANT reduced_constant_expression_p short-cut.
2022-10-21 Jakub Jelinek <jakub@redhat.com>
PR c++/107295
* constexpr.cc (reduced_constant_expression_p) <case CONSTRUCTOR>:
Return false for VECTOR_TYPE CONSTRUCTORs even without
CONSTRUCTOR_NO_CLEARING set on them.
(cxx_eval_bare_aggregate): If constant but !changed, fold before
returning VECTOR_TYPE_P CONSTRUCTOR.
(cxx_eval_constant_expression) <case CONSTRUCTOR>: Don't fold
TREE_CONSTANT CONSTRUCTOR, just return it.
* g++.dg/ext/vector42.C: New test.
Tejas Joshi [Tue, 28 Jun 2022 11:03:53 +0000 (16:33 +0530)]
Enable AMD znver4 support and add instruction reservations
2022-09-28 Tejas Joshi <TejasSanjay.Joshi@amd.com>
gcc/ChangeLog:
* common/config/i386/cpuinfo.h (get_amd_cpu): Recognize znver4.
* common/config/i386/i386-common.cc (processor_names): Add znver4.
(processor_alias_table): Add znver4 and modularize old znvers.
* common/config/i386/i386-cpuinfo.h (processor_subtypes):
AMDFAM19H_ZNVER4.
* config.gcc (x86_64-*-* |...): Likewise.
* config/i386/driver-i386.cc (host_detect_local_cpu): Let
-march=native recognize znver4 cpus.
* config/i386/i386-c.cc (ix86_target_macros_internal): Add znver4.
* config/i386/i386-options.cc (m_ZNVER4): New definition.
(m_ZNVER): Include m_ZNVER4.
(processor_cost_table): Add znver4.
* config/i386/i386.cc (ix86_reassociation_width): Likewise.
* config/i386/i386.h (processor_type): Add PROCESSOR_ZNVER4.
(PTA_ZNVER1): New definition.
(PTA_ZNVER2): Likewise.
(PTA_ZNVER3): Likewise.
(PTA_ZNVER4): Likewise.
* config/i386/i386.md (define_attr "cpu"): Add znver4 and rename
md file.
* config/i386/x86-tune-costs.h (znver4_cost): New definition.
* config/i386/x86-tune-sched.cc (ix86_issue_rate): Add znver4.
(ix86_adjust_cost): Likewise.
* config/i386/znver1.md: Rename to znver.md.
* config/i386/znver.md: Add new reservations for znver4.
* doc/extend.texi: Add details about znver4.
* doc/invoke.texi: Likewise.
gcc/testsuite/ChangeLog:
* gcc.target/i386/funcspec-56.inc: Handle new march.
* g++.target/i386/mv29.C: Likewise.
Arsen Arsenović [Wed, 12 Oct 2022 19:47:35 +0000 (21:47 +0200)]
libstdc++: respect with-{headers, newlib} for default hosted value
This saves us a build flag when building for freestanding targets.
libstdc++-v3/ChangeLog:
* acinclude.m4: Default hosted to off if building without
headers and without newlib.
* configure: Regenerate.
Jonathan Wakely [Tue, 18 Oct 2022 19:49:42 +0000 (20:49 +0100)]
libstdc++: Fix std::move_only_function for incomplete parameter types
The std::move_only_function::__param_t alias template attempts to
optimize argument passing for the invoker, by passing by rvalue
reference for types that are non-trivial or large. However, the
precondition for is_trivally_copyable makes it unsuitable for using
here, and can cause ODR violations. Just use is_scalar instead, and pass
all class types (even small, trivial ones) by value.
libstdc++-v3/ChangeLog:
* include/bits/mofunc_impl.h (move_only_function::__param_t):
Use __is_scalar instead of is_trivially_copyable.
* testsuite/20_util/move_only_function/call.cc: Check parameters
involving incomplete types.
Thomas Schwinge [Sat, 15 Oct 2022 22:07:20 +0000 (00:07 +0200)]
Restore 'libgomp.oacc-c-c++-common/nvptx-sese-1.c' SESE regions checking [PR107195, PR107344]
That is, adjust for optimization introduced with recent
commit r13-3217-gc4d15dddf6b9eacb36f535807ad2ee364af46e04
"[PR107195] Set range to zero when nonzero mask is 0", where GCC now
understands that after 'r *= 2;', 'r & 1' will never hold here, and thus
transforms/optimizes/"disturbs" the original code such that GCC/nvptx's later
"Neuter whole SESE regions" optimization no longer is applicable to it:
UNSUPPORTED: libgomp.oacc-c/../libgomp.oacc-c-c++-common/nvptx-sese-1.c -DACC_DEVICE_TYPE_nvidia=1 -DACC_MEM_SHARED=0 -foffload=nvptx-none -O0
PASS: libgomp.oacc-c/../libgomp.oacc-c-c++-common/nvptx-sese-1.c -DACC_DEVICE_TYPE_nvidia=1 -DACC_MEM_SHARED=0 -foffload=nvptx-none -O2 (test for excess errors)
PASS: libgomp.oacc-c/../libgomp.oacc-c-c++-common/nvptx-sese-1.c -DACC_DEVICE_TYPE_nvidia=1 -DACC_MEM_SHARED=0 -foffload=nvptx-none -O2 execution test
[-PASS:-]{+FAIL:+} libgomp.oacc-c/../libgomp.oacc-c-c++-common/nvptx-sese-1.c -DACC_DEVICE_TYPE_nvidia=1 -DACC_MEM_SHARED=0 -foffload=nvptx-none -O2 scan-nvptx-none-offload-rtl-dump mach "SESE regions:.* [0-9]+{[0-9]+->[0-9]+(\\.[0-9]+)+}"
Same for C++.
It's unclear to me if this is an actual "problem", which optimization is "more
important", so I've filed PR107344 "GCC/nvptx SESE region optimization" to
capture this question, and here restore what we intend to be testing (to my
understanding) in 'libgomp.oacc-c-c++-common/nvptx-sese-1.c'.
PR tree-optimization/107195
PR target/107344
libgomp/
* testsuite/libgomp.oacc-c-c++-common/nvptx-sese-1.c: Restore SESE
regions checking.
Thomas Schwinge [Mon, 17 Oct 2022 07:10:03 +0000 (09:10 +0200)]
Add 'gcc.dg/tree-ssa/pr107195-3.c' [PR107195]
... to display optimization performed as of recent
commit r13-3217-gc4d15dddf6b9eacb36f535807ad2ee364af46e04
"[PR107195] Set range to zero when nonzero mask is 0".
PR tree-optimization/107195
gcc/testsuite/
* gcc.dg/tree-ssa/pr107195-3.c: New.
Richard Biener [Fri, 21 Oct 2022 07:45:44 +0000 (09:45 +0200)]
tree-optimization/107323 - loop distribution partition ordering issue
The following reverts part of the PR94125 fix which causes us to
use a bogus partition ordering after applying versioning for
alias to the testcase in PR107323. Instead PR94125 is fixed by
appropriately considering to be merged SCCs when skipping edges
we want to ignore because of the alias versioning.
PR tree-optimization/107323
* tree-loop-distribution.cc (pg_unmark_merged_alias_ddrs):
New function.
(loop_distribution::break_alias_scc_partitions): Revert
postorder save/restore from the PR94125 fix. Instead
make sure to not ignore edges from SCCs we are going to
merge.
* gcc.dg/tree-ssa/pr107323.c: New testcase.
Monk Chiang [Fri, 21 Oct 2022 05:01:59 +0000 (13:01 +0800)]
RISC-V: Add type attribute for atomic instructions.
gcc/ChangeLog:
* config/riscv/riscv.md: Add atomic type attribute.
* config/riscv/sync.md: Add atomic type for atomic instructions.
Jakub Jelinek [Fri, 21 Oct 2022 07:16:44 +0000 (09:16 +0200)]
match.pd: Fix up gcc.dg/pr54346.c on i686-linux [PR54346]
The pr54346.c testcase FAILs on i686-linux (without -msse*) for multiple
reasons. One is the trivial missing -Wno-psabi which the following patch
adds, but that isn't enough. The thing is that without native vector
support, we have VEC_PERM_EXPRs in the IL and are actually considering
the nested VEC_PERM_EXPRs into one VEC_PERM_EXPR optimization, but punt
because can_vec_perm_const_p (result_mode, op_mode, sel2, false) is false.
Such a test makes sense to prevent "optimizing" two VEC_PERM_EXPRs
that can be handled by the backend natively into one VEC_PERM_EXPR
that can't be handled. But if both of the original VEC_PERM_EXPRs
can't be handled natively either, having just one VEC_PERM_EXPR that will be
lowered by generic vec lowering is IMHO still better than 2.
Or even if we trade just one VEC_PERM_EXPR that can't be handled plus
one that can to one that can't be handled.
Also, removing the testcase's executable permissions...
2022-10-21 <jakub@redhat.com>
PR tree-optimization/54346
* match.pd ((vec_perm (vec_perm@0 @1 @2 VECTOR_CST) @0 VECTOR_CST)):
Optimize nested VEC_PERM_EXPRs even if target can't handle the
new one provided we don't increase number of VEC_PERM_EXPRs the
target can't handle.
* gcc.dg/pr54346.c: Add -Wno-psabi to dg-options.
Jakub Jelinek [Fri, 21 Oct 2022 07:00:41 +0000 (09:00 +0200)]
c++: Fix up mangling ICE with void{} [PR106863]
We ICE on the following testcase during mangling, finish_compound_literal
returns for void{} void_node and the mangler doesn't handle it.
Handling void_node in the mangler seems problematic to me, because
we don't know for which case it has been created.
The following patch arranges to mangle it as other compound literals
with no operands, so it demangles as void{}, by returning a void type
COMPOUND_LITERAL_P with no elements if processing_template_decl.
Otherwise it keeps returning void_node.
2022-10-21 Jakub Jelinek <jakub@redhat.com>
PR c++/106863
* semantics.cc (finish_compound_literal): For void{}, if
processing_template_decl return a COMPOUND_LITERAL_P
CONSTRUCTOR rather than void_node.
* g++.dg/cpp0x/dr2351-2.C: New test.
Дилян Палаузов [Thu, 20 Oct 2022 15:05:04 +0000 (17:05 +0200)]
Don't build readline/libreadline.a, when --with-system-readline is supplied
https://sourceware.org/bugzilla/show_bug.cgi?id=18632
The bundled libreadline is always built, even if the system is
./configure'd --with-system-readline and the build libreadline.a is not
used.
Proposed patch:
Fix ./configure.ac not to proceed readline/, when --with-system-
readline is provided
* configure.ac: Don't configure readline if --with-system-readline is
used.
* configure: Re-generate.
Ju-Zhe Zhong [Mon, 17 Oct 2022 08:36:42 +0000 (16:36 +0800)]
RISC-V: Add RVV vsetvl/vsetvlmax intrinsics and tests.
gcc/ChangeLog:
* config.gcc: Add riscv-vector-builtins-bases.o and riscv-vector-builtins-shapes.o
* config/riscv/riscv-vector-builtins.cc (DEF_RVV_I_OPS): New macro.
(DEF_RVV_FUNCTION): Ditto.
(handle_pragma_vector): Add intrinsic framework.
* config/riscv/riscv.cc (riscv_print_operand): Add operand print for vsetvl/vsetvlmax.
* config/riscv/riscv.md: include vector.md.
* config/riscv/t-riscv: Add riscv-vector-builtins-bases.o and riscv-vector-builtins-shapes.o
* config/riscv/riscv-vector-builtins-bases.cc: New file.
* config/riscv/riscv-vector-builtins-bases.h: New file.
* config/riscv/riscv-vector-builtins-functions.def: New file.
* config/riscv/riscv-vector-builtins-shapes.cc: New file.
* config/riscv/riscv-vector-builtins-shapes.h: New file.
* config/riscv/riscv-vector-builtins-types.def: New file.
* config/riscv/vector.md: New file.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/vsetvl-1.c: New test.
Ju-Zhe Zhong [Mon, 17 Oct 2022 08:20:43 +0000 (16:20 +0800)]
RISC-V: Add RVV intrinsic basic framework.
gcc/ChangeLog:
* config.gcc: Add gt files since function_instance is GTY ((user)).
* config/riscv/riscv-builtins.cc (riscv_init_builtins): Add RVV intrinsic framework.
(riscv_builtin_decl): Ditto.
(riscv_expand_builtin): Ditto.
* config/riscv/riscv-protos.h (builtin_decl): New function.
(expand_builtin): Ditto.
(enum riscv_builtin_class): New enum to classify RVV intrinsic and RISC-V general built-in.
* config/riscv/riscv-vector-builtins.cc (class GTY): New declaration.
(struct registered_function_hasher): New struct.
(DEF_RVV_OP_TYPE): New macro.
(DEF_RVV_TYPE): Ditto.
(DEF_RVV_PRED_TYPE): Ditto.
(GTY): New declaration.
(add_attribute): New function.
(check_required_extensions): Ditto.
(rvv_arg_type_info::get_tree_type): Ditto.
(function_instance::function_instance): Ditto.
(function_instance::operator==): Ditto.
(function_instance::any_type_float_p): Ditto.
(function_instance::get_return_type): Ditto.
(function_instance::get_arg_type): Ditto.
(function_instance::hash): Ditto.
(function_instance::call_properties): Ditto.
(function_instance::reads_global_state_p): Ditto.
(function_instance::modifies_global_state_p): Ditto.
(function_instance::could_trap_p): Ditto.
(function_builder::function_builder): Ditto.
(function_builder::~function_builder): Ditto.
(function_builder::allocate_argument_types): Ditto.
(function_builder::register_function_group): Ditto.
(function_builder::append_name): Ditto.
(function_builder::finish_name): Ditto.
(function_builder::get_attributes): Ditto.
(function_builder::add_function): Ditto.
(function_builder::add_unique_function): Ditto.
(function_call_info::function_call_info): Ditto.
(function_expander::function_expander): Ditto.
(function_expander::add_input_operand): Ditto.
(function_expander::generate_insn): Ditto.
(registered_function_hasher::hash): Ditto.
(registered_function_hasher::equal): Ditto.
(builtin_decl): Ditto.
(expand_builtin): Ditto.
(gt_ggc_mx): Define for using GCC garbage collect.
(gt_pch_nx): Define for using GCC garbage collect.
* config/riscv/riscv-vector-builtins.def (DEF_RVV_OP_TYPE): New macro.
(DEF_RVV_PRED_TYPE): Ditto.
(vbool64_t): Add suffix.
(vbool32_t): Ditto.
(vbool16_t): Ditto.
(vbool8_t): Ditto.
(vbool4_t): Ditto.
(vbool2_t): Ditto.
(vbool1_t): Ditto.
(vint8mf8_t): Ditto.
(vuint8mf8_t): Ditto.
(vint8mf4_t): Ditto.
(vuint8mf4_t): Ditto.
(vint8mf2_t): Ditto.
(vuint8mf2_t): Ditto.
(vint8m1_t): Ditto.
(vuint8m1_t): Ditto.
(vint8m2_t): Ditto.
(vuint8m2_t): Ditto.
(vint8m4_t): Ditto.
(vuint8m4_t): Ditto.
(vint8m8_t): Ditto.
(vuint8m8_t): Ditto.
(vint16mf4_t): Ditto.
(vuint16mf4_t): Ditto.
(vint16mf2_t): Ditto.
(vuint16mf2_t): Ditto.
(vint16m1_t): Ditto.
(vuint16m1_t): Ditto.
(vint16m2_t): Ditto.
(vuint16m2_t): Ditto.
(vint16m4_t): Ditto.
(vuint16m4_t): Ditto.
(vint16m8_t): Ditto.
(vuint16m8_t): Ditto.
(vint32mf2_t): Ditto.
(vuint32mf2_t): Ditto.
(vint32m1_t): Ditto.
(vuint32m1_t): Ditto.
(vint32m2_t): Ditto.
(vuint32m2_t): Ditto.
(vint32m4_t): Ditto.
(vuint32m4_t): Ditto.
(vint32m8_t): Ditto.
(vuint32m8_t): Ditto.
(vint64m1_t): Ditto.
(vuint64m1_t): Ditto.
(vint64m2_t): Ditto.
(vuint64m2_t): Ditto.
(vint64m4_t): Ditto.
(vuint64m4_t): Ditto.
(vint64m8_t): Ditto.
(vuint64m8_t): Ditto.
(vfloat32mf2_t): Ditto.
(vfloat32m1_t): Ditto.
(vfloat32m2_t): Ditto.
(vfloat32m4_t): Ditto.
(vfloat32m8_t): Ditto.
(vfloat64m1_t): Ditto.
(vfloat64m2_t): Ditto.
(vfloat64m4_t): Ditto.
(vfloat64m8_t): Ditto.
(vv): Ditto.
(vx): Ditto.
(v): Ditto.
(wv): Ditto.
(wx): Ditto.
(x_x_v): Ditto.
(vf2): Ditto.
(vf4): Ditto.
(vf8): Ditto.
(vvm): Ditto.
(vxm): Ditto.
(x_x_w): Ditto.
(v_v): Ditto.
(v_x): Ditto.
(vs): Ditto.
(mm): Ditto.
(m): Ditto.
(vf): Ditto.
(vm): Ditto.
(wf): Ditto.
(vfm): Ditto.
(v_f): Ditto.
(ta): Ditto.
(tu): Ditto.
(ma): Ditto.
(mu): Ditto.
(tama): Ditto.
(tamu): Ditto.
(tuma): Ditto.
(tumu): Ditto.
(tam): Ditto.
(tum): Ditto.
* config/riscv/riscv-vector-builtins.h (GCC_RISCV_VECTOR_BUILTINS_H): New macro.
(RVV_REQUIRE_RV64BIT): Ditto.
(RVV_REQUIRE_ZVE64): Ditto.
(RVV_REQUIRE_ELEN_FP_32): Ditto.
(RVV_REQUIRE_ELEN_FP_64): Ditto.
(enum operand_type_index): New enum.
(DEF_RVV_OP_TYPE): New macro.
(enum predication_type_index): New enum.
(DEF_RVV_PRED_TYPE): New macro.
(enum rvv_base_type): New enum.
(struct rvv_builtin_suffixes): New struct.
(struct rvv_arg_type_info): Ditto.
(struct rvv_type_info): Ditto.
(struct rvv_op_info): Ditto.
(class registered_function): New class.
(class function_base): Ditto.
(class function_shape): Ditto.
(struct function_group_info): New struct.
(class GTY): New class.
(class function_builder): Ditto.
(class function_call_info): Ditto.
(function_call_info::function_returns_void_p): New function.
(class function_expander): New class.
(function_instance::operator!=): New function.
(function_expander::expand): Ditto.
(function_expander::add_input_operand): Ditto.
(function_base::call_properties): Ditto.
Haochen Jiang [Thu, 26 May 2022 07:46:40 +0000 (15:46 +0800)]
i386: Auto vectorize sdot_prod, udot_prod with VNNIINT8 instruction.
gcc/ChangeLog:
* config/i386/sse.md (ssedvecmode): Rename from VI1SI.
(ssedvecmodelower): Rename from vi1si.
(sdot_prod<mode>): New define_expand.
(udot_prod<mode>): Ditto.
gcc/testsuite/ChangeLog:
* gcc.target/i386/vnniint8-auto-vectorize-1.c: New test.
* gcc.target/i386/vnniint8-auto-vectorize-2.c: Ditto.
Kong Lingling [Wed, 29 Sep 2021 01:48:20 +0000 (09:48 +0800)]
Support Intel AVX-VNNI-INT8
gcc/ChangeLog
* common/config/i386/cpuinfo.h (get_available_features): Detect
avxvnniint8.
* common/config/i386/i386-common.cc
(OPTION_MASK_ISA2_AVXVNNIINT8_SET): New.
(OPTION_MASK_ISA2_AVXVNNIINT8_UNSET): Ditto.
(ix86_handle_option): Handle -mavxvnniint8.
* common/config/i386/i386-cpuinfo.h (enum processor_features):
Add FEATURE_AVXVNNIINT8.
* common/config/i386/i386-isas.h: Add ISA_NAME_TABLE_ENTRY for
avxvnniint8.
* config.gcc: Add avxvnniint8intrin.h.
* config/i386/avxvnniint8intrin.h: New file.
* config/i386/cpuid.h (bit_AVXVNNIINT8): New.
* config/i386/i386-builtin.def: Add new builtins.
* config/i386/i386-c.cc (ix86_target_macros_internal): Define
__AVXVNNIINT8__.
* config/i386/i386-options.cc (isa2_opts): Add -mavxvnniint8.
(ix86_valid_target_attribute_inner_p): Handle avxvnniint8.
* config/i386/i386-isa.def: Add DEF_PTA(AVXVNNIINT8) New..
* config/i386/i386.opt: Add option -mavxvnniint8.
* config/i386/immintrin.h: Include avxvnniint8intrin.h.
* config/i386/sse.md (UNSPEC_VPMADDUBSWACCD
UNSPEC_VPMADDUBSWACCSSD,UNSPEC_VPMADDWDACCD,
UNSPEC_VPMADDWDACCSSD): Rename according to new style.
(vpdp<vpdotprodtype>_<mode>): New define_insn.
* doc/extend.texi: Document avxvnniint8.
* doc/invoke.texi: Document -mavxvnniint8.
* doc/sourcebuild.texi: Document target avxvnniint8.
gcc/testsuite/ChangeLog
* g++.dg/other/i386-2.C: Add -mavxvnniint8.
* g++.dg/other/i386-3.C: Ditto.
* gcc.target/i386/avx-check.h: Add avxvnniint8 check.
* gcc.target/i386/sse-12.c: Add -mavxvnniint8.
* gcc.target/i386/sse-13.c: Ditto.
* gcc.target/i386/sse-14.c: Ditto.
* gcc.target/i386/sse-22.c: Ditto.
* gcc.target/i386/sse-23.c: Ditto.
* gcc.target/i386/funcspec-56.inc: Add new target attribute.
* lib/target-supports.exp
(check_effective_target_avxvnniint8): New.
* gcc.target/i386/avxvnniint8-1.c: Ditto.
* gcc.target/i386/avxvnniint8-vpdpbssd-2.c: Ditto.
* gcc.target/i386/avxvnniint8-vpdpbssds-2.c: Ditto.
* gcc.target/i386/avxvnniint8-vpdpbsud-2.c: Ditto.
* gcc.target/i386/avxvnniint8-vpdpbsuds-2.c: Ditto.
* gcc.target/i386/avxvnniint8-vpdpbuud-2.c: Ditto.
* gcc.target/i386/avxvnniint8-vpdpbuuds-2.c: Ditto.
Co-authored-by: Hongyu Wang <hongyu.wang@intel.com>
Co-authored-by: Haochen Jiang <haochen.jiang@intel.com>
Hongyu Wang [Tue, 28 Sep 2021 07:30:14 +0000 (15:30 +0800)]
Support Intel AVX-IFMA
gcc/
* common/config/i386/i386-common.cc
(OPTION_MASK_ISA_AVXIFMA_SET, OPTION_MASK_ISA2_AVXIFMA_UNSET,
OPTION_MASK_ISA2_AVX2_UNSET): New macro.
(ix86_handle_option): Handle -mavxifma.
* common/config/i386/i386-cpuinfo.h (processor_types): Add
FEATURE_AVXIFMA.
* common/config/i386/i386-isas.h: Add ISA_NAME_TABLE_ENTRY for
avxifma.
* common/config/i386/cpuinfo.h (get_available_features):
Detect avxifma.
* config.gcc: Add avxifmaintrin.h
* config/i386/avx512ifmavlintrin.h: (_mm_madd52lo_epu64): Change
to macro.
(_mm_madd52hi_epu64): Likewise.
(_mm256_madd52lo_epu64): Likewise.
(_mm256_madd52hi_epu64): Likewise.
* config/i386/avxifmaintrin.h: New header.
* config/i386/cpuid.h (bit_AVXIFMA): New.
* config/i386/i386-builtin.def: Add new builtins, and correct
pattern names for AVX512IFMA.
* config/i386/i386-builtins.cc (def_builtin): Handle AVX-IFMA
builtins like AVX-VNNI.
* config/i386/i386-c.cc (ix86_target_macros_internal): Define
__AVXIFMA__.
* config/i386/i386-expand.cc (ix86_check_builtin_isa_match):
Relax ISA masks for AVXIFMA.
* config/i386/i386-isa.def: Add AVXIFMA.
* config/i386/i386-options.cc (isa2_opts): Add -mavxifma.
(ix86_valid_target_attribute_inner_p): Handle avxifma.
* config/i386/i386.md (isa): Add attr avxifma and avxifmavl.
* config/i386/i386.opt: Add option -mavxifma.
* config/i386/immintrin.h: Inculde avxifmaintrin.h.
* config/i386/sse.md (avx_vpmadd52<vpmadd52type>_<mode>):
Remove.
(vpamdd52<vpmadd52type><mode><sd_maskz_name>): Remove.
(vpamdd52huq<mode>_maskz): Rename to ...
(vpmadd52huq<mode>_maskz): ... this.
(vpamdd52luq<mode>_maskz): Rename to ...
(vpmadd52luq<mode>_maskz): ... this.
(vpmadd52<vpmadd52type><mode>): New define_insn.
(vpmadd52<vpmadd52type>v8di): Likewise.
(vpmadd52<vpmadd52type><mode>_maskz_1): Likewise.
(vpamdd52<vpmadd52type><mode>_mask): Rename to ...
(vpmadd52<vpmadd52type><mode>_mask): ... this.
* doc/invoke.texi: Document -mavxifma.
* doc/extend.texi: Document avxifma.
* doc/sourcebuild.texi: Document target avxifma.
gcc/testsuite/
* gcc.target/i386/avx-check.h: Add avxifma check.
* gcc.target/i386/avx512ifma-vpmaddhuq-1.c: Remane..
* gcc.target/i386/avx512ifma-vpmaddhuq-1a.c: To this.
* gcc.target/i386/avx512ifma-vpmaddluq-1.c: Ditto.
* gcc.target/i386/avx512ifma-vpmaddluq-1a.c: Ditto.
* gcc.target/i386/avx512ifma-vpmaddhuq-1b.c: New Test.
* gcc.target/i386/avx512ifma-vpmaddluq-1b.c: Ditto.
* gcc.target/i386/avx-ifma-1.c: Ditto.
* gcc.target/i386/avx-ifma-2.c: Ditto.
* gcc.target/i386/avx-ifma-3.c: Ditto.
* gcc.target/i386/avx-ifma-4.c: Ditto.
* gcc.target/i386/avx-ifma-5.c: Ditto.
* gcc.target/i386/avx-ifma-6.c: Ditto.
* gcc.target/i386/avx-ifma-vpmaddhuq-2.c: Ditto.
* gcc.target/i386/avx-ifma-vpmaddluq-2.c: Ditto.
* gcc.target/i386/sse-12.c: Add -mavxifma.
* gcc.target/i386/sse-13.c: Ditto.
* gcc.target/i386/sse-14.c: Ditto.
* gcc.target/i386/sse-22.c: Ditto.
* gcc.target/i386/sse-23.c: Ditto.
* g++.dg/other/i386-2.C: Ditto.
* g++.dg/other/i386-3.C: Ditto.
* gcc.target/i386/funcspec-56.inc: Add new target attribute.
* lib/target-supports.exp
(check_effective_target_avxifma): New.
GCC Administrator [Fri, 21 Oct 2022 00:17:52 +0000 (00:17 +0000)]
Daily bump.
Harald Anlauf [Wed, 19 Oct 2022 20:37:56 +0000 (22:37 +0200)]
Fortran: error recovery with references of bad array constructors [PR105633]
gcc/fortran/ChangeLog:
PR fortran/105633
* expr.cc (find_array_section): Move check for NULL pointers so
that both subscript triplets and vector subscripts are covered.
gcc/testsuite/ChangeLog:
PR fortran/105633
* gfortran.dg/pr105633.f90: New test.
Co-authored-by: Steven G. Kargl <kargl@gcc.gnu.org>
Aldy Hernandez [Thu, 20 Oct 2022 16:26:42 +0000 (18:26 +0200)]
[PR c++/106654] Handle non-irange ranges in get_range_global for default defs.
With the upcoming [[assume]] work, Andrew has pointed out that
non-irange ranges are not handled in get_range_global for
SSA_NAME_IS_DEFAULT_DEF. This patch fixes the oversight.
PR c++/106654
gcc/ChangeLog:
* value-query.cc (get_range_global): Handle non integer ranges for
default def SSA names.
Aldy Hernandez [Wed, 19 Oct 2022 15:06:41 +0000 (17:06 +0200)]
Add op[12]_range for UNORDERED_LT entries in range-op.
gcc/ChangeLog:
* range-op-float.cc (foperator_unordered_lt::op1_range): New.
(foperator_unordered_lt::op2_range): New.
Torbjörn SVENSSON [Fri, 23 Sep 2022 17:08:30 +0000 (19:08 +0200)]
testsuite: Sanitize fails for SP FPU on Arm
This patch stops reporting fails for Arm targets with single
precision floating point unit for types wider than 32 bits (the width
of float on arm-none-eabi).
As reported in PR102017, fenv is reported as supported in recent
versions of newlib. At the same time, for some Arm targets, the
implementation in libgcc does not support exceptions and thus, the
test fails with a call to abort().
gcc/testsuite/ChangeLog:
* lib/target-supports.exp
(check_effective_target_fenv_exceptions_double): New.
(check_effective_target_fenv_exceptions_long_double): New.
* gcc.dg/c2x-float-7.c: Split into 3 tests...
* gcc.dg/c2x-float-7a.c: Float part of c2x-float-7.c.
* gcc.dg/c2x-float-7b.c: Double part of c2x-float-7.c.
* gcc.dg/c2x-float-7c.c: Long double part of c2x-float-7.c.
* gcc.dg/pr95115.c: Switch to fenv_exceptions_double.
* gcc.dg/torture/float32x-nan-floath.c: Likewise.
* gcc.dg/torture/float32x-nan.c: Likewise.
* gcc.dg/torture/float64-nan-floath.c: Likewise.
* gcc.dg/torture/float64-nan.c: Likewise.
* gcc.dg/torture/inf-compare-1.c: Likewise.
* gcc.dg/torture/inf-compare-2.c: Likewise.
* gcc.dg/torture/inf-compare-3.c: Likewise.
* gcc.dg/torture/inf-compare-4.c: Likewise.
* gcc.dg/torture/inf-compare-5.c: Likewise.
* gcc.dg/torture/inf-compare-6.c: Likewise.
* gcc.dg/torture/inf-compare-7.c: Likewise.
* gcc.dg/torture/inf-compare-8.c: Likewise.
* gcc.dg/torture/pr52451.c: Likewise.
* gcc.dg/torture/pr82692.c: Likewise.
* gcc.dg/torture/inf-compare-1-float.c: New test.
* gcc.dg/torture/inf-compare-2-float.c: New test.
* gcc.dg/torture/inf-compare-3-float.c: New test.
* gcc.dg/torture/inf-compare-4-float.c: New test.
* gcc.dg/torture/inf-compare-5-float.c: New test.
* gcc.dg/torture/inf-compare-6-float.c: New test.
* gcc.dg/torture/inf-compare-7-float.c: New test.
* gcc.dg/torture/inf-compare-8-float.c: New test.
Co-Authored-By: Yvan ROUX <yvan.roux@foss.st.com>
Signed-off-by: Torbjörn SVENSSON <torbjorn.svensson@foss.st.com>