util/format: allow unpacking less than a block from rgtc

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Acked-by: Eric Engestrom <eric@igalia.com>
Tested-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18248>

util/format: fix broken indentation

This file had a mixture of tabs and spaces for indent.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Acked-by: Eric Engestrom <eric@igalia.com>
Tested-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18248>

mesa: add format-helper for rgtc

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Acked-by: Eric Engestrom <eric@igalia.com>
Tested-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18248>

mesa/st: add context-flag for rgtc

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Acked-by: Eric Engestrom <eric@igalia.com>
Tested-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18248>

radv/ci: cleanup lists of failures/flakes

When tests are already in the flakes list, it's useless to mark them
as expected failures.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Martin Roukala (né Peres) <martin.roukala@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18592>

turnip: use vk_descriptor_set_layout

Mainly for vk_descriptor_set_layout_{ref,unref}.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18588>

turnip: use vk_buffer

Mainly for vk_buffer_range.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18588>

freedreno: We really don't need aligned vbo's

The logic was inverted, we don't need aligned for later gens.

Fixes: 60912f1ebd3 ("freedreno: we don't need aligned vbo's")
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18605>

freedreno/drm/virtio: Handle read after upload

If we get CPU access (such as a read) after an upload transfer, we need
to ensure that the host has handled the upload.  Do this by stalling
when the buffer is mapped.  (The previous commit ensures we don't try to
do a pointless upload for an already mapped buffer.)

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18604>

freedreno/drm/virtio: Don't prefer upload for mapped buffers

The upload path is intended to avoid stalling on host in order to mmap
recently allocated buffers.  But if we already had to mmap it, no point
in taking the upload path.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18604>

freedreno/virtio: Don't upload if we have valid range

A transfer that only partially writes the staging buffer could overwrite
valid buffer contents, unless we are told that it is ok to discard the
entire range.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18604>

mesa: Lower mediump temps and CS shared when the driver supports FP16+INT16.

Typically GLSL mediump lowering will have lowered all the ALU ops
generating the values to 16-bit, and once vars_to_ssa happens the mediump
temps disappear.  However, if they don't disappear (for example, the var
gets indirected and eventually gets lowered to scratch or indirect
lowering), then you don't want the storage upconverted to 32-bit.

Also, if a CS shared var is declared mediump, then storing it as 16 bit
prevents conversions around the load store assuming the ALU ops related to
them are 16 bit.  For gfxbench aztec ruins, the CS shared var sizes are
cut in half, improving overall perf by 0.805549% +/- 0.0953482% (n=6) on
gl-5-normal.

freedreno shader-db:
total instructions in shared programs: 2917577 -> 2917743 (<.01%)
instructions in affected programs: 46141 -> 46307 (0.36%)
total last-baryf in shared programs: 109712 -> 109492 (-0.20%)
last-baryf in affected programs: 638 -> 418 (-34.48%)
total full in shared programs: 190275 -> 190218 (-0.03%)
full in affected programs: 156 -> 99 (-36.54%)
total constlen in shared programs: 492596 -> 492600 (<.01%)
constlen in affected programs: 8 -> 12 (50.00%)

total cat6 in shared programs: 33019 -> 33107 (0.27%)
cat6 in affected programs: 3604 -> 3692 (2.44%)
total stp in shared programs: 3626 -> 3670 (1.21%)
stp in affected programs: 3336 -> 3380 (1.32%)
total ldp in shared programs: 1718 -> 1762 (2.56%)
ldp in affected programs: 1680 -> 1724 (2.62%)
(this is all in aztec ruins)

total sstall in shared programs: 195656 -> 195182 (-0.24%)
sstall in affected programs: 3249 -> 2775 (-14.59%)
total (ss) in shared programs: 52823 -> 52966 (0.27%)
(ss) in affected programs: 1733 -> 1876 (8.25%)
total systall in shared programs: 507928 -> 508687 (0.15%)
systall in affected programs: 103010 -> 103769 (0.74%)
total (sy) in shared programs: 23185 -> 23196 (0.05%)
(sy) in affected programs: 1276 -> 1287 (0.86%)
total waves in shared programs: 435290 -> 435302 (<.01%)
waves in affected programs: 12 -> 24 (100.00%)
total loops in shared programs: 407 -> 405 (-0.49%)
loops in affected programs: 9 -> 7 (-22.22%)

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18452>

nir/lower_mediump_vars: Don't lower mediump shared vars with atomic access.

I don't know of any GPUs doing 16-bit atomic accesses, nor do I know of
anybody wanting that in shaders.  But deqp has GLES CTS cases that set
mediump on shared variables, so just skip lowering for those vars.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18452>

freedreno/ir3: Consistently lower mediump inputs to 16-bit (when we can).

If every use was a conversion to 16, then ir3_cf would fold it into the
bary instruction.  But if something had generated a highp comparison of
the mediump input with a mediump op result, it would get stuck as highp,
even though we could have used 16-bit values without upconverting.

This fixes dEQP-GLES2.functional.shaders.algorithm.rgb_to_hsl_fragment on
ANGLE on turnip, closing #7043.  fossil-db results are mixed:

fossil-db:
Totals from 697 (4.65% of 14988) affected shaders:
MaxWaves: 10712 -> 10736 (+0.22%)
Instrs: 82394 -> 83572 (+1.43%); split: -1.31%, +2.74%
CodeSize: 178280 -> 180118 (+1.03%); split: -0.46%, +1.49%
NOPs: 15887 -> 16067 (+1.13%); split: -7.48%, +8.61%
MOVs: 1297 -> 1328 (+2.39%); split: -6.86%, +9.25%
Full: 3730 -> 3842 (+3.00%); split: -1.80%, +4.80%
(ss): 1877 -> 1849 (-1.49%); split: -5.59%, +4.10%
(sy): 1249 -> 1255 (+0.48%); split: -1.04%, +1.52%
(ss)-stall: 6809 -> 6364 (-6.54%); split: -13.85%, +7.31%
(sy)-stall: 17059 -> 17257 (+1.16%); split: -6.51%, +7.67%
Cat0: 17220 -> 17400 (+1.05%); split: -6.90%, +7.94%
Cat1: 5307 -> 6366 (+19.95%); split: -6.93%, +26.89%
Cat2: 39138 -> 39101 (-0.09%); split: -0.31%, +0.22%
Cat3: 16772 -> 16741 (-0.18%)
Cat5: 1269 -> 1276 (+0.55%)

I tried to pick some apps to test that looked the most impacted, and
indeed the results are mixed:

cookie_run_kingdom:         +0.275514% +/- 0.0883816% (n=68)
trex_200:                   +0.0943847% +/- 0.0297073% (n=1463)
command_and_conquer_rivals: no difference (n=131)
war_planet_online:          no difference (n=120)
lego_legacy:                -0.192131% +/- 0.152083% (n=99)
among_us:                   -0.625227% +/- 0.385419% (n=60)

Given that the perf results are small and go both ways, and apparently
we're an outlier in not always lowering mediump inputs to 16-bit, just do
it for consistency with other drivers.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18506>

intel/compiler/fs: Use DF to load constants when has_64bit_int is not supported

This was already been done to gen7 platforms, so now extending to all
platforms without has_64bit_int.

Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18577>

intel/compiler/fs: Fix compilation of shaders with SHADER_OPCODE_SHUFFLE of float64 type

During the lower_regioning() optimization, required_exec_type() is
returning BRW_REGISTER_TYPE_UQ type when processing
SHADER_OPCODE_SHUFFLE instructions of type BRW_REGISTER_TYPE_DF but
MTL has float64 support but lacks int64 support causing shader
compilation to fail.

To fix that we could make required_exec_type() return
BRW_REGISTER_TYPE_DF in such case but SHADER_OPCODE_SHUFFLE virtual
instruction runs in the integer pipeline(inferred_exec_pipe()).

So here replacing the has_64bit check by has_64bit_int, this will
properly handle older and newer cases making this function return
BRW_REGISTER_TYPE_UD.
Then lower_exec_type() will take care to generate 2 32bits operations
to accomplish the same.

While at it also dropping the 'devinfo->verx10 == 70' check as
GFX7_FEATURES fall into the same category as MTL, has float64 but no
int64 support.

Fixes at least this crucible tests:
func.uniform-subgroup.exclusive.fadd64.q0
func.uniform-subgroup.exclusive.fmin64.q0
func.uniform-subgroup.exclusive.fmax64.q0

Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18577>

radv: stop checking for NULL pipelines in radv_CmdBindPipeline()

This should never happen now.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18567>

radv: stop dirtying the graphics pipeline when restoring it

radv_CmdBindPipeline() does it already.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18567>

radv: reset the compute pipeline when the saved one was NULL

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18567>

radv: do not bind NULL graphics pipeline when restoring the meta state

It's invalid to bind NULL pipelines, but make sure to reset it to
its previous NULL state.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18567>

radv: stop setting redundant viewport/scissor for internal operations

Only emit them when it's needed.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18567>

drm-shim: Allow drm-shim to work with glibc fortify.

Signed-off-by: David Riley <davidriley@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18558>

ci/panvk: Skip dEQP-VK.api.object_management.max_concurrent.query_pool

This test times out occasionally. Let's disable it for now.

Reported-by: David Heidelberg <david.heidelberg@collabora.com>
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Acked-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18578>

ci/traces: remove first line with YAML version to prevent failure

Older libyaml (0.2.2) fail with YAML 1.2, just drop it.

Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18595>

ci: add jq utility

Needed as a dependency for the yq utility.

Also bump x86-build-base image.

Fixes: f2649b93e29e ("ci: performance traces: make use of no-perf label")

Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18595>

ci: use xargs instead of find -exec

This allows us to see failure when yamllint return non-zero.

Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18595>

venus: Use VkPhysicalDeviceVulkan13{Features,Properties}

Add the structs to vn_physical_device, just like we do for the 1.1 and
1.2 structs.

Prepares for Vulkan 1.3 enablement. No intended change in behavior.

Tested with gpu Intel Tigerlake on CrOS device volteer.

I tested only a small subset of dEQP because this branch only touches
the code for VkPhysicalDevice{Features2,Properties2}.

  vulkan-cts-1.3.3.0
  dEQP-VK.api.info.*
  dEQP-VK.api.smoke.*
  pass/skip/fail = 3796/9/0

I tested Dota 2 on borealis on volteer, with non-Proton Vulkan.  The
game launches and reaches the main menu. Same with Hades with DX on
Proton 7.

Signed-off-by: Chad Versace <chadversary@chromium.org>
Reviewed-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18158>

venus: Fix features/properties for unavailable extensions

In vn_physical_device_init_features() and
vn_physical_device_init_properties(), we queried many extension structs
even if the extension was unavailable. Afterwards we copied the
undefined values from the extension structs into the core structs.

Signed-off-by: Chad Versace <chadversary@chromium.org>
Reviewed-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18158>

venus: Add macros VN_SET_CORE_*

Used to refactor vn_physical_device.c.  The new code easier to read and
has less duplication.

Signed-off-by: Chad Versace <chadversary@chromium.org>
Reviewed-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18158>

venus: Refactor VN_ADD_TO_PNEXT

Motivation is easier sorting and readability.

- In VN_ADD_TO_PNEXT_OF, re-arrange params to allow sorting. Param1 is
  invariant in each block. Param2 is sType.

- In VN_ADD_EXT_TO_PNEXT_OF, make its initial params match those of
  VN_ADD_TO_PNEXT_OF.

- Then sort the macro calls.

Signed-off-by: Chad Versace <chadversary@chromium.org>
Reviewed-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18158>

venus: Rename some feature/property structs

Make the variable name more closely match the type name.
This also allows them to sort correctly.

  argb_4444_formats     -> _4444_formats
  eight_bit_storage     -> _8bit_storage
  sixteen_bit_storage   -> _16bit_storage

While touching vn_physical_device.[ch], also run clang-format.

Signed-off-by: Chad Versace <chadversary@chromium.org>
Reviewed-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18158>

zink: handle split acquire/present

if the swapchain image is acquired in a different cmdbuf than it gets
presented with, the acquire semaphore will have already been submitted
by this point, and the swapchain should be flagged as such

cc: mesa-stable

Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18557>

radv: avoid bottlenecking on sequential sparse buffer binds

it's more costly to submit individual sparse buffer binds than to
merge them and submit bigger binds, so try to pre-compare and flatten
out the bind array as much as possible to reduce ioctl counts

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18507>

docs: add more features

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17956>

lavapipe: ARM/EXT_rasterization_order_attachment_access

another no-op

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17956>

lavapipe: VK_EXT_attachment_feedback_loop_layout

no-op

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17956>

v3dv: expose VK_EXT_load_store_op_none

This extension adds new NONE attachment load / store operations,
which are identical to the DONT_CARE variants with the difference
that DONT_CARE doesn't ensure that the original contents of the
memory within the render area are preserved and these new versions
do (with some caveats).

Our implementation was not destroying data with DONT_CARE anyway
so we already support the new semantics. Our implementation is
such that we don't need to do anything specific with the new
operations and the current behavior will do what is expected.

We pass all the tests under:
dEQP-VK.renderpass*.load_store_op_none.*

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18570>

v3dv: don't load an attachment for unaligned render area if we are not storing

If the render area is not aligned to tile boundaries it means we have partially
covered tiles in the framebuffer. In this case, we always need to load the tile
buffer from memory in order to preserve the contents outside the render area
on the tile buffer store. However, if in this scenario we know we won't be
storing the tile buffer we can skip the load safely.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18570>

turnip: implement VK_EXT_multi_draw

vkoverhead running:
    * draw numbers are reported as thousands of operations per second
    * percentages for draw cases are relative to 'draw'
   0, draw,                                      29151,        100.0%
   1, draw_multi,                                35449,        121.6%
   2, draw_vertex,                               28907,        99.2%
   3, draw_multi_vertex,                         56658,        194.4%

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11502>

pvr: Fix multiple file descriptor leaks.

Signed-off-by: Rajnesh Kanwal <rajnesh.kanwal@imgtec.com>
Reported-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18594>

tu: Initial implementation of VK_EXT_inline_uniform_block

This is a trivial implementation where we just insert a UBO descriptor
pointing to the actual data and then treat it as a normal UBO everywhere
else. In theory an indirect CP_LOAD_STATE would be more efficient than
ldc.k to preload inline uniform blocks to constants. However we will
always need the UBO descriptor anyway, even if we lower the limits
enough to always be able to preload them, because with variable pointers
we may have a pointer that could be to either an inline uniform block or
regular uniform block. So, using an indirect CP_LOAD_STATE should be an
optimization on top of this.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17960>

tu: Don't preload variable-count descriptors

We don't know how many descriptors will actually be valid, which could
lead to preloading descriptors out-of-bounds of the descriptor size.
This was leading to GPU hangs on some tests once we enabled inline
uniforms.

Fixes: d9fcf5de55a ("turnip: Enable nonuniform descriptor indexing")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17960>

tu: Fix descriptor set size bounds

This old code looks like it was left around from anv. Make it use the
limits the rest of the code uses.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17960>

nir/algebraic: optimize fabs(bcsel(b, fneg(a), a))

fossil-db (Sienna Cichlid):
Totals from 207 (0.15% of 134913) affected shaders:
VGPRs: 7152 -> 6928 (-3.13%)
CodeSize: 762404 -> 752888 (-1.25%)
MaxWaves: 6138 -> 6146 (+0.13%)
Instrs: 144031 -> 142184 (-1.28%)
Latency: 817783 -> 807286 (-1.28%)
InvThroughput: 151031 -> 147497 (-2.34%)
VClause: 1490 -> 1453 (-2.48%)
SClause: 3357 -> 3331 (-0.77%); split: -0.92%, +0.15%
Copies: 9632 -> 9555 (-0.80%); split: -0.81%, +0.01%
Branches: 4306 -> 4270 (-0.84%)
PreSGPRs: 11232 -> 11218 (-0.12%); split: -0.15%, +0.03%
PreVGPRs: 6307 -> 6121 (-2.95%)

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14772>

ir3: Prevent reordering movmsk with kill

`kill` changes which fibers are active, thus reodering instructions
which depend on which fibers are active - is wrong.

The issue was hidden because only `ballot(true)` is translated to movmsk
immidiately, while others are passed as MACRO and don't properly
take part in ir3_sched (which does the reordering).

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7162

Fixes CTS test (on gen3+):
 dEQP-VK.spirv_assembly.instruction.terminate_invocation.terminate.subgroup_ballot

Fixes: b1b80c06a78e62b2d8477b07f12b0153435b66a8
("ir3: Implement nir subgroup intrinsics")

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18413>

pvr: add required pixel formats

As per section 33.3 ("Required Format Support") of the Vulkan 1.0 spec - see
tables 42 to 52.

Signed-off-by: Frank Binns <frank.binns@imgtec.com>
Reviewed-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18572>

iris: disable preemption on VFG, Wa_14015207028 for DG2

This workaround disables batch level preemption for Polygon,
Trifan and Lineloop primitive topologies.

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18456>

anv: disable preemption on VFG, Wa_14015207028 for DG2

This workaround disables batch level preemption for Polygon,
Trifan and Lineloop primitive topologies.

v2: cleanups (José)

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18456>

intel/genxml: add VFG_PREEMPTION_CHICKEN_BITS register

This can be used to disable batch preemption on DG2+ either
completely or with selected primitive topologies.

Commit adds bit explicitly for Polygon, Trifan and LineLoop
topologies for Wa_14015207028.

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18456>

broadcom: fix dependencies in static_library() calls

The first argument is the name of the library, and the second argument
is the list of files; those two got a bit mixed up.

Fixes: 1ae8018a6af81eec4832 ("meson: Add support for the vc4 driver.")
Fixes: 4f3e380fa0f192f90e66 ("meson: Add support for the vc5 driver.")
Signed-off-by: Eric Engestrom <eric@igalia.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18593>

r300: add some synchronization for KIL

Set texture semaphore wait at the first control flow instruction
after the KIL.

Fixes: dEQP-GLES2.functional.shaders.discard.dynamic_loop_always

Signed-off-by: Pavel Ondračka <pavel.ondracka@gmail.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Filip Gawin <filip@gawin.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18576>

radv: Explicitly store the VA of accel structs

Gets rid of a bit of code and fixes the RRA accel_struct_vas table if
the BO is freed before vkDestroyAccelerationStructureKHR is called.

Signed-off-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18530>

radv/rra: Replace aliasing assert with a warning

Signed-off-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Friedrich Vock <friedrich.vock@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18530>

radv: Make the radv_buffer_get_va parameter const

Signed-off-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Friedrich Vock <friedrich.vock@gmx.de>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18530>

radv/rra: Remove redundant bounds validation

Signed-off-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Friedrich Vock <friedrich.vock@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18530>

radv/rra: Map accel struct VAs to handles

When validating a BVH, rra_validate_node uses _mesa_hash_table_u64_search to lookup, whether a BLAS pointer is valid. Since _mesa_hash_table_u64_search returns the data field of the found entry, we need to populate it. Otherwise, the NULL-check won't work.

Fixes: 5749806 ("radv: Add Radeon Raytracing Analyzer trace dumping utilities")
Signed-off-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Friedrich Vock <friedrich.vock@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18530>

virgl/ci: Update virglrenderer

Update virglrenderer past to version 0.10.1

Signed-off-by: Corentin Noël <corentin.noel@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18418>

c11: Update the values of enum mtx_plain, mtx_recursive, mtx_timed to make sure mtx_recursive != mtx_plain | mtx_recursive

According to c11 standards, there is 4 variant of mtx_init parameter,
mtx_plain
mtx_timed
mtx_plain|mtx_recursive
mtx_timed|mtx_recursive

Directly use mtx_recursive is not a thing, so we need make sure mtx_plain and mtx_plain|mtx_recursive are not equal,
So now we choose the values from Android c11 threads.h for enum mtx_plain, mtx_recursive, mtx_timed, to make sure
c11/threads.h be more c11 conformance, and can raise error when the type parameter of mtx_init are not one of
mtx_plain
mtx_timed
mtx_plain|mtx_recursive
mtx_timed|mtx_recursive

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18445>

svga: direct use of mtx_recursive is not c11 conformance

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18445>

radeonsi: direct use of mtx_recursive is not c11 conformance

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18445>

mesa: direct use of mtx_recursive is not c11 conformance

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18445>

freedreno: Remap high/norm/low priorities

At the gallium level, we only have three priorities.  But if kernel
supports preemption we'll have 3*nr_rings priority levels.  We'd prefer
to have the priorities that userspace picks be distributed over the
entire range of priorities so that preemption can work.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18584>

freedreno: nr_rings -> nr_priorities

This was renamed in the UABI header over a year ago, see
fc40e5e10c3b ("drm/msm: Utilize gpu scheduler priorities")

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18584>

freedreno: Misc indent fix

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18584>

turnip: add support for VK_KHR_global_priority

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18510>

turnip: add tu_physical_device::submitqueue_priority_count

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18510>

turnip: fix error handling for tu_queue_init

tu_queue_finish can only be called on initialized queues.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18510>

frontends/va: add HRD, filler data enable and etc

HRD parameters and filler data enable and skip frame
enable data are needed even though some application
doesn't use them.

Also for per picture rate control, max_qp and min_qp
are added.

Signed-off-by: Ruijing Dong <ruijing.dong@amd.com>
Reviewed-By: Sil Vilerino <sivileri@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18534>

frontends/va: add max_frame_size into rate control

why:
max au size and per picture rate control data structure
need to follow the input

how:
have max_frame_size as the input to rate control
also re-calculate other rate control related params

Signed-off-by: Ruijing Dong <ruijing.dong@amd.com>
Reviewed-by: Sil Vilerino <sivileri@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18534>

frontends/va: change getEncParamPreset location

why:
getEncParamPreset functions overwrite the incoming
messages.

how:
To change a location after the decoder is created,
so that if no incoming message the default ones
will be used otherwise the new messages will
overwrite the default values.

Signed-off-by: Ruijing Dong <ruijing.dong@amd.com>
Reviewed-by: Sil Vilerino <sivileri@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18534>

frontend/va: remove some unnecessary code

clean up some code related to h264 encoding.

Signed-off-by: Ruijing Dong <ruijing.dong@amd.com>
Reviewed-By: Sil Vilerino <sivileri@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18534>

subprojects: uprev perfetto to v29.0

This is mainly to get perfetto's commit 3e7228376 ("tracing: Clean up
platform TLS state on shutdown").

Acked-by: Rob Clark <robdclark@chromium.org>
Acked-by: Sami Kyöstilä <skyostil@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18502>

vulkan: update ALLOWED_ANDROID_VERSION for api level 33

Reviewed-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18476>

venus: ignore pInheritanceInfo if not secondary command buffer

TEST: no segfault in dEQP-VK.api.command_buffers.bad_inheritance_info_random

Fixes: 6f5289df533 ("venus: refactor VkCommandBufferBeginInfo fixups to function")
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18583>

turnip: Only emit descriptor loads for active stages in the pipeline.

zink has a push descriptor template layout that has every possible stage,
which gets used regardless of what stages are in the pipeline.  By
skipping over the unused stages, we cut the CP overhead.

Improves TU_DEBUG=sysmem gfxbench gl_driver2 on zink by 6.57% +/-
0.331143% (n=5).

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18562>

ci/turnip: Add missing a618 full-run bypass fails.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18562>

wsi/x11: Fix the is-visual-supported check

This was sort of well intentioned, but wrong. bits_per_rgb_value is the
number of significant bits in the color (channel) specification, not the
number of bits used to name that color within the pixel. If you have a
depth 24 visual but the colormap is 11 bits deep then each of those
channels selects one of 256 11-bit color values in the output ramp.

The open source drivers mostly don't expose anything like that, but
nvidia does, and we refuse to work. That's silly. Practically speaking
we can probably render to any TrueColor or DirectColor visual that your
X server exposes, since it is probably not going to have visuals for
non-color-renderable formats. Just check the visual class instead.

Likewise when matching formats to visuals, count the bits in the rgb
masks in the visual.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6995
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18381>

nir/algebraic: optimize bits=umin(bits, 32-(offset&0x1f))

Optimizes patterns which are created by recent versions of vkd3d-proton,
when constant folding doesn't eliminate it entirely:
- ubitfield_extract(value, offset, umin(bits, 32-(offset&0x1f)))
- ibitfield_extract(value, offset, umin(bits, 32-(offset&0x1f)))
- bitfield_insert(base, insert, offset, umin(bits, 32-(offset&0x1f)))

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13225>

radeonsi: invalidate L2 when using dcc stores

This is only needed on chips with tcc_rb_non_coherent=1.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7084
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18494>

mesa: remove fallback for GL_DEPTH_STENCIL

st_TexSubImage has this "default to fallback for depth-stencil" since
2013. I think it's time to remove this limitation - hopefully all
drivers will be happy with the change to avoid adding yet another CAP.

This helps CS:GO startup a lot, because the fallback path is very very
slow.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18484>

mesa: simplify _mesa_texstore_z24_s8 and s8_z24

The spec says:

   If the base internal format is DEPTH_STENCIL and format
   is not DEPTH_STENCIL, then the values of the stencil
   index texture components are undefined.

Which can be translated as: we don't need to bother preserving
the original stencil values.

Suggested by Emma Anholt.

Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18484>

mesa: avoid reading back textures from VRAM

This can be very slow on dGPU.

I tried a different version that would allocate a full row
and then do a single memcpy per row but the performance
was similar so I kept the simple version.

Cc: mesa-stable
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18484>

venus: add support for VK_EXT_multi_draw

Test:
./deqp-vk -n dEQP-VK.draw.*multi_draw*

Test run totals:
  Passed:        11520/11520 (100.0%)
  Failed:        0/11520 (0.0%)
  Not supported: 0/11520 (0.0%)
  Warnings:      0/11520 (0.0%)
  Waived:        0/11520 (0.0%)

Signed-off-by: Juston Li <justonli@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18304>

venus: sync to latest venus protocol headers

- v1.3.227 update
- added VK_EXT_multi_draw

Signed-off-by: Juston Li <justonli@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18304>

nouveau: Fix compiler warnings about silly address checks in ir_print.

in/out/sv are arrays, so &array[i] is a non-null pointer.  Presumably
numSysVals/Inputs/Outputs are only incremented when there's data in the
arrays, anyway.

Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18536>

turnip: reduce MAX_STORAGE_BUFFER_RANGE

Reduce MAX_STORAGE_BUFFER_RANGE from (1<<29) to (1<<27).  While (1<<28)
is fine based on my tests, let's match what the latest version of the
blob does.

Tested on a618 and a635.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18322>

rusticl/device: print error when libclc fails to load

Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18580>

asahi: Handle blending with MRT

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18525>

asahi: Don't crash on <4 channel render targets

It doesn't matter what we put in the swizzle for the unused components,
but if we try to stuff out-of-bounds PIPE_SWIZZLE_0/1/NONE values,
we'll crash in GenXML. Fixes failing tests in

   dEQP-GLES3.functional.fragment_out.basic.fixed.*

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18525>

agx: Don't use nir_find_variable_with_driver_location

io_semantics is the preferred alternative.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18525>

agx: Lower txs to a descriptor crawl

There's no native txs instruction... but we can emulate one :-) This is
heavy on shader ALU, but in the production driver, it'll all be hoisted
up to the preamble shader and so it shouldn't matter much. This
keeps the driver itself simple and low overhead, with a completely
obvious generalization to bindless.

Passes dEQP-GLES3.functional.shaders.texture_functions.texturesize.*

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18525>

agx: Implement load_global(_constant)

Found in compute shaders, maps to a subset of device_load, and will be
used for some lowerings soon.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18525>

agx: Implement txd

Handles all cases except for cube maps, which don't seem to work
properly, so those are lowered.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18525>

agx: Implement texture offsets and comparators

Texture offsets and shadow comparison values get grouped into a vector
passed by register. Comparison values are provided as-is (fp32). Texture
offsets are packed into nibbles, but we can do this on the CPU, as
nonconstant offsets are forbidden in GLSL at least. They're also
forbidden in Vulkan/SPIR-V without ImageGatherExtended/
shaderImageGatherExtended. I'm happy kicking the NIR lowering can down
the line, this commit is complicated enough already.

Passes dEQP-GLES3.functional.shaders.texture_functions.texture.* and
dEQP-GLES3.functional.shaders.texture_functions.textureoffset.*

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18525>

agx: Make p_combine take a dynamic src count

For larger vectors.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18525>

agx,asahi: Implement nir_intrinsic_load_texture_base_agx

Save off what we pass to BIND_TEXTURE.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18525>

nir: Add nir_intrinsic_texture_base_agx sysval

For non-bindless textures, get the base address of the texture
descriptor array, so we can crawl descriptors in the shader. For
bindless, this isn't needed (since the bindless handle will be the
address itself).

jekstrand suggested the idea of the descriptor crawl. It worked out
pretty well, all considered.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18525>

panfrost: Honour cso->req_local_mem

Fixes api.min_max_local_mem_size.

nir->info.shared_size can't be trusted in OpenCL.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18559>

panfrost: Respect buffer offset for OpenCL

This is so dumb. Panfrost port of d98b82a1039 ("iris/cs: take buffer offsets
into account for CL")

Fixes buffer.sub_buffers_read_write

Fixes: 80b90a0f2b8 ("panfrost: Implement panfrost_set_global_binding")
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Suggested-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18560>

pvr: Update FWIF 3d and compute register structures

This matches changes made in FW 1.17.OS@6285007.

Signed-off-by: Sarah Walker <sarah.walker@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18440>