review.tizen.org Git - platform/upstream/mesa.git/log

Revert "radeonsi/ci: update stoney fail -> flakes"

This is partial reverts commit 5ed2265fbf7971800df5fdcf025886f5554f8598.
As the xfail should not be removed from radeonsi-stoney-fails.txt
that point out by Emma Anholt

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19860>

ci: Update radeonsi-raven xfail to flake

Partial revert "ci/amd: add raven flakes which was previously failing"

This reverts commit fbf93ef82145978858779e95385364b53e2385a4.

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7738
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19860>

ci: Add intel kbl xfail to flake

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7738

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19860>

v3dv: pre-allocate actual events instead of event descriptors

Instead of keeping a free list of "event descriptors" which are
just the offsets in the BO state that are available, pre-allocate
the events. This is simpler as it doesn't require to allocate these
event descriptors at all.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20053>

commit_in_branch.py: variables cleanup

Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19988>

commit_in_branch.py: add support for checking staging branches

Or any branch that contains a `/` slash.

Cc: mesa-stable
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19988>

commit_in_branch.py: fix tests

Apparently these were backported since I wrote these tests ^^

Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19988>

ir3: Don't save/restore disasm string pointer

It's not in the key, so it randomly may or may not be present, and if it
is present then we don't actually save/restore the contents, so we will
save/restore random pointer values from the last run. Turnip already
disables searching the shader cache when assembly is requested, but
still wrote the final ir3_shader_variant which resulted in trying to
save random stale pointers when saving off the executable if a
subsequent compile hit that cache entry.

This fixes flakes in
dEQP-VK.pipeline.pipeline_library.shader_module_identifier.pipeline_from_id.*
for me.

Fixes: 56909868cd1 ("turnip: implement VK_KHR_pipeline_executable_properties")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20056>

tu: Fix binding NULL descriptor sets

This fixes the new test
dEQP-VK.pipeline.pipeline_library.graphics_library.misc.other.null_descriptor_set_in_monolithic_pipeline.

Fixes: e9f5de11d40 ("tu: Initial implementation of VK_EXT_graphics_pipeline_library")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20057>

radv: enable lower shader call vectorizing

Totals from 5 (71.43% of 7) affected shaders:
MaxWaves: 48 -> 50 (+4.17%)
Instrs: 32012 -> 32070 (+0.18%)
CodeSize: 172672 -> 172932 (+0.15%)
VGPRs: 512 -> 496 (-3.12%)
Latency: 715333 -> 715279 (-0.01%); split: -0.03%, +0.02%
InvThroughput: 149540 -> 146150 (-2.27%); split: -2.29%, +0.02%
VClause: 900 -> 897 (-0.33%)
Copies: 4173 -> 4199 (+0.62%); split: -0.12%, +0.74%
Branches: 1512 -> 1511 (-0.07%)
PreVGPRs: 475 -> 469 (-1.26%)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20075>

radv: stop emitting R_00B8A0_COMPUTE_PGM_RSRC3 from the CS preamble

It will be always emitted as part of the compute pipeline.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20054>

radv: disable VRS entirely on GFX11

Based on registers, VRS changed a lot and it's unclear how to program
it. This disable VK_KHR_fragment_shading_rate, VRS flat shading and
RADV_FORCE_VRS.

Cc: 22.3 mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20054>

radv: do not enable NGG culling on GFX11

RadeonSI disables it as well. It's really unclear if it will help or
not (eg. NGG culling never helped on GFX10).

Cc: 22.3 mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20054>

radv: do not enable DCC for MSAA images without FMASK

I don't know how this is supposed to work, especially for fast clears
because CMASK should be cleared to 0xC but FMASK implies CMASK.
This fixes a bunch of MSAA test failures on GFX10.3 with
RADV_DEBUG=nofmask.

Cc: 22.3 mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20054>

radv: set INTERPOLATE_COMP_Z to 0 on GFX11

Ported from RadeonSI to fix a EQAA bug.

Cc: 22.3 mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20054>

radv: set missing SPI_SHADER_PGM_xxx registers on GFX11

Found by inspection.

Cc: 22.3 mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20054>

nir: Add helper to create passthrough GS shader

Based on nir_create_passthrough_tcs and d3d12_make_passthrough_gs, this
creates a passthrough geometry shader that can be used by drivers that
needs to emulate some graphics features in the geometry shader.

Reviewed-by: Rob Clark <robclark@freedesktop.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19987>

anv: enable lower_shader_calls vectorizing

On Q2RTX RT shaders :

Totals from 7 (22.58% of 31) affected shaders:
Instrs: 15453 -> 14418 (-6.70%)
Cycles: 232647 -> 224959 (-3.30%)
Send messages: 574 -> 481 (-16.20%)
Spill count: 118 -> 106 (-10.17%)
Fill count: 156 -> 140 (-10.26%)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20058>

nir/lower_shader_calls: enable vectorizer

We cannot fully use the vectorizer outside of this pass because once
stack load/store operations have been lower to global load/store, the
robustness rule applies to those as they would to application
load/store.

But this is all internal and we know it doesn't require out of bound
checking. So doing the vectorizing here is the best solution. We just
have to teach the vectorizer about our intrinsics.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20058>

nir/lower_shader_calls: add a pass to split load/store into scalars

We'll run this pass prior to opt_load_store_vectorize to maximize the
effect of the optimization.

At the moment opt_load_store_vectorize is unable to pack this :

  store vec3
  store vec3
  store vec2

into this :

  store vec4
  store vec3

If your backend can only do vec4 stores max.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20058>

nir/lower_shader_calls: avoid moving loads into loops

This is similar to what opt_gcm is doing. Moving a load inside a loop
will increase memory bandwidth.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20058>

panfrost/blend: Fix invalid const values leading to NIR validation errors

Using a designated initializer like this leaves padding bits, which form
part of the aliasing u64/f64 member of the union, uninitialised, but a
nir_const_value must always have the unused bits zeroed out. Thus, use
the nir_const_value_for_float helper instead like everywhere else which
will do a memset 0 for us first.

Without this, using the pan_blend shader in a build with validation
enabled fails with:

  NIR validation failed after nir_lower_vars_to_ssa
  ...
            vec4 32 ssa_58 = load_const (0x3f7cfcfd /* 0.988235 */, 0x3f7cfcfd /* 0.988235 */, 0x3f7cfcfd /* 0.988235 */, 0x3f800000 /* 1.000000 */)
  error: memcmp(val, &cmp_val, sizeof(cmp_val)) == 0 (../src/compiler/nir/nir_validate.c:976)

Fixes: 1378c67bcf9e ("panfrost/blend: Inline blend constants")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20071>

venus: fix android wsi with global fencing disabled

Fixes: b21e4a7990c ("venus: put android wsi on the sub-optimal path")

Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20049>

radeonsi/vcn: set current pic index correctly

video corruption observed while running decode test for av1
content in chromeos.

solution is when target buffer is found in render pic list and when
target codec is null, set curr_pic_indx as index to the
pic in render pic list.

Cc: mesa-stable
Signed-off-by: Sajeesh Sidharthan <sajeesh.sidharthan@amd.com>
Reviewed-by: Boyuan Zhang <Boyuan.Zhang@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20000>

nir/lower_int64: fix shift lowering

Starting with !19748 lowered 64 bit shifts were showing wrong results for
shifts with insignificant bits set.

nir shifts are defined to only look at the least significant bits. The
lowering has take this into account.

So there are two things going on:
1. the `ieq` and `uge` further down depend on `y` being masked.
2. the calculation of `reverse_count` actually depends on a masked `y` as
well, due to the `(iabs (iadd y -32))` giving a different result for
shifts > 31;

Fixes: 41f3e9e5f5d ("nir: Implement lowering of 64-bit shift operations")
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19995>

ci/freedreno: Add another blend_equation_advanced flake.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20066>

panfrost: add GALLIUM_HUD=draw-calls

Signed-off-by: Italo Nicola <italonicola@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20063>

tu: Use right enum for compute active_shader_stages

This is VkShaderStageFlags, not VkPipelineStageFlags. Fixes preloading
descriptors for compute dispatches.

Fixes: d862a2ebcbf ("turnip: Only emit descriptor loads for active stages in the pipeline.")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20059>

turnip: Drop the cs argument from tu6_emit_cache_flush*().

It's always draw_cs or cs.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19939>

turnip: Clean up a repeated pattern around tu6_emit_flushes().

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19939>

turnip: Make tu_emit_cache_flush_ccu manage flush bits like other paths.

Everyone else sets the cache bits directly then calls tu6_emit_flushes on
them.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19939>

radv: inline gfx10_emit_streamout_{begin,end}()

Instead of having 2 different paths.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Tatsuyuki Ishi <ishitatsuyuki@gmail.com
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19632>

meson: Enable system_has_kms_drm for android

This allows to build libgbm when system = 'android' is set in
the cross_file.

Cc: "22.3" "22.2" mesa-stable
Signed-off-by: Roman Stratiienko <r.stratiienko@gmail.com>
Acked-by: Mauro Rossi <issor.oruam@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20033>

radv: compile GS copy shader after geometry shader

This affects the pipeline feedback durations: GS copy shader compilation
is now included in the GS compilation duration.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18898>

radv,aco: remove old streamout code

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18898>

radv,aco: remove old GS copy shader code

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18898>

radv,aco: implement GS copy shaders using NIR

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18898>

radv: make radv_use_llvm_for_stage device parameter const

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18898>

radv: lower streamout in NIR

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18898>

radv,aco: export legacy vertex outputs in NIR

This new behaviour will let us insert exports in GS copy shader control
flow.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18898>

pvr: Add missing valgrind includes and fix unused return value.

On including the header the compiler started throwing warnings
about the return value not being used when setting and getting the
vbits.

This commit adds the missing valgrind related headers and fixes the
warnings caused by including them.

Signed-off-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Reviewed-by: Matt Coster <matt.coster@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20035>

docs/zink: document missing max-image requirements

This should bring Zink's documentation up to speed with the previous
commit.

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19780>

mesa/main: verify more texture-limits for GL 4.1

OpenGL 4.1 also increased the minimum 3D and cube texture size as
well as the minimum number of texture-array layers. Let's also
verify these to prevent enbaling too recent GL versions on layered
drivers link Zink, VirGL etc.

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19780>

zink: check maxImageDimension1D as well as maxImageDimension2D

According to the docs for PIPE_CAP_MAX_TEXTURE_2D_SIZE, it's the limit
both for 2D *and* 1D textures. So let's take the min of the two vulkan
features here instead of assuming they're the same.

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19780>

freedreno: fix PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS for a6xx

We're reporting 2048 for VkPhysicalDeviceLimits::maxImageArrayLayers on
Turnip, so we should be able to use 2048 for OpenGL as well. And that's
the minimum required value for OpenGL 4.1 support.

According to http://vulkan.gpuinfo.org/, it seems like values of 2048
should be possible for at least as low as some Adreno 4xx GPUs. But
since we don't support recent GL versions on those, we this won't make a
big difference. So let's leave that up to someone who actually knows
what they're doing!

Acked-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19780>

d3d12: fix return-value for PIPE_CAP_MAX_TEXTURE_3D_LEVELS

D3D12_REQ_TEXTURE3D_U_V_OR_W_DIMENSION is 2^11, not 2^10 like the
comment said, and the code assumed. We need to add one to account for
the base-level.

Let's add a static_assert here to prove that this is the right value.

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19780>

d3d12: fix max-array-layers

We used to need this, because we incorrectly multiplied the cube array
sizes by 6. Now that this has been fixed, we can actually support the
OpenGL 4.1 limit for this.

Fixes: 7118b2136e9 ("d3d12: Don't multiply cube array sizes by 6")
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19780>

radv: use HTILE for VRS image only on GFX10.3

Based on registers, GFX11 no longer uses HTILE.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19962>

radv: do not clear VRS_HTILE_ENCODING on GFX11

This field no longer exists.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19962>

pvr: Query kernel for free list max size

Signed-off-by: Sarah Walker <sarah.walker@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19976>

tu: Fix fault with variable-count inline uniform blocks

This seems to have been triggered by some recent CTS changes which
changed the random number generation. I'm seeing context faults in
dEQP-VK.binding_model.descriptorset_random.sets4.dynindexed.ubolimitlow.sbolimitlow.sampledimghigh.lowimgnotex.iublimitlow.nouab.comp.noia.0
that are fixed by this.

Fixes: 37cde2c6348 ("tu: Rewrite inline uniform implementation")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20039>

intel/isl: Add MOCS settings for MTL platforms

Add MOCS settings for Xe platforms based on cache settings for L3/L4
and display.

Rework:
* Jordan: Use intel_device_info_is_mtl()

BSpec: 45101
Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20045>

AOSP: Add intel_hasvk vulkan library suffix

Required to correctly install vulkan.intel_hasvk.so module
after commit 50013ca9 ("intel: add a hasvk vulkan driver")

In order to set property ro.hardware.vulkan as 'intel_hasvk' for the correct iGPU parts at init stage,
i915 'graphics version' can only be detected by means of /sys/kernel/debug/dri/0/i915_capabilities
and debugfs needs to be mounted at early-init stage

https://review.lineageos.org/c/LineageOS/android_device_lge_g3-common/+/19875

Cc: "22.3" mesa-stable
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Tapani Pälli <tapani.palli@intel.com>
Tested-by: Mauro Rossi <issor.oruam@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20048>

ac/nir: legacy vs/gs use nir_xfb_info to replace pipe_stream_output_info

pipe_stream_output_info is built from nir_xfb_info, why not just use
nir_xfb_info directly.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20015>

iris: Use devinfo::has_flat_ccs instead of verx10

The assumption that GFX12.5 devices don't have AUX map is
invalid since MTL's introduction.

Signed-off-by: Jianxun Zhang <jianxun.zhang@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20043>

intel/dev: Set 'has_flat_ccs' flag for DG2

The code paths of flat ccs should be working on DG2 because
they are routed by other conditions like GFXVer so far. But
using this flag is the intended way, and we need to have
this change prior to updating these conditions with the flag.

Ref: 5262475242b ("intel/dev: Add a has_flat_ccs flag")

Signed-off-by: Jianxun Zhang <jianxun.zhang@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20043>

intel/isl: Disable CCS on MTL

MTL requires some ccs/aux-map changes from Jianxun Zhang, which are
still in progress. So, for now we disable ccs on MTL.

Rework:
* Drop change in isl_surf_supports_ccs (Nanley)

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20046>

anv, iris: Make use of devinfo::has_caching_uapi

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19911>

intel/dev: Add devinfo::has_caching_uapi (and disable for dg1 and dg2+)

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19911>

ci/alpine: disable mold on Alpine builds

All the timeouts started close to Mold linking phase, disable it.

See:
- https://gitlab.freedesktop.org/mesa/mesa/-/jobs/32502446
- https://gitlab.freedesktop.org/mesa/mesa/-/jobs/32465151

Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20032>

radeonsi/vcn/enc: add encoder statistics support

Signed-off-by: Thong Thai <thong.thai@amd.com>
Reviewed-by: Boyuan Zhang <boyuan.zhang@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19512>

frontends/va: add ability for encoder to output statistics

Signed-off-by: Thong Thai <thong.thai@amd.com>
Reviewed-by: Boyuan Zhang <boyuan.zhang@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19512>

ail: Split off test-miptree.cpp from test-layout.cpp

Keep test-layout.cpp for the simple smoke tests, and move the big pile
of miptree tests to its own file.

Signed-off-by: Asahi Lina <lina@asahilina.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20031>

ail: Add uncompressed twiddled texture sizing tests

Signed-off-by: Asahi Lina <lina@asahilina.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20031>

ail: Rename test-compression.cpp to test-comp-twiddled.cpp

To better align with the analogous test-uncomp-twiddled.cpp

Signed-off-by: Asahi Lina <lina@asahilina.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20031>

ail: Add more compression size test cases

Also sort the table in a consistent way, to make it easier to add
tests without creating duplicates in the future.

Signed-off-by: Asahi Lina <lina@asahilina.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20031>

ail: Fix logic for buffer alignment

It turns out that specifically Z/S single-layer textures have the main
miptree padded to the page size, but not others.

Signed-off-by: Asahi Lina <lina@asahilina.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20031>

ail: Fix compression metadata buffer sizing corner cases

Although the metadata is possibly one byte per 8x4 block, the
logical block size for compression/allocation is a 16x16 block,
so align to that. Also align the initial dimensions to that size,
and change the minification to a simple DIV_ROUND_UP.

Signed-off-by: Asahi Lina <lina@asahilina.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20031>

asahi: Pass through layer alignment flag to the hardware

Signed-off-by: Asahi Lina <lina@asahilina.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20031>

ail: Introduce layer_alignment flag

The hardware uses this flag to determine whether layer strides are
implicitly aligned to the page size or not.

Signed-off-by: Asahi Lina <lina@asahilina.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20031>

radv/llvm: add clip distance outputs manually if they're missing

It's possible that undef is written to clip/cull distance outputs and
they're eliminated, and we never set any position export to done=1 because
outinfo->pos_exports was calculated with the expectation that clip/cull is
exported.

Eliminating the export and fixing the done=1 bit hangs because the
hardware is still expecting clip/cull distances.

Fixes dEQP-VK.rasterization.provoking_vertex.transform_feedback.first.line_list
hang with LLVM.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19200>

aco: Combine constant bit test to s_bitcmp.

Foz-DB Navi21:
Totals from 73988 (54.84% of 134913) affected shaders:
VGPRs: 2959768 -> 2959752 (-0.00%)
SpillSGPRs: 10250 -> 10697 (+4.36%); split: -0.64%, +5.00%
SpillVGPRs: 2326 -> 2291 (-1.50%); split: -2.24%, +0.73%
CodeSize: 261339476 -> 261045912 (-0.11%); split: -0.12%, +0.00%
Scratch: 239616 -> 238592 (-0.43%)
Instrs: 49214044 -> 49188242 (-0.05%); split: -0.06%, +0.00%
Latency: 413214139 -> 413296229 (+0.02%); split: -0.03%, +0.05%
InvThroughput: 71741622 -> 71786300 (+0.06%); split: -0.07%, +0.13%
VClause: 856838 -> 856973 (+0.02%); split: -0.01%, +0.02%
SClause: 1504502 -> 1504567 (+0.00%); split: -0.01%, +0.02%
Copies: 4058433 -> 4060424 (+0.05%); split: -0.03%, +0.08%
Branches: 1502953 -> 1502945 (-0.00%); split: -0.00%, +0.00%
PreSGPRs: 3081927 -> 3081531 (-0.01%); split: -0.02%, +0.01%
PreVGPRs: 2513990 -> 2513992 (+0.00%)

The vast majority of instruction count regressions are caused by parallel-rdp.

Signed-off-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18870>

aco: Combine bit test to s_bitcmp.

Foz-DB Navi21:
Totals from 6396 (4.74% of 134913) affected shaders:
VGPRs: 483280 -> 483152 (-0.03%); split: -0.03%, +0.01%
SpillSGPRs: 8119 -> 7941 (-2.19%)
CodeSize: 63377880 -> 63268556 (-0.17%); split: -0.20%, +0.03%
MaxWaves: 86778 -> 86810 (+0.04%)
Instrs: 11745621 -> 11725857 (-0.17%); split: -0.20%, +0.03%
Latency: 162400148 -> 162282230 (-0.07%); split: -0.08%, +0.01%
InvThroughput: 29179429 -> 29133173 (-0.16%); split: -0.16%, +0.00%
VClause: 208032 -> 208100 (+0.03%); split: -0.01%, +0.05%
SClause: 431390 -> 430849 (-0.13%); split: -0.24%, +0.11%
Copies: 896222 -> 893285 (-0.33%); split: -0.62%, +0.30%
Branches: 349806 -> 348770 (-0.30%); split: -0.90%, +0.60%
PreSGPRs: 618908 -> 613773 (-0.83%); split: -0.83%, +0.00%
PreVGPRs: 482901 -> 482893 (-0.00%)

Signed-off-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18870>

aco: Combine s_abs and s_sub/s_add to s_absdiff.

Totals from 2 (0.00% of 134913) affected shaders:
CodeSize: 1344 -> 1336 (-0.60%)
Instrs: 277 -> 275 (-0.72%)

Signed-off-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18870>

aco: Ignore instructions with exec operands in follow_operand.

No Foz-DB changes.

Signed-off-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18870>

aco/optimizer: Cleanup ctx.uses handling for patterns which use follow_operand(..., true).

No Foz-DB changes.

Signed-off-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18870>

r600/sfn: always use four slots for Cayman trans ops

This is a partial revert of
ed6204eb0 (r600/sfn: only use 3 channels on Cayman for trans ops)

The scheduler and/or optimizer passes generate faulty code when
we use only three slots as decribed in the spec. So for now disable
this optimization.

Fixes: ed6204eb0 (r600/sfn: only use 3 channels on Cayman for trans ops)
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7774

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20034>

radv: reduce CPU overhead when emitting streamout descriptors

Only the last VGT stage can have streamout.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19723>

asahi: Implement DISCARD_WHOLE_RESOURCE

We can reallocate to avoid a flush.

Scrolling rosenzweig.io in Firefox with WebRender enabled is now vsyncing at
60fps instead of being capped around 50fps. SuperTuxKart is noticeably faster as
well, though this was prompted by WebRender.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20013>

agx: Don't depend sampler view on BO

The BO can change when shadowing, fix up at drawtime.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20013>

agx: Add merge helpers to GenXML

From panfrost.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20013>

agx: Make empty texture pack to all-zeroes

So we can do partial textures.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20013>

radv: only install 00-radv-defaults.conf if xmlconfig is used

RADV has its own drirc file. Make sure it also uses the xmlconfig
enable option.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20029>

asahi: Fix remaining build issues on macOS

Signed-off-by: Asahi Lina <lina@asahilina.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20030>

asahi: add fallback for DRM_FORMAT_MOD_INVALID on macOS

Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19879>

radv: emit DB_RENDER_OVERRIDE2 as part of the framebuffer

The number of samples from the image has to match the number of samples
from the pipeline anyways.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19906>

freedreno/decode: add missing dependency

The source code for rddecompiler includes adreno_common.xml.h, which is
a generated header. In order to ensure that the header has been written
when compiling rddecompiler.c, we need a dependency here.

Fixes: 03d80e0a6d3 ("freedreno/decode: Add 'rddecompiler' tool")
Acked-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20003>

freedreno/rddecompiler: Fix memory leak.

Fix defect reported by Coverity Scan.

Resource leak (RESOURCE_LEAK)
leaked_storage: Variable stream_data going out of scope leaks the storage it points to.

Fixes: a7773c3c4c7 ("freedreno/rddecompiler: Add shader disasm/asm support")
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20028>

clover: test for nir fp64 lowering options for cl_khr_fp64

With NIR we have softfp64, but we don't really want this for CL,
so check whether fp64 is lowered to a software implementation.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7750

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19919>

pvr: Setup tile buffers.

Signed-off-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20007>

pvr: Don't print out secondaries if they aren't used.

Signed-off-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20008>

pvr: Add '+' before desc offsets in debug output.

Having the '+' makes it more obvious that it's the offset of the
primary/secondary.

Signed-off-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20008>

pvr: Use glsl syntax to show set and binding number.

This makes the descriptor set debug output's descriptor set number
and binding number more obvious. The previous format wasn't as
obvious unless you knew how to read it.

Signed-off-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20008>

pvr: Change how desc set debug output section dividers are printed.

Instead of hard coding in the exact string to print out for the
divider, now we're printing the same char n times so we only need
to specify the character and how many times to retreat it.

Signed-off-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20008>

pvr: Don't print inactive bindings.

Previously all bindings were printed out and an "X" was used to
indicate if a binding was not active for a particular stage.
This commit just skips those bindings entirely reducing possible
confusion.

Signed-off-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20008>

pvr: Print out empty row if dynamic primaries or secondaries are missing.

Signed-off-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20008>

pvr: Explain why dynamic descriptors are allocated separately.

Signed-off-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20008>

radv/rt: Check space before emitting descriptors

Found by inspection.

cc: mesa-stable

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20020>

radv/ray_queries: Fix AABB handling

AABB intersections always have to be committed manually.
-> We don't have to copy opaque ones to closest.

It's also invalid to query t for candidate AABBs.

Totals from 7 (14.29% of 49) affected shaders:
CodeSize: 171008 -> 169672 (-0.78%)
Instrs: 32499 -> 32250 (-0.77%); split: -0.78%, +0.01%
Latency: 418859 -> 414759 (-0.98%); split: -0.98%, +0.00%
InvThroughput: 89182 -> 88251 (-1.04%); split: -1.05%, +0.00%
VClause: 602 -> 599 (-0.50%)
SClause: 837 -> 835 (-0.24%)
Copies: 4804 -> 4802 (-0.04%); split: -0.35%, +0.31%
Branches: 1593 -> 1585 (-0.50%)
PreSGPRs: 567 -> 566 (-0.18%)

Fixes: 3f72061 ("radv/rq: Use the common traversal helper")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19698>