Felipe Clark [Mon, 28 Sep 2020 15:03:38 +0000 (11:03 -0400)]
drm/amd/display: Fix max brightness pixel accuracy
[WHY]
It was detected in some Freesync HDR tests that displays were not
reaching their maximum nominal brightness.
[HOW]
The Multi-plane combiner (MPC) Output Gamma (OGAM) block builds a
discrete Lookup Table (LUT). When the display's maximum brightness
falls in between two values, having to be linearly interpolated by
the hardware, rounding issues might occur that will cause the
display to never reach its maximum brightness.
The fix involves doing the calculations backwards, ensuring that
the interpolation in the maximum brightness values translates to an
output of 1.0.
Signed-off-by: Felipe Clark <felclark@amd.com>
Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Aric Cyr [Thu, 8 Oct 2020 13:25:29 +0000 (09:25 -0400)]
drm/amd/display: Don't trigger flip twice when ODM combine in use
[Why]
When ODM combine is in use we trigger multiple update events causing
issues with variable refresh rate.
[How]
Only trigger on a single ODM instance.
Signed-off-by: Aric Cyr <aric.cyr@amd.com>
Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alvin Lee [Thu, 8 Oct 2020 17:32:35 +0000 (13:32 -0400)]
drm/amd/display: Update GSL state if leaving immediate flip
[Why]
We should leave GSL if we're not doing immediate flip no matter if
we're doing pipe split or not
[How]
Check for updating GSL state whenever we're not doing
immediate flip
v2: Squash in build fix (Alex)
Signed-off-by: Aric Cyr <aric.cyr@amd.com>
Signed-off-by: Alvin Lee <alvin.lee2@amd.com>
Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Yu-Ting Shen [Tue, 6 Oct 2020 05:36:56 +0000 (13:36 +0800)]
drm/amd/display: disable seamless boot for VSC_SDP
[WHY]
VBIOS will not enable VSC_SDP during pre-OS to lead
MISC1[6] wasn't matched with driver.
[HOW]
disabled seamless boot if sink supports VSC_SDP
Signed-off-by: Yu-Ting Shen <Yu-ting.Shen@amd.com>
Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Yongqiang Sun [Wed, 7 Oct 2020 16:02:16 +0000 (12:02 -0400)]
drm/amd/display: Reduce height of visual confirm on right side.
[Why]
right side visual confirm is too thick due to it is 4 times of
left side (16 lines).
[How]
Change factor from 4 to 2.
Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Isabel Zhang [Tue, 6 Oct 2020 21:34:40 +0000 (17:34 -0400)]
drm/amd/display: Revert check for flip pending before locking pipes
[Why]
Causes underflow regression
[How]
This reverts commit
99d1437aa0ac1f598e9aabca8bf0e8a40c38f8a1
Signed-off-by: Isabel Zhang <isabel.zhang@amd.com>
Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Brandon Syu [Tue, 6 Oct 2020 02:15:05 +0000 (10:15 +0800)]
drm/amd/display: skip avmute action
[Why]
For some monitors,
they can't display under BIOS with avmute enabled.
[How]
Add monitor patch for skip avmute action.
Signed-off-by: Brandon Syu <Brandon.Syu@amd.com>
Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Roman Li [Mon, 5 Oct 2020 15:28:30 +0000 (11:28 -0400)]
drm/amd/display: Refactor ABM_MASK_SH_LIST_DCN301 naming
[Why]
All DCN3x resources share ABM_MASK_SH_LIST_DCN301 definition.
The naming is misleading since it looks like DCN30 code
depends on next version DCN301, which in fact is vice-versa.
[How]
Refactor the naming to ABM_MASK_SH_LIST_DCN30.
v2: squash in build fixes (Alex)
Signed-off-by: Roman Li <roman.li@amd.com>
Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Martin Leung [Fri, 2 Oct 2020 19:50:36 +0000 (15:50 -0400)]
drm/amd/display: adding reading OEM init_data to dcn3
why:
missing OEM data to control graphics card functions
how:
load it into init_data. copied over from dcn2 implementation.
copied destruction sequence as well.
Signed-off-by: Martin Leung <martin.leung@amd.com>
Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Sung Lee [Mon, 5 Oct 2020 16:14:31 +0000 (12:14 -0400)]
drm/amd/display: DCN2.1 Disable 48MHz Powerdown Debug Option
[WHY & HOW]
Currently disable 48mhz debug option only disables on boot.
Need to put option check in update_clocks as well to make it
affect more areas.
Signed-off-by: Sung Lee <sung.lee@amd.com>
Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Aric Cyr [Mon, 5 Oct 2020 14:16:32 +0000 (10:16 -0400)]
drm/amd/display: 3.2.107
Signed-off-by: Aric Cyr <aric.cyr@amd.com>
Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Nikola Cornij [Sat, 3 Oct 2020 04:21:50 +0000 (00:21 -0400)]
drm/amd/display: Add an option to limit max DSC target bpp per sink
[Why] Can be used for debug purposes
[How] Add max target bpp override field and related handling
Signed-off-by: Nikola Cornij <nikola.cornij@amd.com>
Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Anthony Koo [Mon, 5 Oct 2020 12:52:25 +0000 (08:52 -0400)]
drm/amd/display: [FW Promotion] Release 0.0.37
| [Header Changes]
| - Add GPINT to change timestamping mode for traces
Signed-off-by: Anthony Koo <Anthony.Koo@amd.com>
Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Reza Amini [Thu, 1 Oct 2020 15:33:51 +0000 (11:33 -0400)]
drm/amd/display: Define PSR ERROR Status bit VSC_SDP
[why]
So we can track VSC SDP errors from display
[how]
Define the bit, and use it in driver logic
Signed-off-by: Reza Amini <Reza.Amini@amd.com>
Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Taimur Hassan [Sun, 4 Oct 2020 19:20:45 +0000 (15:20 -0400)]
drm/amd/display: Raise DPG height during timing synchronization
[Why]
Underflow counter increases in AGM when performing some mode switches due
to timing sync, which is a known hardware issue.
[How]
Temporarily raise DPG height during timing sync so that underflow is not
reported.
Signed-off-by: Taimur Hassan <syed.hassan@amd.com>
Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alvin Lee [Fri, 2 Oct 2020 21:53:35 +0000 (17:53 -0400)]
drm/amd/display: Set WM set A to 0 if full pstate not supported
[Why]
If full pstate is not supported, we should set WM set A
to 0 to prevent any hangs
[How]
If pstate is not supported, set watermark set A to 0
Signed-off-by: Alvin Lee <alvin.lee2@amd.com>
Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Eryk Brol [Thu, 1 Oct 2020 17:35:42 +0000 (13:35 -0400)]
drm/amd/display: Reverting "Add connector to the state if DSC debugfs is set"
This reverts commit
c44a22b3128d143a66421004b728eed688c21ee6.
Reason for revert: Patch introduces performance issues and might
cause memory consistency problems with multiple connectors.
Signed-off-by: Eryk Brol <eryk.brol@amd.com>
Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Ashley Thomas [Thu, 1 Oct 2020 07:16:05 +0000 (00:16 -0700)]
drm/amd/display: Source minimum HBlank support
[Why]
Some sink devices wish to have access to the minimum
HBlank supported by the ASIC.
[How]
Make the ASIC minimum HBlank available in Source
Device information address 0x340.
Signed-off-by: Ashley Thomas <Ashley.Thomas2@amd.com>
Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Dmytro Laktyushkin [Wed, 16 Sep 2020 13:20:23 +0000 (09:20 -0400)]
drm/amd/display: enable odm + full screen mpo on dcn21
[WHY & HOW]
Enable ODM Combine + Fullscreen MPO on DCN2.1
For lower power consumption in video use cases.
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Signed-off-by: Sung Lee <sung.lee@amd.com>
Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Dmytro Laktyushkin [Fri, 18 Sep 2020 19:05:09 +0000 (15:05 -0400)]
drm/amd/display: add dcn21 bw validation
[Why&How]
Create a separate dcn21_fast_validate_bw function for dcn21.
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Sung Lee [Tue, 25 Aug 2020 19:52:17 +0000 (15:52 -0400)]
drm/amd/display: Add Bounding Box State for Low DF PState but High Voltage State
[WHY]
DF PState and Voltage State are coupled such that one cannot be
raised without raising the other. This uses more power than
is necessary in high bandwidth scenarios.
[HOW]
Add logic to create a new bounding box state that allows for
DF PState to be low while Voltage State is high. Watermarks
vlevel calculation logic was also udpated to assume
state 1 contains the new optimized state.
Signed-off-by: Sung Lee <sung.lee@amd.com>
Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Mon, 12 Oct 2020 13:40:04 +0000 (15:40 +0200)]
drm/amdgpu: nuke amdgpu_vm_bo_split_mapping v2
Merge the functionality mostly into amdgpu_vm_bo_update_mapping.
This way we can even handle small contiguous system pages without
to much extra CPU overhead.
v2: fix typo, keep the cursor as it is for now
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Madhav Chauhan <madhav.chauhan@amd.com> (v1)
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Mon, 12 Oct 2020 11:09:36 +0000 (13:09 +0200)]
drm/amdgpu: increase the reserved VM size to 2MB
Ideally this should be a multiple of the VM block size.
2MB should at least fit for Vega/Navi.
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Madhav Chauhan <madhav.chauhan@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Tao Zhou [Tue, 20 Oct 2020 08:47:10 +0000 (16:47 +0800)]
drm/amd/pm: update driver if version for dimgrey_cavefish
Per PMFW 59.9.0.
Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
John Clements [Mon, 26 Oct 2020 06:57:13 +0000 (14:57 +0800)]
drm/amdgpu: added support for psp fw attestation
loaded fw can be queried from sys fs interface
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: John Clements <john.clements@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Xiaomeng Hou [Fri, 23 Oct 2020 07:39:53 +0000 (15:39 +0800)]
drm/amdgpu: enable IP discovery for vangogh
enable IP discovery for vangogh.
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Xiaomeng Hou <Xiaomeng.Hou@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
David Galiffi [Wed, 29 Apr 2020 17:31:12 +0000 (13:31 -0400)]
drm/amd/display: Fixed panic during seamless boot.
[why]
get_pixel_clk_frequency_100hz is undefined in clock_source_funcs.
[how]
set function pointer: ".get_pixel_clk_frequency_100hz = get_pixel_clk_frequency_100hz"
Signed-off-by: David Galiffi <David.Galiffi@amd.com>
Reviewed-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
xinhui pan [Fri, 23 Oct 2020 05:41:12 +0000 (13:41 +0800)]
drm/amdgpu: Fix size calculation when init onchip memory
Size is page count here.
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: xinhui pan <xinhui.pan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Mauro Carvalho Chehab [Fri, 23 Oct 2020 16:32:49 +0000 (18:32 +0200)]
drm/amdgpu_dm: fix a typo
dm_comressor_info -> dm_compressor_info
The kernel-doc markup is right, but the struct itself
and their references contain a typo.
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Mauro Carvalho Chehab [Fri, 23 Oct 2020 16:32:58 +0000 (18:32 +0200)]
drm/amdgpu: fix some kernel-doc markups
Some functions have different names between their prototypes
and the kernel-doc markup.
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Mauro Carvalho Chehab [Fri, 23 Oct 2020 16:32:50 +0000 (18:32 +0200)]
amdgpu: fix a few kernel-doc markup issues
A kernel-doc markup can't be mixed with a random comment,
as it causes parsing problems.
While here, change an invalid kernel-doc markup into
a common comment.
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Harish Kasiviswanathan [Thu, 22 Oct 2020 13:57:54 +0000 (09:57 -0400)]
drm/amdgpu: During compute disable GFXOFF for Sienna_Cichlid
Workaround to fix the soft hang observed in certain compute
applications.
Acked-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Madhav Chauhan [Fri, 16 Oct 2020 12:33:07 +0000 (18:03 +0530)]
drm/amdgpu: don't map BO in reserved region
2MB area is reserved at top inside VM.
Suggested-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Madhav Chauhan <madhav.chauhan@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Bhawanpreet Lakha [Fri, 29 May 2020 19:27:06 +0000 (15:27 -0400)]
drm/amdgpu/display: add MALL support (v2)
Enable Memory Access at Last Level (MALL) feature for display.
v2: squash in 64 bit division fixes
Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Likun Gao [Fri, 1 May 2020 20:24:33 +0000 (16:24 -0400)]
drm/amdgpu: add support to configure MALL for sienna_cichlid (v2)
Enable Memory Access at Last Level (MALL) feature for sienna_cichlid.
v2: drop module option. We need to add UAPI so userspace can
request MALL per buffer.
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Fri, 1 May 2020 20:41:41 +0000 (16:41 -0400)]
drm/amdgpu: add GC 10.3 NOALLOC registers
This adds the NOALLOC registers.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Tom Rix [Mon, 19 Oct 2020 14:43:11 +0000 (07:43 -0700)]
drm/amdgpu: remove unneeded break
A break is not needed if it is preceded by a return or break
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Tom Rix <trix@redhat.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Tianci.Yin [Wed, 14 Oct 2020 09:05:50 +0000 (17:05 +0800)]
drm/amdgpu: add DID for navi10 blockchain SKU
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Guchun Chen <guchun.chen@amd.com>
Signed-off-by: Tianci.Yin <tianci.yin@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Tianci.Yin [Thu, 22 Oct 2020 03:40:26 +0000 (11:40 +0800)]
drm/amdgpu: disable DCN and VCN for navi10 blockchain SKU(v3)
The blockchain SKU has no display and video support, remove them.
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Tianci.Yin <tianci.yin@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Likun Gao [Wed, 21 Oct 2020 16:50:07 +0000 (00:50 +0800)]
drm/amdgpu: correct the cu and rb info for sienna cichlid
Skip disabled sa to correct the cu_info and active_rbs for sienna cichlid.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Kenneth Feng [Wed, 21 Oct 2020 09:30:02 +0000 (17:30 +0800)]
drm/amd/pm: remove the average clock value in sysfs
if it's fine-grained clock dpm, remove the average clock value and
reflects the real clock.
Signed-off-by: Kenneth Feng <kenneth.feng@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Mauro Carvalho Chehab [Wed, 21 Oct 2020 12:17:22 +0000 (14:17 +0200)]
drm: amdgpu: kernel-doc: update some adev parameters
Running "make htmldocs: produce lots of warnings on those files:
./drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c:177: warning: Excess function parameter 'man' description in 'amdgpu_vram_mgr_init'
./drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c:177: warning: Excess function parameter 'p_size' description in 'amdgpu_vram_mgr_init'
./drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c:211: warning: Excess function parameter 'man' description in 'amdgpu_vram_mgr_fini'
./drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c:177: warning: Excess function parameter 'man' description in 'amdgpu_vram_mgr_init'
./drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c:177: warning: Excess function parameter 'p_size' description in 'amdgpu_vram_mgr_init'
./drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c:211: warning: Excess function parameter 'man' description in 'amdgpu_vram_mgr_fini'
./drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c:177: warning: Excess function parameter 'man' description in 'amdgpu_vram_mgr_init'
./drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c:177: warning: Excess function parameter 'p_size' description in 'amdgpu_vram_mgr_init'
./drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c:211: warning: Excess function parameter 'man' description in 'amdgpu_vram_mgr_fini'
./drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c:177: warning: Excess function parameter 'man' description in 'amdgpu_vram_mgr_init'
./drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c:177: warning: Excess function parameter 'p_size' description in 'amdgpu_vram_mgr_init'
./drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c:211: warning: Excess function parameter 'man' description in 'amdgpu_vram_mgr_fini'
./drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c:90: warning: Excess function parameter 'man' description in 'amdgpu_gtt_mgr_init'
./drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c:90: warning: Excess function parameter 'p_size' description in 'amdgpu_gtt_mgr_init'
./drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c:134: warning: Excess function parameter 'man' description in 'amdgpu_gtt_mgr_fini'
./drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c:90: warning: Excess function parameter 'man' description in 'amdgpu_gtt_mgr_init'
./drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c:90: warning: Excess function parameter 'p_size' description in 'amdgpu_gtt_mgr_init'
./drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c:134: warning: Excess function parameter 'man' description in 'amdgpu_gtt_mgr_fini'
./drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:675: warning: Excess function parameter 'dev' description in 'amdgpu_device_asic_init'
./drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:675: warning: Excess function parameter 'dev' description in 'amdgpu_device_asic_init'
./drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:675: warning: Excess function parameter 'dev' description in 'amdgpu_device_asic_init'
./drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:675: warning: Excess function parameter 'dev' description in 'amdgpu_device_asic_init'
They're related to the repacement of some parameters by adev,
and due to a few renamed parameters.
While here, uniform the name of the parameter for it to be
the same on all functions using a pointer to struct amdgpu_device.
Update the kernel-doc documentation accordingly.
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Sumera Priyadarsini [Wed, 21 Oct 2020 18:26:10 +0000 (23:56 +0530)]
drm/amdgpu: Return boolean types instead of integer values
Return statements for functions returning bool should use truth
and false instead of 1 and 0 respectively.
Modify cik_event_interrupt.c to return false instead of 0.
Issue found with Coccinelle.
Signed-off-by: Sumera Priyadarsini <sylphrenadin@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Yifan Zhang [Tue, 20 Oct 2020 06:40:16 +0000 (14:40 +0800)]
drm/amd/display: Fix the display corruption issue on Navi10
[Why]
Screen corruption on Navi10 card
[How]
Set system context in DCN only on Renoir
Tested-by: Matt Coffin <mcoffin13@gmail.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com>
Reviewed-by: Roman Li <Roman.Li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Kenneth Feng [Wed, 21 Oct 2020 08:15:47 +0000 (16:15 +0800)]
drm/amd/pm: fix pp_dpm_fclk
fclk value is missing in pp_dpm_fclk. add this to correctly show the current value.
Signed-off-by: Kenneth Feng <kenneth.feng@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
John Clements [Wed, 21 Oct 2020 08:20:42 +0000 (16:20 +0800)]
Revert drm/amdgpu: disable sienna chichlid UMC RAS
This reverts commit
265c280a4807419249644156654e5c40a235ea84.
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: John Clements <john.clements@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Kenneth Feng [Wed, 21 Oct 2020 06:03:08 +0000 (14:03 +0800)]
drm/amd/pm: fix the wrong fan speed in fan1_input
fix the wrong fan speed in fan1_input when the fan control mode is manual.
the fan speed value is not correct when we set manual mode to fan1_enalbe - 1.
since the fan speed in the metrics table always reflects the real fan speed,we
can fetch the fan speed for both auto and manual mode.
Signed-off-by: Kenneth Feng <kenneth.feng@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Bas Nieuwenhuizen [Tue, 20 Oct 2020 22:31:13 +0000 (00:31 +0200)]
drm/amd/display: Initialize num_pkrs on VANGOGH.
As far a I can tell uses a variant of DCN3xx which uses num_pkrs.
If we do not initialize the variable we will set the register field
to ilog2(0) = -1, though the mask will reduce that to 7. Pretty sure
7 is not the value we want here.
Signed-off-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-and-Tested-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Likun Gao [Tue, 20 Oct 2020 08:50:03 +0000 (16:50 +0800)]
drm/amd/pm: update driver if file for sienna cichlid
Update driver if file for sienna cichlid.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Likun Gao [Tue, 20 Oct 2020 08:29:30 +0000 (16:29 +0800)]
drm/amd/pm: fix pcie information for sienna cichlid
Fix the function used for sienna cichlid to get correct PCIE information
by pp_dpm_pcie.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Fri, 16 Oct 2020 16:56:26 +0000 (12:56 -0400)]
drm/amdgpu/gmc10: remove dummy read workaround for newer chips
Sienna Cichlid and newer have a hw fix so no longer require
the workaround.
Reviewed-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Chengming Gui [Tue, 20 Oct 2020 02:54:23 +0000 (10:54 +0800)]
drm/amd/amdgpu: enable noretry for Sienna_Cichlid/Navy_Flounder/Dimgrey_Cavefish
set noretry default value to 1 for
sienna_cichlid/navy_founder/dimgrey_cavefish.
Signed-off-by: Chengming Gui <Jack.Gui@amd.com>
Reviewed-by: Guchun Chen <guchun.chen@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Boyuan Zhang [Fri, 16 Oct 2020 22:19:15 +0000 (18:19 -0400)]
drm/amdgpu: enable VCN PG and CG for vangogh
Enable VCN 3.0 PG and CG for Vangogh by setting up flags.
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jay Cornwall [Sat, 17 Oct 2020 13:38:43 +0000 (08:38 -0500)]
drm/amdkfd: Use same SQ prefetch setting as amdgpu
0 causes instruction fetch stall at cache line boundary under some
conditions on Navi10. A non-zero prefetch is the preferred default
in any case.
Fixes soft hang in Luxmark.
Signed-off-by: Jay Cornwall <jay.cornwall@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Kevin Wang [Fri, 16 Oct 2020 08:59:25 +0000 (16:59 +0800)]
drm/amd/swsmu: correct wrong feature bit mapping
1. when smc feature bit isn't mapped,
the feature state isn't showed on sysfs node of pp_features.
2. add pp_features table title
Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Dennis Li [Wed, 14 Oct 2020 09:11:41 +0000 (17:11 +0800)]
drm/amdgpu: protect eeprom update from GPU reset
because i2c is unstable in GPU reset, driver need protect
eeprom update from GPU reset, to not miss any bad page record.
Signed-off-by: Dennis Li <Dennis.Li@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Fri, 16 Oct 2020 14:02:56 +0000 (10:02 -0400)]
drm/amdgpu: move amdgpu_num_kcq handling to a helper
Add a helper so we can set per asic default values. Also,
the module parameter is currently clamped to 8, but clamp it
per asic just in case some asics have different limits in the
future. Enable the option on gfx6,7 as well for consistency.
Acked-by: Nirmoy Das <nirmoy.das@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Andrey Grodzovsky [Fri, 16 Oct 2020 14:50:44 +0000 (10:50 -0400)]
drm/amd/psp: Fix sysfs: cannot create duplicate filename
psp sysfs not cleaned up on driver unload for sienna_cichlid
Fixes:
ce87c98db428e7 ("drm/amdgpu: Include sienna_cichlid in USBC PD FW support.")
Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Bhawanpreet Lakha [Thu, 15 Oct 2020 17:32:31 +0000 (13:32 -0400)]
drm/amd/display: Fix DCN302 makefile
Some setups will fail to build. So copy dcn301 makefile setup
which is known to work
Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Bhawanpreet Lakha [Thu, 15 Oct 2020 14:50:18 +0000 (10:50 -0400)]
drm/amd/display: Use amdgpu_socbb.h instead of redefining structs
Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Andrey Grodzovsky [Wed, 14 Oct 2020 17:12:30 +0000 (13:12 -0400)]
drm/amd/display: Avoid MST manager resource leak.
On connector destruction call drm_dp_mst_topology_mgr_destroy
to release resources allocated in drm_dp_mst_topology_mgr_init.
Do it only if MST manager was initilized before otherwsie a crash
is seen on driver unload/device unplug.
Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Andrey Grodzovsky [Wed, 14 Oct 2020 17:10:06 +0000 (13:10 -0400)]
drm/amd/display: Revert "drm/amd/display: Fix a list corruption"
This fixes regression on device unplug and/or driver unload.
[ 65.681501 < 0.000004>] BUG: kernel NULL pointer dereference, address:
0000000000000008
[ 65.681504 < 0.000003>] #PF: supervisor write access in kernel mode
[ 65.681506 < 0.000002>] #PF: error_code(0x0002) - not-present page
[ 65.681507 < 0.000001>] PGD
7c9437067 P4D
7c9437067 PUD
7c9db7067 PMD 0
[ 65.681511 < 0.000004>] Oops: 0002 [#1] SMP NOPTI
[ 65.681512 < 0.000001>] CPU: 8 PID: 127 Comm: kworker/8:1 Tainted: G W O 5.9.0-rc2-dev+ #59
[ 65.681514 < 0.000002>] Hardware name: System manufacturer System Product Name/PRIME X470-PRO, BIOS 4406 02/28/2019
[ 65.681525 < 0.000011>] Workqueue: events drm_connector_free_work_fn [drm]
[ 65.681535 < 0.000010>] RIP: 0010:drm_atomic_private_obj_fini+0x11/0x60 [drm]
[ 65.681537 < 0.000002>] Code: de 4c 89 e7 e8 70 f2 ba f8 48 8d 65 d8 5b 41 5c 41 5d 41 5e 41 5f 5d c3 90 0f 1f 44 00 00 48 8b 47 08 48 8b 17 55 48 89 e5 53 <48> 89 42 08 48 89 10 48 b8 00 01 00 00 00 00 ad de 48 89 fb 48 89
[ 65.681541 < 0.000004>] RSP: 0018:
ffffa5fa805efdd8 EFLAGS:
00010246
[ 65.681542 < 0.000001>] RAX:
0000000000000000 RBX:
ffff9a4b094654d8 RCX:
0000000000000000
[ 65.681544 < 0.000002>] RDX:
0000000000000000 RSI:
ffffffffba197bc2 RDI:
ffff9a4b094654d8
[ 65.681545 < 0.000001>] RBP:
ffffa5fa805efde0 R08:
ffffffffba197b82 R09:
0000000000000040
[ 65.681547 < 0.000002>] R10:
ffffa5fa805efdc8 R11:
000000000000007f R12:
ffff9a4b09465888
[ 65.681549 < 0.000002>] R13:
ffff9a4b36f20010 R14:
ffff9a4b36f20290 R15:
ffff9a4b3a692840
[ 65.681551 < 0.000002>] FS:
0000000000000000(0000) GS:
ffff9a4b3ea00000(0000) knlGS:
0000000000000000
[ 65.681553 < 0.000002>] CS: 0010 DS: 0000 ES: 0000 CR0:
0000000080050033
[ 65.681554 < 0.000001>] CR2:
0000000000000008 CR3:
00000007c9c82000 CR4:
00000000003506e0
[ 65.681556 < 0.000002>] Call Trace:
[ 65.681561 < 0.000005>] drm_dp_mst_topology_mgr_destroy+0xc4/0xe0 [drm_kms_helper]
[ 65.681612 < 0.000051>] amdgpu_dm_connector_destroy+0x3d/0x110 [amdgpu]
[ 65.681622 < 0.000010>] drm_connector_free_work_fn+0x78/0x90 [drm]
[ 65.681624 < 0.000002>] process_one_work+0x164/0x410
[ 65.681626 < 0.000002>] worker_thread+0x4d/0x450
[ 65.681628 < 0.000002>] ? rescuer_thread+0x390/0x390
[ 65.681630 < 0.000002>] kthread+0x10a/0x140
[ 65.681632 < 0.000002>] ? kthread_unpark+0x70/0x70
[ 65.681634 < 0.000002>] ret_from_fork+0x22/0x30
This reverts commit
1545fbf97eafc1dbdc2923e58b4186b16a834784.
Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jiansong Chen [Fri, 16 Oct 2020 12:43:06 +0000 (20:43 +0800)]
drm/amd/pm: drop navy_flounder hardcode of using soft pptable
Drop navy_flounder hardcode of using soft pptable, so that it
can use pptable from vbios when available.
Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Mihir Bhogilal Patel [Thu, 15 Oct 2020 12:27:26 +0000 (17:57 +0530)]
drm/amdgpu: add a list in VM for BOs in the done state
Add a new list in VM for done state i.e. BOs which are
invalidated and updated in PTEs.
Signed-off-by: Mihir Bhogilal Patel <Mihir.Patel@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Likun Gao [Thu, 15 Oct 2020 02:48:15 +0000 (10:48 +0800)]
drm/amdgpu: update golden setting for sienna_cichlid
Update golden setting for sienna_cichlid.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Kevin Wang [Fri, 16 Oct 2020 03:07:47 +0000 (11:07 +0800)]
drm/amd/swsmu: add missing feature map for sienna_cichlid
it will cause smu sysfs node of "pp_features" show error.
Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Kevin Wang [Wed, 14 Oct 2020 12:09:57 +0000 (20:09 +0800)]
drm/amdgpu: remove gfxhub_v1_1_funcs set
remove duplicate gfxhub v1.1 function set.
put function of gfxhub_v1_1_get_xgmi_info to gfxhub v1_0 function set.
Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Chengming Gui [Tue, 13 Oct 2020 04:18:27 +0000 (12:18 +0800)]
drm/amd/amdgpu: set the default value of noretry to 1 for some dGPUs
noretry = 0 cause some dGPU's kfd page fault tests fail,
so set noretry to 1 for these special ASICs:
vega20/navi10/navi14
v2: merge raven and default case due to the same setting
v3: remove ARCTURUS
Signed-off-by: Chengming Gui <Jack.Gui@amd.com>
Acked-by: Felix Kuhling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Huang Rui [Thu, 15 Oct 2020 02:59:40 +0000 (10:59 +0800)]
drm/amdgpu/display: enable display ip block for vangogh
This patch is to enable display IP block for vangogh platforms.
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Huang Rui [Thu, 15 Oct 2020 07:12:23 +0000 (15:12 +0800)]
drm/amdgpu/display: fix the NULL pointer reference on dmucb on dcn301
DCN301 needs to use dmub create abm instance instead of dce.
[ 1138.854204] BUG: kernel NULL pointer dereference, address:
0000000000000000
[ 1138.854206] #PF: supervisor instruction fetch in kernel mode
[ 1138.854207] #PF: error_code(0x0010) - not-present page
[ 1138.854208] PGD 0 P4D 0
[ 1138.854212] Oops: 0010 [#1] SMP NOPTI
[ 1138.854216] CPU: 6 PID: 1240 Comm: modprobe Tainted: G W OE 5.9.0-rc2-custom #1
[ 1138.854217] Hardware name: AMD Chachani-VN/Chachani-VN, BIOS BAerithA104 10/01/2020
[ 1138.854221] RIP: 0010:0x0
[ 1138.854224] Code: Bad RIP value.
[ 1138.854226] RSP: 0018:
ffffc90001c4f638 EFLAGS:
00010286
[ 1138.854228] RAX:
0000000000000000 RBX:
ffff88804f2b2800 RCX:
ffffc90001c4f740
[ 1138.854229] RDX:
00000000000000e8 RSI:
ffffc90001c4f640 RDI:
ffff88805816f300
[ 1138.854230] RBP:
ffffc90001c4f850 R08:
ffffc90001c4f644 R09:
ffffc90001c4f654
[ 1138.854231] R10:
ffffc90001c4f72c R11:
ffffc90001c4f740 R12:
ffffc90001c4f640
[ 1138.854232] R13:
ffffc90001c4f728 R14:
0000000000000000 R15:
ffff888007296381
[ 1138.854235] FS:
00007f5f44d84540(0000) GS:
ffff88805e380000(0000) knlGS:
0000000000000000
[ 1138.854236] CS: 0010 DS: 0000 ES: 0000 CR0:
0000000080050033
[ 1138.854237] CR2:
ffffffffffffffd6 CR3:
00000000194f4000 CR4:
0000000000050ee0
[ 1138.854239] Call Trace:
[ 1138.854447] dmub_init_abm_config+0x220/0x267 [amdgpu]
[ 1138.854654] dm_late_init+0x197/0x1ad [amdgpu]
[ 1138.854846] ? dm_late_init+0x197/0x1ad [amdgpu]
[ 1138.854999] amdgpu_device_ip_late_init+0x6f/0x21b [amdgpu]
[ 1138.855148] amdgpu_device_init+0x1b7f/0x1cfb [amdgpu]
[ 1138.855293] amdgpu_driver_load_kms+0x2c/0x26e [amdgpu]
[ 1138.855437] amdgpu_pci_probe+0x1c7/0x249 [amdgpu]
[ 1138.920489] local_pci_probe+0x48/0x80
[ 1138.920492] pci_device_probe+0x10f/0x1c0
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Yifan Zhang [Fri, 17 Jul 2020 08:28:46 +0000 (16:28 +0800)]
drm/amd/display: add S/G support for Renoir
S/G (scatter/gather) display support for display
buffers in system memory.
Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com>
Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Yifan Zhang [Mon, 31 Aug 2020 07:56:24 +0000 (15:56 +0800)]
drm/amd/display: setup system context in dm_init
[why]
display S/G mode fails in Renoir
[how]
Setup system context in dm init.
Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com>
Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Mihir Bhogilal Patel [Thu, 8 Oct 2020 10:16:38 +0000 (15:46 +0530)]
drm/amdgpu: Add debugfs entry for printing VM info
Create new debugfs entry to print memory info using VM buffer
objects.
V2: Added Common function for printing BO info.
Dump more VM lists for evicted, moved, relocated, invalidated.
Removed dumping VM mapped BOs.
V3: Fixed coding style comments, renamed print API and variables.
V4: Fixed coding style comments.
Signed-off-by: Mihir Bhogilal Patel <Mihir.Patel@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Thu, 15 Oct 2020 06:57:46 +0000 (14:57 +0800)]
drm/amdgpu: correct the gpu reset handling for job != NULL case
Current code wrongly treat all cases as job == NULL.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-and-tested-by: Jane Jian <Jane.Jian@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Likun Gao [Wed, 30 Sep 2020 06:34:08 +0000 (14:34 +0800)]
drm/amdgpu: add rlc iram and dram firmware support
Support to load RLC iram and dram ucode when RLC firmware struct use v2.2
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Likun Gao [Wed, 14 Oct 2020 06:05:18 +0000 (14:05 +0800)]
drm/amdgpu: add function to program pbb mode for sienna cichlid
Add function for sienna_cichlid to force PBB workload mode to zero by
checking whether there have SE been harvested.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jiansong Chen [Thu, 15 Oct 2020 02:42:58 +0000 (10:42 +0800)]
Revert "drm/amdgpu: disable gfxoff temporarily for navy_flounder"
This reverts commit
39ad082459373facaa255b0791595d018597a164.
TDR issue has been resovled by pmfw update.
Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Tue, 13 Oct 2020 06:17:29 +0000 (14:17 +0800)]
drm/amd/pm: properly setting GPO feature on UMD pstate entering/exiting
Disable/enable the GPO feature on UMD pstate entering/exiting.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Tue, 18 Aug 2020 09:58:06 +0000 (17:58 +0800)]
drm/amdgpu: fulfill Navi gfx and pcie settings on umd pstate switching(V2)
Fulfill Navi gfx and pcie settings on umd pstate switching.
V2: temporarily skip the pcie ASPM setting considering the ASPM function
is not fully enabled yet
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Tue, 18 Aug 2020 09:10:48 +0000 (17:10 +0800)]
drm/amdgpu: add interface for setting MGCG perfmon
Enable Navi1X MGCG perfmon setting.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Tue, 18 Aug 2020 08:50:44 +0000 (16:50 +0800)]
drm/amdgpu: add interface for setting ASPM
Support NAVI10 ASPM setting.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Tue, 18 Aug 2020 04:43:25 +0000 (12:43 +0800)]
drm/amd/pm: correct gfx and pcie settings on umd pstate switching(V2)
For entering UMD stable Pstate, the operations to enter rlc_safe
mode, disable mgcg_perfmon and disable PCIE aspm are needed. And
the opposite operations should be performed on UMD stable Pstate
exiting.
V2: take those ASICs(CI/SI/VI) which may not support this into
consideration
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Sat, 10 Oct 2020 01:58:41 +0000 (09:58 +0800)]
drm/amd/pm: populate Arcturus PCIE link state
Populate current link speed, width and clock domain frequency.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Sat, 10 Oct 2020 01:36:02 +0000 (09:36 +0800)]
drm/amd/pm: populate the bootup LCLK frequency
As for other clock domains.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Huang Rui [Wed, 14 Oct 2020 14:12:02 +0000 (22:12 +0800)]
drm/amdgpu: disable gpa mode for direct loading
This patch fixes the gfx hang while use firmware direct loading mode.
Signed-off-by: Huang Rui <ray.huang@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Tom Rix [Wed, 14 Oct 2020 21:18:06 +0000 (14:18 -0700)]
drm/amdgpu: add missing newline at eof
Representative checkpatch.pl warning
WARNING: adding a line without newline at end of file
30: FILE: drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.h:30:
+#endif
Signed-off-by: Tom Rix <trix@redhat.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Wed, 14 Oct 2020 17:39:39 +0000 (13:39 -0400)]
drm/amdgpu/display: DRM_AMD_DC_DCN3_02 depends on DRM_AMD_DC_DCN3_01
Fix this to avoid build problems if DRM_AMD_DC_DCN3_02 is defined, but
DRM_AMD_DC_DCN3_01 is not.
Fixes:
36d26912e8d854 ("drm/amd/display: Add support for DCN302 (v2)")
Acked-by: Nirmoy Das <nirmoy.das@amd.com>
Acked-by: Randy Dunlap <rdunlap@infradead.org>
Reported-by: Randy Dunlap <rdunlap@infradead.org>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Kent Russell [Wed, 14 Oct 2020 11:47:32 +0000 (07:47 -0400)]
drm/amdkfd: Use kvfree in destroy_crat_image
Now that we use kvmalloc for the crat_image, we need to use kvfree when
we destroy this.
Fixes:
d0e63b343e575e ("drm/amdkfd: Use kvmalloc instead of kmalloc for VCRAT")
Reported-by: Morris Zhang <shiwu.zhang@amd.clm>
Signed-off-by: Kent Russell <kent.russell@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Veerabadhran G [Thu, 8 Oct 2020 17:00:02 +0000 (22:30 +0530)]
drm/amdgpu: vcn and jpeg ring synchronization
Synchronize the ring usage for vcn1 and jpeg1 to workaround a hardware bug.
Signed-off-by: Veerabadhran Gopalakrishnan <veerabadhran.gopalakrishnan@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Wed, 30 Sep 2020 15:13:28 +0000 (23:13 +0800)]
drm/amdgpu: enable GDDR6 save-restore support for dimgrey_cavefish
add mp0 11_0_12 for dimgrey_cavefish to the mem training
supported list, otherwise the modeprobe would fail
on dimgrey_cavefish with latest vbios.
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Huang Rui [Tue, 13 Oct 2020 11:19:31 +0000 (19:19 +0800)]
drm/amdgpu: fix the issue that apu has no smu firmware binary
The driver needn't load smu binary on APU platforms.
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Madhav Chauhan <madhav.chauhan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Wed, 2 Sep 2020 08:10:10 +0000 (16:10 +0800)]
drm/amd/pm: increase mclk switch threshold to 200 us
To avoid underflow seen on Polaris10 with some 3440x1440
144Hz displays. As the threshold of 190 us cuts too close
to minVBlankTime of 192 us.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Mauro Carvalho Chehab [Tue, 13 Oct 2020 11:54:20 +0000 (13:54 +0200)]
docs: amdgpu: fix a warning when building the documentation
As reported by Sphinx:
Documentation/gpu/amdgpu.rst:200: WARNING: Inline emphasis start-string without end-string.
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Mauro Carvalho Chehab [Tue, 13 Oct 2020 11:54:27 +0000 (13:54 +0200)]
drm/amd/display: kernel-doc: document force_timing_sync
As warned when running "make htmldocs":
./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h:345: warning: Function parameter or member 'force_timing_sync' not described in 'amdgpu_display_manager'
This new struct member was not documented at kernel-doc markup.
Fixes:
3d4e52d0cf24 ("drm/amd/display: Add debugfs for forcing stream timing sync")
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Bernard Zhao [Mon, 12 Oct 2020 11:46:16 +0000 (04:46 -0700)]
drm/amd/display: remove no need return value
Functions (disable_all_writeback_pipes_for_stream &
dc_enable_stereo & dc_post_update_surfaces_to_stream)
always return true, there is no need to keep the return value.
This change is to make the code a bit more readable.
Signed-off-by: Bernard Zhao <bernard@vivo.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
kernel test robot [Mon, 12 Oct 2020 21:20:49 +0000 (05:20 +0800)]
drm/amdgpu: fix semicolon.cocci warnings
drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.c:608:2-3: Unneeded semicolon
Remove unneeded semicolon.
Generated by: scripts/coccinelle/misc/semicolon.cocci
Fixes:
b4a7db71ea06 ("drm/amdgpu: add per device user friendly xgmi events for vega20")
CC: Jonathan Kim <jonathan.kim@amd.com>
Signed-off-by: kernel test robot <lkp@intel.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Mon, 12 Oct 2020 14:12:28 +0000 (10:12 -0400)]
drm/amdgpu/swsmu: init the baco mutex in early_init
GPU reset might get called during init time, before
sw_init has been called.
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Roman Li [Thu, 8 Oct 2020 17:32:47 +0000 (13:32 -0400)]
drm/amd/display: Add green_sardine support to DM
Display Manager support for green_sardine
Signed-off-by: Roman Li <Roman.Li@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Roman Li [Thu, 8 Oct 2020 17:28:41 +0000 (13:28 -0400)]
drm/amd/display: Add green_sardine support to DC
Display Core support for green_sardine
Signed-off-by: Roman Li <Roman.Li@amd.com>
Acked-by: Hersen Wu <hersenxs.wu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Tao Zhou [Sat, 10 Oct 2020 07:45:35 +0000 (15:45 +0800)]
drm/amdgpu: add DM block for dimgrey_cavefish
Add DM block support for dimgrey_cavefish.
Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Jack Gui <Jack.Gui@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>