Kazushi (Jam) Marukawa [Fri, 1 Jul 2022 10:24:33 +0000 (19:24 +0900)]
[VE][NFC] Correct comment
Florian Hahn [Fri, 1 Jul 2022 10:12:00 +0000 (11:12 +0100)]
[LV] Update test for #56319 to use interleave group.
The original test was over-reduced. It requires an interleave group, so
the last vector iteration of the epilogue vector loop doesn't execute.
Valentin Clement [Fri, 1 Jul 2022 10:04:19 +0000 (12:04 +0200)]
[flang] File omp_lib.f90 is not a standard intrinsic module
This patch is part of the upstreaming effort from fir-dev branch.
Reviewed By: jeanPerier
Differential Revision: https://reviews.llvm.org/D128976
Co-authored-by: V Donaldson <vdonaldson@nvidia.com>
Daniel Bertalan [Fri, 1 Jul 2022 09:47:34 +0000 (11:47 +0200)]
[lld-macho] Fix left shift of negative value UB
I introduced this mistake in
573c7e6b3c79c7ce80a2221e000fab7dd20c0bb4.
Fixes the failure on this UBSan bot:
https://lab.llvm.org/buildbot/#/builders/5/builds/25537
Dmitry Preobrazhensky [Fri, 1 Jul 2022 09:34:59 +0000 (12:34 +0300)]
[AMDGPU][GFX908][DOC][NFC] Update assembler syntax description
Summary of changes:
- Remove dst for global_atomic_add_f32, global_atomic_pk_add_f16.
- Make vdata input-only for buffer_atomic_add_f32, buffer_atomic_pk_add_f16.
- Other minor improvements.
Simon Pilgrim [Fri, 1 Jul 2022 09:36:01 +0000 (10:36 +0100)]
Revert rG057db2002bb3: [X86] combineAndnp - constant fold ANDNP(C,X) -> AND(~C,X)
If the LHS op has a single use then using the more general AND op is likely to allow commutation, load folding, generic folds etc.
Reverted due to reports from @alexfh about it causing an infinite loop (repro still pending).
Dmitry Preobrazhensky [Mon, 27 Jun 2022 16:30:44 +0000 (19:30 +0300)]
[AMDGPU][GFX940][DOC][NFC] Update assembler syntax description
Summary of changes:
- Update SMEM syntax (see https://reviews.llvm.org/D127314).
- Minor improvements.
Florian Hahn [Fri, 1 Jul 2022 09:09:23 +0000 (10:09 +0100)]
[LV] Add test case for #56319.
Test case for PR56319.
Nico Weber [Fri, 1 Jul 2022 08:31:35 +0000 (04:31 -0400)]
[gn build] (manually) port
fe66aebd7551 (PseudoCLI)
Nico Weber [Wed, 25 May 2022 12:39:29 +0000 (08:39 -0400)]
[gn build] (manually) port
cd2292ef824 (PseudoCXX)
This target will be used in the next commit.
Christian Kandeler [Fri, 1 Jul 2022 08:43:23 +0000 (04:43 -0400)]
[clangd] Also mark output arguments of array subscript expressions
... with the "usedAsMutableReference" semantic token modifier.
It's quite unusual to declare the index parameter of a subscript
operator as a non-const reference type, but arguably that makes it even
more helpful to be aware of it when working with such code.
Reviewed By: nridge
Differential Revision: https://reviews.llvm.org/D128892
Serge Pavlov [Fri, 1 Jul 2022 08:32:56 +0000 (15:32 +0700)]
Revert "[FPEnv] Allow CompoundStmt to keep FP options"
On some buildbots test `ast-print-fp-pragmas.c` fails, need to investigate it.
This reverts commit
0401fd12d4aa0553347fe34d666fb236d8719173.
This reverts commit
b822efc7404bf09ccfdc1ab7657475026966c3b2.
Valentin Clement [Fri, 1 Jul 2022 08:36:45 +0000 (10:36 +0200)]
[flang] Fix for broken/degenerate forall case
Fix for broken/degenerate forall case where there is no assignment to an
array under the explicit iteration space. While this is a multiple
assignment, semantics only raises a warning.
The fix is to add a test that the explicit space has any sort of array
to be updated, and if not then the do_loop nest will not require a
terminator to forward array values to the next iteration.
This patch is part of the upstreaming effort from fir-dev branch.
Reviewed By: jeanPerier
Differential Revision: https://reviews.llvm.org/D128973
Co-authored-by: Eric Schweitz <eschweitz@nvidia.com>
Mikhail Goncharov [Fri, 1 Jul 2022 08:33:48 +0000 (10:33 +0200)]
[fix/build] bazel rule for ParallelCombiningOpInterface
Muhammad Omair Javaid [Fri, 1 Jul 2022 08:21:27 +0000 (12:21 +0400)]
[LLDB] Xfail TestStepNoDebug.py AArch64/Windows
LLDB fails to step in/out/over code with missing debug information.
This is only reproducible on AArch64/Windows. I have reported a issue
upstream at llvm.org/pr56292
This patch Xfail TestStepNoDebug.py for AArch64/Windows.
Chen Zheng [Wed, 29 Jun 2022 09:07:23 +0000 (05:07 -0400)]
[SCEV] pre-commit test case for D127835, NFC
Serge Pavlov [Fri, 1 Jul 2022 08:17:04 +0000 (15:17 +0700)]
Fix warning on unhandled enumeration value
Valentin Clement [Fri, 1 Jul 2022 08:16:09 +0000 (10:16 +0200)]
[flang] Add correct number of args for wait
Add source coordinates to BeginWait and BeginWaitAll calls
This patch is part of the upstreaming effort from fir-dev branch.
Reviewed By: jeanPerier
Differential Revision: https://reviews.llvm.org/D128970
Co-authored-by: V Donaldson <vdonaldson@nvidia.com>
Chen Zheng [Mon, 27 Jun 2022 13:56:20 +0000 (09:56 -0400)]
[InstructionSimplify] handle denormal input for fcmp
Handle denormal constant input for fcmp instructions based on the
denormal handling mode.
Reviewed By: spatel, dcandler
Differential Revision: https://reviews.llvm.org/D128647
Daniel Bertalan [Thu, 30 Jun 2022 09:01:18 +0000 (11:01 +0200)]
[lld-macho] Handle LOH_ARM64_ADRP_LDR linker optimization hints
This linker optimization hint transforms a pair of adrp+ldr (immediate)
instructions into an ldr (literal) load from a PC-relative address if
it is 4-byte aligned and within +/- 1 MiB, as ldr can encode a signed
19-bit offset that gets multiplied by 4.
In the wild, only a small number of these hints are applicable because
not many loads end up close enough to the data segment. However, the
added helper functions will be useful in implementing the rest of the
LOH types.
Differential Revision: https://reviews.llvm.org/D128942
Serge Pavlov [Mon, 28 Sep 2020 07:32:06 +0000 (14:32 +0700)]
[FPEnv] Allow CompoundStmt to keep FP options
AST does not have special nodes for pragmas. Instead a pragma modifies
some state variables of Sema, which in turn results in modified
attributes of AST nodes. This technique applies to floating point
operations as well. Every AST node that can depend on FP options keeps
current set of them.
This technique works well for options like exception behavior or fast
math options. They represent instructions to the compiler how to modify
code generation for the affected nodes. However treatment of FP control
modes has problems with this technique. Modifying FP control mode
(like rounding direction) usually requires operations on hardware, like
writing to control registers. It must be done prior to the first
operation that depends on the control mode. In particular, such
operations are required for implementation of `pragma STDC FENV_ROUND`,
compiler should set up necessary rounding direction at the beginning of
compound statement where the pragma occurs. As there is no representation
for pragmas in AST, the code generation becomes a complicated task in
this case.
To solve this issue FP options are kept inside CompoundStmt. Unlike to FP
options in expressions, these does not affect any operation on FP values,
but only inform the codegen about the FP options that act in the body of
the statement. As all pragmas that modify FP environment may occurs only
at the start of compound statement or at global level, such solution
works for all relevant pragmas. The options are kept as a difference
from the options in the enclosing compound statement or default options,
it helps codegen to set only changed control modes.
Differential Revision: https://reviews.llvm.org/D123952
Nikita Popov [Wed, 29 Jun 2022 08:48:40 +0000 (10:48 +0200)]
[ConstExpr] Don't create insertvalue expressions
In preparation for the removal in D128719, this stops creating
insertvalue constant expressions (well, unless they are directly
used in LLVM IR).
Differential Revision: https://reviews.llvm.org/D128792
Nicolas Vasilache [Thu, 30 Jun 2022 10:37:21 +0000 (03:37 -0700)]
[mlir][SCF] Add a ParallelCombiningOpInterface to decouple scf::PerformConcurrently from its contained operations
This allows purging references of scf.ForeachThreadOp and scf.PerformConcurrentlyOp from
ParallelInsertSliceOp.
This will allowmoving the op closer to tensor::InsertSliceOp with which it should share much more
code.
In the future, the decoupling will also allow extending the type of ops that can be used in the
parallel combinator as well as semantics related to multiple concurrent inserts to the same
result.
Differential Revision: https://reviews.llvm.org/D128857
Nicolas Vasilache [Wed, 29 Jun 2022 08:59:33 +0000 (01:59 -0700)]
[mlir][vector] Untangle TransferWriteDistribution and avoid crashing in the 0-D case.
This revision avoids a crash in the 0-D case of distributing vector.transfer ops out of
vector.warp_execute_on_lane_0.
Due to the code complexity and lack of documentation, it took untangling the implementation
before realizing that the simple fix was to fail in the 0-D case.
The rewrite is still very useful to understand this code better.
Differential Revision: https://reviews.llvm.org/D128793
Nikita Popov [Tue, 21 Jun 2022 08:34:41 +0000 (10:34 +0200)]
[SCCP] Only handle unknown lattice values in resolvedUndefsIn()
This is a minor refinement of resolvedUndefsIn(), mostly for clarity.
If the value of an instruction is undef, then that's already a legal
final result -- we can safely rauw such an instruction with undef.
We only need to mark unknown values as overdefined, as that's the
result we get for an instruction that has not been processed because
it has an undef operand.
Differential Revision: https://reviews.llvm.org/D128251
Piotr Sobczak [Fri, 1 Jul 2022 06:18:09 +0000 (08:18 +0200)]
[AMDGPU] Add WMMA clang builtins
Add WMMA clang builtins and tests. Extra changes in code
are needed to handle function overloads.
WavefrontSize 32:
__builtin_amdgcn_wmma_f32_16x16x16_f16_w32
__builtin_amdgcn_wmma_f32_16x16x16_bf16_w32
__builtin_amdgcn_wmma_f16_16x16x16_f16_w32
__builtin_amdgcn_wmma_bf16_16x16x16_bf16_w32
__builtin_amdgcn_wmma_i32_16x16x16_iu8_w32
__builtin_amdgcn_wmma_i32_16x16x16_iu4_w32
WavefrontSize 64:
__builtin_amdgcn_wmma_f32_16x16x16_f16_w64
__builtin_amdgcn_wmma_f32_16x16x16_bf16_w64
__builtin_amdgcn_wmma_f16_16x16x16_f16_w64
__builtin_amdgcn_wmma_bf16_16x16x16_bf16_w64
__builtin_amdgcn_wmma_i32_16x16x16_iu8_w64
__builtin_amdgcn_wmma_i32_16x16x16_iu4_w64
Reviewed By: rampitec
Differential Revision: https://reviews.llvm.org/D128952
Piotr Sobczak [Fri, 1 Jul 2022 06:18:03 +0000 (08:18 +0200)]
[AMDGPU] Update WMMA intrinsics with explicit f16 types
Update intrinsics to use n x f16 and n x i16 instead
of 32-bit types. This may avoid the need for a bitcast
and is probably less confusing.
Depends on making v16f16 and v16i16 types legal.
Reviewed By: rampitec
Differential Revision: https://reviews.llvm.org/D128951
Chen Zheng [Fri, 1 Jul 2022 06:36:23 +0000 (02:36 -0400)]
[NFC] add --match-full-lines to the RUN line
Haojian Wu [Tue, 28 Jun 2022 20:37:03 +0000 (22:37 +0200)]
[pseudo] Define a clangPseudoCLI library.
- define a common data structure Language which is a compiled result of the
bnf grammar. It is defined in Language.h;
- creates a clangPseudoCLI lib which defines a grammar commandline flag and
expose a function to get the Language. It supports --grammar=cxx,
--grammmar=/path/to/file.bnf;
- use the clangPseudoCLI in clang-pseudo, fuzzer, and benchmark tools (
simplify the code and use the prebuilt cxx grammar);
Split out from https://reviews.llvm.org/D127448.
Differential Revision: https://reviews.llvm.org/D128679
Valentin Clement [Fri, 1 Jul 2022 06:29:19 +0000 (08:29 +0200)]
[flang] Fix APFloat conversion cases
This patch is part of the upstreaming effort from fir-dev branch.
Reviewed By: PeteSteinfeld
Differential Revision: https://reviews.llvm.org/D128935
Co-authored-by: Eric Schweitz <eschweitz@nvidia.com>
Co-authored-by: Peter Steinfeld <psteinfeld@nvidia.com>
Chen Zheng [Fri, 24 Jun 2022 12:04:06 +0000 (08:04 -0400)]
[Inline] don't add noalias metadata for unknown objects.
The unidentified objects recognized in `getUnderlyingObjects` may
still alias to the noalias parameter because `getUnderlyingObjects`
may not check deep enough to get the underlying object because of
`MaxLookup`. The real underlying object for the unidentified object
may still be the noalias parameter.
Originally Patched By: tingwang
Reviewed By: nikic
Differential Revision: https://reviews.llvm.org/D127202
Pavel Labath [Thu, 21 Apr 2022 08:57:18 +0000 (10:57 +0200)]
[lldb] Add tests which simulate the various std::string layouts
Checking whether a formatter change does not break some of the supported
string layouts is difficult because it requires tracking down and/or
building different versions and build configurations of the library.
The purpose of this patch is to avoid that by providing an in-tree
simulation of the string class. It is a reduced version of the real
string class, obtained by elimitating all non-trivial code, leaving
just the internal data structures used by the data formatter. Different
versions of the class can be simulated through preprocessor defines.
The test (ab)uses the fact that our formatters kick in for any
double-underscore sub-namespace of `std`, so it avoids colliding with
the real string class by declaring the test class in the std::__lldb
namespace.
I do not consider this to be a replacement for the existing data
formatter tests, as producing this kind of a test is not trivial, and it
is easy to make a mistake in the process. However, it's also not
realistic to expect that every person changing the data formatter will
test it against all versions of the real class, so I think it can be
useful as a first line of defence.
Adding support for new layouts can become particularly unwieldy, but
this complexity will also be reflected in the actual code, so if we find
ourselves needing to support too many variants, we may need to start
dropping support for old ones, or come up with a completely different
strategy.
Differential Revision: https://reviews.llvm.org/D124155
Pavel Labath [Mon, 20 Jun 2022 13:47:27 +0000 (15:47 +0200)]
[lldb/dyld-posix] Avoid reading the module list in inconsistent states
New glibc versions (since 2.34 or including this
<https://github.com/bminor/glibc/commit/
ed3ce71f5c64c5f07cbde0ef03554ea8950d8f2c>
patch) trigger the rendezvous breakpoint after they have already added
some modules to the list. This did not play well with our dynamic
loader plugin which was doing a diff of the the reported modules in the
before (RT_ADD) and after (RT_CONSISTENT) states. Specifically, it
caused us to miss some of the modules.
While I think the old behavior makes more sense, I don't think that lldb
is doing the right thing either, as the documentation states that we
should not be expecting a consistent view in the RT_ADD (and RT_DELETE)
states.
Therefore, this patch changes the lldb algorithm to compare the module
list against the previous consistent snapshot. This fixes the previous
issue, and I believe it is more correct in general. It also reduces the
number of times we are fetching the module info, which should speed up
the debugging of processes with many shared libraries.
The change in RefreshModules ensures we don't broadcast the loaded
notification for the dynamic loader (ld.so) module more than once.
Differential Revision: https://reviews.llvm.org/D128264
Emre Kultursay [Fri, 1 Jul 2022 05:44:01 +0000 (13:44 +0800)]
[PATCH] [lldb-server] Skip shared regions for memory allocation
Differential Revision: https://reviews.llvm.org/D128832
Hubert Tong [Fri, 1 Jul 2022 04:03:58 +0000 (00:03 -0400)]
[clang][NFC][tests] dr208.c optional signext handling
Fixes llvm/llvm-project#56325.
jacquesguan [Thu, 30 Jun 2022 11:24:31 +0000 (19:24 +0800)]
[mlir][Vector] Fold InsertStridedSliceOp of ExtractStridedSliceOp.
This patch supports to fold InsertStridedSliceOp(ExtractStridedSliceOp(dst), dst) to dst.
Differential Revision: https://reviews.llvm.org/D128903
jacquesguan [Thu, 30 Jun 2022 08:30:59 +0000 (16:30 +0800)]
[mlir][Vector] Fold InsertStridedSliceOp of two splat with the same input to splat.
This patch folds InsertStridedSliceOp(SplatOp(X):src_type, SplatOp(X):dst_type) to SplatOp(X):dst_type.
Reviewed By: Mogball
Differential Revision: https://reviews.llvm.org/D128891
Volodymyr Sapsai [Fri, 24 Jun 2022 02:05:50 +0000 (19:05 -0700)]
[ODRHash diagnostics] Move common code for calculating diag locations in `DiagnoseODRMismatch` into a lambda. NFC.
Differential Revision: https://reviews.llvm.org/D128489
Fangrui Song [Fri, 1 Jul 2022 02:11:27 +0000 (19:11 -0700)]
Remove unneeded cl::ZeroOrMore. NFC
Fangrui Song [Fri, 1 Jul 2022 02:04:44 +0000 (19:04 -0700)]
[mlir] Remove unneeded cl::ZeroOrMore for ListOption variables. NFC
Volodymyr Sapsai [Thu, 23 Jun 2022 03:18:42 +0000 (20:18 -0700)]
[ODRHash diagnostics] Split `err_module_odr_violation_mismatch_decl_diff` into per-entity diagnostics. NFC.
We'll need to add more cases for Objective-C entities and adding
everything to `err_module_odr_violation_mismatch_decl_diff` makes it
harder to work with over time.
Differential Revision: https://reviews.llvm.org/D128488
wren romano [Mon, 27 Jun 2022 23:28:45 +0000 (16:28 -0700)]
[mlir][tblgen] Improving error messages
This differential improves two error conditions, by detecting them earlier and by providing better messages to help users understand what went wrong.
Reviewed By: jpienaar
Differential Revision: https://reviews.llvm.org/D128555
Xiang1 Zhang [Fri, 1 Jul 2022 01:05:36 +0000 (09:05 +0800)]
[ISel] Match all bits when merge undefs for DAG combine
Reviewed By: RKSimon
Differential Revision: https://reviews.llvm.org/D128570
Xiang1 Zhang [Fri, 1 Jul 2022 00:59:04 +0000 (08:59 +0800)]
Revert "[ISel] Match all bits when merge undef(s) for DAG combine"
This reverts commit
5fe5aa284efed1ee1492e1f266351b35f0a8bb69.
Xiang1 Zhang [Thu, 30 Jun 2022 11:07:25 +0000 (19:07 +0800)]
[ISel] Match all bits when merge undef(s) for DAG combine
Alexey Bataev [Fri, 1 Jul 2022 00:10:04 +0000 (17:10 -0700)]
[SLP][NFC]Cleanup up operands of the removed insertelements, NFC.
Replace all operands of the insertelement instruction, replaced by
shuffles, by poisons to avoid false-positive reports about incorrect function.
Craig Topper [Tue, 28 Jun 2022 23:10:22 +0000 (16:10 -0700)]
[X86] Pre-commit tests for D128769. NFC
Craig Topper [Fri, 1 Jul 2022 00:15:55 +0000 (17:15 -0700)]
[RISCV] Avoid repeated code in SelectAddrRegImm. NFC
Paul Walker [Fri, 24 Jun 2022 08:21:28 +0000 (09:21 +0100)]
[SVE] Use CPY to zero active lanes of a floating point vector.
Patterns exist for the integer case that are trivially expandable
to cover 0.0f.
Differential Revision: https://reviews.llvm.org/D128669
Paul Walker [Wed, 22 Jun 2022 15:05:17 +0000 (16:05 +0100)]
[SVE] Extend "and(ipg,cmp(x,y))" patterns to cover the case when y is an immediate.
Differential Revision: https://reviews.llvm.org/D128479
Alexander Yermolovich [Thu, 30 Jun 2022 23:50:49 +0000 (16:50 -0700)]
[BOLT][DWARF] Support mix mode DWARF
Added support for mixing monolithic DWARF5 with legacy DWARF, and monolithic legacy and DWARF5 split dwarf.
Reviewed By: maksfb
Differential Revision: https://reviews.llvm.org/D128232
Christopher Di Bella [Sat, 25 Jun 2022 00:17:30 +0000 (00:17 +0000)]
[runtimes] adds llvm-libgcc to the list of runtimes to be sorted
llvm-libgcc is not a part of `LLVM_ALL_RUNTIMES` because llvm-libgcc is
incompatible with an explicit libunwind and compiler-rt. This meant that
it was being filtered out and not built.
Differential Revision: https://reviews.llvm.org/D128568
Fangrui Song [Thu, 30 Jun 2022 23:39:23 +0000 (16:39 -0700)]
[MC][Mips] Support .reloc *, BFD_RELOC_{NONE,16,32,64}, *
... to match most other common architectures which already support BFD_RELOC_*.
BFD_RELOC_NONE provides a generic way indicating a dependency between two
sections and is useful for some instrumentations which encode symbol index
information (e.g. `.cg_profile`).
Kazushi (Jam) Marukawa [Sat, 25 Jun 2022 02:34:08 +0000 (11:34 +0900)]
[VE] Support load/store vm regsiters
Support load/store vm registers to memory location as a first step.
As a next step, support load/store vm registers to stack location.
This patch also adds several regression tests for not only load/store
vm registers but also missing load/store for vr registers.
Reviewed By: efocht
Differential Revision: https://reviews.llvm.org/D128610
Julian Lettner [Thu, 30 Jun 2022 19:13:15 +0000 (12:13 -0700)]
[Sanitizer][Darwin] Lookup dyld image header via shared cache
On macOS 13+, dyld itself has moved into the shared cache. Looking it
up via vm_region_recurse_64() now causes spins/hangs/crashes. We use a
different set of dyld APIs to find the image header in the shared cache.
rdar://
92131949
Differential Revision: https://reviews.llvm.org/D128936
Rashmi Mudduluru [Wed, 29 Jun 2022 21:21:42 +0000 (14:21 -0700)]
Adds AST matcher for ObjCStringLiteral
Differential Revision: https://reviews.llvm.org/D128103
Craig Topper [Thu, 30 Jun 2022 22:10:31 +0000 (15:10 -0700)]
[RISCV] Remove an unnecessary copy of X0 in selectShiftMask.
We know which instruction we're emitting so its ok to directly
encode X0 into the instruction. We only need to create a copy when
a constant 0 is selected without context of what instructions uses it.
Nuno Lopes [Thu, 30 Jun 2022 22:01:27 +0000 (23:01 +0100)]
[NFC] Switch a few uses of undef to poison as placeholders for unreachble code
Corentin Jabot [Wed, 29 Jun 2022 17:13:19 +0000 (19:13 +0200)]
Improve the formatting of static_assert messages
Display 'static_assert failed: message' instead of
'static_assert failed "message"' to be consistent
with other implementations and be slightly more
readable.
Reviewed By: #libc, aaron.ballman, philnik, Mordante
Differential Revision: https://reviews.llvm.org/D128844
rdzhabarov [Thu, 30 Jun 2022 21:43:09 +0000 (21:43 +0000)]
[fix/build] Fix bazel build rule.
Zequan Wu [Thu, 30 Jun 2022 21:32:31 +0000 (14:32 -0700)]
[LLDB][NativePDB] Return LLDB_INVALID_ADDRESS in PdbIndex::MakeVirtualAddress when input is invalid due to missing address info in symbol/public records.
Naje George [Thu, 30 Jun 2022 21:26:54 +0000 (14:26 -0700)]
[flang] Expand semantics test coverage of collective subroutines
Add non-standard conforming calls that violate the intent(inout)
of errmsg argument for co_sum, co_max, co_min, and co_broadcast.
Add non-standard conforming calls that violate the argument
typing of errmsg argument for co_max, co_min, and co_broadcast.
Add standard conforming calls that reorder keyword arguments
for co_sum and co_reduce.
Reviewed By: ktras
Differential Revision: https://reviews.llvm.org/D128468
William Huang [Thu, 30 Jun 2022 18:12:20 +0000 (18:12 +0000)]
[InstCombine] Changing constant-indexed GEP of GEP to i8* for merging
When merging GEP of GEP with constant indices, if the second GEP's offset is not divisible by the first GEP's element size, convert both type to i8* and merge.
Reviewed By: nikic
Differential Revision: https://reviews.llvm.org/D125934
Craig Topper [Thu, 30 Jun 2022 21:11:09 +0000 (14:11 -0700)]
[RISCV] Make custom isel for (add X, imm) used by load/stores more selective.
Only handle immediates that would produce an ADDI or ADDIW of Lo12
as the final instruction in their materialization.
As the test change show this removes immediates that materialize
with lui+addiw that is not the same as lui+addi.
LLVM GN Syncbot [Thu, 30 Jun 2022 21:13:26 +0000 (21:13 +0000)]
[gn build] Port
0f94d2b385e7
Piotr Sobczak [Thu, 30 Jun 2022 19:58:57 +0000 (21:58 +0200)]
[AMDGPU] Make v16i16/v16f16 legal
There are upcoming intrinsics to use the new types.
Reviewed By: rampitec
Differential Revision: https://reviews.llvm.org/D128865
Reid Kleckner [Thu, 30 Jun 2022 21:07:46 +0000 (14:07 -0700)]
Fix test expectation positioning relative to FIXME comment
This new test was failing because the line number delta wasn't right.
Naje George [Thu, 30 Jun 2022 20:59:14 +0000 (13:59 -0700)]
[flang] Add new semantics test for team_number function
Add new semantics test for team_number and rename existing
team_number semantics test.
Reviewed By: ktras
Differential Revision: https://reviews.llvm.org/D128309
Mogball [Thu, 23 Jun 2022 19:02:45 +0000 (19:02 +0000)]
[mlir] Add Dead Code Analysis
This patch implements the analysis state classes needed for sparse data-flow analysis and implements a dead-code analysis using those states to determine liveness of blocks, control-flow edges, region predecessors, and function callsites.
Depends on D126751
Reviewed By: rriddle, phisiart
Differential Revision: https://reviews.llvm.org/D127064
Nuno Lopes [Thu, 30 Jun 2022 20:46:19 +0000 (21:46 +0100)]
[NFC] Switch a few uses of undef to poison as placeholders for unreachble code
Marc Auberer [Thu, 30 Jun 2022 20:46:25 +0000 (20:46 +0000)]
[Kaleidoscope] Remove unused function argument
Removes an unused function argument from a code listing in the Kaleidoscope turorial in step 9.
Reviewed By: dblaikie, MaskRay
Differential Revision: https://reviews.llvm.org/D128628
Kostya Serebryany [Tue, 28 Jun 2022 18:36:30 +0000 (11:36 -0700)]
[libFuzzer] Extend the fuzz target intarface to allow -1 return value.
With this change, fuzz targets may choose to return -1
to indicate that the input should not be added to the corpus
regardless of the coverage it generated.
Reviewed By: morehouse
Differential Revision: https://reviews.llvm.org/D128749
Craig Topper [Thu, 30 Jun 2022 20:03:32 +0000 (13:03 -0700)]
[InstCombine] Fix a Wparentheses warning in an assert. NFC
Craig Topper [Thu, 30 Jun 2022 19:27:46 +0000 (12:27 -0700)]
[RISCV] Replace some uses of XLenVT in RISCVDAGToDAGISel::Select with the original Node VT. NFCI
These should contain the same thing, but we aren't consistent about
which we use.
Since we call ReplaceNode, it seems more correct to use the initial VT.
Jay Foad [Thu, 30 Jun 2022 15:31:49 +0000 (16:31 +0100)]
[AMDGPU] GFX11: automatically release VGPRs at the end of the shader
GFX11 has a new message type MSG_DEALLOC_VGPRS which can be used to
release a shader's VGPRs. Sending this at the end of a shader (just
before the s_endpgm) can help overall system performance in cases where
the s_endpgm would have to wait for outstanding VMEM stores to complete
before releasing the VGPRs.
Differential Revision: https://reviews.llvm.org/D128442
Sanjay Patel [Thu, 30 Jun 2022 19:00:12 +0000 (15:00 -0400)]
[InstCombine] canonicalize 'icmp (trunc X), C' to 'icmp (X & Mask), C'
I looked at canonicalizing in the other direction, but that causes
many potential regressions and infinite loops because we already
(possibly wrongly) canonicalize "trunc X to i1" into an and+icmp.
This has a data layout restriction to avoid creating illegal
mask instructions, but we could remove that if we can show
that the backend can undo this when needed.
The motivating example from issue #56119 is modeled by the
PhaseOrdering test.
Sanjay Patel [Thu, 30 Jun 2022 18:06:19 +0000 (14:06 -0400)]
[InstCombine] add tests for icmp (trunc X), C; NFC
Sanjay Patel [Thu, 30 Jun 2022 17:58:23 +0000 (13:58 -0400)]
[PhaseOrdering] add test to show missing folds from PR56119; NFC
issue #56119
Sanjay Patel [Thu, 30 Jun 2022 12:10:51 +0000 (08:10 -0400)]
[AMDGPU] add alternate tests for max-offset codegen; NFC
As discussed in D128123, the existing test shows a possible
regression when converting sub to xor. This adds tests that
avoid that pattern but still has a offset near 65535. Also,
add a test with the canonical IR for the existing test to show
if the transform is happening with the expected pattern in IR.
Aaron Ballman [Thu, 30 Jun 2022 19:46:13 +0000 (15:46 -0400)]
Test and document some C99 DRs
This captures the first 15 or so DRs in C99
Simon Pilgrim [Thu, 30 Jun 2022 19:25:41 +0000 (20:25 +0100)]
[SLP][X86] Add 32-bit vector stores to help vectorization opportunities
Building on the work on D124284, this patch tags v4i8 and v2i16 vector loads as custom, enabling SLP to try to vectorize these types ending in a partial store (using the SSE MOVD instruction) - we already do something similar for 64-bit vector types.
Differential Revision: https://reviews.llvm.org/D127604
Jonas Hahnfeld [Wed, 29 Jun 2022 20:30:56 +0000 (22:30 +0200)]
[Interpreter] Pass target features to JIT
This is required to support RISC-V where the '+d' target feature
indicates the presence of the D instruction set extension, which
changes to the Hard-float 'd' ABI.
Differential Revision: https://reviews.llvm.org/D128853
Sam McCall [Thu, 30 Jun 2022 17:50:40 +0000 (19:50 +0200)]
[pseudo] Add ForestNode descendants iterator, print ambiguous/opaque node stats.
Differential Revision: https://reviews.llvm.org/D128930
Jim Ingham [Thu, 30 Jun 2022 19:09:31 +0000 (12:09 -0700)]
Apparently you need a special makefile flag to use threads on Linux.
This is a follow-up to https://reviews.llvm.org/D128776.
Fazlay Rabbi [Thu, 30 Jun 2022 17:59:33 +0000 (10:59 -0700)]
[OpenMP] Initial parsing and sema support for 'parallel masked taskloop' construct
This patch gives basic parsing and semantic support for
"parallel masked taskloop" construct introduced in
OpenMP 5.1 (section 2.16.9)
Differential Revision: https://reviews.llvm.org/D128834
Jim Ingham [Wed, 29 Jun 2022 01:06:30 +0000 (18:06 -0700)]
Threads which hit a breakpoint but fail the condition are considered
not to be hit. But another thread might be hit at the same time and
actually stop. So we have to be sure to switch the first thread's
stop info to eStopReasonNone or we'll report a hit when the condition
failed, which is confusing.
Differential Revision: https://reviews.llvm.org/D128776
Jonas Devlieghere [Thu, 30 Jun 2022 18:35:12 +0000 (11:35 -0700)]
Revert "Deferred Concept Instantiation Implementation"
This reverts commit
2f207439521d62d9551b2884158368e8b34084e5 because it
triggers an assertion when building an LLDB test program:
Assertion failed: (InstantiatingSpecializations.empty() && "failed to
clean up an InstantiatingTemplate?"), function ~Sema, file
/Users/buildslave/jenkins/workspace/lldb-cmake/llvm-project/clang/lib/Sema/Sema.cpp,
line 458.
More details in https://reviews.llvm.org/D126907.
Craig Topper [Thu, 30 Jun 2022 18:28:02 +0000 (11:28 -0700)]
[RISCV] Use getVTList to simplify creation of vleff MachineSDNode. NFC
We don't need to pass the 3 VTs separately, we already have a list
available to us.
Fangrui Song [Thu, 30 Jun 2022 18:30:34 +0000 (11:30 -0700)]
[llvm-objdump] Default to --mcpu=future for PPC64
GNU objdump disassembles all unknown instructions by default. Match this user
friendly behavior with the cpu value `future`.
Differential Revision: https://reviews.llvm.org/D127824
Fangrui Song [Thu, 30 Jun 2022 18:17:55 +0000 (11:17 -0700)]
[llvm-objdump] Default to --mattr=+all for AArch64
GNU objdump disassembles all unknown instructions by default. Match this user
friendly behavior with the target feature "all" (D128029) designed for disassemblers.
Reviewed By: jhenderson
Differential Revision: https://reviews.llvm.org/D128030
Craig Topper [Thu, 30 Jun 2022 18:05:18 +0000 (11:05 -0700)]
[RISCV] Use the VT passed into selectImm instead of XLenVT. NFCI
I think the VT pased in will always be XLen.
Katherine Rasmussen [Wed, 22 Jun 2022 19:01:04 +0000 (12:01 -0700)]
[flang] Add semantics test for `get_team`
Add a semantics test for the intrinsic function `get_team`.
Differential Revision: https://reviews.llvm.org/D128370
Javed Absar [Sun, 5 Jun 2022 12:42:13 +0000 (13:42 +0100)]
[mlir][Inliner] Support recursion in Inliner
This fixes Bug https://github.com/llvm/llvm-project/issues/53492
and uses InlineHistory to track recursive inlining.
Reviewed By: rriddle
Differential Revision: https://reviews.llvm.org/D127072
Benoit Jacob [Thu, 30 Jun 2022 15:56:15 +0000 (15:56 +0000)]
Useful error when input dim is unused by LHS/RHS.
Differential Revision: https://reviews.llvm.org/D128925
Aaron Ballman [Thu, 30 Jun 2022 17:38:42 +0000 (13:38 -0400)]
Revert "[clang] Emit SARIF Diagnostics: Create `clang::SarifDocumentWriter` interface"
This reverts commit
329fae7103d355e728cc326a0a9abef889ccc577.
This should fix failing test bots like:
https://lab.llvm.org/buildbot/#/builders/91/builds/11328
Fangrui Song [Thu, 30 Jun 2022 17:37:58 +0000 (10:37 -0700)]
[AArch64] Add target feature "all"
This is used by disassemblers: `llvm-mc -disassemble -mattr=` and `llvm-objdump --mattr=`.
The main use case is for llvm-objdump to disassemble all known instructions
(D128030).
In user-facing tools, "all" is intentionally not supported in producers:
integrated assembler (`.arch_extension all`), clang -march (`-march=armv9.3a+all`).
Due to the code structure, `llvm-mc -mattr=+all` `llc -mattr=+all` are not
rejected (they are internal tool). Add `llvm/test/CodeGen/AArch64/mattr-all.ll`
to catch behavior changes.
AArch64SysReg::SysReg::haveFeatures: check `FeatureAll` to print
`AArch64SysReg::SysReg::AltName` for some system registers (e.g. `ERRIDR_EL1, RNDR`).
AArch64.td: add `AssemblerPredicateWithAll` to additionally test `FeatureAll`.
Change all `AssemblerPredicate` (except `UseNegativeImmediates`) to `AssemblerPredicateWithAll`.
utils/TableGen/{DecoderEmitter,SubtargetFeatureInfo}.cpp: support arbitrarily
nested all_of, any_of, and not.
Note: A predicate supports all_of, any_of, and not. For a target (though
currently not for AArch64) an encoding may be disassembled differently with
different target features.
Note: AArch64MCCodeEmitter::computeAvailableFeatures is not available to
the disassembler.
Reviewed By: peter.smith, lenary
Differential Revision: https://reviews.llvm.org/D128029
Martin Sebor [Thu, 30 Jun 2022 17:22:28 +0000 (11:22 -0600)]
[InstCombine] Fix memrchr logic error that prevents folding
Correct a logic bug in the memrchr enhancement added in D123629 that
makes it ineffective in a subset of cases.
Reviewed By: nikic
Differential Revision: https://reviews.llvm.org/D128856
Fangrui Song [Thu, 30 Jun 2022 17:32:38 +0000 (10:32 -0700)]
[AArch64] Make FeatureFuseAdrpAdd a tune feature
Update D120104 to add FeatureFuseAdrpAdd to Processor#TuneFeatures
instead of Processor#Features, similar to FeatureFuseAES, and matching
Tune*.
This enables FeatureFuseAdrpAdd for `clang -mcpu=xxx -mtune=generic` even
if xxx does not set FeatureFuseAdrpAdd.
Reviewed By: alexander-shaposhnikov, peter.smith
Differential Revision: https://reviews.llvm.org/D128787
Vaibhav Yenamandra [Thu, 30 Jun 2022 17:23:15 +0000 (13:23 -0400)]
[clang] Emit SARIF Diagnostics: Create `clang::SarifDocumentWriter` interface
Create an interface for writing SARIF documents from within clang:
The primary intent of this change is to introduce the interface
clang::SarifDocumentWriter, which allows incrementally adding
diagnostic data to a JSON backed document. The proposed interface is
not yet connected to the compiler internals, which will be covered in
future work. As such this change will not change the input/output
interface of clang.
This change also introduces the clang::FullSourceRange type that is
modeled after clang::SourceRange + clang::FullSourceLoc, this is useful
for packaging a pair of clang::SourceLocation objects with their
corresponding SourceManagers.
Previous discussions:
RFC for this change: https://lists.llvm.org/pipermail/cfe-dev/2021-March/067907.html
https://lists.llvm.org/pipermail/cfe-dev/2021-July/068480.html
SARIF Standard (2.1.0):
https://docs.oasis-open.org/sarif/sarif/v2.1.0/os/sarif-v2.1.0-os.html
Differential Revision: https://reviews.llvm.org/D109701
Matthew Voss [Thu, 30 Jun 2022 16:44:23 +0000 (09:44 -0700)]
[llvm-reduce] Change initialization order to fix bots. NFC
Fixes this error:
/var/lib/buildbot/sanitizer-buildbot6/sanitizer-x86_64-linux-android/build/
llvm-project/llvm/tools/llvm-reduce/TestRunner.cpp:20:7:
error: field 'TM' will be initialized after field 'ToolName'
[-Werror,-Wreorder-ctor]
TM(std::move(TM)), ToolName(ToolName) {
^~~~~~~~~~~~~~~~~ ~~~~~~~~~~~~~~~~~~
Program(std::move(Program)) TM(std::move(TM))
1 error generated.
https://lab.llvm.org/buildbot/\#/builders/77/builds/19154