Tapani Pälli [Wed, 26 Feb 2020 08:30:42 +0000 (10:30 +0200)]
mesa/st: toggle EXT_texture_norm16 based on format support
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2556
Fixes:
7f467d4f738 ("mesa: GL_EXT_texture_norm16 extension plumbing")
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3941>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3941>
Tapani Pälli [Wed, 26 Feb 2020 08:29:49 +0000 (10:29 +0200)]
i965: toggle on EXT_texture_norm16
Fixes:
7f467d4f738 ("mesa: GL_EXT_texture_norm16 extension plumbing")
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3941>
Tapani Pälli [Wed, 26 Feb 2020 08:27:04 +0000 (10:27 +0200)]
mesa: introduce boolean toggle for EXT_texture_norm16
Fixes:
7f467d4f738 ("mesa: GL_EXT_texture_norm16 extension plumbing")
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3941>
Juan A. Suarez Romero [Wed, 8 Jan 2020 10:48:29 +0000 (10:48 +0000)]
nir/lower_double_ops: add note for lowering mod
Add a note to clarify that while Vulkan allows mod(x,y) to be in [0, y]
range, OpenGL does not allow it, so the lowering ensures the result is
always in [0, y) range, as this lowering is shared by the Vulkan and
OpenGL implementation.
Reviewed-by: Elie Tournier <elie.tournier@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3315>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3315>
Samuel Pitoiset [Wed, 26 Feb 2020 09:21:24 +0000 (10:21 +0100)]
radv: fix creating null devices if KHR_display is enabled
Found this while replaying pipelines with Fossilize, it worked
fine with vkpipeline-db.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3959>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3959>
Andreas Baierl [Wed, 26 Feb 2020 08:17:57 +0000 (09:17 +0100)]
gitlab-ci: Add add a set of lima flakes
Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Signed-off-by: Andreas Baierl <ichgeh@imkreisrum.de>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3957>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3957>
Samuel Pitoiset [Thu, 20 Feb 2020 08:27:07 +0000 (09:27 +0100)]
radv: make use of ac_gpu_info::max_wave64_per_simd
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3899>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3899>
Samuel Pitoiset [Thu, 20 Feb 2020 08:26:03 +0000 (09:26 +0100)]
radv/gfx10: adjust the number of VGPRs used to compute waves
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3899>
Samuel Pitoiset [Thu, 20 Feb 2020 07:50:29 +0000 (08:50 +0100)]
radv/gfx10: adjust the LDS size used to compute waves
It's 128KB per CU in WGP.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3899>
Samuel Pitoiset [Thu, 20 Feb 2020 08:25:44 +0000 (09:25 +0100)]
radv/gfx10: adjust SGPRs/VGPRs related info
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3899>
Samuel Pitoiset [Thu, 20 Feb 2020 08:24:38 +0000 (09:24 +0100)]
radv/gfx10: adjust the number of simd per compute unit
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3899>
Samuel Pitoiset [Thu, 20 Feb 2020 08:19:44 +0000 (09:19 +0100)]
ac: add more ac_gpu_info related shader fields
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3899>
Samuel Pitoiset [Thu, 20 Feb 2020 07:48:38 +0000 (08:48 +0100)]
ac,radeonsi: add ac_gpu_info::lds_size_per_cu
Both RadeonSI and RADV use the WGP mode, so we can assume 128KB on
GFX10.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3899>
Samuel Pitoiset [Mon, 17 Feb 2020 13:45:47 +0000 (14:45 +0100)]
radv: implement a dummy winsys for creating devices without AMDGPU
To allow developers to test the compiler backends without having
any AMD GPUs. To create a null device, set eg.
RADV_FORCE_FAMILY=polaris10 in your environment.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3872>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3872>
Mathias Fröhlich [Sun, 16 Feb 2020 10:13:43 +0000 (11:13 +0100)]
egl: Factor out dri2_add_pbuffer_configs_for_visuals {device,surfaceless}.
v2: dri2_add_configs_for_visuals -> dri2_add_pbuffer_configs_for_visuals
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Signed-off-by: Mathias Fröhlich <Mathias.Froehlich@web.de>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3790>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3790>
Mathias Fröhlich [Sun, 9 Feb 2020 18:01:53 +0000 (19:01 +0100)]
egl: Fix A2RGB10 platform_{device,surfaceless} PBuffer configs.
The __DRI_IMAGE_FORMAT_* part wants to be handled for the *101010
type formats as well. Factor out a common function for that task.
That again makes the piglit egl_ext_device_base test work again
for hardware drivers.
v2: Factor out a common function for that task.
v3: dri2_pbuffer_visuals -> dri2_pbuffer_visuals
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Fixes:
9acb94b6236 "egl: Enable 10bpc EGLConfigs for platform_{device,surfaceless}"
Signed-off-by: Mathias Fröhlich <Mathias.Froehlich@web.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3790>
Jonathan Marek [Sun, 23 Feb 2020 22:30:15 +0000 (17:30 -0500)]
turnip: enable fullDrawIndexUint32/independentBlend/dualSrcBlend/logicOp
These are already implemented but missing from VkPhysicalDeviceFeatures.
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3923>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3923>
Jonathan Marek [Sun, 23 Feb 2020 22:29:37 +0000 (17:29 -0500)]
turnip: enable sampleRateShading feature
There's still a TODO related to key->sample_shading, but it doesn't look
like it changes anything in ir3, so it works without that.
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3923>
Matt Turner [Tue, 25 Feb 2020 21:15:29 +0000 (13:15 -0800)]
intel/tools: Do not print type/qualifiers/name for c_literal
External tools may wish to choose their own type, qualifiers, and name,
so do not emit our own.
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3952>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3952>
Sagar Ghuge [Fri, 7 Feb 2020 22:25:59 +0000 (14:25 -0800)]
intel/tools: Allow i965_disasm to disassemble c_literal input type
Added extra argument named 'type' which can be 'bin' (default if
ommited) or 'c_literal' for input type.
Change 'binary-path' argument name to 'input-path'.
v2:
- Use util_dynarray for assembly (Matt Turner)
- Read data in 8 bytes chunk (Matt Turner)
- Fix help option (Akeem Abodunrin)
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3952>
Sagar Ghuge [Fri, 7 Feb 2020 22:36:12 +0000 (14:36 -0800)]
intel/tools: Print c_literals 4 byte wide
We already print hex value a byte wide, instead of printing c_literal
byte wide, we can print it 4 byte wide, which gives us 2 different
combinations.
v2: Fix the aliasing issue (Matt Turner)
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3952>
Sagar Ghuge [Thu, 6 Feb 2020 22:39:20 +0000 (14:39 -0800)]
intel/tools: Add test for state register as source
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3952>
Sagar Ghuge [Sat, 8 Feb 2020 00:04:15 +0000 (16:04 -0800)]
intel/tools: Add test for address register as source
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3952>
Sagar Ghuge [Thu, 6 Feb 2020 22:11:55 +0000 (14:11 -0800)]
intel/tools: Set correct address register file and number in i965_asm
We need to use already created brw_reg and set correct file type,
register number and sub register number.
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3952>
Sagar Ghuge [Wed, 5 Feb 2020 00:38:44 +0000 (16:38 -0800)]
intel/tools: Handle STATE_REG in typed source operand
Also stop using brw_sr0_reg function as it return new brw_reg, we
already created register, all we have to is just set file, register
number and subnr.
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3952>
Sagar Ghuge [Wed, 5 Feb 2020 00:37:01 +0000 (16:37 -0800)]
intel/tools: Handle illegal instruction
Allow assembler to handle illegal instruction even though mesa doesn't
use it but might be required at some point in future.
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3952>
Eric Anholt [Wed, 19 Feb 2020 00:03:19 +0000 (16:03 -0800)]
meson: Disable bison's -Wdeprecated since we still support old bison.
We can't stop using deprecated keywords because we maintain support for
ancient bison. Silence the warning so that builds are less noisy.
Acked-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3868>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3868>
Jason Ekstrand [Fri, 21 Feb 2020 19:39:16 +0000 (13:39 -0600)]
anv: Always enable the data cache
Because we set the needs_data_cache bit from the NIR during compilation,
any time a shader was pulled out of the pipeline cache, we wouldn't set
the bit and the data cache was disabled. Fortunately, on Gen8+, this
bit is ignored because we always use the ALL section in the L3$ config
instead of separate DC and RO sections. On Gen7, however, this meant
that we were basically never running with the data cache enabled and our
compute performance was suffering massively because of it. This commit
improves Geekbench 5 scores on my Haswell GT3 by roughly 330% (no,
that's not a typo).
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3912>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3912>
Lionel Landwerlin [Fri, 18 Oct 2019 11:40:42 +0000 (14:40 +0300)]
intel/aub_dump: stub the waits when overriding the device
We don't actually want to wait on anything, just complete submitting
the commands as fast as possible.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3705>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3705>
Lionel Landwerlin [Sat, 11 Jan 2020 15:05:46 +0000 (17:05 +0200)]
intel/tools/aub_dump: fix crash when using the default legacy context
When execbuffer->rsvd1 == 0, the legacy context is used. Ensure we
have context created for this.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3705>
Lionel Landwerlin [Sat, 11 Jan 2020 15:04:49 +0000 (17:04 +0200)]
intel/tools/aub_dump: move aub file initialization to maybe_init()
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3705>
Icenowy Zheng [Tue, 25 Feb 2020 09:48:12 +0000 (17:48 +0800)]
lima: expose fragment shader derivatives capability
Support for fragment shader derivatives has landed in the Lima PP
compiler for a long time, but its capability is not exposed yet.
Expose the support now.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3944>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3944>
Jose Maria Casanova Crespo [Mon, 11 Nov 2019 00:46:24 +0000 (01:46 +0100)]
v3d: Sync on last CS when non-compute stage uses resource written by CS
When a resource is written by a compute shader and then used by a
non-compute stage we sync on last compute job to guarantee that the
resource has been completely written when the next stage reads resources.
In the other cases how flushes are done guarantee the serialization of
the writes and reads.
To reproduce the failure the following tests should be executed in batch
as last test don't fail when run isolated:
KHR-GLES31.core.shader_image_load_store.basic-allFormats-load-fs
KHR-GLES31.core.shader_image_load_store.basic-allFormats-loadStoreComputeStage
KHR-GLES31.core.shader_image_load_store.basic-allTargets-load-cs
KHR-GLES31.core.shader_image_load_store.advanced-sync-vertexArray
v2: Use fence dep instead of bo_wait (Eric Anholt)
v3: Rename struct names (Iago Toral)
Document why is not needed on graphics->compute case. (Iago Toral)
Follow same code pattern of the other update of in_sync_bcl.
v4: Fixed comments style. (Iago Toral)
Fixes KHR-GLES31.core.shader_image_load_store.advanced-sync-vertexArray
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
CC: 19.3 20.0 <mesa-stable@lists.freedesktop.org>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2700>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2700>
Andreas Baierl [Thu, 20 Feb 2020 11:43:46 +0000 (12:43 +0100)]
gitlab-ci: Enable the lima job again
Flaky tests should be fixed to the best of our knowledge.
Fails and skips lists should be up-to-date again.
Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Signed-off-by: Andreas Baierl <ichgeh@imkreisrum.de>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3884>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3884>
Andreas Baierl [Wed, 19 Feb 2020 15:49:07 +0000 (16:49 +0100)]
gitlab-ci: lima: Add flaky tests to the skips list
Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Signed-off-by: Andreas Baierl <ichgeh@imkreisrum.de>
Cc: <mesa-stable@lists.freedesktop.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3884>
Marek Olšák [Tue, 25 Feb 2020 00:10:21 +0000 (19:10 -0500)]
nir: fix gl_nir_lower_images for bindless images
Fixes:
7342b859afb5a7e7f9fb1813e7ab3a55a1c8a704
Reviewed-by: Eric Anholt <eric@anholt.net>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3938>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3938>
Rob Clark [Tue, 25 Feb 2020 00:25:06 +0000 (16:25 -0800)]
freedreno/computerator: fix build dependency
Ensure the generated register headers are built before computerator uses
them.
Reported-by: Clayton Craft <clayton.a.craft@intel.com>
Signed-off-by: Rob Clark <robdclark@chromium.org>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3939>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3939>
Dave Airlie [Mon, 24 Feb 2020 00:29:46 +0000 (10:29 +1000)]
glx/drisw: fix shm put image fallback
The fallback to the non-shm put path used the wrong width here
as the pixmap is still allocated in a shared segment, so the
width needs to reflect that.
Fixes:
02c3dad0f3b4 ("Call shmget() with permission 0600 instead of 0777")
Reviewed-by: Michel Dänzer <mdaenzer@redhat.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3823>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3823>
Dave Airlie [Mon, 24 Feb 2020 00:19:51 +0000 (10:19 +1000)]
glx/drisw: return false if shmid == -1
If an attempt to create an shm pixmap in XCreateDrawable fails
then it ends up with the shmid == -1. This means the get image
path needs to fallback so return false in this case to use the
non-shm get image path.
Fixes:
02c3dad0f3b4 ("Call shmget() with permission 0600 instead of 0777")
Reviewed-by: Michel Dänzer <mdaenzer@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3823>
Dave Airlie [Fri, 14 Feb 2020 05:03:24 +0000 (15:03 +1000)]
glx/drisw: add getImageShm2 path
This adds return values to the get image path, so the caller can fallback.
Fixes:
02c3dad0f3b4 ("Call shmget() with permission 0600 instead of 0777")
Reviewed-by: Michel Dänzer <mdaenzer@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3823>
Dave Airlie [Fri, 14 Feb 2020 05:00:13 +0000 (15:00 +1000)]
dri: add another get shm variant.
When Brian in
02c3dad0f3b4d26e0faa5cc51d06bc50d693dcdc restricted
the shm permissions it means we hit the fallback paths in some
scenarios we hadn't before.
When you use Xephyr to xdmcp from one user to another the new perms
stop the X server (running as user a) attaching to the SHM segments
from gnome-shell (running as user b).
In this case however only the GLX side of the code had insight into this,
and the dri could was meant of fall back, and it worked for put image
fine but the get image path was broken, since there was no indication
in the broken case of the need to fallback.
This adds a return type to a new interface member that lets the
caller know it has to fallback.
Fixes:
02c3dad0f3b4 ("Call shmget() with permission 0600 instead of 0777")
Reviewed-by: Michel Dänzer <mdaenzer@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3823>
Eric Anholt [Mon, 24 Feb 2020 23:57:31 +0000 (15:57 -0800)]
ci: Blacklist another freedreno flaky test.
This is the recurring flake from the last week, including spuriously
failing a pipeline once.
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3937>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3937>
Jason Ekstrand [Mon, 24 Feb 2020 23:46:29 +0000 (17:46 -0600)]
intel/isl: Add isl_aux_info.c to Makefile.sources
This should fix the Android build.
Fixes:
58d4749e56 "isl: Add a module which manages aux resolves"
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Reported-by: Clayton Craft <clayton.a.craft@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3934>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3934>
Rafael Antognolli [Wed, 19 Feb 2020 17:15:49 +0000 (09:15 -0800)]
intel/blorp: Implement GEN:BUG:
1605967699.
v2:
- Update comments and refactor code (Lionel).
- Only apply workaround to stencil resolves.
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3909>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3909>
Erik Faye-Lund [Wed, 19 Feb 2020 11:46:25 +0000 (12:46 +0100)]
gallium/util: remove unused debug_print_foo helpers
These are unused, so let's just get rid of them.
Reviewed-by: Eric Anholt <eric@anholt.net>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3901>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3901>
Erik Faye-Lund [Wed, 19 Feb 2020 11:42:38 +0000 (12:42 +0100)]
gallium/util: do not use debug_print_format
These are the only two places we use this macro, and it's no longer very
gallium-specific. So let's get rid of this, and just use debug_printf
and util_format_name directly instead.
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3901>
Erik Faye-Lund [Wed, 19 Feb 2020 11:51:08 +0000 (12:51 +0100)]
util: move debug_memory_{begin,end} to os_memory_debug.h
This is where the other debug_memory_* functions are declared, so let's
move it here for symmetry.
This allows us to drop an include of u_debug_gallium.h, which makes us
depend on gallium-headers in non-gallium code.
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3901>
Jonathan Marek [Tue, 21 Jan 2020 02:16:13 +0000 (21:16 -0500)]
hud: add GALLIUM_HUD_SCALE
Scale hud by an integer factor, for high DPI displays.
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3931>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3931>
Jonathan Marek [Mon, 24 Feb 2020 15:56:50 +0000 (10:56 -0500)]
turnip: move tile_load_ib/sysmem_clear_ib into draw_cs
Avoids having to calculate reserved sizes for substream cs, also matches
what the blob does.
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Eric Anholt <eric@anholt.net>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3925>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3925>
Jonathan Marek [Mon, 24 Feb 2020 14:40:56 +0000 (09:40 -0500)]
turnip: make cond_exec helper easier to use
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3925>
Jonathan Marek [Mon, 24 Feb 2020 14:14:07 +0000 (09:14 -0500)]
turnip: remove marker seqno
Use robclark's new crashdec/devcoredump thing instead.
Note: not sure this ever really worked because it didn't WFI.
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3925>
Jonathan Marek [Mon, 24 Feb 2020 14:02:41 +0000 (09:02 -0500)]
turnip: automatically reserve cmdstream space in emit_pkt4/emit_pkt7
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3925>
Jonathan Marek [Mon, 24 Feb 2020 13:57:00 +0000 (08:57 -0500)]
turnip: add tu_device pointer to tu_cs
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3925>
Jonathan Marek [Mon, 24 Feb 2020 15:26:02 +0000 (10:26 -0500)]
turnip: fix COND_EXEC reserved size in tu_query
Conditionally executed dwords must be in the same bo.
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3925>
Rob Clark [Sun, 23 Feb 2020 19:53:32 +0000 (11:53 -0800)]
freedreno/computerator: add computerator
A standalone tool to compile and run compute shaders from ir3 assembly.
Mostly to have an easy way to experiment with instructions.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3926>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3926>
Rob Clark [Sun, 23 Feb 2020 19:52:02 +0000 (11:52 -0800)]
freedreno/ir3: allow block->predecessors to be null
This way we can also use ir3_print from computerator, which mostly
bypasses the ir3_block construct (since it doesn't need to do
scheduling, etc)
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3926>
Rob Clark [Sun, 23 Feb 2020 19:51:17 +0000 (11:51 -0800)]
freedreno/computerator: rename prefix asm->ir3
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3926>
Rob Clark [Sun, 23 Feb 2020 19:47:01 +0000 (11:47 -0800)]
freedreno/computerator: polish out some of the rust
Updates for differences between fdre-a3xx's early version of ir3, and
what we have now in mesa. And updates for instruction name and syntax
changes.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3926>
Rob Clark [Fri, 21 Feb 2020 22:31:39 +0000 (14:31 -0800)]
freedreno/computerator: import parser/lexer from fdre-a3xx
Import the rusty old parser from freedreno.git
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3926>
Icenowy Zheng [Sat, 22 Feb 2020 08:54:56 +0000 (16:54 +0800)]
lima: remove its hash table entry when invalidating a resource
When a resouce is already invalidated, its hash table entry becomes
useless. In addition, the lima_job_free() function won't remove the hash
table entry for invalidated resource. So the hash entry should be
removed when invalidating the resource, otherwise bogus hash entry might
be left in the table, and when the resource is reused in another job,
the code will find the freed job when invalidating and thus result in crash.
Fixes:
c64994433c0d ("lima: track write submits of context (v3)")
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3917>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3917>
Caio Marcelo de Oliveira Filho [Sat, 11 Jan 2020 00:25:02 +0000 (16:25 -0800)]
nir, intel: Move use_scoped_memory_barrier to nir_options
This option will be used later by GLSL, so move to a common struct.
Because nir_options is filled in the compiler instead of the Vulkan
driver, fix that up. GLSL will ignore that for now.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3913>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3913>
Caio Marcelo de Oliveira Filho [Thu, 9 Jan 2020 18:05:31 +0000 (10:05 -0800)]
nir/tests: Use nir_scoped_memory_barrier() helper
Most of the vars tests already had a local helper, so just drop it in
favor of the one in nir_builder. Remaining two tests changed to use
the helper.
The load_store_vectorizer tests were using the specific memory
barriers, but since scoped barriers are also handled, prefer that.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3913>
Caio Marcelo de Oliveira Filho [Thu, 9 Jan 2020 18:03:12 +0000 (10:03 -0800)]
nir: Add the alias NIR_MEMORY_ACQ_REL
This will help upcoming C++ code that will have to combine those two
semantics. In C++ it is not possible to do this without a cast or
adding an operator| to the enum. Since having the short form will
also be convient to C, we picked the former solution.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3913>
Caio Marcelo de Oliveira Filho [Thu, 9 Jan 2020 18:01:53 +0000 (10:01 -0800)]
nir/builder: Add nir_scoped_memory_barrier()
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3913>
Eric Anholt [Wed, 5 Feb 2020 22:54:42 +0000 (14:54 -0800)]
freedreno: Switch to using lowered image intrinsics.
This cuts out a bunch of deref chain walking that the compiler can do for
us.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3728>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3728>
Eric Anholt [Wed, 5 Feb 2020 23:46:40 +0000 (15:46 -0800)]
nir: Move intel's intrinsic_image_coordinate_components() to core nir.
This is a query that both Intel and freedreno need to do. We can simplify
it a lot with the new glsl_get_sampler_dim_coordinate_components()
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3728>
Eric Anholt [Wed, 5 Feb 2020 23:01:01 +0000 (15:01 -0800)]
freedreno/ir3: Fix the arg to ir3_get_num_components_for_image_format()
GLuint worked fine for storing our enum, but it should be an enum
pipe_format since the image-formats merge.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3728>
Eric Anholt [Wed, 5 Feb 2020 22:45:33 +0000 (14:45 -0800)]
prog_to_nir: Reuse glsl_get_sampler_dim_coordinate_components().
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3728>
Eric Anholt [Wed, 5 Feb 2020 22:45:33 +0000 (14:45 -0800)]
tgsi_to_nir: Reuse glsl_get_sampler_dim_coordinate_components().
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3728>
Eric Anholt [Wed, 5 Feb 2020 22:43:35 +0000 (14:43 -0800)]
freedreno/ir3: Reuse glsl_get_sampler_dim_coordinate_components() in tex_info.
Now that we have access to the interior switch statement not going through
the txs special case for coord_components, we can just use it.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3728>
Eric Anholt [Wed, 5 Feb 2020 22:41:14 +0000 (14:41 -0800)]
spirv_to_nir: Reuse glsl_sampler_dim_coordinate_components().
We just needed to move the SUBPASS_MS case in, and the rest of the cases
match up.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3728>
Eric Anholt [Wed, 5 Feb 2020 22:36:01 +0000 (14:36 -0800)]
glsl: Factor out the sampler dim coordinate components switch statement.
I want to reuse this in NIR image intrinsics in backends, which just have
dim/is_array.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3728>
Eric Anholt [Fri, 24 Jan 2020 00:33:24 +0000 (16:33 -0800)]
v3d: Ask the state tracker to lower image accesses off of derefs.
This saves a bunch of hassle in handling derefs in the backend, and would
be needed for reasonable handling of dynamic indexing of image arrays.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3728>
Eric Anholt [Thu, 23 Jan 2020 18:52:39 +0000 (10:52 -0800)]
gallium: Add a cap for enabling lowering of image load/store intrinsics.
The deref stuff is hard to handle in a backend supporting dynamic
indexing, while the lowering can easily turn that into the same kind of
dynamic indexing we do for textures, UBOs, and SSBOs.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3728>
Eric Anholt [Thu, 23 Jan 2020 18:49:02 +0000 (10:49 -0800)]
nir: Make image lowering optionally handle the !bindless case as well.
iris was doing this internally, but let's rename the function and move the
iris code there.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3728>
Eric Anholt [Thu, 23 Jan 2020 18:42:15 +0000 (10:42 -0800)]
nir: Rename gl_nir_lower_bindless_images.c in preparation for extending it.
The bulk of it can be reused to implement iris's internal non-bindless
image lowering, which I would like to reuse in freedreno, v3d, and
nir-to-tgsi.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3728>
Nanley Chery [Fri, 21 Feb 2020 19:49:55 +0000 (11:49 -0800)]
i965: Use isl_aux_state_transition_write()
v2. Dirty shadow miptrees independent of aux. (Jason)
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2957>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2957>
Nanley Chery [Fri, 8 Nov 2019 23:11:05 +0000 (15:11 -0800)]
i965: Use ISL's access preparation functions
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2957>
Nanley Chery [Fri, 8 Nov 2019 23:13:16 +0000 (15:13 -0800)]
iris: Use isl_aux_state_transition_write()
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2957>
Nanley Chery [Fri, 8 Nov 2019 23:11:05 +0000 (15:11 -0800)]
iris: Use ISL's access preparation functions
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2957>
Nanley Chery [Fri, 8 Nov 2019 23:07:34 +0000 (15:07 -0800)]
iris: Use isl_aux_usage_has_fast_clear()
Make sure fast-clears aren't attempted or allowed for ISL_AUX_USAGE_MC.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2957>
Nanley Chery [Thu, 21 Nov 2019 17:00:02 +0000 (09:00 -0800)]
isl: Add a module which manages aux resolves
Provide a generic interface which manages aux resolves in ISL. The
feature differences between this and what's in iris is:
* Support for media compression. ISL_AUX_USAGE_MC behaves differently
from many other usages of CCS, so it was useful to implement this
support upfront, while designing the interfaces.
* Optimizations for full-surface writes. For example, after a
full-surface write occurs with ISL_AUX_USAGE_CCS_E in the PARTIAL_CLEAR
state, isl_aux_state_transition_write() returns COMPRESSED_NO_CLEAR
instead of COMPRESSED_CLEAR.
A performance suggestion for main-surface-invalidating/replacing writes
is given as a comment instead of adding a boolean to
isl_aux_prepare_access(). This avoids extra validation and should be
simple enough for the caller to handle.
v2. Add assertions. (Jason)
v3. Use switches in 2 more functions. (Jason)
Store aux metadata in a static table. (Jason)
Change prepare and finish function signatures. (Jason)
Keep isl_aux_state_transition_* functions separate.
v4. (Jason)
Assert against resolving in AUX_INVALID.
Rename aux_info struct to aux_usage_info.
Drop the justification for each aux_usage_info field.
Split out the NONE case in write function.
Restructure tests to more easily confirm coverage.
Rename access_compressed field to compressed.
Make write behavior less ambiguous.
v5. (Jason)
Add more detail above WRITES_RESOLVE_AMBIGUATE.
Add ISL_AUX_USAGE_MC to WritesResolveAmbiguate.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2957>
Kristian H. Kristensen [Sat, 15 Feb 2020 00:47:06 +0000 (16:47 -0800)]
freedreno/ir3: Lower output precision
This lowers mediump FS outputs to fp16 in the ir3 backend. For now
this is a modest improvement, which mostly helps us whittle down the
full mediump work. Once the GLSL level support lands, then right hand
side of the store output intrinsics will be fp16 expressions and we'll
cancel out the fp16 -> fp32 -> fp 16 round trip here.
We've had different attempts at implementing this: rewriting stores in
the GLSL IR, lowering GLSL IR outputs to temporaries and inserting
conversions when writing the temporaries to the outputs. In the end,
GLSL ends up getting in the way a lot and doing it at the nir level is
easier and still possible since we have the output var precisions.
This part of the fp16 work is more of a step on the way towards full
fp16 support and will add a few extra conversion instructions:
total instructions in shared programs: 8151 -> 8163 (0.15%)
instructions in affected programs: 1187 -> 1199 (1.01%)
helped: 4
HURT: 10
total nops in shared programs: 3146 -> 3152 (0.19%)
nops in affected programs: 563 -> 569 (1.07%)
helped: 5
HURT: 10
total non-nops in shared programs: 5005 -> 5011 (0.12%)
non-nops in affected programs: 92 -> 98 (6.52%)
helped: 0
HURT: 3
total dwords in shared programs: 12832 -> 12800 (-0.25%)
dwords in affected programs: 96 -> 64 (-33.33%)
helped: 1
HURT: 0
total last-baryf in shared programs: 118 -> 115 (-2.54%)
last-baryf in affected programs: 21 -> 18 (-14.29%)
helped: 1
HURT: 0
total full in shared programs: 424 -> 417 (-1.65%)
full in affected programs: 15 -> 8 (-46.67%)
helped: 7
HURT: 0
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3822>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3822>
Kristian H. Kristensen [Wed, 19 Feb 2020 21:13:15 +0000 (13:13 -0800)]
nir/types: Add glsl_float16_type() helper
This returns the float16 version of a float type.
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3822>
Hyunjun Ko [Mon, 18 Nov 2019 09:54:09 +0000 (09:54 +0000)]
freedreno/ir3: handle half registers for arrays during register allocation.
So far we only handle full regs of arrays during pre-allocation.
This patch is to handle half regs of arrays and also consider the size
of half regs when finding out conflicts.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3822>
Hyunjun Ko [Mon, 5 Aug 2019 06:36:38 +0000 (06:36 +0000)]
nir: Add optimization for doing removing f16/f32 conversions
This eliminates conversions between f16 and f32 where possible. We can
always remove an upcast followed by a down cast, that is:
f2f16 ( f2f32 (a) ) -> a
f2fmp ( f2f32 (a) ) -> a
In the other direction, f2f16 loses precision and can't be undone by a
f2f32. However, by definition it's always safe to elminate f2fmp:
f2f32 ( f2fmp (a) ) -> a
v2. [Neil Roberts (nroberts@igalia.com)]
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3822>
Hyunjun Ko [Fri, 11 Oct 2019 08:38:36 +0000 (08:38 +0000)]
freedreno/ir3: Add new ir3 pass to fold out fp16 conversions
This pass tries to fold f2f16 conversion into alu instructions.
This will be useful to help reduce the number of instructions once
mesa starts supporting precision lowering. For example:
add.f r0.w, r0.w, c0.x
cov.f32f16 hr2.x, r0.w
to
add.f hr2.x, r0.w, c0.x
Additionally this pass also tries to fold f2f16 conversion into load_input
instruction:
bary.f r0.x, 3, r0.w
cov.f32f16 hr0.x, r0.x
to
bary.f hr1.x, 3, r0.x
v2: Edit to not fold OPC_MAX_F and OPC_MIN_F, since that's not valid.
v3: Add OPC_ABSNEG_F to the blacklist as well.
v4: Don't remove dead cov instructions, DCE will do that later; don't
iterate through sources when a cov only has one; remove special
handling of IR3_REG_ARRAY and IR3_REG_RELATIV.
v5: Handle folding into u32.u32 movs of floats correctly, don't bail
out on IR3_REG_RELATIV or IR3_REG_ARRAY movs.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3822>
Neil Roberts [Wed, 9 Oct 2019 10:36:22 +0000 (12:36 +0200)]
nir/opcodes: Add nir_op_f2fmp
This opcode is the same as the f2f16 opcode except that it comes with
a promise that it is safe to optimise it out if the result is
immediately converted back to a 32-bit float again. Normally this
would be a lossy conversion and so it would be visible to the
application, but if the conversion is generated as part of the mediump
lowering process then this removal doesn’t matter. The opcode is
eventually replaced with a regular f2f16 in the late optimisations so
the backends don’t need to handle it.
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3822>
Indrajit Kumar Das [Mon, 20 Jan 2020 08:49:47 +0000 (14:19 +0530)]
glapi/copyimage: Implement CopyImageSubDataNV
Implement CopyImageSubDataNV from NV_copy_image spec.
This is derived out of the existing implementation of CopyImageSubData.
It differs from CopyImageSubData in accordance with the differences
laid down in the ARB_copy_image spec.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3649>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3649>
Chris Wilson [Sat, 22 Feb 2020 15:51:15 +0000 (15:51 +0000)]
iris: Fix import sync-file into syncobj
When importing a sync-file, the kernel expects to be told which syncobj
to replace with the new fence -- it does not automatically create a new
handle for us. Abide by this rule and create a new syncobj for the
imported sync-file.
Fixes:
f459c56be6bf ("iris: Add fence support using drm_syncobj")
Cc: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3919>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3919>
Alyssa Rosenzweig [Wed, 5 Feb 2020 20:17:44 +0000 (15:17 -0500)]
pan/midgard: Implement load/store_shared
Shared memory is implemented almost identically to global memory from an
ISA perspective, so let's handle the new intrinsics. We include a code
path for constant offsets, which doesn't come up for globals.
Fixes dEQP-GLES31.functional.compute.basic.shared_var_single_invocation
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3775>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3775>
Alyssa Rosenzweig [Tue, 4 Feb 2020 14:46:17 +0000 (09:46 -0500)]
pan/midgard: Implement nir_intrinsic_get_buffer_size
We route it as a sysval. Fixes dEQP-GLES31.functional.compute.basic.ssbo_unsized_arr_single_invocation
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3775>
Alyssa Rosenzweig [Tue, 5 Nov 2019 13:59:49 +0000 (08:59 -0500)]
pan/midgard: Lower SSBOs in NIR
We need to lower SSBOs to globals regardless. Rather than do this in our
backend like we do now, use the common NIR pass, which will support
bounds checking.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3775>
Eduardo Lima Mitev [Sun, 9 Feb 2020 21:07:03 +0000 (21:07 +0000)]
turnip/pipeline: Don't assume tu_shader is a valid object
Fixes a crash in tu6_emit_fs_config() when 'shader' argument is
assumed to be non-null, which is possible.
Fixes dEQP test:
dEQP-VK.api.descriptor_set.descriptor_set_layout_lifetime.graphics
Reviewed-by: Jonathan Marek <jonathan@marek.ca>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3756>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3756>
Samuel Pitoiset [Thu, 20 Feb 2020 12:19:41 +0000 (13:19 +0100)]
radv: add the trace BO to the BO list at submit time
Instead of adding it in every command buffer.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3891>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3891>
Krzysztof Raszkowski [Fri, 21 Feb 2020 13:05:33 +0000 (14:05 +0100)]
gallium/swr: Fix min/max range index draw
Reviewed-by: Jan Zielinski <jan.zielinski@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3905>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3905>
Kenneth Graunke [Wed, 5 Feb 2020 08:53:10 +0000 (00:53 -0800)]
iris: Set MOCS for constant packets on Gen12+
It seems to be back, and we shouldn't use 0, as that's now considered
an error.
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3720>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3720>
Kenneth Graunke [Wed, 5 Feb 2020 08:52:45 +0000 (00:52 -0800)]
iris: Fix BLORP vertex buffers to respect ISL MOCS settings
Fixes:
a4da6008b6a ("iris: Use mocs from isl_dev.")
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3720>
Kenneth Graunke [Wed, 5 Feb 2020 09:02:30 +0000 (01:02 -0800)]
iris: Make mocs an inline helper in iris_resource.h
Now that it uses ISL rather than genxml code, there's no need for it to
live as a vtable function inside the state module. We can just make it
a static inline helper in iris_resource.h so it's available throughout
the codebase.
Fixes:
a4da6008b6a ("iris: Use mocs from isl_dev.")
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3720>
Eric Anholt [Thu, 20 Feb 2020 18:15:43 +0000 (10:15 -0800)]
ci: Remove a useless filtering of the lava logs.
We don't print every case any more, so no need to filter them out. This
makes it so the output form "lavacli jobs logs" gets line-buffered into
"tee" and you can actually see what happened when the job is stuck but
before it times out.
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3883>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3883>