Mike Blumenkrantz [Wed, 27 Apr 2022 13:33:32 +0000 (09:33 -0400)]
zink: add supported present modes to kopper displaytarget
for use later
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16193>
Cristian Ciocaltea [Mon, 25 Apr 2022 11:02:38 +0000 (14:02 +0300)]
ci: Limit Intel CPU scaling frequency for performance tests
As an additional measure to mitigate thermal throttling, set the upper
limit for the CPU scaling frequency to 65% of maximum allowed by the
hardware.
The impact on the overall tests duration should be minimal since the
performance tests do not really put high load on the CPU.
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
Reviewed-by: Guilherme Gallo <guilherme.gallo@collabora.com>
Acked-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16164>
Cristian Ciocaltea [Wed, 20 Apr 2022 23:56:40 +0000 (02:56 +0300)]
ci: Add CPU frequency adjustment capability
Update intel-gpu-freq.sh script to offer the possibility to adjust CPU
operating frequencies in addition to GPU.
Note this is currently limited to just setting the maximum scaling
frequency as percentage of the maximum frequency allowed by the
hardware.
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
Reviewed-by: Guilherme Gallo <guilherme.gallo@collabora.com>
Acked-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16164>
Icecream95 [Tue, 26 Apr 2022 22:31:14 +0000 (10:31 +1200)]
panfrost: Fix pack_32_2x16 implementation
Fixes:
6f0eff548c1 ("pan/bi: Implement packing ops between 32-bit vec1 and 16-bit vec2")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16181>
Samuel Pitoiset [Mon, 25 Apr 2022 06:40:28 +0000 (08:40 +0200)]
radv: use correct push constants range for internal operations
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16131>
Juan A. Suarez Romero [Wed, 27 Apr 2022 09:32:00 +0000 (11:32 +0200)]
v3d/simulator: add support for AMD cards
Dumb buffers do not work with AMD gpus. So use AMD ioctl to create
proper buffers.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16187>
Juan A. Suarez Romero [Wed, 27 Apr 2022 09:30:06 +0000 (11:30 +0200)]
v3dv: store device_id on device init
Instead of calling later an ioctl to get the device id, let's store it
while initializing the physical device.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16187>
Jason Ekstrand [Wed, 27 Apr 2022 00:52:28 +0000 (19:52 -0500)]
panvk: Eliminate unused vertex attributes
We use nir_assign_io_var_locations() which compacts the varyings and
eliminates any unused input slots. We need to do the same thing when
processing pVertexAttributeDescriptions[] or else we'll end up with
mismatches between the shader and the state setup code.
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16183>
Jason Ekstrand [Tue, 26 Apr 2022 22:43:59 +0000 (17:43 -0500)]
panvk: Take buffer offsets into account in BindVertexBuffers
Found by inspection. No idea what all it fixes.
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16183>
David Heidelberg [Mon, 18 Apr 2022 14:15:11 +0000 (16:15 +0200)]
ci/iris: Enable SKQP on Tiger Lake boards
- SKQP gets included now in all amd64 LAVA builds.
- add test job for Tiger Lake (tgl)
- add manual test job for Whiskey Lake (whl), because all runners are
already used
- document that we have 13 tgl machines
Tests failed (on tgl):
- gl_simpleaaclip_aaclip, 1 pixel off : https://okias.pages.freedesktop.org/-/mesa/-/jobs/
21790629/artifacts///results/gl/report.html
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16048>
David Heidelberg [Mon, 18 Apr 2022 14:15:11 +0000 (16:15 +0200)]
ci: intel: Merge anv and iris into src/intel/ci
This commit make simple adding tests which use both GL(ES) and VK.
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16048>
Erik Faye-Lund [Tue, 26 Apr 2022 10:20:07 +0000 (12:20 +0200)]
vulkan: drop empty vulkan_wsi_args
This is always empty, so let's just get rid of it.
Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16162>
Erik Faye-Lund [Tue, 26 Apr 2022 10:10:35 +0000 (12:10 +0200)]
vulkan: use c_msvc_compat_args for shared code
Due to both Lavapipe on Windows and Dozen, we need to support MSVC in
the shared Vulkan code. So let's make sure we compile with the
compatibility flags for it.
Techinically speaking, we also need this in the wsi subdir, because we
also compile wsi_common_win32.c with MSVC. But wsi_common_wayland.c
contains void-pointer arithmetic, causing compiler errors if we do.
Fixing that properly is a bit more involved, because Meson doesn't love
passing different compiler arguments per source-file. The alternative is
to remove the void-pointer arithmetic, but that seems a bit pointless as
this code will never be compiled on MSVC.
So, let's leave that one out for now. We can probably do better in the
future, but this gets us a step further.
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6386
Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16162>
Samuel Pitoiset [Tue, 26 Apr 2022 12:23:36 +0000 (14:23 +0200)]
radv: enable radv_disable_sinking_load_input_fs for Grid Autosport
Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4228
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16165>
Samuel Pitoiset [Tue, 26 Apr 2022 12:20:56 +0000 (14:20 +0200)]
radv: allow to disable sinking of load inputs for FS via drirc
To workaround game bugs where partial derivatives are used in
non-uniform control flow. A proper solution needs to be implemented,
but as a quick fix disabling nir_opt_sink() works.
Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16165>
Lucas Stach [Sun, 10 Apr 2022 11:30:35 +0000 (13:30 +0200)]
etnaviv: add tile size helper
On older GPUs a color tile was always 64 Byte. On new GPUs with
CACHE128B256BPERLINE support the tile size is either 128 Byte or
256 Byte depending on the TS mode. Add a helper to return the
color tile size and use in in places that use hard-coded tile
size values or do their own calculation.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9255>
Lucas Stach [Sun, 10 Apr 2022 11:14:09 +0000 (13:14 +0200)]
etnaviv: use feature bit to check for big tile support
128B/256B tile support is not a HALTI5 property, but has its own
separate feature bit.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9255>
Lucas Stach [Fri, 8 Apr 2022 13:14:39 +0000 (15:14 +0200)]
etnaviv: properly set additional DEC400 compression states
With access to HALTI5 GPUs with and without DEC400 compression it's
obvious that the previous compression state setup only worked when
DEC400 was present. Properly set up the compression state bits.
This is only the second part of the fix, first part is moving the
compression state to the correct bit location, which has already
happened via the import of new rnndb headers.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9255>
Lucas Stach [Sun, 10 Apr 2022 10:59:34 +0000 (12:59 +0200)]
etnaviv: add support for big tile RS states
On GPUs with the CACHE128B256BPERLINE feature the RS gained some
new state bits to deal with the new additional information required
for this big tile support.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9255>
Lucas Stach [Sun, 10 Apr 2022 10:47:21 +0000 (12:47 +0200)]
etnaviv: clean up tiling setup in etna_compile_rs_state
Using the raw layout bits in the tiling setup makes this function harder
to read than necessary. Use the tiling bit defines and assign them to
some local bools with a proper name to make this easier to read.
No functional change.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9255>
Lucas Stach [Sat, 9 Apr 2022 17:00:12 +0000 (19:00 +0200)]
etnaviv: use feature bit for one const src per instuction limitation
Support for multiple constant sources per instruction is not a HALTI5
capability, there is a separate feature bit to signal the availability
of this shader core enhancement.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9255>
Lucas Stach [Wed, 20 Jan 2021 12:39:05 +0000 (13:39 +0100)]
etnaviv: use feature flag to determine which RS states to use
We used the number of pipes to determine which state registers to use
for the RS pipe address configuration, as the dual pipe GPUs were the
first one where the new states were used. This isn't correct though,
as now there are single pipe GPUs which also use the new state
addresses.
There actually is a feature flag telling us to use the new RS pipe
address states, use it. As this feature flag is not available on early
GPUs using the new base address (mostly because we don't have HWDB
entries for them), still check for more than a single pipe as an
additional clue to use new states.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9255>
Lucas Stach [Wed, 20 Jan 2021 12:51:41 +0000 (13:51 +0100)]
etnaviv: use new PE pipe address states on >= HALTI0
We used the number of pipes to determine which state registers to use
for the PE pipe address configuration, as the dual pipe GPUs were the
first one where those new states were used. Now there are some new
single pipe GPUs where this logic breaks. HALTI0 added the new PE
address states and all GPUs with at least this feature level are using
the new states exclusively, even if they only have a single PE pipe.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9255>
Lucas Stach [Thu, 21 Jan 2021 14:56:18 +0000 (15:56 +0100)]
etnaviv: correct bits per tile and clear value for HALTI5
Bits per tile and the tile clear value are not determined by the
HALTI version, but by two separate feature bits that are not always
present on HALTI5 GPUs. With big 128B/256B tile support the bits
per tile are always 4.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9255>
Lucas Stach [Sat, 9 Apr 2022 21:14:16 +0000 (23:14 +0200)]
etnaviv: update headers from rnndb
Update to rnndb commit
ad665b720421.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9255>
Lucas Stach [Wed, 20 Jan 2021 11:58:53 +0000 (12:58 +0100)]
etnaviv: fill all minor GPU features from the kernel
The kernel exposes more minor GPU feature registers. Fill them
all into our internal feature struct.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9255>
Lucas Stach [Thu, 21 Jan 2021 14:50:38 +0000 (15:50 +0100)]
etnaviv: don't supertile textures if supertiling is disabled via debug option
The debug option only disables the general can_supertile spec of the GPU, so
we should also take this into account when deciding about the layout of a
sampler resource.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9255>
Samuel Pitoiset [Mon, 18 Apr 2022 12:46:09 +0000 (14:46 +0200)]
radv: fix handling divisor == 0 with dynamic vertex input state
When the divisor is 0, the compiler should generate a different VS
prolog instead of re-using a previous prolog that uses nontrivial
divisors. This is because divisor == 0 and divisor > 1 should use
a different path to guarantee that the index is correctly computed.
Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16009>
Gert Wollny [Mon, 25 Apr 2022 06:41:47 +0000 (08:41 +0200)]
r600: Add support for TGSI_OPCODE_ATOMIMIN and IMAX
With NTT these opcodes are now emitted and need to be handled.
Fixes:
a4840e15ab77b44a72cabd7d503172e8357477eb
r600: Use nir-to-tgsi instead of TGSI when the NIR debug opt is disabled.
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16130>
Gert Wollny [Sun, 24 Apr 2022 12:25:45 +0000 (14:25 +0200)]
r600: tune nir options
* Don't lower fp64 to software when on Cayman but
* lower fpow only when on native NIR, the TGSI backend handles
TGSI_OPCODE_POW
Fixes:
a4840e15ab77b44a72cabd7d503172e8357477eb
r600: Use nir-to-tgsi instead of TGSI when the NIR debug opt is disabled.
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16130>
Gert Wollny [Sun, 24 Apr 2022 11:24:44 +0000 (13:24 +0200)]
r600/sb: Don't optimize float GT and GE
Sine NAN's can be involved the result can't be deducted like this.
Also with NTT inplace now we can assume that most possible
arithmetic optimizations have already been applied.
Piglit: spec@glsl-1.30@execution@range_analysis_fsat_of_nan
Fixes:
a4840e15ab77b44a72cabd7d503172e8357477eb
r600: Use nir-to-tgsi instead of TGSI when the NIR debug opt is disabled.
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16130>
Gert Wollny [Sun, 24 Apr 2022 15:03:42 +0000 (17:03 +0200)]
ntt: remove dead input variables before lowering FS IO
Because for fragment shaders we still use the variables, and
lower_io_to_vector may leave dead variables that duplicate inputs
that are now vectorized, we have to call this pass, because otherwise
we will may hit the assertion
src/gallium/auxiliary/tgsi/tgsi_ureg.c:318:
ureg_DECL_fs_input_centroid_layout:
Assertion `(ureg->input[i].usage_mask & usage_mask) == 0'
This is relevant for
spec@arb_enhanced_layouts@execution@component-layout@*
on r600/ntt
Fixes:
a4840e15ab77b44a72cabd7d503172e8357477eb
r600: Use nir-to-tgsi instead of TGSI when the NIR debug opt is disabled
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16130>
Gert Wollny [Sun, 24 Apr 2022 12:25:01 +0000 (14:25 +0200)]
nir: Don't optimize to 64 bit fsub if the driver doesn't support it
Fixes:
a4840e15ab77b44a72cabd7d503172e8357477eb
r600: Use nir-to-tgsi instead of TGSI when the NIR debug opt is disabled.
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16130>
Yiwei Zhang [Tue, 26 Apr 2022 19:25:54 +0000 (19:25 +0000)]
venus: flush when batched draw calls reach a threshold
Add VN_DRAW_CMD_BATCH_LIMIT option
e.g. for Android
adb shell setprop mesa.vn.draw.cmd.batch.limit 100
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16110>
Yiwei Zhang [Tue, 26 Apr 2022 18:10:05 +0000 (18:10 +0000)]
venus: refactor vn_cmd_submit
The caller checks cmd->state instead.
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16110>
Yiwei Zhang [Fri, 22 Apr 2022 22:06:23 +0000 (22:06 +0000)]
venus: add VN_PERF option no_async_queue_submit
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16110>
Yiwei Zhang [Fri, 22 Apr 2022 21:47:38 +0000 (21:47 +0000)]
venus: add VN_PERF option no_async_buffer_create
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16110>
Yiwei Zhang [Fri, 22 Apr 2022 21:37:27 +0000 (21:37 +0000)]
venus: add env perf options and introduce no_async_set_alloc
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16110>
Yiwei Zhang [Tue, 26 Apr 2022 18:26:16 +0000 (18:26 +0000)]
venus: refactor to add struct vn_env
This is to prepare for adding perf options.
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16110>
Jason Ekstrand [Tue, 26 Apr 2022 16:34:35 +0000 (11:34 -0500)]
nir: Constant fold sampler/texture offsets
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16171>
Jason Ekstrand [Tue, 26 Apr 2022 16:28:36 +0000 (11:28 -0500)]
nir/constant_folding: Break TXB folding into a helper function
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16171>
Yiwei Zhang [Tue, 26 Apr 2022 06:11:46 +0000 (06:11 +0000)]
venus: fix view format for ahb image
There's below AHB VU on the image view:
VUID-VkImageViewCreateInfo-image-02399
If image has an external format, format must be VK_FORMAT_UNDEFINED
This is well hidden and completely missed from the original venus ahb
implementation.
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16159>
Mike Blumenkrantz [Mon, 25 Apr 2022 18:32:59 +0000 (14:32 -0400)]
kopper: copy a bunch of code for texture_from_pixmap
seems to work?
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16152>
Mike Blumenkrantz [Mon, 25 Apr 2022 18:15:17 +0000 (14:15 -0400)]
kopper: store whether screen has dmabuf support
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16152>
Mike Blumenkrantz [Mon, 25 Apr 2022 18:14:45 +0000 (14:14 -0400)]
kopper: move drawable geometry updating up in function
no functional changes
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16152>
Mike Blumenkrantz [Mon, 25 Apr 2022 14:41:46 +0000 (10:41 -0400)]
kopper: always fetch and store drawable info
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16152>
Mike Blumenkrantz [Mon, 25 Apr 2022 14:00:08 +0000 (10:00 -0400)]
drisw: remove dead code
this was from a very early version of kopper, but it can no longer
be reached
Fixes:
d760a9151b7 ("gallium: Learn about kopper")
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16152>
Icecream95 [Tue, 26 Apr 2022 20:23:35 +0000 (08:23 +1200)]
panfrost: Enable NIR lowering of half float packing
The GLSL lowering of half float packing involves software conversion
to half-float; instead, use the lowering in NIR.
Both Midgard and Bifrost are already set to lower the instructions to
bit operations, but change mdg_should_scalarize so that the lowerable
split variants of the pack/unpack instructions are generated.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16175>
Mike Blumenkrantz [Mon, 25 Apr 2022 19:46:28 +0000 (15:46 -0400)]
zink: fix up swapchain depth buffer geometry during fb update
due to desync between the frontend and the driver, the size that the
depth buffer was created with may not match the size of the swapchain if
the window is being resized very quickly, so just go ahead and clobber
the existing depth buffer with a series of very illegal internal object
replacements to make everything match up
do not try at home.
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16151>
Mike Blumenkrantz [Mon, 25 Apr 2022 19:43:40 +0000 (15:43 -0400)]
zink: fix/improve swapchain surface info updating
if the swapchain is updated, the base surface info needs to be updated
so that the surface info used for the framebuffer is updated
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16151>
Mike Blumenkrantz [Mon, 25 Apr 2022 19:41:30 +0000 (15:41 -0400)]
kopper: add DISPLAY_TARGET bind for depth buffer
this doesn't affect functionality and is only used for validation
in the driver
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16151>
Konstantin Seurer [Tue, 19 Apr 2022 10:20:08 +0000 (12:20 +0200)]
radv: Copy shader modules to avoid use after free
The vkd3d-proton ray tracing tests delete shader modules after creating
pipeline libraries from them. This resulted in a use after free when
creating ray tracing pipelines.
Signed-off-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16027>
Konstantin Seurer [Tue, 26 Apr 2022 07:36:29 +0000 (09:36 +0200)]
vulkan: Add a shader module clone helper
Signed-off-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16027>
Alyssa Rosenzweig [Tue, 19 Apr 2022 20:42:03 +0000 (16:42 -0400)]
panfrost: Add a test for pan_image_layout_init
Would have caught a significant issue with ETC2 handling. Luckily Midgard dEQP
failed on this, even though Bifrost didn't (due to explicit strides?)
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15991>
Alyssa Rosenzweig [Tue, 19 Apr 2022 21:54:57 +0000 (17:54 -0400)]
panfrost: Simplify how image_layout_init is called
Rather than using it as a catch-all initialize, use it to fill in derived from
fields from a partially initialized image_layout. This is easier to understand
and, more importantly, easier to unit test.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15991>
Alyssa Rosenzweig [Sat, 16 Apr 2022 15:48:24 +0000 (11:48 -0400)]
panfrost: Unit test block size queries
Simple interface, make sure we don't screw it up.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15991>
Alyssa Rosenzweig [Tue, 19 Apr 2022 20:36:45 +0000 (16:36 -0400)]
panfrost: Remove unused dev argument
This function has enough arguments as it is... Motivated by wanting to unit test
this monster.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15991>
Alyssa Rosenzweig [Sat, 16 Apr 2022 14:47:02 +0000 (10:47 -0400)]
panfrost: Unify paths through image_layout_init
We can always align the width/height, now that block_size is defined (as 1x1)
for linear textures. We can also remove the useless effective_depth assignment.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15991>
Alyssa Rosenzweig [Sat, 16 Apr 2022 14:42:43 +0000 (10:42 -0400)]
panfrost: Unify panfrost_block_size paths
Handle linear, interleaved, and AFBC formats. This requires taking a format, as
block compressed u-interleaved textures have a different tile size than other
u-interleaved textures.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15991>
Alyssa Rosenzweig [Sat, 16 Apr 2022 14:37:07 +0000 (10:37 -0400)]
panfrost: Use pan_block_size in layout calculation
This gets rid of the weird "call block_dim twice with a mystery argument"
pattern, and will allow us to further unify code.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15991>
Alyssa Rosenzweig [Sat, 16 Apr 2022 14:31:18 +0000 (10:31 -0400)]
panfrost: Extract panfrost_afbc_is_wide helper
Rather than open-code the > 16 check in multiple places and have to justify it
in each. This is easier to understand at the call sites.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15991>
Alyssa Rosenzweig [Sat, 16 Apr 2022 14:28:17 +0000 (10:28 -0400)]
panfrost: Don't pretend to support multiplane AFBC
This requires tons of driver changes we're not ready for. In the mean time, this
will just get in the way of refactoring AFBC support.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15991>
Alyssa Rosenzweig [Sat, 16 Apr 2022 14:26:49 +0000 (10:26 -0400)]
panfrost: Use panfrost_afbc_superblock_width
..instead of panfrost_block_dim. This is clearer, and gets rid of block dim
users.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15991>
Alyssa Rosenzweig [Sat, 16 Apr 2022 14:23:33 +0000 (10:23 -0400)]
panfrost: Add afbc_superblock_{size, width, height} helpers
...and use them to implement block_dim transitionally.
These should be clearer than the general block_dim.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15991>
Alyssa Rosenzweig [Tue, 26 Apr 2022 15:34:45 +0000 (11:34 -0400)]
panfrost: Always use 64-bit SD with strides
Midgard has multiple Surface Descriptor formats selectable in the texture
descriptor. Previously, we have used both the "64-bit surface descriptor" and
the "64-bit surface descriptor with 32-bit line stride and 32-bit layer stride".
A delicate routine tried to guess what stride the hardware will use if we don't
specify it explicitly, and omit the stride if it matches. Unfortunately, that
routine is broken in at least two ways:
* Textures with ASTC must always specify an explicit stride. Failing to do so
(like we were doing) is invalid.
* It applies even for interleaved textures. The comment above the function
saying otherwise is incorrect. (TODO: double check this)
Bifrost onwards always specify the strides explicitly. Let's just do that and
unify the gens. What is lost from doing this? A ludicrously trivial amount of
memory and texture descriptor cache space. 8 bytes per layer*level per texture,
in fact. Compared to the size of the textures being addressed, the memory usage
is trivial. The texture descriptor cache size maybe matters more. But given
Arm's hardware people went this direction for Bifrost and stuck to it, I doubt
it matters much.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15991>
Alyssa Rosenzweig [Sat, 16 Apr 2022 14:02:51 +0000 (10:02 -0400)]
panfrost: Split pan_layout.c from pan_texture.c
Before we used GenXML, pan_texture mixed layout code with texture descriptor
packing code. For the most part, the layout code is generation-independent; the
pack code is not. We introduced an anti-pattern where the file was compiled N+1
times: N times for each PAN_ARCH value, and an extra time with no PAN_ARCH
value. And then the contents of the file changed completely depending on
PAN_ARCH. This is a pretty weird construction.
Let's instead split off the layout file from the descriptor file, compile the
layout file once, and compile the descriptor file per-gen.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15991>
Alyssa Rosenzweig [Tue, 26 Apr 2022 15:08:38 +0000 (11:08 -0400)]
panfrost: Advertise all textures in drm-shim
I was rather confused when I couldn't reproduce an ASTC bug under drm-shim...
Fix that.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15991>
Yevhenii Kolesnikov [Thu, 21 Apr 2022 18:20:13 +0000 (21:20 +0300)]
nir: Remove single-source phis before opt_if_loop_last_continue
We might have some single-source phis leftover after prior optimizations. We
want to get rid of them before merging the blocks.
Fixes:
5921a19d4b0 ("nir: add if opt opt_if_loop_last_continue()")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6312
Signed-off-by: Yevhenii Kolesnikov <yevhenii.kolesnikov@globallogic.com>
Reviewed-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16095>
Lucas Stach [Tue, 19 Apr 2022 10:54:55 +0000 (12:54 +0200)]
etnaviv: set VIVS_GL_VERTEX_ELEMENT_CONFIG depending on prim type
New blob versions always emit this state on GPUs that don't have the
NEW_GPIPE feature bit before drawing a primitive, as it needs to be
set according to the primitive type.
Closes: #2933
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16094>
Lucas Stach [Tue, 19 Apr 2022 10:47:41 +0000 (12:47 +0200)]
etnaviv: update headers from rnndb
Update to etna_viv commit
100009142dc2.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16094>
Jason Ekstrand [Fri, 22 Apr 2022 17:48:22 +0000 (12:48 -0500)]
vulkan/log: Allow but warn for client-invisible objects
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16107>
Jason Ekstrand [Fri, 22 Apr 2022 17:46:02 +0000 (12:46 -0500)]
vulkan/log: Allow but warn if called with a NULL object
Most of the time when the logging code is invoked, it means we're
already in an edge case. It should be as robust as possible, otherwise
we risk making hard to debug things even harder. To that end, instead
of blowing up if passed a NULL object on the list, handle it as
gracefully as we can.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16107>
Jason Ekstrand [Wed, 20 Apr 2022 16:37:19 +0000 (11:37 -0500)]
spirv: Handle Op*MulExtended for non-32-bit types
Fixes:
58bcebd987b7 ("spirv: Allow [i/u]mulExtended to use new nir opcode")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6306
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16060>
Alyssa Rosenzweig [Thu, 7 Apr 2022 14:34:00 +0000 (10:34 -0400)]
panfrost: Kick off v9 support in the driver
Call panfrost_cmdstream_screen_init_v9.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16035>
Alyssa Rosenzweig [Tue, 5 Apr 2022 16:38:38 +0000 (12:38 -0400)]
panfrost: Compile for v9
Now that everything is ported!
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16035>
Alyssa Rosenzweig [Tue, 19 Apr 2022 13:54:02 +0000 (09:54 -0400)]
panfrost: Generate Valhall Malloc IDVS jobs
These look similar to Bifrost IDVS but with a twist: memory allocation is
handled by the hardware, and the descriptors are split up. Add the handling for
these.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16035>
Alyssa Rosenzweig [Thu, 14 Apr 2022 22:54:24 +0000 (18:54 -0400)]
panfrost: Use dirty flags to emit v9 descriptors
These new descriptors take the place of removed descriptors like the RSD, and
need corresponding dirty tracking.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16035>
Alyssa Rosenzweig [Tue, 19 Apr 2022 13:54:19 +0000 (09:54 -0400)]
panfrost: Specialize shader descriptors for Valhall
Instead of being globbed into the RSD, Valhall uses minimal shader program
descriptors. For IDVS, we need separate descriptors for position and varying
shaders. It's actually worse -- we need separate descriptors for drawing points
and drawing lines/triangles in order to skip over the gl_PointSize write. Adapt
prepare_shader to upload all these descriptors.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16035>
Alyssa Rosenzweig [Thu, 7 Apr 2022 14:26:00 +0000 (10:26 -0400)]
panfrost: Specialize ZSA state for Valhall
Now we have a much nicer Z/Stencil Descriptor.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16035>
Alyssa Rosenzweig [Tue, 19 Apr 2022 13:54:14 +0000 (09:54 -0400)]
panfrost: Specialize vertex elements for Valhall
The split between attribute descriptors and buffer descriptors parallels that of
Bifrost's attribute descriptors and attribute buffer descriptors, with some
shuffling and simplication.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16035>
Alyssa Rosenzweig [Tue, 19 Apr 2022 13:54:12 +0000 (09:54 -0400)]
panfrost: Simplify attribute format expression
Chew through a layer of indirection for clarity.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16035>
Alyssa Rosenzweig [Tue, 19 Apr 2022 13:54:10 +0000 (09:54 -0400)]
panfrost: Specialize rasterizer state for Valhall
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16035>
Alyssa Rosenzweig [Tue, 19 Apr 2022 14:10:48 +0000 (10:10 -0400)]
panfrost: Adapt compute job emit for Valhall
Similar data structure, simpler packing.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16035>
Alyssa Rosenzweig [Tue, 19 Apr 2022 14:09:28 +0000 (10:09 -0400)]
panfrost: Use common state emit for compute jobs
This reduces the "specialness" of the Bifrost compute job emit path. It's not
useful in its own right since we currently put compute jobs in their own batch.
This could be optimized.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16035>
Alyssa Rosenzweig [Tue, 19 Apr 2022 13:54:15 +0000 (09:54 -0400)]
panfrost: Don't fix up alpha test on Bifrost
Since
7d1d7cdf575 ("panfrost: Don't check alpha test in fs_required on
Bifrost+"), we don't use the alpha testing state on Bifrost. So the fixup isn't
needed either.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16035>
Alyssa Rosenzweig [Thu, 7 Apr 2022 15:27:28 +0000 (11:27 -0400)]
panfrost: Port uniform/UBO logic to Valhall
Use Valhall descriptors, and report sizes so we can accurately inform the
hardware of sizes.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16035>
Alyssa Rosenzweig [Thu, 7 Apr 2022 15:26:30 +0000 (11:26 -0400)]
panfrost: Add helper to emit UBOs
Either as uniform remap table entries on Bifrost, or as simple buffer
descriptors on Valhall. The underlying hardware is different (and there are
compiler changes for load_ubo handling), but the high level UBO upload logic
does not have to care about that.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16035>
Alyssa Rosenzweig [Tue, 5 Apr 2022 16:37:59 +0000 (12:37 -0400)]
panfrost: Compile libpanfrost for v9
Now that everything is ported.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16035>
Alyssa Rosenzweig [Thu, 13 Jan 2022 22:42:15 +0000 (17:42 -0500)]
panfrost: Don't allocate storage for PSIZ on Valhall
It's implicit.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16035>
Alyssa Rosenzweig [Tue, 26 Apr 2022 14:13:14 +0000 (10:13 -0400)]
pan/blit: Support v9 data structures
Now that everything is appropriately refactored, we can support Valhall's data
structures in the blitter. Things look similar to Bifrost, but the RSD no longer
exists.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16035>
Alyssa Rosenzweig [Tue, 26 Apr 2022 14:01:33 +0000 (10:01 -0400)]
pan/blit: Prepare for Valhall port
Valhall's data structures are organized differently. In particular, they don't
use RSDs. So we need to reshuffle the blitter's data structures so we can map to
Valhall.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16035>
Alyssa Rosenzweig [Tue, 26 Apr 2022 14:06:02 +0000 (10:06 -0400)]
pan/blit: Generalize texture alignment
For Valhall compat.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16035>
Alyssa Rosenzweig [Tue, 26 Apr 2022 14:02:15 +0000 (10:02 -0400)]
pan/blit: Compile blit shaders without IDVS
On Valhall, the fragment shader differs based on whether IDVS or the legacy
geometry flow is used be. In particular, varyings are accessed differently.
We use the legacy geometry flow for blitting on all GPUs, so indicate this in
the shader inputs.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16035>
Alyssa Rosenzweig [Tue, 19 Apr 2022 14:15:01 +0000 (10:15 -0400)]
panfrost: Add texture features enum to v9.xml
Required to query texture features on Valhall. It's technically the same as
previous Malis (except for narrow ASTC), but conceptually it's different as
plane descriptors have superseded indexed pixel formats for block compressed
textures.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16035>
Adam Jackson [Mon, 7 Mar 2022 16:53:05 +0000 (11:53 -0500)]
docs: Update supported drivers for 22.x
nouveau doesn't support pre-nv30 anymore, pre-DX9 drivers are no longer
supported generally, and llvmpipe jits on more than just x86.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15489>
Adam Jackson [Thu, 10 Mar 2022 21:14:21 +0000 (16:14 -0500)]
docs: Note EGL enum allocation for EGL_EXT_present_opaque
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15489>
Jason Ekstrand [Mon, 25 Apr 2022 17:25:17 +0000 (12:25 -0500)]
vulkan: Use ALL_COMMANDS_BIT for waits/signals instead of ~0
This is a bit more accurate for what's going on and, while all Mesa
drivers today seem to be ok with extra bits, ensures we're passing a
valid Vulkan thing.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16145>
Jason Ekstrand [Mon, 25 Apr 2022 16:08:42 +0000 (11:08 -0500)]
vulkan: Set signals[i].stageMask = ALL_COMMANDS for QueueSubmit2 wrapping
My understanding of the signal masks is that they control what stages
must complete before the semaphore is signaled. Using 0 theoretically
means the semaphore could be signaled immediately without waiting on
anything. Use ~0 instead to say it depends on everything.
Fixes:
97f0a4494b97 ("vulkan: implement legacy entrypoints on top of VK_KHR_synchronization2")
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16145>
David Heidelberg [Fri, 15 Apr 2022 15:18:32 +0000 (17:18 +0200)]
ci: skqp: update URL
The file and functionality isn't present in `main` branch anymore.
Acked-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Guilherme Gallo <guilherme.gallo@collabora.com>
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15973>
Erik Faye-Lund [Tue, 19 Apr 2022 12:51:03 +0000 (14:51 +0200)]
panvk: quiet non-conformant warning on ci
This helper has built-in support to be quieted, which seems like a good
idea to do on ci.
We're already setting the env var in the CI environment, so no need to
do that here.
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16033>
projects / platform / upstream / mesa.git / log