Jakub Jelinek [Tue, 12 May 2020 07:17:09 +0000 (09:17 +0200)]
openmp: Implement discovery of implicit declare target to clauses
This attempts to implement what the OpenMP 5.0 spec in declare target section
says as ammended by the 5.1 changes so far (related to device_type(host)), except
that it doesn't have the device(ancestor: ...) handling yet because we do not
support it yet, and I've left so far out the except lambda note, because I need
that clarified.
2020-05-12 Jakub Jelinek <jakub@redhat.com>
* omp-offload.h (omp_discover_implicit_declare_target): Declare.
* omp-offload.c: Include context.h.
(omp_declare_target_fn_p, omp_declare_target_var_p,
omp_discover_declare_target_fn_r, omp_discover_declare_target_var_r,
omp_discover_implicit_declare_target): New functions.
* cgraphunit.c (analyze_functions): Call
omp_discover_implicit_declare_target.
* testsuite/libgomp.c/target-39.c: New test.
Richard Biener [Tue, 14 Jan 2020 14:25:26 +0000 (15:25 +0100)]
Fold &MEM[0 + CST]->a.b.c to a constant
This canonicalizes those to a constant literal.
2020-05-12 Richard Biener <rguenther@suse.de>
* gimple-fold.c (maybe_canonicalize_mem_ref_addr): Canonicalize
literal constant &MEM[..] to a constant literal.
Richard Biener [Mon, 11 May 2020 13:26:09 +0000 (15:26 +0200)]
tree-optimization/95045 - fix SM with exit exiting multiple loops
Since we apply SM to an edge which exits multiple loops we have
to make sure to commit insertions on it immediately since otherwise
store order is not preserved.
2020-05-12 Richard Biener <rguenther@suse.de>
PR tree-optimization/95045
* dbgcnt.def (lim): Add debug-counter.
* tree-ssa-loop-im.c: Include dbgcnt.h.
(find_refs_for_sm): Use lim debug counter for store motion
candidates.
(do_store_motion): Rename form store_motion. Commit edge
insertions...
(store_motion_loop): ... here.
(tree_ssa_lim): Adjust.
Ulrich Drepper [Tue, 12 May 2020 05:38:28 +0000 (07:38 +0200)]
Actually comment the new tests
Ulrich Drepper [Tue, 12 May 2020 05:37:09 +0000 (07:37 +0200)]
Implent C++20 std::atomic_flag::test
* include/bits/atomic_base.h (atomic_flag): Implement test member
function.
* include/std/version: Define __cpp_lib_atomic_flag_test.
* testsuite/29_atomics/atomic_flag/test/explicit.cc: New file.
* testsuite/29_atomics/atomic_flag/test/implicit.cc: New file.
Kelvin Nilsen [Tue, 12 May 2020 02:37:41 +0000 (21:37 -0500)]
rs6000: Built-in cleanups for vec_clzm, vec_ctzm, and vec_gnb
Changes to the built-in specification occurred after early patches
added support for these. The name of vec_clzm became vec_cntlzm,
and vec_ctzm became vec_cnttzm. Four of the overloaded forms of
vec_gnb were removed, and the fourth argument redefined as an
unsigned int, not an unsigned char. This patch reflects those
changes in the code and test cases. Eight of the vec_gnb test
cases are removed as a result.
[gcc]
2020-05-11 Kelvin Nilsen <kelvin@gcc.gnu.org>
* config/rs6000/altivec.h (vec_clzm): Rename to vec_cntlzm.
(vec_ctzm): Rename to vec_cnttzm.
* config/rs6000/rs6000-c.c (altivec_resolve_overloaded_builtin):
Change fourth operand for vec_ternarylogic to require
compatibility with unsigned SImode rather than unsigned QImode.
* config/rs6000/rs6000-call.c (altivec_overloaded_builtins):
Remove overloaded forms of vec_gnb that are no longer needed.
* doc/extend.texi (PowerPC AltiVec Built-in Functions Available
for a Future Architecture): Replace vec_clzm with vec_cntlzm;
replace vec_ctzm with vec_cntlzm; remove four unwanted forms of
vec_gnb; move vec_ternarylogic documentation into this section
and replace const unsigned char with const unsigned int as its
fourth argument.
[gcc/testsuite]
2020-05-11 Kelvin Nilsen <kelvin@gcc.gnu.org>
* gcc.target/powerpc/vec-clzm-0.c: Rename to...
* gcc.target/powerpc/vec-cntlzm-0.c: ...this.
* gcc.target/powerpc/vec-clzm-1.c: Rename to...
* gcc.target/powerpc/vec-cntlzm-1.c: ...this.
* gcc.target/powerpc/vec-ctzm-0.c: Rename to...
* gcc.target/powerpc/vec-cnttzm-0.c: ...this.
* gcc.target/powerpc/vec-ctzm-1.c: Rename to...
* gcc.target/powerpc/vec-cnttzm-1.c: ...this.
* gcc.target/powerpc/vec-gnb-8.c: Rename to...
* gcc.target/powerpc/vec-gnb-0.c: ...this, deleting the old file.
* gcc.target/powerpc/vec-gnb-9.c: Rename to...
* gcc.target/powerpc/vec-gnb-1.c: ...this, deleting the old file.
* gcc.target/powerpc/vec-gnb-10.c: Rename to...
* gcc.target/powerpc/vec-gnb-2.c: ...this, deleting the old file.
* gcc.target/powerpc/vec-gnb-3.c: Delete.
* gcc.target/powerpc/vec-gnb-4.c: Delete.
* gcc.target/powerpc/vec-gnb-5.c: Delete.
* gcc.target/powerpc/vec-gnb-6.c: Delete.
* gcc.target/powerpc/vec-gnb-7.c: Delete.
Carl Love [Tue, 12 May 2020 02:22:07 +0000 (21:22 -0500)]
rs6000: Add xxgenpcvwm and xxgenpcvdm
Add support for xxgenpcv[dw]m, along with individual and overloaded
built-in functions for access.
[gcc]
2020-05-11 Carl Love <cel@us.ibm.com>
* config/rs6000/altivec.h (vec_genpcvm): New #define.
* config/rs6000/rs6000-builtin.def (XXGENPCVM_V16QI): New built-in
instantiation.
(XXGENPCVM_V8HI): Likewise.
(XXGENPCVM_V4SI): Likewise.
(XXGENPCVM_V2DI): Likewise.
(XXGENPCVM): New overloaded built-in instantiation.
* config/rs6000/rs6000-call.c (altivec_overloaded_builtins): Add
entries for FUTURE_BUILTIN_VEC_XXGENPCVM.
(altivec_expand_builtin): Add special handling for
FUTURE_BUILTIN_VEC_XXGENPCVM.
(builtin_function_type): Add handling for
FUTURE_BUILTIN_XXGENPCVM_{V16QI,V8HI,V4SI,V2DI}.
* config/rs6000/vsx.md (VSX_EXTRACT_I4): New mode iterator.
(UNSPEC_XXGENPCV): New constant.
(xxgenpcvm_<mode>_internal): New insn.
(xxgenpcvm_<mode>): New expansion.
* doc/extend.texi: Add documentation for vec_genpcvm built-ins.
[gcc/testsuite]
2020-05-11 Carl Love <cel@us.ibm.com>
* gcc.target/powerpc/xxgenpc-runnable.c: New.
eric fang [Mon, 20 Apr 2020 08:42:01 +0000 (08:42 +0000)]
runtime: fix TestCallersNilPointerPanic
The expected result of TestCallersNilPointerPanic has changed in
GoLLVM. This CL makes some elements of the expected result optional
so that this test passes in both gccgo and GoLLVM.
Reviewed-on: https://go-review.googlesource.com/c/gofrontend/+/230138
Ian Lance Taylor [Mon, 11 May 2020 23:23:44 +0000 (16:23 -0700)]
syscall: append to environment in tests, don't clobber it
This is a partial backport of https://golang.org/cl/233318.
It's only a partial backport because part of the change was
already applied to libgo in CL 193497 as part of the update
to the Go 1.13beta1 release.
Fixes PR go/95061
Reviewed-on: https://go-review.googlesource.com/c/gofrontend/+/233359
GCC Administrator [Tue, 12 May 2020 00:16:19 +0000 (00:16 +0000)]
Daily bump.
Ian Lance Taylor [Mon, 11 May 2020 22:28:55 +0000 (15:28 -0700)]
compiler: use const std::string& in a couple of places
Use a reference to avoid copying a std::string.
Fixes go/94766
Reviewed-on: https://go-review.googlesource.com/c/gofrontend/+/233320
Kelvin Nilsen [Mon, 11 May 2020 21:33:19 +0000 (16:33 -0500)]
rs6000: Vector string isolate instructions
Adds new instructions vstribr, vstrihr, vstribl, and vstrihl, with
overloaded built-in support.
[gcc]
2020-05-11 Kelvin Nilsen <kelvin@gcc.gnu.org>
* config/rs6000/altivec.h (vec_strir): New #define.
(vec_stril): Likewise.
(vec_strir_p): Likewise.
(vec_stril_p): Likewise.
* config/rs6000/altivec.md (UNSPEC_VSTRIR): New constant.
(UNSPEC_VSTRIL): Likewise.
(vstrir_<mode>): New expansion.
(vstrir_code_<mode>): New insn.
(vstrir_p_<mode>): New expansion.
(vstrir_p_code_<mode>): New insn.
(vstril_<mode>): New expansion.
(vstril_code_<mode>): New insn.
(vstril_p_<mode>): New expansion.
(vstril_p_code_<mode>): New insn.
* config/rs6000/rs6000-builtin.def (__builtin_altivec_vstribr):
New built-in function.
(__builtin_altivec_vstrihr): Likewise.
(__builtin_altivec_vstribl): Likewise.
(__builtin_altivec_vstrihl): Likewise.
(__builtin_altivec_vstribr_p): Likewise.
(__builtin_altivec_vstrihr_p): Likewise.
(__builtin_altivec_vstribl_p): Likewise.
(__builtin_altivec_vstrihl_p): Likewise.
(__builtin_vec_strir): New overloaded built-in function.
(__builtin_vec_stril): Likewise.
(__builtin_vec_strir_p): Likewise.
(__builtin_vec_stril_p): Likewise.
* config/rs6000/rs6000-call.c (altivec_overloaded_builtins):
Define overloaded forms of __builtin_vec_strir,
__builtin_vec_stril, __builtin_vec_strir_p, and
__builtin_vec_stril_p.
* doc/extend.texi (PowerPC AltiVec Built-in Functions Available
for a Future Architecture): Add description of vec_stril,
vec_stril_p, vec_strir, and vec_strir_p built-in functions.
[gcc]
2020-05-11 Kelvin Nilsen <kelvin@gcc.gnu.org>
* gcc.target/powerpc/vec-stril-0.c: New.
* gcc.target/powerpc/vec-stril-1.c: New.
* gcc.target/powerpc/vec-stril-10.c: New.
* gcc.target/powerpc/vec-stril-11.c: New.
* gcc.target/powerpc/vec-stril-12.c: New.
* gcc.target/powerpc/vec-stril-13.c: New.
* gcc.target/powerpc/vec-stril-14.c: New.
* gcc.target/powerpc/vec-stril-15.c: New.
* gcc.target/powerpc/vec-stril-16.c: New.
* gcc.target/powerpc/vec-stril-17.c: New.
* gcc.target/powerpc/vec-stril-18.c: New.
* gcc.target/powerpc/vec-stril-19.c: New.
* gcc.target/powerpc/vec-stril-2.c: New.
* gcc.target/powerpc/vec-stril-20.c: New.
* gcc.target/powerpc/vec-stril-21.c: New.
* gcc.target/powerpc/vec-stril-22.c: New.
* gcc.target/powerpc/vec-stril-23.c: New.
* gcc.target/powerpc/vec-stril-3.c: New.
* gcc.target/powerpc/vec-stril-4.c: New.
* gcc.target/powerpc/vec-stril-5.c: New.
* gcc.target/powerpc/vec-stril-6.c: New.
* gcc.target/powerpc/vec-stril-7.c: New.
* gcc.target/powerpc/vec-stril-8.c: New.
* gcc.target/powerpc/vec-stril-9.c: New.
* gcc.target/powerpc/vec-stril_p-0.c: New.
* gcc.target/powerpc/vec-stril_p-1.c: New.
* gcc.target/powerpc/vec-stril_p-10.c: New.
* gcc.target/powerpc/vec-stril_p-11.c: New.
* gcc.target/powerpc/vec-stril_p-2.c: New.
* gcc.target/powerpc/vec-stril_p-3.c: New.
* gcc.target/powerpc/vec-stril_p-4.c: New.
* gcc.target/powerpc/vec-stril_p-5.c: New.
* gcc.target/powerpc/vec-stril_p-6.c: New.
* gcc.target/powerpc/vec-stril_p-7.c: New.
* gcc.target/powerpc/vec-stril_p-8.c: New.
* gcc.target/powerpc/vec-stril_p-9.c: New.
* gcc.target/powerpc/vec-strir-0.c: New.
* gcc.target/powerpc/vec-strir-1.c: New.
* gcc.target/powerpc/vec-strir-10.c: New.
* gcc.target/powerpc/vec-strir-11.c: New.
* gcc.target/powerpc/vec-strir-12.c: New.
* gcc.target/powerpc/vec-strir-13.c: New.
* gcc.target/powerpc/vec-strir-14.c: New.
* gcc.target/powerpc/vec-strir-15.c: New.
* gcc.target/powerpc/vec-strir-16.c: New.
* gcc.target/powerpc/vec-strir-17.c: New.
* gcc.target/powerpc/vec-strir-18.c: New.
* gcc.target/powerpc/vec-strir-19.c: New.
* gcc.target/powerpc/vec-strir-2.c: New.
* gcc.target/powerpc/vec-strir-20.c: New.
* gcc.target/powerpc/vec-strir-21.c: New.
* gcc.target/powerpc/vec-strir-22.c: New.
* gcc.target/powerpc/vec-strir-23.c: New.
* gcc.target/powerpc/vec-strir-3.c: New.
* gcc.target/powerpc/vec-strir-4.c: New.
* gcc.target/powerpc/vec-strir-5.c: New.
* gcc.target/powerpc/vec-strir-6.c: New.
* gcc.target/powerpc/vec-strir-7.c: New.
* gcc.target/powerpc/vec-strir-8.c: New.
* gcc.target/powerpc/vec-strir-9.c: New.
* gcc.target/powerpc/vec-strir_p-0.c: New.
* gcc.target/powerpc/vec-strir_p-1.c: New.
* gcc.target/powerpc/vec-strir_p-10.c: New.
* gcc.target/powerpc/vec-strir_p-11.c: New.
* gcc.target/powerpc/vec-strir_p-2.c: New.
* gcc.target/powerpc/vec-strir_p-3.c: New.
* gcc.target/powerpc/vec-strir_p-4.c: New.
* gcc.target/powerpc/vec-strir_p-5.c: New.
* gcc.target/powerpc/vec-strir_p-6.c: New.
* gcc.target/powerpc/vec-strir_p-7.c: New.
* gcc.target/powerpc/vec-strir_p-8.c: New.
* gcc.target/powerpc/vec-strir_p-9.c: New.
Kelvin Nilsen [Mon, 11 May 2020 21:25:03 +0000 (16:25 -0500)]
rs6000: Add xxeval and vec_ternarylogic
Add the xxeval insn and access it via the vec_ternarylogic built-in
function. As part of this, add support to the built-in function
infrastructure for functions that take four arguments.
[gcc]
2020-05-11 Kelvin Nilsen <wschmidt@linux.ibm.com>
* config/rs6000/altivec.h (vec_ternarylogic): New #define.
* config/rs6000/altivec.md (UNSPEC_XXEVAL): New constant.
(xxeval): New insn.
* config/rs6000/predicates.md (u8bit_cint_operand): New predicate.
* config/rs6000/rs6000-builtin.def: Add handling of new macro
RS6000_BUILTIN_4.
(BU_FUTURE_V_4): New macro. Use it.
(BU_FUTURE_OVERLOAD_4): Likewise.
* config/rs6000/rs6000-c.c (altivec_build_resolved_builtin): Add
handling for quaternary built-in functions.
(altivec_resolve_overloaded_builtin): Add special-case handling
for __builtin_vec_xxeval.
* config/rs6000/rs6000-call.c: Add handling of new macro
RS6000_BUILTIN_4 in initialization of rs6000_builtin_info,
bdesc0_arg, bdesc1_arg, bdesc2_arg, bdesc_3arg,
bdesc_altivec_preds, bdesc_abs, and bdesc_htm arrays.
(altivec_overloaded_builtins): Add definitions for
FUTURE_BUILTIN_VEC_XXEVAL.
(bdesc_4arg): New array.
(htm_expand_builtin): Add handling for quaternary built-in
functions.
(rs6000_expand_quaternop_builtin): New function.
(rs6000_expand_builtin): Add handling for quaternary built-in
functions.
(rs6000_init_builtins): Initialize builtin_mode_to_type entries
for unsigned QImode and unsigned HImode.
(builtin_quaternary_function_type): New function.
(rs6000_common_init_builtins): Add handling of quaternary
operations.
* config/rs6000/rs6000.h (RS6000_BTC_QUATERNARY): New defined
constant.
(RS6000_BTC_PREDICATE): Change value of constant.
(RS6000_BTC_ABS): Likewise.
(rs6000_builtins): Add support for new macro RS6000_BUILTIN_4.
* doc/extend.texi (PowerPC AltiVec Built-In Functions Available
for a Future Architecture): Add description of vec_ternarylogic
built-in function.
[gcc/testsuite]
2020-05-11 Kelvin Nilsen <wschmidt@linux.ibm.com>
* gcc.target/powerpc/vec-ternarylogic-0.c: New.
* gcc.target/powerpc/vec-ternarylogic-1.c: New.
* gcc.target/powerpc/vec-ternarylogic-10.c: New.
* gcc.target/powerpc/vec-ternarylogic-2.c: New.
* gcc.target/powerpc/vec-ternarylogic-3.c: New.
* gcc.target/powerpc/vec-ternarylogic-4.c: New.
* gcc.target/powerpc/vec-ternarylogic-5.c: New.
* gcc.target/powerpc/vec-ternarylogic-6.c: New.
* gcc.target/powerpc/vec-ternarylogic-7.c: New.
* gcc.target/powerpc/vec-ternarylogic-8.c: New.
* gcc.target/powerpc/vec-ternarylogic-9.c: New.
Kelvin Nilsen [Mon, 11 May 2020 21:16:15 +0000 (16:16 -0500)]
rs6000: Add pdepd and pextd
Add scalar instructions for parallel bit deposit and extract, with
built-in function support.
[gcc]
2020-05-11 Kelvin Nilsen <kelvin@gcc.gnu.org>
* config/rs6000/rs6000-builtin.def (__builtin_pdepd): New built-in
function.
(__builtin_pextd): Likewise.
* config/rs6000/rs6000.md (UNSPEC_PDEPD): New constant.
(UNSPEC_PEXTD): Likewise.
(pdepd): New insn.
(pextd): Likewise.
* doc/extend.texi (Basic PowerPC Built-in Functions Available for
a Future Architecture): Add descriptions of __builtin_pdepd and
__builtin_pextd functions.
[gcc/testsuite]
2020-05-11 Kelvin Nilsen <kelvin@gcc.gnu.org>
* gcc.target/powerpc/pdep-0.c: New.
* gcc.target/powerpc/pdep-1.c: New.
* gcc.target/powerpc/pextd-0.c: New.
* gcc.target/powerpc/pextd-1.c: New.
Kelvin Nilsen [Mon, 11 May 2020 21:09:53 +0000 (16:09 -0500)]
rs6000: Add vclrlb and vclrrb
Add new vector instructions to clear leftmost and rightmost bytes.
[gcc]
2020-05-11 Kelvin Nilsen <kelvin@gcc.gnu.org>
* config/rs6000/altivec.h (vec_clrl): New #define.
(vec_clrr): Likewise.
* config/rs6000/altivec.md (UNSPEC_VCLRLB): New constant.
(UNSPEC_VCLRRB): Likewise.
(vclrlb): New insn.
(vclrrb): Likewise.
* config/rs6000/rs6000-builtin.def (__builtin_altivec_vclrlb): New
built-in function.
(__builtin_altivec_vclrrb): Likewise.
(__builtin_vec_clrl): New overloaded built-in function.
(__builtin_vec_clrr): Likewise.
* config/rs6000/rs6000-call.c (altivec_overloaded_builtins):
Define overloaded forms of __builtin_vec_clrl and
__builtin_vec_clrr.
* doc/extend.texi (PowerPC AltiVec Built-in Functions Available
for a Future Architecture): Add descriptions of vec_clrl and
vec_clrr.
[gcc/testsuite]
2020-05-11 Kelvin Nilsen <kelvin@gcc.gnu.org>
* gcc.target/powerpc/vec-clrl-0.c: New.
* gcc.target/powerpc/vec-clrl-1.c: New.
* gcc.target/powerpc/vec-clrr-0.c: New.
* gcc.target/powerpc/vec-clrr-1.c: New.
Bill Schmidt [Mon, 11 May 2020 21:04:55 +0000 (16:04 -0500)]
Fix change log ordering from previous commit
Joseph Myers [Mon, 11 May 2020 20:42:46 +0000 (20:42 +0000)]
Update gcc .po files.
* be.po, da.po, de.po, el.po, es.po, fi.po, fr.po, hr.po, id.po,
ja.po, nl.po, ru.po, sr.po, sv.po, tr.po, uk.po, vi.po, zh_CN.po,
zh_TW.po: Update.
Kelvin Nilsen [Mon, 11 May 2020 20:10:24 +0000 (15:10 -0500)]
rs6000: Add cntlzdm and cnttzdm
Add support for new scalar instructions for counting leading or
trailing zeros under control of a bitmask.
[gcc]
2020-05-11 Kelvin Nilsen <kelvin@gcc.gnu.org>
* config/rs6000/rs6000-builtin.def (__builtin_cntlzdm): New
built-in function definition.
(__builtin_cnttzdm): Likewise.
* config/rs6000/rs6000.md (UNSPEC_CNTLZDM): New constant.
(UNSPEC_CNTTZDM): Likewise.
(cntlzdm): New insn.
(cnttzdm): Likewise.
* doc/extend.texi (Basic PowerPC Built-in Functions available for
a Future Architecture): Add descriptions of __builtin_cntlzdm and
__builtin_cnttzdm functions.
[gcc/testsuite]
2020-05-11 Kelvin Nilsen <kelvin@gcc.gnu.org>
* gcc.target/powerpc/cntlzdm-0.c: New test.
* gcc.target/powerpc/cntlzdm-1.c: New test.
* gcc.target/powerpc/cnttzdm-0.c: New test.
* gcc.target/powerpc/cnttzdm-1.c: New test.
Jason Merrill [Mon, 11 May 2020 19:46:59 +0000 (15:46 -0400)]
c++: Fix specialization of constrained member template.
The resolution of comment CA104 clarifies that we need to do direct
substitution of constraints in order to determine which member template
corresponds to an explicit specialization.
gcc/cp/ChangeLog
2020-05-11 Jason Merrill <jason@redhat.com>
Resolve C++20 NB comment CA104
* pt.c (determine_specialization): Compare constraints for
specialization of member template of class instantiation.
Jason Merrill [Mon, 11 May 2020 19:46:59 +0000 (15:46 -0400)]
c++: tree walk into TYPENAME_TYPE.
While looking at 92583/92654 it occurred to me that typename types needed
the same fix. So extract_locals_r also needs to see the TYPE_CONTEXT of a
TYPENAME_TYPE. But it must not look through a typedef.
Most tree walking in the front end wants to walk through the syntactic form
of a type of expression, and doesn't care about the type referred to by a
typedef. But min_vis_r does care.
gcc/cp/ChangeLog
2020-05-11 Jason Merrill <jason@redhat.com>
PR c++/92583
PR c++/92654
* tree.c (cp_walk_subtrees): Stop at typedefs.
Handle TYPENAME_TYPE here.
* pt.c (find_parameter_packs_r): Not here.
(for_each_template_parm_r): Clear *walk_subtrees.
* decl2.c (min_vis_r): Look through typedefs.
Jason Merrill [Mon, 11 May 2020 19:39:44 +0000 (15:39 -0400)]
c++: Better diagnostic in converted const expr.
This improves the diagnostic from
error: could not convert ‘((A<>*)(void)0)->A<>::e’ from
‘<unresolved overloaded function type>’ to ‘bool’
to
error: cannot convert ‘A<>::e’ from type ‘void (A<>::)()’ to type ‘bool’
gcc/cp/ChangeLog
2020-05-11 Jason Merrill <jason@redhat.com>
* call.c (implicit_conversion_error): Split out from...
(perform_implicit_conversion_flags): ...here.
(build_converted_constant_expr_internal): Use it.
Jason Merrill [Mon, 11 May 2020 19:39:44 +0000 (15:39 -0400)]
c++: Use of 'this' in parameter declaration [PR90748]
We were incorrectly accepting the use of 'this' at parse time and then
crashing when we tried to instantiate it. It is invalid because 'this' is
not in scope until after the function-cv-quals. So let's hoist setting
current_class_ptr up from cp_parser_late_return_type_opt into
cp_parser_direct_declarator where it can work for noexcept as well.
gcc/cp/ChangeLog
2020-05-11 Jason Merrill <jason@redhat.com>
PR c++/90748
* parser.c (inject_parm_decls): Set current_class_ptr here.
(cp_parser_direct_declarator): And here.
(cp_parser_late_return_type_opt): Not here.
(cp_parser_noexcept_specification_opt): Nor here.
(cp_parser_exception_specification_opt)
(cp_parser_late_noexcept_specifier): Remove unneeded parameters.
Harald Anlauf [Mon, 11 May 2020 19:27:11 +0000 (21:27 +0200)]
PR fortran/95053 - ICE in gfc_divide(): Bad basic type
The fix for PR 93499 introduced a too strict check in gfc_divide
that could trigger errors in the early parsing phase. Relax the
check and defer to a later stage.
gcc/fortran/
2020-05-11 Harald Anlauf <anlauf@gmx.de>
PR fortran/95053
* arith.c (gfc_divide): Do not error out if operand 2 is
non-numeric. Defer checks to later stage.
gcc/testsuite/
2020-05-11 Harald Anlauf <anlauf@gmx.de>
PR fortran/95053
* gfortran.dg/pr95053.f: New test.
Jason Merrill [Mon, 11 May 2020 18:05:46 +0000 (14:05 -0400)]
c++: Make references to __cxa_pure_virtual weak.
If a program has no other dependencies on libstdc++, we shouldn't require it
just for __cxa_pure_virtual, which is only there to give a prettier
diagnostic before crashing the program; resolving the reference to NULL will
also crash, just without the diagnostic.
gcc/cp/ChangeLog
2020-05-11 Jason Merrill <jason@redhat.com>
* decl.c (cxx_init_decl_processing): Call declare_weak for
__cxa_pure_virtual.
Jason Merrill [Mon, 11 May 2020 18:05:46 +0000 (14:05 -0400)]
c++: Improve print_tree of static_assert.
We weren't printing the condition and message of a STATIC_ASSERT.
It's also unnecessary to duplicate the code for instantiating a
STATIC_ASSERT between tsubst_expr and instantiate_class_template_1.
gcc/cp/ChangeLog
2020-05-11 Jason Merrill <jason@redhat.com>
* pt.c (instantiate_class_template_1): Call tsubst_expr for
STATIC_ASSERT member.
* ptree.c (cxx_print_xnode): Handle STATIC_ASSERT.
Jason Merrill [Mon, 11 May 2020 18:05:46 +0000 (14:05 -0400)]
c++: Remove redundant code.
We walk the lambda captures in cp_walk_subtrees, so we don't also need to
walk them here.
gcc/cp/ChangeLog
2020-05-11 Jason Merrill <jason@redhat.com>
* pt.c (find_parameter_packs_r) [LAMBDA_EXPR]: Remove redundant
walking of capture list.
Jason Merrill [Mon, 11 May 2020 18:05:46 +0000 (14:05 -0400)]
c++: Remove LOOKUP_EXPLICIT_TMPL_ARGS.
This flag is redundant with the explicit_targs field in the overload
candidate information.
gcc/cp/ChangeLog
2020-05-11 Jason Merrill <jason@redhat.com>
* cp-tree.h (LOOKUP_EXPLICIT_TMPL_ARGS): Remove.
* call.c (build_new_function_call): Don't set it.
(build_new_method_call_1): Likewise.
(build_over_call): Check cand->explicit_targs instead.
Jason Merrill [Mon, 11 May 2020 18:05:46 +0000 (14:05 -0400)]
c++: Tweak VLA representation.
If we put the SAVE_EXPR for a VLA size inside the MINUS_EXPR rather than
outside, it will work better with constant folding.
The equivalent change was made in the C front-end in 2004, in commit
r0-64535-g8b0b9aefd29dfe6398857bcf5628662e2f0e21f6
gcc/cp/ChangeLog
2020-05-11 Jason Merrill <jason@redhat.com>
* decl.c (compute_array_index_type_loc): Stabilize before building
the MINUS_EXPR.
Jason Merrill [Mon, 11 May 2020 18:05:46 +0000 (14:05 -0400)]
c++: Avoid unnecessary deprecated warnings.
There's no need to warn that a deprecated function uses a deprecated type,
that just adds noise. We were preventing that in start_decl, but that
didn't help member declarations that go through grokfield. So handle it in
grokdeclarator instead, which is shared between them.
gcc/cp/ChangeLog
2020-05-11 Jason Merrill <jason@redhat.com>
* decl.c (grokdeclarator): Adjust deprecated_state here.
(start_decl): Not here.
Uros Bizjak [Mon, 11 May 2020 18:12:14 +0000 (20:12 +0200)]
i386: Add V2SFmode sqrt insn pattern [PR95046]
gcc/ChangeLog:
2020-05-11 Uroš Bizjak <ubizjak@gmail.com>
PR target/95046
* config/i386/mmx.md (sqrtv2sf2): New insn pattern.
testsuite/ChangeLog:
2020-05-11 Uroš Bizjak <ubizjak@gmail.com>
PR target/95046
* gcc.target/i386/pr95046-1.c (test_sqrt): Add.
Ian Lance Taylor [Mon, 11 May 2020 17:51:21 +0000 (10:51 -0700)]
libbacktrace: declare getpagesize if necessary
libbacktrace/
PR libbacktrace/95012
* configure.ac: Check for getpagesize declaration.
* mmap.c: Declare getpagesize if necessary.
* mmapio.c: Likewise.
Kelvin Nilsen [Mon, 11 May 2020 16:41:23 +0000 (11:41 -0500)]
rs6000: Add vcfuged instruction
Add the new vector centrifuge-doubleword instruction and built-in
function access.
[gcc]
2020-05-11 Kelvin Nilsen <kelvin@gcc.gnu.org>
* config/rs6000/altivec.h (vec_cfuge): New #define.
* config/rs6000/altivec.md (UNSPEC_VCFUGED): New constant.
(vcfuged): New insn.
* config/rs6000/rs6000-builtin.def (__builtin_altivec_vcfuged):
New built-in function.
* config/rs6000/rs6000-call.c (builtin_function_type): Add
handling for FUTURE_BUILTIN_VCFUGED case.
* doc/extend.texi (PowerPC AltiVec Built-in Functions Available
for a Future Architecture): Add description of vec_cfuge built-in
function.
[gcc/testsuite]
2020-05-11 Kelvin Nilsen <kelvin@gcc.gnu.org>
* gcc.target/powerpc/vec-cfuged-0.c: New test.
* gcc.target/powerpc/vec-cfuged-1.c: New test.
Kelvin Nilsen [Mon, 11 May 2020 16:01:32 +0000 (11:01 -0500)]
rs6000: Add scalar cfuged instruction
Add the centifuge-doubleword instruction and built-in access.
[gcc]
2020-05-11 Kelvin Nilsen <kelvin@gcc.gnu.org>
* config/rs6000/rs6000-builtin.def (BU_FUTURE_MISC_0): New
#define.
(BU_FUTURE_MISC_1): Likewise.
(BU_FUTURE_MISC_2): Likewise.
(BU_FUTURE_MISC_3): Likewise.
(__builtin_cfuged): New built-in function definition.
* config/rs6000/rs6000.md (UNSPEC_CFUGED): New constant.
(cfuged): New insn.
* doc/extend.texi (Basic PowerPC Built-in Functions Available for
a Future Architecture): New subsubsection.
[gcc/testsuite]
2020-05-11 Kelvin Nilsen <kelvin@gcc.gnu.org>
* gcc.target.powerpc/cfuged-0.c: New test.
* gcc.target.powerpc/cfuged-1.c: New test.
Richard Biener [Mon, 11 May 2020 11:40:37 +0000 (13:40 +0200)]
tree-optimization/95049 - fix not terminating RPO VN iteration
This rejects lattice changes from one constant to another.
2020-05-11 Richard Biener <rguenther@suse.de>
PR tree-optimization/95049
* tree-ssa-sccvn.c (set_ssa_val_to): Reject lattice transition
between different constants.
* gcc.dg/torture/pr95049.c: New testcase.
Richard Sandiford [Mon, 11 May 2020 15:51:48 +0000 (16:51 +0100)]
tree-pretty-print: Handle boolean types
AVX512-style masks and SVE-style predicates can be difficult
to debug in gimple dumps, since the types are printed like this:
vector(4) <unnamed type> foo;
Some important details are hidden by that <unnamed type>,
such as the number of bits in an element and whether the type
is signed or unsigned.
This patch uses an ad-hoc syntax for printing unnamed
boolean types. Normal frontend ones should be handled
by the earlier TYPE_NAME code.
2020-05-11 Richard Sandiford <richard.sandiford@arm.com>
gcc/
* tree-pretty-print.c (dump_generic_node): Handle BOOLEAN_TYPEs.
Kelvin Nilsen [Mon, 11 May 2020 15:13:14 +0000 (10:13 -0500)]
rs6000: Add vgnb
Add support for the vgnb instruction, which gathers every Nth bit
per vector element.
[gcc]
2020-05-11 Kelvin Nilsen <kelvin@gcc.gnu.org>
Bill Schmidt <wschmidt@linux.ibm.com>
* config/rs6000/altivec.h (vec_gnb): New #define.
* config/rs6000/altivec.md (UNSPEC_VGNB): New constant.
(vgnb): New insn.
* config/rs6000/rs6000-builtin.def (BU_FUTURE_OVERLOAD_1): New
#define.
(BU_FUTURE_OVERLOAD_2): Likewise.
(BU_FUTURE_OVERLOAD_3): Likewise.
(__builtin_altivec_gnb): New built-in function.
(__buiiltin_vec_gnb): New overloaded built-in function.
* config/rs6000/rs6000-call.c (altivec_overloaded_builtins):
Define overloaded forms of __builtin_vec_gnb.
(rs6000_expand_binop_builtin): Add error checking for 2nd argument
of __builtin_vec_gnb.
(builtin_function_type): Mark return value and arguments unsigned
for FUTURE_BUILTIN_VGNB.
* doc/extend.texi (PowerPC AltiVec Built-in Functions Available
for a Future Architecture): Add description of vec_gnb built-in
function.
[gcc/testsuite]
2020-05-11 Kelvin Nilsen <kelvin@gcc.gnu.org>
Bill Schmidt <wschmidt@linux.ibm.com>
* gcc.target/powerpc/vec-gnb-0.c: New test.
* gcc.target/powerpc/vec-gnb-1.c: New test.
* gcc.target/powerpc/vec-gnb-10.c: New test.
* gcc.target/powerpc/vec-gnb-2.c: New test.
* gcc.target/powerpc/vec-gnb-3.c: New test.
* gcc.target/powerpc/vec-gnb-4.c: New test.
* gcc.target/powerpc/vec-gnb-5.c: New test.
* gcc.target/powerpc/vec-gnb-6.c: New test.
* gcc.target/powerpc/vec-gnb-7.c: New test.
* gcc.target/powerpc/vec-gnb-8.c: New test.
* gcc.target/powerpc/vec-gnb-9.c: New test.
Kelvin Nilsen [Mon, 11 May 2020 15:04:03 +0000 (10:04 -0500)]
rs6000: Add vector pdep/pext
Add support for the vpdepd and vpextd instructions that perform
vector parallel bit deposit and vector parallel bit extract.
[gcc]
2020-05-11 Kelvin Nilsen <kelvin@gcc.gnu.org>
Bill Schmidt <wschmidt@linux.ibm.com>
* config/rs6000/altivec.h (vec_pdep): New macro implementing new
built-in function.
(vec_pext): Likewise.
* config/rs6000/altivec.md (UNSPEC_VPDEPD): New constant.
(UNSPEC_VPEXTD): Likewise.
(vpdepd): New insn.
(vpextd): Likewise.
* config/rs6000/rs6000-builtin.def (__builtin_altivec_vpdepd): New
built-in function.
(__builtin_altivec_vpextd): Likewise.
* config/rs6000/rs6000-call.c (builtin_function_type): Add
handling for FUTURE_BUILTIN_VPDEPD and FUTURE_BUILTIN_VPEXTD
cases.
* doc/extend.texi (PowerPC Altivec Built-in Functions Available
for a Future Architecture): Add description of vec_pdep and
vec_pext built-in functions.
[gcc/testsuite]
2020-05-11 Kelvin Nilsen <kelvin@gcc.gnu.org>
* gcc.target/powerpc/vec-pdep-0.c: New.
* gcc.target/powerpc/vec-pdep-1.c: New.
* gcc.target/powerpc/vec-pext-0.c: New.
* gcc.target/powerpc/vec-pext-1.c: New.
Kelvin Nilsen [Mon, 11 May 2020 14:35:01 +0000 (09:35 -0500)]
rs6000: Add vector count under mask
Add support for new vclzdm and vctzdm vector instructions that
count leading and trailing zeros under control of a mask.
[gcc]
2020-05-11 Kelvin Nilsen <kelvin@gcc.gnu.org>
Bill Schmidt <wschmidt@linux.ibm.com>
* config/rs6000/altivec.h (vec_clzm): New macro.
(vec_ctzm): Likewise.
* config/rs6000/altivec.md (UNSPEC_VCLZDM): New constant.
(UNSPEC_VCTZDM): Likewise.
(vclzdm): New insn.
(vctzdm): Likewise.
* config/rs6000/rs6000-builtin.def (BU_FUTURE_V_0): New macro.
(BU_FUTURE_V_1): Likewise.
(BU_FUTURE_V_2): Likewise.
(BU_FUTURE_V_3): Likewise.
(__builtin_altivec_vclzdm): New builtin definition.
(__builtin_altivec_vctzdm): Likewise.
* config/rs6000/rs6000-c.c (rs6000_target_modify_macros): Cause
_ARCH_PWR_FUTURE macro to be defined if OPTION_MASK_FUTURE flag is
set.
* config/rs6000/rs6000-call.c (builtin_function_type): Set return
value and parameter types to be unsigned for VCLZDM and VCTZDM.
* config/rs6000/rs6000.c (rs6000_builtin_mask_calculate): Add
support for TARGET_FUTURE flag.
* config/rs6000/rs6000.h (RS6000_BTM_FUTURE): New macro constant.
* doc/extend.texi (PowerPC Altivec Built-in Functions Available
for a Future Architecture): New subsubsection.
[gcc/testsuite]
2020-05-11 Kelvin Nilsen <kelvin@gcc.gnu.org>
* gcc.target/powerpc/vec-clzm-0.c: New test.
* gcc.target/powerpc/vec-clzm-1.c: New test.
* gcc.target/powerpc/vec-ctzm-0.c: New test.
* gcc.target/powerpc/vec-ctzm-1.c: New test.
Richard Biener [Fri, 8 May 2020 10:03:30 +0000 (12:03 +0200)]
tree-optimization/94988 - enhance SM some more
This enhances store-order preserving store motion to handle the case
of non-invariant dependent stores in the sequence of unconditionally
executed stores on exit by re-issueing them as part of the sequence
of stores on the exit. This fixes the observed regression of
gcc.target/i386/pr64110.c which relies on store-motion of 'b'
for a loop like
for (int i = 0; i < j; ++i)
*b++ = x;
where for correctness we now no longer apply store-motion. With
the patch we emit the correct
tem = b;
for (int i = 0; i < j; ++i)
{
tem = tem + 1;
*tem = x;
}
b = tem;
*tem = x;
preserving the original order of stores. A testcase reflecting
the miscompilation done by earlier GCC is added as well.
This also fixes the reported ICE in PR95025 and adds checking code
to catch it earlier - the issue was not-supported refs propagation
leaving stray refs in the sequence.
2020-05-11 Richard Biener <rguenther@suse.de>
PR tree-optimization/94988
PR tree-optimization/95025
* tree-ssa-loop-im.c (seq_entry): Make a struct, add from.
(sm_seq_push_down): Take extra parameter denoting where we
moved the ref to.
(execute_sm_exit): Re-issue sm_other stores in the correct
order.
(sm_seq_valid_bb): When always executed, allow sm_other to
prevail inbetween sm_ord and record their stored value.
(hoist_memory_references): Adjust refs_not_supported propagation
and prune sm_other from the end of the ordered sequences.
* gcc.dg/torture/pr94988.c: New testcase.
* gcc.dg/torture/pr95025.c: Likewise.
* gcc.dg/torture/pr95045.c: Likewise.
* g++.dg/asan/pr95025.C: New testcase.
Tobias Burnus [Mon, 11 May 2020 14:39:20 +0000 (16:39 +0200)]
[Fortran] Fix/modify present() handling for assumed-shape optional (PR 94672)
gcc/fortran/
2020-05-07 Tobias Burnus <tobias@codesourcery.com>
PR fortran/94672
* trans.h (gfc_conv_expr_present): Add use_saved_decl=false argument.
* trans-expr.c (gfc_conv_expr_present): Likewise; use DECL directly
and only if use_saved_decl is true, use the actual PARAM_DECL arg (saved
descriptor).
* trans-array.c (gfc_trans_dummy_array_bias): Set local 'arg.0'
variable to NULL if 'arg' is not present.
* trans-openmp.c (gfc_omp_check_optional_argument): Simplify by checking
'arg.0' instead of the true PARM_DECL.
(gfc_omp_finish_clause): Remove setting 'arg.0' to NULL.
gcc/testsuite/
2020-05-07 Jakub Jelinek <jakub@redhat.com>
Tobias Burnus <tobias@codesourcery.com>
PR fortran/94672
* gfortran.dg/gomp/pr94672.f90: New.
* gfortran.dg/missing_optional_dummy_6a.f90: Update scan-tree.
Uros Bizjak [Mon, 11 May 2020 14:37:19 +0000 (16:37 +0200)]
i386: Improve basic vectorized V2SFmode operations [PR95046]
Use plain "v" constraint for AVX alternatives and add "prefix" attribute.
gcc/ChangeLog:
PR target/95046
* config/i386/mmx.md (mmx_addv2sf3): Use "v" constraint
instead of "Yv" for AVX alternatives. Add "prefix" attribute.
(*mmx_addv2sf3): Ditto.
(*mmx_subv2sf3): Ditto.
(*mmx_mulv2sf3): Ditto.
(*mmx_<code>v2sf3): Ditto.
(mmx_ieee_<ieee_maxmin>v2sf3): Ditto.
Fei Yang [Mon, 11 May 2020 14:18:47 +0000 (15:18 +0100)]
aarch64: Fix ICE when expanding scalar floating move with -mgeneral-regs-only. [PR94991]
In the testcase for PR94991, we are doing FAIL for scalar floating move expand
pattern since TARGET_FLOAT is false with option -mgeneral-regs-only. But move
expand pattern cannot fail. It would be better to replace the FAIL with code
that bitcasts to the equivalent integer mode using gen_lowpart.
2020-05-11 Felix Yang <felix.yang@huawei.com>
gcc/
PR target/94991
* config/aarch64/aarch64.md (mov<mode>):
Bitcasts to the equivalent integer mode using gen_lowpart
instead of doing FAIL for scalar floating point move.
gcc/testsuite/
PR target/94991
* gcc.target/aarch64/mgeneral-regs_5.c: New test.
Alex Coplan [Mon, 11 May 2020 14:18:46 +0000 (15:18 +0100)]
[PATCH] aarch64: prefer using csinv, csneg in zero extend contexts
Given the C code:
unsigned long long inv(unsigned a, unsigned b, unsigned c)
{
return a ? b : ~c;
}
Prior to this patch, AArch64 GCC at -O2 generates:
inv:
cmp w0, 0
mvn w2, w2
csel w0, w1, w2, ne
ret
and after applying the patch, we get:
inv:
cmp w0, 0
csinv w0, w1, w2, ne
ret
The new pattern also catches the optimization for the symmetric case where the
body of foo reads a ? ~b : c.
Similarly, with the following code:
unsigned long long neg(unsigned a, unsigned b, unsigned c)
{
return a ? b : -c;
}
GCC at -O2 previously gave:
neg:
cmp w0, 0
neg w2, w2
csel w0, w1, w2, ne
but now gives:
neg:
cmp w0, 0
csneg w0, w1, w2, ne
ret
with the corresponding code for the symmetric case as above.
2020-05-11 Alex Coplan <alex.coplan@arm.com>
gcc/
* config/aarch64/aarch64.c (aarch64_if_then_else_costs): Add case
to correctly calculate cost for new pattern (*csinv3_uxtw_insn3).
* config/aarch64/aarch64.md (*csinv3_utxw_insn1): New.
(*csinv3_uxtw_insn2): New.
(*csinv3_uxtw_insn3): New.
* config/aarch64/iterators.md (neg_not_cs): New.
gcc/testsuite/
* gcc.target/aarch64/csinv-neg.c: New test.
Kelvin Nilsen [Mon, 11 May 2020 13:49:06 +0000 (08:49 -0500)]
Fix missing files from previous commit.
Kelvin Nilsen [Mon, 11 May 2020 13:44:48 +0000 (08:44 -0500)]
rs6000: powerpc_future_ok and powerpc_future_hw
Dejagnu targets for these.
2020-05-11 Kelvin Nilsen <kelvin@gcc.gnu.org>
* gcc.target/powerpc/dg-future-0.c: New.
* gcc.target/powerpc/dg-future-1.c: New.
* lib/target-supports.exp (check_powerpc_future_hw_available):
Replace -mfuture with -mcpu=future.
(check_effective_target_powerpc_future_ok): Likewise.
(is-effective-target): Add powerpc_future_hw.
François Dumont [Mon, 11 May 2020 12:07:06 +0000 (14:07 +0200)]
Revert "libstdc++ Enhance thread safety of debug mode iterators"
This reverts commit
0b83c4fabb899fdbb3ae60ed75b7004b7859fae9.
Kito Cheng [Mon, 11 May 2020 09:51:03 +0000 (17:51 +0800)]
testsuite: Require gnu-tm support for pr94856.C
- The testcase uses the -fgnu-tm option but does not ensure that support
is enabled. This patch adds the test to the testcase.
* gcc/testsuite/g++.dg/ipa/pr94856.C: Require fgnu-tm.
Uros Bizjak [Mon, 11 May 2020 09:16:31 +0000 (11:16 +0200)]
i386: Vectorize basic V2SFmode operations [PR94913]
Enable V2SFmode vectorization and vectorize V2SFmode PLUS,
MINUS, MULT, MIN and MAX operations using XMM registers.
To avoid unwanted secondary effects (e.g. exceptions), load values
to XMM registers using MOVQ that clears high bits of the XMM
register outside V2SFmode.
The compiler now vectorizes e.g.:
float r[2], a[2], b[2];
void
test_plus (void)
{
for (int i = 0; i < 2; i++)
r[i] = a[i] + b[i];
}
to:
movq a(%rip), %xmm0
movq b(%rip), %xmm1
addps %xmm1, %xmm0
movlps %xmm0, r(%rip)
ret
gcc/ChangeLog:
PR target/95046
* config/i386/i386.c (ix86_vector_mode_supported_p):
Vectorize 3dNOW! vector modes for TARGET_MMX_WITH_SSE.
* config/i386/mmx.md (*mov<mode>_internal): Do not set
mode of alternative 13 to V2SF for TARGET_MMX_WITH_SSE.
(mmx_addv2sf3): Change operand predicates from
nonimmediate_operand to register_mmxmem_operand.
(addv2sf3): New expander.
(*mmx_addv2sf3): Add SSE/AVX alternatives. Change operand
predicates from nonimmediate_operand to register_mmxmem_operand.
Enable instruction pattern for TARGET_MMX_WITH_SSE.
(mmx_subv2sf3): Change operand predicate from
nonimmediate_operand to register_mmxmem_operand.
(mmx_subrv2sf3): Ditto.
(subv2sf3): New expander.
(*mmx_subv2sf3): Add SSE/AVX alternatives. Change operand
predicates from nonimmediate_operand to register_mmxmem_operand.
Enable instruction pattern for TARGET_MMX_WITH_SSE.
(mmx_mulv2sf3): Change operand predicates from
nonimmediate_operand to register_mmxmem_operand.
(mulv2sf3): New expander.
(*mmx_mulv2sf3): Add SSE/AVX alternatives. Change operand
predicates from nonimmediate_operand to register_mmxmem_operand.
Enable instruction pattern for TARGET_MMX_WITH_SSE.
(mmx_<code>v2sf3): Change operand predicates from
nonimmediate_operand to register_mmxmem_operand.
(<code>v2sf3): New expander.
(*mmx_<code>v2sf3): Add SSE/AVX alternatives. Change operand
predicates from nonimmediate_operand to register_mmxmem_operand.
Enable instruction pattern for TARGET_MMX_WITH_SSE.
(mmx_ieee_<ieee_maxmin>v2sf3): Ditto.
testsuite/ChangeLog:
PR target/95046
* gcc.target/i386/pr95046-1.c: New test.
Mark Eggleston [Thu, 23 Apr 2020 09:33:14 +0000 (10:33 +0100)]
Fortran : Spurious warning message with -Wsurprising PR59107
This change is from a patch developed for gcc-5. The code
has moved on since then requiring a change to interface.c
2020-05-11 Janus Weil <janus@gcc.gnu.org>
Dominique d'Humieres <dominiq@lps.ens.fr>
gcc/fortran/
PR fortran/59107
* gfortran.h: Rename field resolved as resolve_symbol_called
and assign two 2 bits instead of 1.
* interface.c (check_dtio_interface1): Use new field name.
(gfc_find_typebound_dtio_proc): Use new field name.
* resolve.c (gfc_resolve_intrinsic): Replace check of the formal
field with resolve_symbol_called is at least 2, if it is not
set the field to 2. (resolve_typebound_procedure): Use new field
name. (resolve_symbol): Use new field name and check whether it
is at least 1, if it is not set the field to 1.
2020-05-11 Mark Eggleston <markeggleston@gcc.gnu.org>
gcc/testsuite/
PR fortran/59107
* gfortran.dg/pr59107.f90: New test.
Martin Liska [Mon, 11 May 2020 07:34:22 +0000 (09:34 +0200)]
Fix typo in fprofile-prefix-path.
PR c/95040
* common.opt: Fix typo in option description.
Martin Liska [Mon, 11 May 2020 07:25:46 +0000 (09:25 +0200)]
Add caveat about parsing of .gcda and .gcno files.
PR gcov-profile/94928
* gcov-io.h: Add caveat about coverage format parsing and
possible outdated documentation.
Xionghu Luo [Mon, 11 May 2020 02:06:20 +0000 (21:06 -0500)]
Add handling of MULT_EXPR/PLUS_EXPR for wrapping overflow in affine combination(PR83403)
Use determine_value_range to get value range info for fold convert expressions
with internal operation PLUS_EXPR/MINUS_EXPR/MULT_EXPR when not overflow on
wrapping overflow inner type. i.e.:
(long unsigned int)((unsigned int)n * 10 + 1)
=>
(long unsigned int)n * (long unsigned int)10 + (long unsigned int)1
With this patch for affine combination, load/store motion could detect
more address refs independency and promote some memory expressions to
registers within loop.
PS: Replace the previous "(T1)(X + CST) as (T1)X - (T1)(-CST))"
to "(T1)(X + CST) as (T1)X + (T1)(CST))" for wrapping overflow.
Bootstrap and regression tested pass on Power8-LE.
gcc/ChangeLog
2020-05-11 Xiong Hu Luo <luoxhu@linux.ibm.com>
PR tree-optimization/83403
* tree-affine.c (expr_to_aff_combination): Replace SSA_NAME with
determine_value_range, Add fold conversion of MULT_EXPR, fix the
previous PLUS_EXPR.
gcc/testsuite/ChangeLog
2020-05-11 Xiong Hu Luo <luoxhu@linux.ibm.com>
PR tree-optimization/83403
* gcc.dg/tree-ssa/pr83403-1.c: New test.
* gcc.dg/tree-ssa/pr83403-2.c: New test.
* gcc.dg/tree-ssa/pr83403.h: New header.
GCC Administrator [Mon, 11 May 2020 00:16:19 +0000 (00:16 +0000)]
Daily bump.
Gerald Pfeifer [Thu, 7 May 2020 22:48:52 +0000 (00:48 +0200)]
i386: Define __ILP32__ and _ILP32 for all 32-bit targets
* config/i386/i386-c.c (ix86_target_macros): Define _ILP32 and
__ILP32__ for 32-bit targets.
François Dumont [Sat, 29 Feb 2020 17:22:55 +0000 (18:22 +0100)]
libstdc++ Enhance thread safety of debug mode iterators
Avoids race condition when checking for an iterator to be singular or
to be comparable to another iterator.
* src/c++/debug.cc
(_Safe_sequence_base::_M_attach_single): Set attached iterator
sequence pointer and version.
(_Safe_sequence_base::_M_detach_single): Reset detached iterator.
(_Safe_iterator_base::_M_attach): Remove attached iterator sequence
pointer and version asignments.
(_Safe_iterator_base::_M_attach_single): Likewise.
(_Safe_iterator_base::_M_detach_single): Remove detached iterator
reset.
(_Safe_iterator_base::_M_singular): Use atomic load to access parent
sequence.
(_Safe_iterator_base::_M_can_compare): Likewise.
(_Safe_iterator_base::_M_get_mutex): Likewise.
(_Safe_local_iterator_base::_M_attach): Remove attached iterator container
pointer and version assignments.
(_Safe_local_iterator_base::_M_attach_single): Likewise.
(_Safe_unordered_container_base::_M_attach_local_single):
Set attached iterator container pointer and version.
(_Safe_unordered_container_base::_M_detach_local_single): Reset detached
iterator.
Harald Anlauf [Sun, 10 May 2020 17:46:06 +0000 (19:46 +0200)]
PR fortran/93499 - ICE on division by zero in declaration statements
Division by zero in declaration statements could sometimes
generate NULL pointers being passed around that lead to ICEs.
2020-05-10 Harald Anlauf <anlauf@gmx.de>
gcc/fortran/
PR fortran/93499
* arith.c (gfc_divide): Catch division by zero.
(eval_intrinsic_f3): Safeguard for NULL operands.
gcc/testsuite/
PR fortran/93499
* gfortran.dg/pr93499.f90: New test.
Ian Lance Taylor [Sun, 10 May 2020 03:34:25 +0000 (20:34 -0700)]
libbacktrace: don't crash if ELF file has no sections
libbacktrace/
* elf.c (elf_add): Bail early if there are no section headers at all.
GCC Administrator [Sun, 10 May 2020 00:16:19 +0000 (00:16 +0000)]
Daily bump.
Ian Lance Taylor [Wed, 19 Feb 2020 18:30:51 +0000 (10:30 -0800)]
libbacktrace: don't free ELF strtab if error occurs after saving syminfo
* elf.c (elf_add): Don't free strtab if an error occurs after
recording symbol information.
Ian Lance Taylor [Sun, 16 Feb 2020 13:20:01 +0000 (05:20 -0800)]
libbacktrace: add Mach-O support
libbacktrace/
PR libbacktrace/88745
* macho.c: New file.
* filetype.awk: Recognize Mach-O files.
* Makefile.am (FORMAT_FILES): Add macho.c.
(check_DATA): New variable. Set to .dSYM if HAVE_DSYMUTIL.
(%.dSYM): New pattern target.
(test_macho_SOURCES, test_macho_CFLAGS): New targets.
(test_macho_LDADD): New target.
(BUILDTESTS): Add test_macho.
(macho.lo): Add dependencies.
* configure.ac: Recognize macho file type. Check for
mach-o/dyld.h. Don't try to run objcopy if we don't find it.
Look for dsymutil and define a HAVE_DSYMUTIL conditional.
* Makefile.in: Regenerate.
* configure: Regenerate.
* config.h.in: Regenerate.
Ian Lance Taylor [Sun, 16 Feb 2020 02:13:28 +0000 (18:13 -0800)]
libbacktrace: support short read
* read.c (backtrace_get_view): Support short read.
Ian Lance Taylor [Sun, 16 Feb 2020 01:56:35 +0000 (17:56 -0800)]
libbacktrace: sometimes read debug sections individually
libbacktrace/
* elf.c (elf_add): If debug sections are very large or far apart,
read them individually rather than as a single view.
Ian Lance Taylor [Sat, 15 Feb 2020 23:29:02 +0000 (15:29 -0800)]
libbacktrace: support fetching executable name using sysctl
This supports FreeBSD and NetBSD when /proc is not mounted.
libbacktrace/
* fileline.c (sysctl_exec_name): New static function.
(sysctl_exec_name1): New macro or static function.
(sysctl_exec_name2): Likewise.
(fileline_initialize): Try sysctl_exec_name[12].
* configure.ac: Check for sysctl args to fetch executable name.
* configure: Regenerate.
* config.h.in: Regenerate.
Eric Botcazou [Sat, 9 May 2020 21:17:39 +0000 (23:17 +0200)]
Update copyright year
Eric Botcazou [Sat, 9 May 2020 21:08:18 +0000 (23:08 +0200)]
Add assertion for access attributes
* gcc-interface/trans.c (Attribute_to_gnu) <Attr_Access>: Assert
that the prefix is not a type.
Eric Botcazou [Sat, 9 May 2020 21:04:38 +0000 (23:04 +0200)]
Fix small issues with -fgnat-encodings=minimal
This is the mode where the GNAT compiler does not use special encodings
in the debug info to describe some Ada constructs, for example packed
array types.
* gcc-interface/ada-tree.h (TYPE_PACKED_ARRAY_TYPE_P): Rename into...
(TYPE_BIT_PACKED_ARRAY_TYPE_P): ...this.
(TYPE_IS_PACKED_ARRAY_TYPE_P): Rename into...
(BIT_PACKED_ARRAY_TYPE_P): ...this.
(TYPE_IMPL_PACKED_ARRAY_P): Adjust to above renaming.
* gcc-interface/gigi.h (maybe_pad_type): Remove IS_USER_TYPE..
* gcc-interface/decl.c (gnat_to_gnu_entity) <E_Variable>: Adjust
call to maybe_pad_type.
<E_Ordinary_Fixed_Point_Type>: Remove const qualifiers for tree.
<E_Signed_Integer_Subtype>: Remove redundant test and redundant call
to associate_original_type_to_packed_array. Turn into assertion.
Call associate_original_type_to_packed_array and modify
gnu_entity_name accordingly. Explicitly set the parallel type
for GNAT encodings.
Call create_type_decl in the misaligned case before maybe_pad_type.
<E_Array_Type>: Do not use the name of the implementation type for
a packed array when not using GNAT encodings.
<E_Array_Subtype>: Move around setting flags. Use the result of the
call to associate_original_type_to_packed_array for gnu_entity_name.
<E_Record_Subtype>: Create XVS type and XVZ variable only if debug
info is requested for the type.
Call create_type_decl if a padded type was created for a type entity
(gnat_to_gnu_component_type): Use local variable and adjust calls to
maybe_pad_type.
(gnat_to_gnu_subprog_type): Adjust call to maybe_pad_type.
(gnat_to_gnu_field): Likewise.
(validate_size): Adjust to renaming of macro.
(set_rm_size): Likewise.
(associate_original_type_to_packed_array): Adjust return type and
return the name of the original type if GNAT encodings are not used
* gcc-interface/misc.c (gnat_get_debug_typ): Remove obsolete stuff.
(gnat_get_fixed_point_type_info): Remove const qualifiers for tree.
(gnat_get_array_descr_info): Likewise and set variables lazily.
Remove call to maybe_debug_type. Simplify a few computations.
(enumerate_modes): Remove const qualifier for tree.
* gcc-interface/utils.c (make_type_from_size): Adjust to renaming.
(maybe_pad_type): Remove IS_USER_TYPE parameter and adjust. Remove
specific code for implementation types for packed arrays.
(compute_deferred_decl_context): Remove const qualifier for tree.
(convert): Adjust call to maybe_pad_type.
(unchecked_convert): Likewise.
* gcc-interface/utils2.c (is_simple_additive_expressio): Likewise.
Eric Botcazou [Sat, 9 May 2020 20:56:14 +0000 (22:56 +0200)]
Fix tree sharing issue with slices
This can happen because we build an array type on the fly in case there
is an apparent type inconsistency in the construct.
* gcc-interface/utils2.c (build_binary_op) <ARRAY_RANGE_REF>: Use
build_nonshared_array_type to build the common type and declare it.
Eric Botcazou [Sat, 9 May 2020 20:52:21 +0000 (22:52 +0200)]
Do not override -fnon-call-exceptions in default mode
This was already the case in -gnatp mode.
* gcc-interface/misc.c (gnat_init_gcc_eh): Do not override the user
for -fnon-call-exceptions in default mode.
Eric Botcazou [Sat, 9 May 2020 20:44:39 +0000 (22:44 +0200)]
Do not make a local copy of large aggregate
This prevents gigi from making a local copy of large aggregates.
* gcc-interface/trans.c (lvalue_required_p) <N_Selected_Component>:
Merge with N_Slice.
<N_Allocator>: Move to...
(lvalue_for_aggregate_p): ...here. New function.
(Identifier_to_gnu): For an identifier with aggregate type, also
call lvalue_for_aggregate_p if lvalue_required_p returned false
before substituting the identifier with the constant.
Eric Botcazou [Sat, 9 May 2020 20:38:29 +0000 (22:38 +0200)]
Fix problematic cases of wrapping
* gcc-interface/trans.c (gnat_to_gnu): Do not wrap boolean values
if they appear in any kind of attribute references.
Eric Botcazou [Sat, 9 May 2020 20:36:11 +0000 (22:36 +0200)]
Accept qualified aggregates in memset path
Aggregates can be surrounded by a qualified expression and this
prepares the support code in gigi for accepting them.
* gcc-interface/trans.c (gnat_to_gnu) <N_Assignment_Statement>: Deal
with qualified "others" aggregates in the memset case.
Eric Botcazou [Sat, 9 May 2020 20:26:25 +0000 (22:26 +0200)]
Fix missing back-annotation for Out parameter
This happens when it is passed by copy and not passed in.
* gcc-interface/decl.c (gnat_to_gnu_param): Also back-annotate the
mechanism in the case of an Out parameter only passed by copy-out.
Eric Botcazou [Sat, 9 May 2020 20:01:24 +0000 (22:01 +0200)]
Small housekeeping work in gigi
No functional changes.
* gcc-interface/gigi.h (change_qualified_type): Move around.
(maybe_vector_array): Likewise.
(maybe_padded_object): New static line function.
* gcc-interface/trans.c (Attribute_to_gnu) <Attr_Component_Size>:
Remove useless code.
<Attr_Null_Parameter>: Remove obsolete code.
(Call_to_gn): Likewise. Use maybe_padded_object to remove padding.
(gnat_to_gnu): Likewise.
<N_String_Literal>: Do not add a useless null character at the end.
<N_Indexed_Component>: Likewise and remove obsolete code.
(add_decl_expr): Likewise.
(maybe_implicit_deref): Likewise.
* gcc-interface/utils.c (maybe_unconstrained_array): Likewise.
* gcc-interface/utils2.c (gnat_invariant_expr): Likewise.
Eric Botcazou [Sat, 9 May 2020 19:37:13 +0000 (21:37 +0200)]
Remove last use of expr_align
It was in the ada/gcc-interface repository and is outdated.
* tree.h (expr_align): Delete.
* tree.c (expr_align): Likewise.
ada/
* gcc-interface/utils2.c: Include builtins.h.
(known_alignment) <ADDR_EXPR>: Use DECL_ALIGN for DECL_P operands
and get_object_alignment for the rest.
Jakub Jelinek [Sat, 9 May 2020 18:27:40 +0000 (20:27 +0200)]
testsuite: Fix up two testcases [PR95008]
two-types-6.c never emitted the warning, even in 4.5/4.6, and pr93382.c
doesn't have properly escaped parens, so doesn't check whether they are
literally present in the message.
2020-05-09 Jakub Jelinek <jakub@redhat.com>
PR testsuite/95008
* gcc.dg/two-types-6.c: Remove dg-warning directive that never
triggered.
* gcc.dg/analyzer/pr93382.c: Properly escape ()s in the diagnostic
message.
Hans-Peter Nilsson [Thu, 6 Feb 2020 17:12:11 +0000 (18:12 +0100)]
cris: Enable "neg" to set condition codes.
While gcc seems to prefer transforming tests on the result of
reversible operations, into tests on the original, it also can
work with the destination, if allocated to the same register as
it commonly-enough is. The re-use is easily covered in a
test-case. (N.B.: the value 0x80000000 appears to be considered
invalid and unimportant.) Spotted as a "microregression" in
libgcc when comparing to the cc0 version.
gcc:
* config/cris/cris.c (cris_select_cc_mode): Return CC_NZmode for
NEG too. Correct comment.
* config/cris/cris.md ("<anz>neg<mode>2<setnz>"): Rename from
"neg<mode>2".
Hans-Peter Nilsson [Thu, 6 Feb 2020 03:46:34 +0000 (04:46 +0100)]
cris: Enable single-bit btst/btstq to set condition codes.
Enables the use of btst / btstq for a single bit (at other bits
than 0, including as indicated by a variable) to set
condition-codes. There's also a bug-fix for the bit-0-btstq
pattern; it shouldn't generate CCmode as only the Z flag is
valid, still using CC_NZmode is ok, as only equality-tests are
generated. The cris_rtx_costs tweak is necessary or else
combine will consider the btst not preferable. It reduces the
difference to cc0-costs beyond the threshold to the
transformation being seen as profitable, but there's still a
difference in values for the pre-split-time btst+branch as
opposed to the cc0 btst and branch, with both appearing to be
the cost of several insns (18 and 22).
gcc:
* config/cris/cris-modes.def (CC_ZnN): New CC_MODE.
* config/cris/cris.c (cris_rtx_costs): Handle pre-split bit-test
* config/cris/cris.md (ZnNNZSET, ZnNNZUSE): New mode_iterators.
(znnCC, rznnCC): New code_attrs.
("*btst<mode>"): Iterator over ZnNNZSET instead of NZVCSET. Remove
obseolete comment. Add belt-and-suspenders mode-test to condition.
Add fixme regarding remaining matched-but-not-generated case.
("*cbranch<mode>4_btstrq1_<CC>"): New insn_and_split.
("*cbranch<mode>4_btstqb0_<CC>"): Rename from
"*cbranch<mode>4_btstq<CC>". Split to CC_NZ instead of CC.
("*b<zcond:code><mode>"): Iterate over ZnNNZUSE instead of NZUSE.
Handle output of CC_ZnNmode.
("*b<nzcond:code>_reversed<mode>"): Ditto.
Hans-Peter Nilsson [Mon, 3 Feb 2020 02:15:01 +0000 (03:15 +0100)]
cris: Enable 32-bit shifts, clz, bswap, umin to set condition codes.
Enables dropping of compares with zero of the result, through
any CCmode substitution.
gcc:
* config/cris/cris.md
("<acc><anz><anzvc><shlr>si3<setcc><setnz><setnzvc>"): Rename
from "<shlr>si3".
("<acc><anz><anzvc>clzsi2<setcc><setnz><setnzvc>"): Rename
from "clzsi2".
("<acc><anz><anzvc>bswapsi2<setcc><setnz><setnzvc>"): Rename
from "bswapsi2".
("*uminsi3<setcc><setnz><setnzvc>"): Rename from "*uminsi3".
Hans-Peter Nilsson [Sun, 2 Feb 2020 11:57:12 +0000 (12:57 +0100)]
cris: Enable general "and", "or", "xor", "not" to set condition codes.
Enabling dropping of compares with zero of the result, through
any CCmode substitution. Beware that this will cause
size-suboptimal operands to appear for e.g. 32-bit "and":
-65536, -256, 255, 65535; for 16-bit "and" -256, -31..-1, 255;
for 8-bit "and" -31..-1. Fixed for 0..31 for 16- and 8-bit
sizes as it seemed worthwhile and used in libgcc.
gcc:
* config/cris/cris.md ("*expanded_andsi<setcc><setnz><setnzvc>"):
Rename from "*expanded_andsi".
("*iorsi3<setcc><setnz><setnzvc>"): Similar from "*iorsi3".
Decorate "cc" attribute to make "cc<cccc><ccnz><ccnzvc>".
("*iorhi3<setcc><setnz><setnzvc>"): Similar from "*iorhi3".
("*iorqi3<setcc><setnz><setnzvc>"): Similar from "*iorqi3".
("*expanded_andhi<setcc><setnz><setnzvc>"): Similar from
"*expanded_andhi". Add quick cc-setting alternative for 0..31.
("*andqi3<setcc><setnz><setnzvc>"): Similar from "*andqi3".
("<acc><anz><anzvc>xorsi3<setcc><setnz><setnzvc>"): Rename
from "xorsi3".
("<acc><anz><anzvc>one_cmplsi2<setcc><setnz><setnzvc>"): Rename
from "one_cmplsi2".
Hans-Peter Nilsson [Fri, 31 Jan 2020 15:03:15 +0000 (16:03 +0100)]
cris: Enable additions and subtractions to set condition codes.
Enabling dropping of compares with zero of the result, through
the non-VC-setting CCmode substitution. Beware that the
substitutions for 8- and 16-bit patterns will in some cases be
size-neutral; e.g. replacing an "addq 1..63,$rN" + "test.w $rN"
or "subq 1..63,$rN" + "test.w $rN" with an "add.w -63..63,$rN".
gcc:
* config/cris/cris.md ("*adddi3<setnz>"): Rename from "*adddi3".
cris: Enable 32-bit addition to set condition codes.
("*subdi3<setnz>"): Similarly from "*subdi3".
("*addsi3<setnz>"): Similarly from "*addsi3".
("*subsi3<setnz>"): Similarly from "*subsi3".
("*addhi3<setnz>"): Similarly from "*addhi3" and decorate the
"cc" attribute to "cc<ccnz>".
("*addqi3<setnz>"): Similarly from "*addqi3".
("*sub<mode>3<setnz>"): Similarly from "*sub<mode>3".
Hans-Peter Nilsson [Fri, 31 Jan 2020 07:24:43 +0000 (08:24 +0100)]
cris: Enable extend operations to SImode to set condition codes.
Enable dropping of compares with zero of the result, through the
three CCmode substitutions and the cmpelim pass.
gcc:
* config/cris/cris.md
("<acc><anz><anzvc>extend<mode>si2<setcc><setnz><setnzvc>"):
Rename from "extend<mode>si2".
("<acc><anz><anzvc>zero_extend<mode>si2<setcc><setnz><setnzvc>"):
Similar, from "zero_extend<mode>si2".
Hans-Peter Nilsson [Thu, 30 Jan 2020 16:14:12 +0000 (17:14 +0100)]
cris: Enable movhi and movqi to set condition codes. Anonymize.
Like with movsi_internal. Looks like the "cc" attribute didn't
need tweaking for "movhi", but did for "movqi". N.B.: disabled
alternatives make cause a later alternative to match.
Also, non-anonymous insns get declarations and gen_* functions.
We don't want that; even if it doesn't affect generated code
it's sloppy. (This may or may not be preferable to the
name decorations obfuscating standard pattern names.)
Also anonymize left-over non-anonymous branches; they haven't
been needing names since the cbranch pattern was made the
generic method.
gcc:
* config/cris/cris.md ("anz", "anzvc", "acc"): New define_subst_attrs.
("<acc><anz><anzvc>movhi<setcc><setnz><setnzvc>"): Rename from
"movhi". Rename "cc" attribute to "cc<cccc><ccnz><ccnzvc>".
("<acc><anz><anzvc>movqi<setcc><setnz><setnzvc>"): Similar from
"movqi". Correct contents of, and rename "cc" attribute to
"cc<cccc><ccnz><ccnzvc>".
("*b<zcond:code><mode>"): Rename from "b<zcond:code><mode>".
("*b<nzvccond:code><mode>"): Rename from "b<nzvccond:code><mode>".
("*b<rnzcond:code><mode>"): Rename from "*b<rnzcond:code><mode>".
Hans-Peter Nilsson [Thu, 30 Jan 2020 07:34:31 +0000 (08:34 +0100)]
cris: Enable *movsi_internal to set condition codes.
Completion of, and first use of, the CRIS-specific parts of the
condition-code-setting framework, making use of the define_subst
machinery and the cmpelim optimization pass. This round, just
moves in SImode. Note the re-use of the cc0 era "cc" attribute
(tweaks needed).
gcc:
* config/cris/cris.md ("cc"): Comment on new use.
("cc_enabled"): New attribute.
("enabled"): Make default fall back to cc_enabled.
("setnz", "ccnz", "setnzvc", "ccnzvc", "setcc", "cccc"): New
default_subst_attrs.
("setnz_subst", "setnzvc_subst", "setcc_subst"): New default_subst.
("*movsi_internal<setcc><setnz><setnzvc>"): Rename from
"*movsi_internal". Correct contents of, and rename attribute
"cc" to "cc<cccc><ccnz><ccnzvc>".
Hans-Peter Nilsson [Mon, 10 Feb 2020 22:55:32 +0000 (23:55 +0100)]
cris: Introduce CC_NZVCmode and CC_NZmode.
This is just the framework bits of splitting CCmode into classes
where the cc-setter can merge mode (CCmode), classes where the
cc-setter must set V and C "usefully" (as well as N and Z flags)
and classes where the cc-setter is something like an arithmetic
instruction, where N and Z are valid but C and V reflect the
operation rather than a compare of the result with zero. This
should yield identical or near-identical code.
The old split of conditions into the ncond and ocond sets took
into account the transformations done by final.c:alter_cond from
cc_status.flags & CC_NO_OVERFLOW, and wasn't a reflection of the
hardware description of the conditions (i.e. whether V mattered
or not).
gcc:
Prepare for cmpelim pass to eliminate redundant compare insns.
* config/cris/cris-modes.def: New file.
* config/cris/cris-protos.h (cris_select_cc_mode): Declare.
(cris_notice_update_cc): Remove left-over declaration.
* config/cris/cris.c (TARGET_CC_MODES_COMPATIBLE): Define.
(cris_select_cc_mode, cris_cc_modes_compatible): New functions.
* config/cris/cris.h (SELECT_CC_MODE): Define.
* config/cris/cris.md (NZSET, NZUSE, NZVCSET, NZVCUSE): New
mode_iterators.
(cond): New code_iterator.
(nzcond): Replacement for incorrect ncond. All callers changed.
(nzvccond): Replacement for ocond. All callers changed.
(rnzcond): Replacement for rcond. All callers changed.
(xCC): New code_attr.
(cmp_op1c, cmp_op0c): Renumber from cmp_op1c and cmp_op2c. All
users changed.
("*cmpdi<NZVCSET:mode>"): Rename from "*cmpdi". Replace
CCmode with iteration over NZVCSET.
("*cmp_ext<BW:mode><NZVCSET:mode>"): Similarly; rename from
"*cmp_ext<mode>".
("*cmpsi<NZVCSET:mode>"): Similarly, from "*cmpsi".
("*cmp<BW:mode><NZVCSET:mode>"): Similarly from "*cmp<mode>".
("*btst<mode>"): Similarly, from "*btst".
("*cbranch<mode><code>4"): Rename from "*cbranch<mode>4",
iterating over cond instead of matching the comparison with
ordered_comparison_operator.
("*cbranch<mode>4_btstq<CC>"): Correct label operand number.
("b<zcond:code><mode>"): Rename from "b<ncond:code>", iterating
over NZUSE.
("b<nzvccond:code><mode>"): Similarly from "b<ocond:code>", over
NZVCUSE. Remove FIXME.
("*b<nzcond:code>_reversed<mode>"): Similarly from
"*b<ncond:code>_reversed", over NZUSE.
("*b<nzvccond:code>_reversed<mode>"): Similarly from
"*b<ocond:code>_reversed", over NZVCUSE. Remove FIXME.
("b<rnzcond:code><mode>"): Similarly from "b<rcond:code>",
over NZUSE. Reinstate "b<oCC>" vs. "b<CC>" mnemonic choice,
depending on CC_NZmode vs. CCmode. Remove FIXME.
("*b<rnzcond:code>_reversed<mode>"): Similarly from
"*b<rcond:code>_reversed", over NZUSE.
("*cstore<mode><code>4"): Rename from "*cstore<mode>4",
iterating over cond instead of matching the comparison with
ordered_comparison_operator.
("*s<nzcond:code><mode>"): Rename from "*s<ncond:code>",
iterating over NZUSE.
("*s<rnzcond:code><mode>"): Similar from "*s<rcond:code>", over
NZUSE. Reinstate "b<oCC>" vs. "b<CC>" mnemonic choice,
depending on CC_NZmode vs. CCmode.
("*s<nzvccond:code><mode>"): Simlar from "*s<ocond:code>", over
NZVCUSE. Remove FIXME.
Hans-Peter Nilsson [Mon, 27 Jan 2020 23:59:41 +0000 (00:59 +0100)]
cris.md: Post-reload, split/generate clobberless zero source moves
A separated follow-up to the previous change: Also emit moves
from zero as not clobbering condition-codes.
(note: actually folded into the previous ChangeLog-entry)
gcc:
* config/cris/cris.md ("movsi"): For a zero-source post-reload,
generate a clobberless variant.
("*mov_fromzero<mode>_split"): New split.
("*mov_fromzero<mode>"): New insn.
Hans-Peter Nilsson [Mon, 27 Jan 2020 03:24:59 +0000 (04:24 +0100)]
cris.md: Post-reload, split/generate clobberless memory destination moves
In preparation for compare-elimination (for it to be obviously
useful), we have to have some common insn in-between that
doesn't clobber condition-codes. A move to memory is an obvious
choice. Note the FIXME: we can do this for a zero source too;
later.
gcc:
* config/cris/cris.md ("movsi"): For memory destination
post-reload, generate clobberless variant.
("*mov_tomem<mode>_split"): New split.
("*mov_tomem<mode>"): New insn.
("enabled", mov_tomem_enabled): Define and use to exclude "x" ->
"Q>m" for less-than-SImode.
Hans-Peter Nilsson [Mon, 27 Jan 2020 00:33:42 +0000 (01:33 +0100)]
config/cris/cris.h (REVERSIBLE_CC_MODE): Define to true.
For some reason (like a buglet in the user in jump.c), defining this makes
a beneficial difference in ledf2, thus this is separated to its own commit.
Also, add comment on (not defining) REVERSE_CONDITION.
gcc:
* config/cris/cris.h (REVERSIBLE_CC_MODE): Define to true.
Hans-Peter Nilsson [Thu, 23 Jan 2020 19:24:36 +0000 (20:24 +0100)]
cris: Define TARGET_FLAGS_REGNUM.
This made a whole lot of difference regarding regressions in the
delay-slot filling. Before this, comparing __lshrdi3 for v10
before/after decc0ration and other nearby functions was worse by
several missing delay-slot fills; now down to 1.
Also, add a comment about *not* defining
TARGET_FIXED_CONDITION_CODE_REGS.
gcc:
* config/cris/cris.c (TARGET_FLAGS_REGNUM): Define.
Hans-Peter Nilsson [Thu, 23 Jan 2020 01:30:49 +0000 (02:30 +0100)]
cris: Emit trivial btstq expected by gcc.target/cris/sync-2i.c, sync-2c.c
As the added FIXME says, the new insn_and_split generates only a
small subset of the bit-tests that can be matched by "*btst" and
that were emitted by the undecc0rated cris.md at combine-time,
but it's naturally separable from a general variant by being
just what's needed for the test-cases that were previously
xfailed, and that no additional CCmodes are required.
gcc:
PR target/93372
* config/cris/cris.md (zcond): New code_iterator.
("*cbranch<mode>4_btstq<CC>"): New insn_and_split.
Hans-Peter Nilsson [Wed, 22 Jan 2020 04:54:15 +0000 (05:54 +0100)]
cris: Move trivially from cc0 to reg:CC model, removing most optimizations.
In the parlance of <https://gcc.gnu.org/wiki/CC0Transition>,
this is a basic "type 2" conversion, without
condition-code-related optimizations (just plain CCmode), but
with "cstore{M}4" defined. CRIS is somewhat similar to the
m68k; most instructions affect condition-codes. To wit, it
lacks sufficient instructions to compose an arbitrary valid
address in a register, specifically from a valid address where
involved registers have to be spilled or adjusted, without
affecting condition-codes in CRIS_CC0_REGNUM aka. dccr.
On the other hand, moving dccr to and from a stackpointer-plus-
constant-offset-address *can* be done without additional register
use, and moving to or from a general register does not affect
it. There's no instruction to add a constant to a register or
to put a constant in a register, without affecting dccr, but
there *is* an instruction to add a register (optionally scaled)
to another without affecting dccr (i.e. "addi"). Also, moves
*to* memory from any register do not affect dccr, and likewise
between another special registers and a general register. Maybe
some of that opens up the solution-space to a better solution
than clobbering dccr until reload_completed; to be investigated.
FAOD: I know what to do in the direction of defining and using
additional CCmodes, but prefer to do the full transition in
smaller steps.
Regarding the similarity to m68k, I didn't follow the steps of
the m68k cc0 transition, making use of the final_postscan_insn
hook as with the a NOTICE_UPDATE_CC machinery. For one, because
it seems to be lacking in that it keeps compare-elimination
restricted to output-time, but also because it seems a bad match
considering that CRIS has delay-slots; better try to eliminate
compares earlier. Another approach which I originally intended
to implement, that of the visium port of defining three variants
for most insns (not counting the define_subst expansions;
unaffecting-before-reload, clobbering and setting), seems
overworked and bloating the machine description. I may be
proven wrong, but I prefer we fix gcc if some something bails on
seeing a parallel with a clobber of that specific hard-register.
Also, I chose to remove most anonymous combination-matching
patterns; matchers, splitters and peepholes instead of
converting them to add clobbers of CRIS_CC0_REGNUM. There are
exclusions: those covered in the test-suite, if trivial enough.
Many of these patterns are used to handle the side-effect-
assignment addressing-modes as put together by combine: a
"prefix instruction" before the main instruction, where the main
instruction uses the post-incremented-register addressing-mode
and the "left-over" instruction-field in the prefixed insn to
assign a register. An example: the hopefully descriptive
"move.d $r9,[$r0=$r1+1234]" compared to "move.d $r9,[$r1+1234]";
both formed by the prefix insn "biap.w 1234,$r1" before
respectively "move.d $r9,[$r0+]" and "move.d $r9,[$r0]". Other
prefix variants exist. Useful, but optional, except where
side-effect assignment was used in a special case in the
function prologue; adjusted to a less optimal combination.
Support like the function cris_side_effect_mode_ok is kept.
I intend to put back as many as I find use for, of those
anonymous patterns in a controlled manner, with self-contained
test-cases proving their usability, rather than symmetry with
other instructions and similar addressing modes, which guided
the original introduction. I've entered pr93372 to track code
performance regressions related to this transition, with focus
on target-side causes and fixes; besides the function prologue
special-case, there were some checking presence of the bit-test
(btstq) instruction.
The now-gone "tst<mode>" patterns deserve a comment too: they
were an artefact from pre-"cbranch" era, now fully folded into
the "cmp<mode>" patterns.
I've left the now-unused "cc" insn attribute in, for the time
being; to be removed, used or transformed to be useful with
further work to fix pr93372. It can't be used as is, because
"normal" doesn't mean "like a compare instruction" but "handled
by NOTICE_UPDATE_CC" and may in fact be reflecting e.g. reverse
operands, something that bit me during the conversion.
gcc:
Move trivially from cc0 to reg:CC model, removing most optimizations.
* config/cris/cris.md: Remove all side-effect patterns and their
splitters. Remove most peepholes. Add clobbers of CRIS_CC0_REGNUM
to all but post-reload control-flow and movem insns. Remove
constraints on all modified expanders. Remove obsoleted cc0-related
references.
(attr "cc"): Remove alternative "rev".
(mode_iterator BWDD, DI_, SI_): New.
(mode_attr sCC_destc, cmp_op1c, cmp_op2c): New.
("tst<mode>"): Remove; fold as "M" alternative into compare insn.
("mstep_shift", "mstep_mul"): Remove patterns.
("s<rcond>", "s<ocond>", "s<ncond>"): Anonymize.
* config/cris/cris.c: Change all non-condition-code,
non-control-flow emitted insns to add a parallel with clobber of
CRIS_CC0_REGNUM, mostly by changing from gen_rtx_SET with
emit_insn to use of emit_move_insn, gen_add2_insn or
cris_emit_insn, as convenient.
(cris_reg_overlap_mentioned_p)
(cris_normal_notice_update_cc, cris_notice_update_cc): Remove.
(cris_movem_load_rest_p): Don't assume all elements in a
PARALLEL are SETs.
(cris_store_multiple_op_p): Ditto.
(cris_emit_insn): New function.
* cris/cris-protos.h (cris_emit_insn): Declare.
Hans-Peter Nilsson [Wed, 22 Jan 2020 04:52:16 +0000 (05:52 +0100)]
gcc/config/cris: Remove shared-library and CRIS v32 support.
Part of the removal of crisv32-* and cris-*-linux* (cris-elf remains).
Essentially everything is gone, including functions and
target-specific definitions and most obvious knock-on effects,
like removing unused functions and arguments.
There's one exception: the register-class effects of the CRIS v32
ACR register are deliberately excluded and left in (i.e. its
use by-number is removed and the ACE_REGS regclass is always
unusable - but present). Changing register class definitions to
remove ACR_REGS and related classes (folding their uses into
remaining classes), causes extra register moves in libgcc (as an
immediate observation; actual net effect unknown), which is
unwanted both for performance reasons and also causing extra
work comparing before/after cc0-machinery-conversion changes
ahead. The actual cause and solution for these negative effects
of cleaning up the register-classes will at the moment have to
remain to-be-investigated.
If CRIS v32 support is reinstated, consider doing the .md part
not as separate patterns with opposite conditions but merged
patterns with necessarily-different alternatives using the
"enabled" attribute (which was not invented back then).
Also, a single ACR-related RTL-dump example in a cris.md
comment, related to a strict_low_part issue is kept, but marked
as obsolete.
Note that the "b" register-constraint (non-ACR registers; can be
used for post-increment) is left in, as that may have extant
uses outside of gcc. Its availability is tested by
gcc.target/cris/asm-b-1.c. When ACR register classes are
removed, it's probably best to make it equal to GENERAL_REGS.
gcc:
* config/cris: Remove shared-library and CRIS v32 support.
Hans-Peter Nilsson [Wed, 22 Jan 2020 04:49:24 +0000 (05:49 +0100)]
gcc/config/cris/t-elfmulti: Remove crisv32 multilib.
Part of the removal of crisv32-* and cris-*-linux* (cris-elf remains).
gcc:
* config/cris/t-elfmulti: Remove crisv32 multilib.
Hans-Peter Nilsson [Wed, 22 Jan 2020 04:47:41 +0000 (05:47 +0100)]
gcc/testsuite: Remove traces of crisv32-* outside gcc.target/cris
Part of the removal of crisv32-* and cris-*-linux* (cris-elf remains).
Uses of "cris*" (as opposed to "cris") are deliberately left unadjusted.
gcc/testsuite:
* gcc.dg/
20020919-1.c, gcc.dg/pr31866.c, gcc.dg/pr46647.c,
gcc.dg/sibcall-10.c, gcc.dg/sibcall-3.c, gcc.dg/sibcall-4.c,
gcc.dg/sibcall-9.c, gcc.dg/torture/cris-asm-mof-1.c,
gcc.dg/torture/cris-volatile-1.c, gcc.dg/torture/pr38948.c,
gcc.dg/tree-ssa/
20040204-1.c, gcc.dg/tree-ssa/loop-1.c,
gcc.dg/weak/typeof-2.c, lib/target-supports.exp: Remove remaining
traces of crisv32-*.
Hans-Peter Nilsson [Wed, 22 Jan 2020 04:45:59 +0000 (05:45 +0100)]
gcc/testsuite: gcc.target/cris: Remove crisv32-* and cris-linux-* tests.
Part of the removal of crisv32-* and cris-*-linux* (cris-elf remains).
After this, within gcc.target, grep -i v32 and grep -i linux
finds no matches, except for a comment in
gcc.target/cris/asmreg-1.c, now grammar-corrected.
gcc/testsuite:
* gcc.target/cris/: Adjust for removing crisv32-* and cris-linux-*.
Hans-Peter Nilsson [Wed, 22 Jan 2020 04:44:32 +0000 (05:44 +0100)]
libgcc: cris: Remove support for crisv32-*-* and cris*-*-linux
Part of the removal of crisv32-* and cris-*-linux* (cris-elf remains).
libgcc:
* config.host: Remove support for crisv32-*-* and cris*-*-linux.
* config/cris/libgcc-glibc.ver, config/cris/t-linux: Remove.
Hans-Peter Nilsson [Wed, 22 Jan 2020 04:42:42 +0000 (05:42 +0100)]
cris: Remove from gcc/config/cris: t-linux, linux.h, linux.opt
Part of the removal of crisv32-* and cris-*-linux* (cris-elf remains).
gcc:
* config/cris/t-linux, config/cris/linux.h, config/cris/linux.opt:
Remove.
Hans-Peter Nilsson [Wed, 22 Jan 2020 04:39:31 +0000 (05:39 +0100)]
config.gcc: Remove support for crisv32-*-* and cris-*-linux*.
Or really, move from the obsolete targets section, to
unsupported targets section, and remove crisv32-*-* and
cris-*-linux* from the rest.
Part of the removal of crisv32-* and cris-*-linux* (cris-elf remains).
gcc:
* config.gcc: Remove support for crisv32-*-* and cris-*-linux*.
Hans-Peter Nilsson [Mon, 10 Feb 2020 03:03:43 +0000 (04:03 +0100)]
dbr: Filter-out TARGET_FLAGS_REGNUM from end_of_function_needs.
Compared to the cc0 version, I noticed a regression in
delay-slot-filling for CRIS for several functions in libgcc with
a similar layout, one being lshrdi3, where with cc0 all
delay-slots were filled, as exposed by the test-case in
gcc.target/cris/pr93372-1.c.
There's one slot that fails to be filled for the decc0rated CRIS
port. A gdb session shows it is because of the automatic
inclusion of TARGET_FLAGS_REGNUM in "registers needed at the end
of the function" because there are insns in the epilogue that
clobber the condition-code register. I'm not trying to tell a
clobber from a set, as parallels with set instead of clobber
seems likely to happen too, for targets with TARGET_FLAGS_REGNUM
set.
Other targets with delay-slots and one dedicated often-clobbered
condition-code-register should consider defining
TARGET_FLAGS_REGNUM. I noticed it improved delay-slot-filling
also in other situations than this.
(Previously approved by Jeff Law.)
gcc:
* resource.c (init_resource_info): Filter-out TARGET_FLAGS_REGNUM
from end_of_function_needs.
GCC Administrator [Sat, 9 May 2020 00:16:15 +0000 (00:16 +0000)]
Daily bump.
H.J. Lu [Fri, 8 May 2020 22:13:04 +0000 (15:13 -0700)]
switchcontext.S: Include <cet.h> and use _CET_ENDBR
When __CET__ is defined, <cet.h> should be included to add Intel CET
marker to object file and _CET_ENDBR should be placed at function entry
to indicate indirect branch target.
* libdruntime/config/x86/switchcontext.S: Include <cet.h> if
__CET__ is defined.
(_CET_ENDBR): New. Define if __CET__ is not defined.
(fiber_switchContext): Add _CET_ENDBR after .cfi_startproc.
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