Marek Olšák [Sun, 5 Jun 2022 22:56:07 +0000 (18:56 -0400)]
gallium: add PIPE_CAP_MAX_CONSTANT_BUFFER_SIZE_UINT for UBOs
We plan to report UINT32_MAX for UBOs.
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16881>
Marek Olšák [Sun, 5 Jun 2022 22:47:09 +0000 (18:47 -0400)]
gallium: rename PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE to *_BUFFER0_*
UBOs will use a larger limit.
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16881>
Marek Olšák [Mon, 6 Jun 2022 04:26:35 +0000 (00:26 -0400)]
st/mesa: round down MaxUniformBlockSize to a multiple of 4 for piglit
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16881>
Marek Olšák [Mon, 6 Jun 2022 03:16:29 +0000 (23:16 -0400)]
st/mesa: limit MaxComputeWorkGroupCount to INT_MAX - 1 due to failing tests
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16881>
Marek Olšák [Sun, 5 Jun 2022 23:54:02 +0000 (19:54 -0400)]
mesa: change GL_MAX_SHADER_STORAGE_BLOCK_SIZE to UINT
so that we can report 4G - 1.
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16881>
Marek Olšák [Sun, 5 Jun 2022 23:54:02 +0000 (19:54 -0400)]
mesa: change GL_MAX_TEXTURE_BUFFER_SIZE to UINT
so that we can report 4G - 1.
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16881>
Marek Olšák [Mon, 6 Jun 2022 00:05:15 +0000 (20:05 -0400)]
mesa: change GL_MAX_UNIFORM_BLOCK_SIZE to UINT
to allow 4GB - 1.
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16881>
Marek Olšák [Sun, 5 Jun 2022 22:34:03 +0000 (18:34 -0400)]
mesa: change GL_MAX_COMPUTE_WORK_GROUP_COUNT to UINT
AMD wants to report UINT32_MAX here.
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16881>
Marek Olšák [Sun, 5 Jun 2022 22:30:13 +0000 (18:30 -0400)]
mesa: clamp UINT values greater than INT_MAX for glGetInteger
so that values greater than INT_MAX report INT_MAX with glGetInteger and
the full value with glGetInteger64. This allows exposing compute grid sizes
and max buffer sizes greater than INT_MAX.
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16881>
Mike Blumenkrantz [Tue, 17 May 2022 18:57:49 +0000 (14:57 -0400)]
mesa/st: use util_streaming_load_memcpy for compute pbo copying
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16732>
Mike Blumenkrantz [Thu, 2 Jun 2022 14:02:57 +0000 (10:02 -0400)]
streaming-memcpy: move to src/util/ and compile unconditionally
this is useful, so make it available for general use
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16732>
Mike Blumenkrantz [Thu, 2 Jun 2022 13:56:11 +0000 (09:56 -0400)]
mesa/streaming-memcpy: add memcpy fallback
this makes it more compatible and able to be used from the caller without ifdefs
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16732>
Emma Anholt [Mon, 6 Jun 2022 21:49:06 +0000 (14:49 -0700)]
ci/crocus: Drop g41's xfail for rgba_half_float_oes.
Something fixed it recently, noticed when I was testing this MR and ran
manual jobs.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16823>
Emma Anholt [Tue, 31 May 2022 20:52:57 +0000 (13:52 -0700)]
glsl: Drop INT_DIV_TO_MUL_RCP lowering.
nir_lower_int_to_float() does this at the end of compilation, no need to
do it up front.
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16823>
Vasily Khoruzhick [Mon, 6 Jun 2022 21:43:43 +0000 (14:43 -0700)]
lima: Lower nir_op_idiv with other scalar math operations.
This will end up appearing in the backend once we move GLSL's
idiv->fmul+frcp lowering to NIR.
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16823>
Emma Anholt [Mon, 6 Jun 2022 18:30:51 +0000 (11:30 -0700)]
nir: Fix idiv lowering on !NativeIntegers when lower_fdiv is also set.
Avoids a regression when turning off GLSL's int div lowering.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16823>
Emma Anholt [Tue, 31 May 2022 20:48:17 +0000 (13:48 -0700)]
glsl: Drop the div-to-mul-rcp lowering for floats.
NIR has fdiv, and all the NIR backends have to have lower_fdiv set
appropriately already since various passes (format conversions,
tgsi_to_nir, nir_fast_normalize(), etc.) might generate one.
This causes softpipe and llvmpipe to now do actual divides, since
lower_fdiv is not set there. Note that llvmpipe's rcp implementation is a
divide of 1.0 by x, so now we're going to be just doing div(x, y) instead
of mul(x, div(1.0, y)).
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16823>
Emma Anholt [Wed, 1 Jun 2022 19:49:59 +0000 (12:49 -0700)]
tgsi_exec: Fix inf/nan handling for divide by zero.
For RCP and for DDIV, we do division without any src1 != 0 checks, and we
should do the same here so that we get infs or nans as appropriate instead
of undefined.
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16823>
Emma Anholt [Tue, 31 May 2022 20:36:15 +0000 (13:36 -0700)]
glsl: Move exp/log-to-exp2/log2 lowering to glsl-to-NIR.
It's way more concise to write as nir_builder calls.
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16823>
Emma Anholt [Tue, 31 May 2022 20:33:14 +0000 (13:33 -0700)]
glsl: Remove stale lower_instructions comments.
Should have been in
3a42e92a4f2f ("glsl: Drop the dead MOD_TO_FLOOR path.")
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16823>
Emma Anholt [Tue, 31 May 2022 20:21:44 +0000 (13:21 -0700)]
gallium+glsl: Remove EmitNoSat/PIPE_CAP_VERTEX_SHADER_SATURATE
The drivers not setting it were:
- nv30, which gets lowering using NIR's lower_fsat flag.
- r300, which gets lowering using NIR's lower_fsat flag.
- a2xx, which has was getting it optimized back to fsat anyway.
This drops the check for the cap from gallium nine. While nine does have
a non-nir path, I think it's safe to assume that if you have SM3
texturing, you can do fsat.
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16823>
Emma Anholt [Tue, 31 May 2022 20:18:09 +0000 (13:18 -0700)]
nouveau/nv30: Make sure fsat is lowered in the VS.
GLSL lowers fsat to clamps based on PIPE_CAP_VERTEX_SHADER_SATURATE
(EmitNoSat), but nir is happy to optimize that back to fsat unless you
tell it not to.
Noticed by inspection while looking at deleting EmitNoSat.
Fixes:
ca1ec7272685 ("nv30/40: Switch to using NIR-to-TGSI by default.")
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16823>
Qiang Yu [Mon, 9 May 2022 13:28:26 +0000 (21:28 +0800)]
radeonsi: replace llvm ls/hs interface lds ops with nir lowered ones
Use ac nir lower pass to generate these lds load/store ops explicitly.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16418>
Timur Kristóf [Thu, 12 May 2022 13:48:24 +0000 (15:48 +0200)]
ac/nir: Add remappability to tess and ESGS I/O lowering passes.
This will be used for radeonsi to map common I/O location to fixed
slots agreed by different shader stages.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16418>
Qiang Yu [Mon, 9 May 2022 13:42:47 +0000 (21:42 +0800)]
ac/nir: skip gl_Layer/gl_ViewportIndex write for LS
This is from radeonsi.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16418>
Qiang Yu [Sun, 8 May 2022 14:10:58 +0000 (22:10 +0800)]
radeonsi: add tcs_vgpr_only_inputs parameter to si_get_nir_shader
Will be used later.
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16418>
Qiang Yu [Sat, 7 May 2022 09:54:02 +0000 (17:54 +0800)]
radeonsi: implement load_lshs_vertex_stride abi
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16418>
Qiang Yu [Sat, 7 May 2022 09:38:04 +0000 (17:38 +0800)]
ac/nir: use nir_intrinsic_load_lshs_vertex_stride_amd
For radeonsi which pass this value by argument.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16418>
Qiang Yu [Sat, 7 May 2022 09:34:54 +0000 (17:34 +0800)]
nir: add nir_intrinsic_load_lshs_vertex_stride_amd
For loading LS-HS vertex stride by shader argument in radeonsi.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16418>
Qiang Yu [Wed, 11 May 2022 07:11:27 +0000 (15:11 +0800)]
ac/llvm: get back nir_intrinsic_load_tess_rel_patch_id_amd
radeonsi will use it. This can be removed again after radeonsi support
radv_nir_lower_abi like lower pass.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16418>
Timothy Arceri [Mon, 6 Jun 2022 03:00:35 +0000 (13:00 +1000)]
glsl: tidy up link_varyings_and_uniforms()
All uniform linking is now done via nir based linker not via this
code so we drop that from its name. We also drop a bunch of unused
parameters.
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16880>
Timothy Arceri [Mon, 6 Jun 2022 02:57:08 +0000 (12:57 +1000)]
glsl: drop extra optimise swizzles call
As per the comment this was meant to tidy things up after varying
linking but varying linking has been moved into a nir based linker
so this extra call is no longer needed.
This optimisation pass is still called in the regular glsl ir
optimisation loop.
No shader-db change on Iris (BDW).
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16880>
Emma Anholt [Tue, 17 May 2022 19:07:06 +0000 (12:07 -0700)]
turnip: Move tile loads back into the draw CS.
Now that we don't need to know if HW binning actually will get used or
not, we can just emit the tile loads into the start of the draw CS.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16826>
Danylo Piliaiev [Wed, 13 Apr 2022 17:37:38 +0000 (20:37 +0300)]
turnip: Allow nested CP_COND_REG_EXEC
This ends up being needed for moving tile loads into the draw cs.
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16826>
Emma Anholt [Wed, 1 Jun 2022 22:01:44 +0000 (15:01 -0700)]
turnip: Allow load/store skipping in vkCmdClearAttachments().
We have to use a 3D draw to make it possible (so it goes through the
binner's visibility calcs), but hopefully the increased overhead for apps
with non-skippable rendering balances against skipping in others.
The real motivation is to get draw-time state out of tile load setup.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16826>
Emma Anholt [Fri, 20 May 2022 04:23:29 +0000 (21:23 -0700)]
turnip: Refactor a bit of subpass attachment processing.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16826>
Emma Anholt [Wed, 1 Jun 2022 21:11:47 +0000 (14:11 -0700)]
turnip: Include 3d-based CmdClearAttachments() in binning visibility.
It means the clear's draw can get skipped when it doesn't intersect with
the tile.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16826>
Emma Anholt [Thu, 19 May 2022 23:40:14 +0000 (16:40 -0700)]
turnip: Refactor a bit of repeated code for subpass setup.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16826>
Emma Anholt [Tue, 17 May 2022 17:51:19 +0000 (10:51 -0700)]
ci/turnip: Add a little forced touch-testing of XFB with no binning requested.
This is just a couple of seconds of runtime.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16826>
Emma Anholt [Mon, 16 May 2022 20:39:04 +0000 (13:39 -0700)]
turnip: Use fb->binning_possible to decide on conditional tile load/stores.
When !fb->binning but fb->binning_possible, we can just set the VSC
per-tile visibility reg to all visible in the "whoops, we'd rather not bin
but we had to anyway for XFB" case. This gets that EndRenderPass state out
of tile_load_cs/store_cs.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16826>
Emma Anholt [Mon, 16 May 2022 20:18:06 +0000 (13:18 -0700)]
turnip: Move binning decisions from FB usage time to FB creation time.
This is mostly about helping me understand which choices are constant for the object as opposed to runtime decisions.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16826>
Emma Anholt [Tue, 17 May 2022 21:28:47 +0000 (14:28 -0700)]
turnip: Refactor a bit of tu6_emit_tile_select().
Reduce redundant code, make the used SET_VISIBILITY_OVERRIDE value clearer.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16826>
Emma Anholt [Tue, 17 May 2022 21:19:50 +0000 (14:19 -0700)]
turnip: Don't bother creating tile_load/store_cs for sysmem rendering.
They won't get called, so don't bother.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16826>
Emma Anholt [Mon, 6 Jun 2022 21:46:56 +0000 (14:46 -0700)]
ci/i915: Update manual piglit job expectations.
These shaders are near the instruction count limit, and something changed.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16896>
Emma Anholt [Mon, 6 Jun 2022 19:51:14 +0000 (12:51 -0700)]
ci/i915: Merge the piglit and deqp runs.
One less button to click.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16896>
Nagappa Koppad, Basanagouda [Mon, 6 Jun 2022 09:10:06 +0000 (14:40 +0530)]
iris:Duplicate DRM fd internally instead of reuse.
Scenario we want to avoid is double close of DRM fd in iris driver.
Signed-off-by: Nagappa Koppad, Basanagouda <basanagouda.nagappa.koppad@intel.com>
Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6620
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16886>
Alyssa Rosenzweig [Sat, 4 Jun 2022 12:52:24 +0000 (08:52 -0400)]
docs: Document Mali-G57 conformance
Update the Panfrost driver documentation and the Mesa 22.2 release notes to
advertise the new Valhall support.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16890>
Alyssa Rosenzweig [Fri, 28 Jan 2022 17:00:37 +0000 (12:00 -0500)]
panfrost: Enable Mali-G57
Everything required for conformant OpenGL ES 3.1 support on Valhall (v9) is now
upstream -- all that's left is to enable implementations! Add the GPU ID for the
Mali-G57 implemented in the MediaTek MT8192 system-on-chip.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16890>
Rhys Perry [Mon, 11 Apr 2022 16:51:42 +0000 (17:51 +0100)]
aco: consider fma with multiplication by power-of-two unfused
fossil-db (Sienna Cichlid):
Totals from 700 (0.43% of 162353) affected shaders:
MaxWaves: 18986 -> 18990 (+0.02%)
Instrs: 546475 -> 539729 (-1.23%); split: -1.24%, +0.00%
CodeSize: 2823716 -> 2808504 (-0.54%); split: -0.55%, +0.01%
VGPRs: 25304 -> 25288 (-0.06%)
Latency: 2180102 -> 2168187 (-0.55%); split: -0.55%, +0.01%
InvThroughput: 466223 -> 457326 (-1.91%)
VClause: 6768 -> 6797 (+0.43%); split: -0.01%, +0.44%
SClause: 12235 -> 12237 (+0.02%); split: -0.22%, +0.24%
Copies: 34498 -> 34479 (-0.06%); split: -0.21%, +0.15%
PreVGPRs: 20968 -> 20958 (-0.05%)
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15862>
Qiang Yu [Thu, 28 Apr 2022 02:26:13 +0000 (10:26 +0800)]
mesa: enable HardwareAcceleratedSelect
Could be enabled/disabled by MESA_HW_ACCEL_SELECT.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15765>
Qiang Yu [Sat, 21 May 2022 12:55:00 +0000 (20:55 +0800)]
virgl: return -1 for PIPE_CAP_ACCELERATED
There's no way currently in virgl to determine whether it's running
above CPU or GPU. This info will be used to disable HW SELECT.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15765>
Qiang Yu [Sat, 21 May 2022 07:35:39 +0000 (15:35 +0800)]
zink: reset PIPE_CAP_ACCELERATED when cpu soft rendering
This field can be used to disable some unsupport/unproper hardware
acceleration. Reset it when zink is runing on cpu rendering.
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15765>
Qiang Yu [Sat, 2 Apr 2022 09:12:20 +0000 (17:12 +0800)]
mesa/st: implement hardware accelerated GL_SELECT
Use an internal geometry shader to handle input primitives. Do full
accurate culling and clipping in the shader and output hit result and
min/max depth to a SSBO for final being written to select buffer.
With multiple result slots in SSBO we can left multiple draws on the
fly and wait them done when buffer is full or exit GL_SELECT mode.
This provides quicker selection response compared to software based
solution. Tested on Discovery Studio 2020: some complex model needs
1~2s selection response time originally, now it's almost selected
immidiately.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15765>
Qiang Yu [Thu, 17 Mar 2022 03:23:22 +0000 (11:23 +0800)]
mesa: pass select result buffer offset as attribute/varying
Will be used by geometry shader to store hit result.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15765>
Qiang Yu [Fri, 13 May 2022 09:34:14 +0000 (17:34 +0800)]
mesa: add HWSelectModeBeginEnd dispatch table
Used when in glBegin/End section and HW GL_RENDER mode.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15765>
Qiang Yu [Sat, 14 May 2022 03:34:41 +0000 (11:34 +0800)]
mesa: set CurrentServerDispatch too when glBegin/End
When glthread not enabled, CurrentClientDispatch and CurrentServerDispatch
should be same. This does not cause problems before because OutsideBeginEnd
and BeginEnd have same BeginEnd entries, so when
CurrentServerDispatch==OutsideBeginEnd
CurrentClientDispatch==BeginEnd
will call into same BeginEnd _mesa_* functions.
But we'll add another dispatch table to replace BeginEnd when HW GL_SELECT
mode, so this needs to be fixed. Otherwise some function like _mesa_Rectf
which always call with CurrentServerDispatch will go into wrong entries.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15765>
Qiang Yu [Fri, 13 May 2022 13:11:47 +0000 (21:11 +0800)]
mapi: add api setup header for hw select mode
Used by GL_SELECT mode dispatch table setup.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15765>
Qiang Yu [Fri, 13 May 2022 11:50:04 +0000 (19:50 +0800)]
mesa/vbo: enclose none-vertex functions with HW_SELECT_MODE
For constructing dispatch table used in GL_SELECT mode. Every vertex
inserted need to also insert a name stack offset attribute.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15765>
Qiang Yu [Wed, 9 Mar 2022 07:03:01 +0000 (15:03 +0800)]
mesa: add hw select name stack code path
HW code path will not flush vertex whenever name stack change.
It will save the current name stack and write to select buffer
only when no space left or exit select mode.
This let us submit multi draws from different name stack at
once instead of submit draws for a single name stack then
wait it finish before submit next one.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15765>
Qiang Yu [Wed, 9 Mar 2022 06:33:22 +0000 (14:33 +0800)]
mesa: refine name stack code to prepare for hw select
No functional change, just pack existing software based implementation into
the HardwareAcceleratedSelect switch, will add hardware implementation in
next commit.
ctx->Select.NameStackDepth is sure to be <=MAX_NAME_STACK_DEPTH, so removed
the overflow check in _mesa_LoadName.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Sgined-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15765>
Qiang Yu [Wed, 9 Mar 2022 03:34:57 +0000 (11:34 +0800)]
mesa: add _mesa_bufferobj_get_subdata
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15765>
Qiang Yu [Mon, 7 Mar 2022 07:37:03 +0000 (15:37 +0800)]
mesa: add hardware accelerated select constant
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15765>
Qiang Yu [Sat, 19 Mar 2022 13:05:33 +0000 (21:05 +0800)]
nir/builder: add load/store array variable helper functions
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15765>
Qiang Yu [Mon, 14 Mar 2022 07:11:34 +0000 (15:11 +0800)]
mesa/vbo: remove unused vbo_context->binding
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15765>
Qiang Yu [Thu, 24 Mar 2022 03:15:58 +0000 (11:15 +0800)]
mesa/program: fix nir output reg overflow
outputs_written is uint64_t, should count max reg number
by util_last_bit64(). Otherwise the following access will
overflow the allocated array with a smaller size.
cc: mesa-stable
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15765>
Alyssa Rosenzweig [Thu, 2 Jun 2022 18:50:39 +0000 (14:50 -0400)]
pan/va: Unit test constant lowering pass
Like other optimizations, breaking this pass may not affect functional
correctness. It's also dead simple to unit test the pass, so we have no excuse
not to. Add unit tests for the functionality we currently support, since we just
extended it and want to make sure everything still works.
This includes tests for use of modifiers to get more small constants. There are
lots of subtle gotchas there, so let's add lots of unit tests to make sure we
got it right.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16862>
Alyssa Rosenzweig [Thu, 2 Jun 2022 23:07:49 +0000 (19:07 -0400)]
pan/va: Try widening small constants
Many small integers are availabled as small constants, but the table of small
constants is tightly packed. Zero and sign extensions are usually required to
access small integers. When packing constants, try zero/sign extension for
unsigned/signed integer instructions respectively.
total instructions in shared programs: 2716912 -> 2707795 (-0.34%)
instructions in affected programs: 1045609 -> 1036492 (-0.87%)
helped: 4460
HURT: 125
helped stats (abs) min: 1.0 max: 58.0 x̄: 2.14 x̃: 1
helped stats (rel) min: 0.14% max: 23.85% x̄: 1.35% x̃: 0.88%
HURT stats (abs) min: 1.0 max: 68.0 x̄: 3.41 x̃: 1
HURT stats (rel) min: 0.34% max: 3.88% x̄: 0.93% x̃: 0.70%
95% mean confidence interval for instructions value: -2.09 -1.89
95% mean confidence interval for instructions %-change: -1.33% -1.25%
Instructions are helped.
total cycles in shared programs: 141984.06 -> 141932.42 (-0.04%)
cycles in affected programs: 552.08 -> 500.44 (-9.35%)
helped: 18
HURT: 0
helped stats (abs) min: 0.015625 max: 11.0 x̄: 2.87 x̃: 0
helped stats (rel) min: 0.50% max: 19.64% x̄: 5.36% x̃: 1.53%
95% mean confidence interval for cycles value: -5.17 -0.56
95% mean confidence interval for cycles %-change: -9.28% -1.44%
Cycles are helped.
total cvt in shared programs: 13805.05 -> 13663.39 (-1.03%)
cvt in affected programs: 6127.45 -> 5985.80 (-2.31%)
helped: 4460
HURT: 125
helped stats (abs) min: 0.015625 max: 0.90625 x̄: 0.03 x̃: 0
helped stats (rel) min: 0.35% max: 50.00% x̄: 5.19% x̃: 4.00%
HURT stats (abs) min: 0.015625 max: 1.0625 x̄: 0.05 x̃: 0
HURT stats (rel) min: 0.77% max: 9.30% x̄: 3.40% x̃: 2.78%
95% mean confidence interval for cvt value: -0.03 -0.03
95% mean confidence interval for cvt %-change: -5.10% -4.81%
Cvt are helped.
total ls in shared programs: 129545 -> 129494 (-0.04%)
ls in affected programs: 495 -> 444 (-10.30%)
helped: 6
HURT: 0
helped stats (abs) min: 2.0 max: 11.0 x̄: 8.50 x̃: 11
helped stats (rel) min: 1.49% max: 19.64% x̄: 13.95% x̃: 19.64%
95% mean confidence interval for ls value: -12.68 -4.32
95% mean confidence interval for ls %-change: -23.23% -4.67%
Ls are helped.
total quadwords in shared programs: 1476416 -> 1469824 (-0.45%)
quadwords in affected programs: 121208 -> 114616 (-5.44%)
helped: 820
HURT: 16
helped stats (abs) min: 8.0 max: 32.0 x̄: 8.28 x̃: 8
helped stats (rel) min: 1.39% max: 50.00% x̄: 11.00% x̃: 10.00%
HURT stats (abs) min: 8.0 max: 32.0 x̄: 12.50 x̃: 8
HURT stats (rel) min: 1.38% max: 10.00% x̄: 6.19% x̃: 7.14%
95% mean confidence interval for quadwords value: -8.14 -7.63
95% mean confidence interval for quadwords %-change: -11.20% -10.15%
Quadwords are helped.
total threads in shared programs: 53633 -> 53663 (0.06%)
threads in affected programs: 39 -> 69 (76.92%)
helped: 33
HURT: 3
helped stats (abs) min: 1.0 max: 1.0 x̄: 1.00 x̃: 1
helped stats (rel) min: 100.00% max: 100.00% x̄: 100.00% x̃: 100.00%
HURT stats (abs) min: 1.0 max: 1.0 x̄: 1.00 x̃: 1
HURT stats (rel) min: 50.00% max: 50.00% x̄: 50.00% x̃: 50.00%
95% mean confidence interval for threads value: 0.64 1.02
95% mean confidence interval for threads %-change: 73.27% 101.73%
Threads are helped.
total spills in shared programs: 154 -> 103 (-33.12%)
spills in affected programs: 75 -> 24 (-68.00%)
helped: 6
HURT: 0
total fills in shared programs: 656 -> 656 (0.00%)
fills in affected programs: 148 -> 148 (0.00%)
helped: 2
HURT: 4
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16862>
Alyssa Rosenzweig [Thu, 2 Jun 2022 19:10:09 +0000 (15:10 -0400)]
pan/va: Try negating small constants when lowering
If a constant is used with a floating point instruction with a floating-point
negate modifier, we can use the modifier to negate constants in the table for
free. Each floating point in the table is positive, so this is required for
negative small constants.
total instructions in shared programs: 2728438 -> 2716912 (-0.42%)
instructions in affected programs: 1418220 -> 1406694 (-0.81%)
helped: 6053
HURT: 94
helped stats (abs) min: 1.0 max: 43.0 x̄: 1.94 x̃: 1
helped stats (rel) min: 0.06% max: 18.18% x̄: 1.34% x̃: 0.84%
HURT stats (abs) min: 1.0 max: 5.0 x̄: 2.34 x̃: 2
HURT stats (rel) min: 0.09% max: 21.43% x̄: 1.87% x̃: 0.91%
95% mean confidence interval for instructions value: -1.93 -1.82
95% mean confidence interval for instructions %-change: -1.34% -1.25%
Instructions are helped.
total cycles in shared programs: 142103 -> 141984.06 (-0.08%)
cycles in affected programs: 766.70 -> 647.77 (-15.51%)
helped: 97
HURT: 0
helped stats (abs) min: 0.015625 max: 40.0 x̄: 1.23 x̃: 0
helped stats (rel) min: 0.27% max: 41.24% x̄: 3.63% x̃: 2.08%
95% mean confidence interval for cycles value: -2.41 -0.04
95% mean confidence interval for cycles %-change: -4.68% -2.57%
Cycles are helped.
total cvt in shared programs: 13983.34 -> 13805.05 (-1.28%)
cvt in affected programs: 7952.45 -> 7774.16 (-2.24%)
helped: 6049
HURT: 98
helped stats (abs) min: 0.015625 max: 0.359375 x̄: 0.03 x̃: 0
helped stats (rel) min: 0.25% max: 100.00% x̄: 4.74% x̃: 2.52%
HURT stats (abs) min: 0.015625 max: 0.078125 x̄: 0.04 x̃: 0
HURT stats (rel) min: 0.17% max: 100.00% x̄: 5.48% x̃: 2.54%
95% mean confidence interval for cvt value: -0.03 -0.03
95% mean confidence interval for cvt %-change: -4.83% -4.32%
Cvt are helped.
total ls in shared programs: 129660 -> 129545 (-0.09%)
ls in affected programs: 601 -> 486 (-19.13%)
helped: 7
HURT: 0
helped stats (abs) min: 3.0 max: 40.0 x̄: 16.43 x̃: 8
helped stats (rel) min: 2.88% max: 41.24% x̄: 17.41% x̃: 12.50%
95% mean confidence interval for ls value: -31.42 -1.44
95% mean confidence interval for ls %-change: -29.25% -5.58%
Ls are helped.
total quadwords in shared programs: 1482728 -> 1476416 (-0.43%)
quadwords in affected programs: 131200 -> 124888 (-4.81%)
helped: 798
HURT: 15
helped stats (abs) min: 8.0 max: 24.0 x̄: 8.06 x̃: 8
helped stats (rel) min: 0.34% max: 50.00% x̄: 10.15% x̃: 6.67%
HURT stats (abs) min: 8.0 max: 8.0 x̄: 8.00 x̃: 8
HURT stats (rel) min: 1.49% max: 100.00% x̄: 11.25% x̃: 2.78%
95% mean confidence interval for quadwords value: -7.92 -7.60
95% mean confidence interval for quadwords %-change: -10.52% -8.99%
Quadwords are helped.
total threads in shared programs: 53585 -> 53633 (0.09%)
threads in affected programs: 51 -> 99 (94.12%)
helped: 49
HURT: 1
helped stats (abs) min: 1.0 max: 1.0 x̄: 1.00 x̃: 1
helped stats (rel) min: 100.00% max: 100.00% x̄: 100.00% x̃: 100.00%
HURT stats (abs) min: 1.0 max: 1.0 x̄: 1.00 x̃: 1
HURT stats (rel) min: 50.00% max: 50.00% x̄: 50.00% x̃: 50.00%
95% mean confidence interval for threads value: 0.88 1.04
95% mean confidence interval for threads %-change: 90.97% 103.03%
Threads are helped.
total spills in shared programs: 125 -> 154 (23.20%)
spills in affected programs: 75 -> 104 (38.67%)
helped: 3
HURT: 4
total fills in shared programs: 800 -> 656 (-18.00%)
fills in affected programs: 476 -> 332 (-30.25%)
helped: 7
HURT: 0
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16862>
Alyssa Rosenzweig [Thu, 2 Jun 2022 23:06:07 +0000 (19:06 -0400)]
pan/va: Record which instructions are signed
We need to distinguish signed integer instructions from unsigned integer
instructions, to distinguish sign-extension and zero-extension of sources.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16862>
Rhys Perry [Mon, 30 May 2022 11:46:20 +0000 (12:46 +0100)]
aco: fix SMEM load_global with VGPR address and non-zero offset
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Fixes:
3e9517c7577 ("aco: implement _amd global access intrinsics")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16775>
Rhys Perry [Mon, 30 May 2022 11:45:10 +0000 (12:45 +0100)]
aco: fix SMEM load_global_amd with non-zero offset
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Fixes:
3e9517c7577 ("aco: implement _amd global access intrinsics")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16775>
Juan A. Suarez Romero [Thu, 2 Jun 2022 15:06:20 +0000 (17:06 +0200)]
v3d: save only required states in blitter
Some blitter operations, like clear, doesn't require to save all the
states.
This is particular important because, besides saving time, the blitter
operation restores the state required for the operation, and if we saved
more states than those, these ones won't be restored and will be leak.
So this also fixes some leaks when running CTS tests.
CC: mesa-stable
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16837>
Juan A. Suarez Romero [Thu, 2 Jun 2022 15:05:07 +0000 (17:05 +0200)]
v3d: use function to initialize refcount
Call proper pipe reference function to initialize the reference
counting.
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16837>
Alyssa Rosenzweig [Fri, 3 Jun 2022 00:13:14 +0000 (20:13 -0400)]
pan/bi: Implement b2i with MUX
The result_type modifier propagation looks for MUX instructions, so using this
canonical b2i implementation allows the sequence b2i(cmp) to be fused.
It's also faster on its own: on Valhall, MUX may be implemented as CSEL on the
CVT unit, while AND may only be implemented on the SFU unit. So in case this
doesn't get fused, we expect 4x better throughput for b2i with this
implementation. Similarly, on Bifrost, MUX may be scheduled to either unit (as
CSEL on FMA or MUX on ADD), whereas AND may only be scheduled to FMA.
Results on Mali-G52:
total instructions in shared programs: 2419171 -> 2414814 (-0.18%)
instructions in affected programs: 272203 -> 267846 (-1.60%)
helped: 767
HURT: 0
helped stats (abs) min: 1.0 max: 138.0 x̄: 5.68 x̃: 2
helped stats (rel) min: 0.12% max: 15.57% x̄: 2.09% x̃: 0.68%
95% mean confidence interval for instructions value: -6.68 -4.68
95% mean confidence interval for instructions %-change: -2.37% -1.82%
Instructions are helped.
total tuples in shared programs: 1932822 -> 1929234 (-0.19%)
tuples in affected programs: 76485 -> 72897 (-4.69%)
helped: 380
HURT: 3
helped stats (abs) min: 1.0 max: 138.0 x̄: 9.46 x̃: 1
helped stats (rel) min: 0.14% max: 15.96% x̄: 3.81% x̃: 0.92%
HURT stats (abs) min: 1.0 max: 6.0 x̄: 2.67 x̃: 1
HURT stats (rel) min: 0.38% max: 8.57% x̄: 3.80% x̃: 2.44%
95% mean confidence interval for tuples value: -11.30 -7.44
95% mean confidence interval for tuples %-change: -4.27% -3.22%
Tuples are helped.
total clauses in shared programs: 356094 -> 355992 (-0.03%)
clauses in affected programs: 3264 -> 3162 (-3.12%)
helped: 80
HURT: 0
helped stats (abs) min: 1.0 max: 9.0 x̄: 1.27 x̃: 1
helped stats (rel) min: 0.81% max: 50.00% x̄: 4.83% x̃: 3.39%
95% mean confidence interval for clauses value: -1.49 -1.06
95% mean confidence interval for clauses %-change: -6.23% -3.43%
Clauses are helped.
total cycles in shared programs: 167337.10 -> 167329.19 (<.01%)
cycles in affected programs: 510.08 -> 502.17 (-1.55%)
helped: 80
HURT: 2
helped stats (abs) min: 0.
041665999999999315 max: 0.
7916659999999993 x̄: 0.10 x̃: 0
helped stats (rel) min: 0.51% max: 13.64% x̄: 2.12% x̃: 1.34%
HURT stats (abs) min: 0.
041665999999999315 max: 0.
0416669999999999 x̄: 0.04 x̃: 0
HURT stats (rel) min: 0.39% max: 2.78% x̄: 1.58% x̃: 1.58%
95% mean confidence interval for cycles value: -0.12 -0.07
95% mean confidence interval for cycles %-change: -2.59% -1.48%
Cycles are helped.
total arith in shared programs: 73819.54 -> 73669.25 (-0.20%)
arith in affected programs: 2840.54 -> 2690.25 (-5.29%)
helped: 383
HURT: 3
helped stats (abs) min: 0.
041665999999999315 max: 5.75 x̄: 0.39 x̃: 0
helped stats (rel) min: 0.33% max: 18.81% x̄: 4.39% x̃: 0.98%
HURT stats (abs) min: 0.
041665999999999315 max: 0.25 x̄: 0.11 x̃: 0
HURT stats (rel) min: 0.39% max: 8.96% x̄: 4.04% x̃: 2.78%
95% mean confidence interval for arith value: -0.47 -0.31
95% mean confidence interval for arith %-change: -4.93% -3.71%
Arith are helped.
total quadwords in shared programs: 1679798 -> 1676259 (-0.21%)
quadwords in affected programs: 72826 -> 69287 (-4.86%)
helped: 381
HURT: 15
helped stats (abs) min: 1.0 max: 142.0 x̄: 9.35 x̃: 1
helped stats (rel) min: 0.25% max: 18.87% x̄: 4.33% x̃: 1.13%
HURT stats (abs) min: 1.0 max: 6.0 x̄: 1.47 x̃: 1
HURT stats (rel) min: 0.30% max: 6.25% x̄: 0.77% x̃: 0.35%
95% mean confidence interval for quadwords value: -10.76 -7.11
95% mean confidence interval for quadwords %-change: -4.71% -3.56%
Quadwords are helped.
Results on Mali-G57:
total instructions in shared programs: 2704193 -> 2699317 (-0.18%)
instructions in affected programs: 293366 -> 288490 (-1.66%)
helped: 758
HURT: 5
helped stats (abs) min: 1.0 max: 151.0 x̄: 6.45 x̃: 2
helped stats (rel) min: 0.11% max: 22.22% x̄: 2.05% x̃: 0.64%
HURT stats (abs) min: 1.0 max: 7.0 x̄: 2.20 x̃: 1
HURT stats (rel) min: 0.22% max: 1.69% x̄: 0.87% x̃: 1.08%
95% mean confidence interval for instructions value: -7.42 -5.36
95% mean confidence interval for instructions %-change: -2.27% -1.79%
Instructions are helped.
total cycles in shared programs: 141711.73 -> 141711.84 (<.01%)
cycles in affected programs: 214.36 -> 214.47 (0.05%)
helped: 4
HURT: 42
helped stats (abs) min: 0.015625 max: 0.359375 x̄: 0.20 x̃: 0
helped stats (rel) min: 1.85% max: 12.78% x̄: 9.12% x̃: 10.93%
HURT stats (abs) min: 0.015625 max: 0.09375 x̄: 0.02 x̃: 0
HURT stats (rel) min: 0.17% max: 17.65% x̄: 0.84% x̃: 0.34%
95% mean confidence interval for cycles value: -0.02 0.03
95% mean confidence interval for cycles %-change: -1.23% 1.17%
Inconclusive result (value mean confidence interval includes 0).
total cvt in shared programs: 14479.14 -> 14474.19 (-0.03%)
cvt in affected programs: 2877.05 -> 2872.09 (-0.17%)
helped: 508
HURT: 209
helped stats (abs) min: 0.015625 max: 0.453125 x̄: 0.02 x̃: 0
helped stats (rel) min: 0.25% max: 16.67% x̄: 1.23% x̃: 0.37%
HURT stats (abs) min: 0.015625 max: 0.296875 x̄: 0.03 x̃: 0
HURT stats (rel) min: 0.15% max: 18.18% x̄: 1.70% x̃: 0.34%
95% mean confidence interval for cvt value: -0.01 -0.00
95% mean confidence interval for cvt %-change: -0.57% -0.18%
Cvt are helped.
total sfu in shared programs: 7875.69 -> 7590.75 (-3.62%)
sfu in affected programs: 1567.38 -> 1282.44 (-18.18%)
helped: 906
HURT: 0
helped stats (abs) min: 0.0625 max: 8.625 x̄: 0.31 x̃: 0
helped stats (rel) min: 2.38% max: 100.00% x̄: 16.80% x̃: 5.63%
95% mean confidence interval for sfu value: -0.37 -0.26
95% mean confidence interval for sfu %-change: -18.43% -15.17%
Sfu are helped.
total quadwords in shared programs: 1468152 -> 1465800 (-0.16%)
quadwords in affected programs: 37104 -> 34752 (-6.34%)
helped: 161
HURT: 2
helped stats (abs) min: 8.0 max: 80.0 x̄: 14.71 x̃: 8
helped stats (rel) min: 1.67% max: 20.00% x̄: 8.05% x̃: 7.69%
HURT stats (abs) min: 8.0 max: 8.0 x̄: 8.00 x̃: 8
HURT stats (rel) min: 3.57% max: 3.85% x̄: 3.71% x̃: 3.71%
95% mean confidence interval for quadwords value: -16.29 -12.57
95% mean confidence interval for quadwords %-change: -8.58% -7.22%
Quadwords are helped.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16857>
Alyssa Rosenzweig [Fri, 6 May 2022 21:02:57 +0000 (17:02 -0400)]
pan/va: Add MUX lowering tests
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16857>
Alyssa Rosenzweig [Fri, 6 May 2022 21:10:56 +0000 (17:10 -0400)]
pan/va: Lower MUX to CSEL where possible
CSEL executes on the conversion unit (CVT), while MUX executes on the special
function unit (SFU). Throughput on CVT is 4x higher than SFU, so this is
(almost) always an optimization.
The "real" MUX is still used for unusual cases, like 8-bit and bitselect.
Note that it's easier for us to use MUX everywhere for the IR. This is an easy
fixup to get better codegen on Valhall without touching the core Bifrost code.
shader-db is a bit of a toss up: register pressure and instruction count are
hurt in some cases due to restrictions on FAU access. In particular, a shader
that muxes between two uniforms needs an extra move due to extra constant
(zero). However, in terms of throughput this is still a win: 2 CVT instructions
(MOV + CSEL) have 2x throughput to 1 SFU instruction (MUX). The MOV has
opportunities for CSE, but that can hurt pressure in turn. Overall, cycles are
helped substantially.
total instructions in shared programs: 2728438 -> 2731597 (0.12%)
instructions in affected programs: 414391 -> 417550 (0.76%)
helped: 87
HURT: 1063
helped stats (abs) min: 1.0 max: 6.0 x̄: 5.17 x̃: 6
helped stats (rel) min: 0.19% max: 15.79% x̄: 4.12% x̃: 4.11%
HURT stats (abs) min: 1.0 max: 56.0 x̄: 3.40 x̃: 2
HURT stats (rel) min: 0.11% max: 23.43% x̄: 1.15% x̃: 0.63%
95% mean confidence interval for instructions value: 2.47 3.03
95% mean confidence interval for instructions %-change: 0.61% 0.90%
Instructions are HURT.
total cycles in shared programs: 142103 -> 142015.75 (-0.06%)
cycles in affected programs: 1263.45 -> 1176.20 (-6.91%)
helped: 281
HURT: 176
helped stats (abs) min: 0.015625 max: 2.234375 x̄: 0.50 x̃: 0
helped stats (rel) min: 0.71% max: 54.17% x̄: 16.93% x̃: 15.31%
HURT stats (abs) min: 0.015625 max: 30.0 x̄: 0.30 x̃: 0
HURT stats (rel) min: 0.84% max: 120.00% x̄: 7.16% x̃: 5.00%
95% mean confidence interval for cycles value: -0.33 -0.05
95% mean confidence interval for cycles %-change: -9.08% -6.22%
Cycles are helped.
total cvt in shared programs: 13983.34 -> 14891.70 (6.50%)
cvt in affected programs: 7498.36 -> 8406.72 (12.11%)
helped: 71
HURT: 4711
helped stats (abs) min: 0.0625 max: 0.0625 x̄: 0.06 x̃: 0
helped stats (rel) min: 5.41% max: 40.00% x̄: 10.23% x̃: 9.30%
HURT stats (abs) min: 0.015625 max: 2.640625 x̄: 0.19 x̃: 0
HURT stats (rel) min: 0.18% max: 141.18% x̄: 16.21% x̃: 9.52%
95% mean confidence interval for cvt value: 0.18 0.20
95% mean confidence interval for cvt %-change: 15.21% 16.42%
Cvt are HURT.
total sfu in shared programs: 11320.44 -> 7882.56 (-30.37%)
sfu in affected programs: 7618.50 -> 4180.62 (-45.13%)
helped: 4782
HURT: 0
helped stats (abs) min: 0.0625 max: 10.5625 x̄: 0.72 x̃: 0
helped stats (rel) min: 1.34% max: 100.00% x̄: 41.91% x̃: 37.50%
95% mean confidence interval for sfu value: -0.75 -0.68
95% mean confidence interval for sfu %-change: -42.68% -41.14%
Sfu are helped.
total ls in shared programs: 129660 -> 129690 (0.02%)
ls in affected programs: 25 -> 55 (120.00%)
helped: 0
HURT: 1
total quadwords in shared programs: 1482728 -> 1484128 (0.09%)
quadwords in affected programs: 58624 -> 60024 (2.39%)
helped: 24
HURT: 195
helped stats (abs) min: 8.0 max: 8.0 x̄: 8.00 x̃: 8
helped stats (rel) min: 3.70% max: 20.00% x̄: 10.34% x̃: 10.00%
HURT stats (abs) min: 8.0 max: 24.0 x̄: 8.16 x̃: 8
HURT stats (rel) min: 1.41% max: 50.00% x̄: 4.84% x̃: 2.56%
95% mean confidence interval for quadwords value: 5.70 7.09
95% mean confidence interval for quadwords %-change: 2.22% 4.14%
Quadwords are HURT.
total spills in shared programs: 125 -> 127 (1.60%)
spills in affected programs: 0 -> 2
helped: 0
HURT: 1
total fills in shared programs: 800 -> 828 (3.50%)
fills in affected programs: 0 -> 28
helped: 0
HURT: 1
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16857>
Alyssa Rosenzweig [Fri, 6 May 2022 21:23:10 +0000 (17:23 -0400)]
pan/va: Implement more lanes
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16857>
Alyssa Rosenzweig [Fri, 6 May 2022 21:09:56 +0000 (17:09 -0400)]
pan/bi: Extract MUX to CSEL optimization
It's portable, and useful to both Bifrost and Valhall, in the clause scheduler
and in an instruction selection respectively. Move it from the Bifrost clause
scheduler to common code so we can share the benefits.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16857>
Frank Binns [Mon, 30 May 2022 17:16:46 +0000 (18:16 +0100)]
pvr: shorten error to err in label names
This is for consistency with the rest of the driver.
Signed-off-by: Frank Binns <frank.binns@imgtec.com>
Reviewed-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16882>
Juan A. Suarez Romero [Tue, 31 May 2022 09:28:14 +0000 (11:28 +0200)]
v3d/ci: Add traces
Add a job to run and test traces from Tracies DB.
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Reviewed-by: Jose Maria Casanova Crespo <jmcasanova@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16809>
Alyssa Rosenzweig [Sat, 4 Jun 2022 13:58:40 +0000 (09:58 -0400)]
panfrost: Don't calculate min/max indices on v9
On Valhall, we always* use memory-allocated IDVS, which does not require min/max
indices. As such, we do not want to calculate min/max indices, as this is quite
slow. Skip this step.
* except for blit shaders, which don't use an index buffer anyway.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16867>
Alyssa Rosenzweig [Sat, 4 Jun 2022 13:57:29 +0000 (09:57 -0400)]
panfrost: Extract panfrost_get_index_buffer helper
Memory-allocated IDVS does not require min/max indices to be calculated, but it
of course requires an index buffer. Extract a helper to upload the index buffer
without calculating bounds.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16867>
Alyssa Rosenzweig [Sat, 4 Jun 2022 13:32:30 +0000 (09:32 -0400)]
pan/va: Do not insert NOPs into empty shaders
It's unnecessary and breaks the empty shader optimizations. Noticed while
inspecting a trace from dEQP-GLES3.functional.color_clear.masked_scissored_rgb,
which does not produce any varyings other than gl_Position in its vertex shader
and hence should omit the varying shader.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16868>
Konstantin Seurer [Sat, 4 Jun 2022 18:50:49 +0000 (20:50 +0200)]
radv: Require an alignment of 64 for accel structs
Top level acceleration structures need the bottom
6 bits to store the root ids of instances. If we
don't require that alignment, more "advanced"
allocators like VMA may sub allocate a buffer
which can lead to the 6 getting lost.
Fixes the Khronos ray tracing Vulkan samples.
Closes: #6598
Signed-off-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16870>
David Heidelberg [Mon, 6 Jun 2022 13:20:43 +0000 (15:20 +0200)]
ci/virgl: traces: temporarily disable nheko trace
Disable nheko trace until apitrace gets fixed.
apitrace currently fails with this trace, when more than 1 run is
requested.
Upstream issue: https://github.com/apitrace/apitrace/issues/800
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16887>
Mike Blumenkrantz [Fri, 3 Jun 2022 18:00:11 +0000 (14:00 -0400)]
zink: remove buffer valid range tracking from blit
I copy/pasted too hard. this code could never be reached
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16877>
Mike Blumenkrantz [Fri, 3 Jun 2022 17:59:11 +0000 (13:59 -0400)]
zink: invalidate blit dsts if fully covered
tiling perf++ since there's no need to load
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16877>
Mike Blumenkrantz [Fri, 3 Jun 2022 17:57:30 +0000 (13:57 -0400)]
zink: hook up surface invalidation to LOAD_OP_DONT_CARE
this should improve perf for tilers
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16877>
Mike Blumenkrantz [Fri, 3 Jun 2022 17:55:44 +0000 (13:55 -0400)]
zink: split out a dynamic render ternary
this is going to get bigger
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16877>
Mike Blumenkrantz [Fri, 3 Jun 2022 17:52:45 +0000 (13:52 -0400)]
zink: rename renderpass attrib value
this never really meant "swapchain", it just meant that load isn't needed
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16877>
Mike Blumenkrantz [Sun, 5 Jun 2022 13:14:30 +0000 (09:14 -0400)]
zink: flag renderpass for change if image resource changes valid state
the next renderpass instance will need to use different load ops,
so flag it here to ensure that gets picked up
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16877>
Mike Blumenkrantz [Fri, 3 Jun 2022 17:50:55 +0000 (13:50 -0400)]
zink: track invalidation for image resources
an image only has valid data if:
* it's imported
* it's written to
* it's mapped for write
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16877>
Mike Blumenkrantz [Fri, 3 Jun 2022 20:40:32 +0000 (16:40 -0400)]
zink: disable EXT_primitives_generated_query on turnip
this is broken
Acked-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16861>
Mike Blumenkrantz [Fri, 3 Jun 2022 20:39:07 +0000 (16:39 -0400)]
zink: remove ANV depth clip control workaround
this was fixed a while ago and I forgot
Acked-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16861>
Mike Blumenkrantz [Fri, 27 May 2022 17:34:09 +0000 (13:34 -0400)]
mesa: handle atomic counter lowering for drivers with big ssbo offset aligns
according to the spec, atomic counters can be bound at any offset divisible by 4,
which means that any driver that uses the ssbo lowering pass and doesn't have
a min offset align of 4 is potentially broken
to handle this, use a statevar to inject the misaligned remainder of the offset
into the shader as a uniform. for well-aligned counter binds, the uniform offset
will be 0
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16749>
Mike Blumenkrantz [Thu, 2 Jun 2022 21:44:34 +0000 (17:44 -0400)]
st/glsl_to_nir: call st_set_prog_affected_state_flags() as late as possible
this function should be called late to allow for other passes potentially
making changes which affect the states in use by shaders
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16749>
Mike Blumenkrantz [Fri, 27 May 2022 17:33:14 +0000 (13:33 -0400)]
mesa: conditionally set constants dirty for atomic counter binds
this is necessary for updating the offset uniforms
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16749>
Mike Blumenkrantz [Fri, 27 May 2022 17:30:11 +0000 (13:30 -0400)]
mesa: add statevar for atomic counter offsets
some hardware can't do a ssbo offset=4, as required by the atomic->ssbo
lowering pass, so for these cases an offset can be passed for the counter
as a uniform, and the shaders can be adjusted accordingly
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16749>
Pavel Ondračka [Fri, 20 May 2022 09:11:07 +0000 (11:11 +0200)]
r300: merge simple movs with constant swizzles together
This pass will merge instructions like these
MOV output[0].x, temp[5].x___;
MOV output[0].yzw, none._001;
into
MOV output[0].xyzw, temp[5].x001;
It is currently very careful with control flow and dependency
tracking, so there is still room for improvements.
Shader-db stats with RV530:
total instructions in shared programs: 132486 -> 132256 (-0.17%)
instructions in affected programs: 6186 -> 5956 (-3.72%)
helped: 65
HURT: 0
total temps in shared programs: 18035 -> 18014 (-0.12%)
temps in affected programs: 295 -> 274 (-7.12%)
helped: 22
HURT: 1
Signed-off-by: Pavel Ondračka <pavel.ondracka@gmail.com>
Reviewed-by: Filip Gawin <filip@gawin.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16657>
Filip Gawin [Sat, 12 Feb 2022 23:28:36 +0000 (00:28 +0100)]
r300: don't check for unitialized reads when rewriting register
This fixes the "Rewrite of inst X failed Can't allocate source
for Inst X src_type=X new_index=X new_mask=X" errors.
The compiler is quite strict when rewriting registers during
the pair allocation and checks that all of the reads of it are
initialized. However the spec doesn't enfore that, and
specifically with control flow depending on user input we can't
really know...
In the following example temp[4].x is written only in one branch,
that might or might not be taken, but this is enough to keep the
compiler happy:
IF aluresult.x___;
MAD temp[4].x, src0.1__, src0.111, src0.000
ENDIF;
src0.xyz = temp[4], src0.w = temp[4]
MAD color[0].xyz, src0.xyz, src0.111, src0.000
MAD color[0].w, src0.w, src0.1, src0.0
After switch to ntt, more IFs are converted to CMP, and the color
write looks like this. Please note that the CMP here is not TGSI
opcode but rather our US_OP_RGB_CMP: src2 >= 0 ? src0 : src1
src0.xyz = temp[4], src0.w = temp[4], src1.xyz = temp[3], src1.w = temp[12], src2.xyz = temp[2]
CMP color[0].xyz, src0.xyz, src1.xyz, -src2.xxx
CMP color[0].w, src0.w, src1.w, -src2.x
At this point temp[4].x is undefined. Now when compiler tries to
allocate register for temp[4] at some previous instruction, it will
find out that it is used as a source in the final CMP and bail out.
Instead of increasing the complexitty even more trying to account for
this, just get rid of the check completelly.
Fixes:
dEQP-GLES2.functional.shaders.indexing.vector_subscript.vec2_dynamic_subscript_write_component_read_fragment,Fail
dEQP-GLES2.functional.shaders.indexing.vector_subscript.vec2_dynamic_subscript_write_direct_read_fragment,Fail
dEQP-GLES2.functional.shaders.indexing.vector_subscript.vec2_dynamic_subscript_write_dynamic_subscript_read_fragment,Fail
dEQP-GLES2.functional.shaders.indexing.vector_subscript.vec2_dynamic_subscript_write_static_loop_subscript_read_fragment,Fail
dEQP-GLES2.functional.shaders.indexing.vector_subscript.vec2_dynamic_subscript_write_static_subscript_read_fragment,Fail
dEQP-GLES2.functional.shaders.indexing.vector_subscript.vec3_dynamic_subscript_write_component_read_fragment,Fail
dEQP-GLES2.functional.shaders.indexing.vector_subscript.vec3_dynamic_subscript_write_direct_read_fragment,Fail
dEQP-GLES2.functional.shaders.indexing.vector_subscript.vec3_dynamic_subscript_write_dynamic_subscript_read_fragment,Fail
dEQP-GLES2.functional.shaders.indexing.vector_subscript.vec3_dynamic_subscript_write_static_loop_subscript_read_fragment,Fail
dEQP-GLES2.functional.shaders.indexing.vector_subscript.vec3_dynamic_subscript_write_static_subscript_read_fragment,Fail
dEQP-GLES2.functional.shaders.indexing.vector_subscript.vec4_dynamic_subscript_write_component_read_fragment,Fail
dEQP-GLES2.functional.shaders.indexing.vector_subscript.vec4_dynamic_subscript_write_direct_read_fragment,Fail
dEQP-GLES2.functional.shaders.indexing.vector_subscript.vec4_dynamic_subscript_write_dynamic_subscript_read_fragment,Fail
dEQP-GLES2.functional.shaders.indexing.vector_subscript.vec4_dynamic_subscript_write_static_loop_subscript_read_fragment,Fail
dEQP-GLES2.functional.shaders.indexing.vector_subscript.vec4_dynamic_subscript_write_static_subscript_read_fragment,Fail
Reviewed-by: Pavel Ondračka <pavel.ondracka@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16657>