Simon Pilgrim [Sun, 17 Oct 2021 17:51:15 +0000 (18:51 +0100)]
[CostModel][X86] Add div/rem by negative power-of-2 constants
We have backend optimizations for these (like we do for power-of-2 divisions), but currently the costmodel doesn't match them
Simon Pilgrim [Sun, 17 Oct 2021 17:12:59 +0000 (18:12 +0100)]
[X86][SLM] Fix BitTest+Set uops + port usage
Both ports are required for BitTest ops. Update the uops counts + port usage based off the most recent llvm-exegesis captures and what Intel AoM / Agner reports as well.
Simon Pilgrim [Sat, 16 Oct 2021 20:41:21 +0000 (21:41 +0100)]
[X86][SLM] Fix uops for PCMPISTR/PCMPISTR instructions
Based off a recent llvm-exegesis capture and what Intel AoM / Agner reports as well.
Simon Pilgrim [Sat, 16 Oct 2021 20:35:12 +0000 (21:35 +0100)]
[X86][SLM] Fix uops for PCLMULQDQ
Based off a recent llvm-exegesis capture and what Intel AoM / Agner reports as well.
Simon Pilgrim [Sat, 16 Oct 2021 20:29:24 +0000 (21:29 +0100)]
[X86][SLM] +1uop for PSHUFBrm xmm
Extra 1uop for folded pshufb ops, based off a recent llvm-exegesis capture and what Intel AoM / Agner reports as well.
Nikita Popov [Sat, 16 Oct 2021 19:02:04 +0000 (21:02 +0200)]
[ConstantRange] Add fast signed multiply
The multiply() implementation is very slow -- it performs six
multiplications in double the bitwidth, which means that it will
typically work on allocated APInts and bypass fast-path
implementations. Add an additional implementation that doesn't
try to produce anything better than a full range if overflow is
possible. At least for the BasicAA use-case, we really don't care
about more precise modeling of overflow behavior. The current
use of multiply() is fine while the implementation is limited to
a single index, but extending it to the multiple-index case makes
the compile-time impact untenable.
Roman Lebedev [Sun, 17 Oct 2021 14:27:40 +0000 (17:27 +0300)]
[X86][Costmodel] Load/store i64 Stride=4 VF=16 interleaving costs
A few more tuples are being queried after D111546. Might be good to model them,
They all require a lot of manual assembly surgery.
The only sched models that for cpu's that support avx2
but not avx512 are: haswell, broadwell, skylake, zen1-3
For load we have:
https://godbolt.org/z/9bnKrefcG - for intels `Block RThroughput: =40.0`; for ryzens, `Block RThroughput: =16.0`
So could pick cost of `40`
For store we have:
https://godbolt.org/z/5s3s14dEY - for intels `Block RThroughput: =40.0`; for ryzens, `Block RThroughput: =16.0`
So we could pick cost of `40`.
I'm directly using the shuffling asm the llc produced,
without any manual fixups that may be needed
to ensure sequential execution.
Reviewed By: RKSimon
Differential Revision: https://reviews.llvm.org/D111945
Roman Lebedev [Sun, 17 Oct 2021 14:27:40 +0000 (17:27 +0300)]
[X86][Costmodel] Load/store i64 Stride=2 VF=32 interleaving costs
A few more tuples are being queried after D111546. Might be good to model them,
They all require a lot of manual assembly surgery.
The only sched models that for cpu's that support avx2
but not avx512 are: haswell, broadwell, skylake, zen1-3
For load we have:
https://godbolt.org/z/MTaKboejM - for intels `Block RThroughput: =32.0`; for ryzens, `Block RThroughput: <=16.0`
So could pick cost of `32`
For store we have:
https://godbolt.org/z/v7xPj3Wd4 - for intels `Block RThroughput: =32.0`; for ryzens, `Block RThroughput: <=32.0`
So we could pick cost of `32`.
I'm directly using the shuffling asm the llc produced,
without any manual fixups that may be needed
to ensure sequential execution.
Reviewed By: RKSimon
Differential Revision: https://reviews.llvm.org/D111944
Roman Lebedev [Sun, 17 Oct 2021 14:27:35 +0000 (17:27 +0300)]
[X86][Costmodel] Load/store i32 Stride=4 VF=32 interleaving costs
A few more tuples are being queried after D111546. Might be good to model them,
They all require a lot of manual assembly surgery.
The only sched models that for cpu's that support avx2
but not avx512 are: haswell, broadwell, skylake, zen1-3
For load we have:
https://godbolt.org/z/11rcvdreP - for intels `Block RThroughput: <=68.0`; for ryzens, `Block RThroughput: <=48.0`
So could pick cost of `68`
For store we have:
https://godbolt.org/z/6aM11fWcP - for intels `Block RThroughput: <=64.0`; for ryzens, `Block RThroughput: <=32.0`
So we could pick cost of `64`.
I'm directly using the shuffling asm the llc produced,
without any manual fixups that may be needed
to ensure sequential execution.
Reviewed By: RKSimon
Differential Revision: https://reviews.llvm.org/D111943
Roman Lebedev [Sun, 17 Oct 2021 14:27:30 +0000 (17:27 +0300)]
[X86][Costmodel] Load/store i32 Stride=3 VF=32 interleaving costs
A few more tuples are being queried after D111546. Might be good to model them,
They all require a lot of manual assembly surgery.
The only sched models that for cpu's that support avx2
but not avx512 are: haswell, broadwell, skylake, zen1-3
For load we have:
https://godbolt.org/z/s5b6E6jsP - for intels `Block RThroughput: <=32.0`; for ryzens, `Block RThroughput: <=24.0`
So could pick cost of `32`
For store we have:
https://godbolt.org/z/efh99d93b - for intels `Block RThroughput: <=48.0`; for ryzens, `Block RThroughput: <=32.0`
So we could pick cost of `48`.
I'm directly using the shuffling asm the llc produced,
without any manual fixups that may be needed
to ensure sequential execution.
Reviewed By: RKSimon
Differential Revision: https://reviews.llvm.org/D111942
Roman Lebedev [Sun, 17 Oct 2021 14:27:26 +0000 (17:27 +0300)]
[X86][Costmodel] Load/store i16 Stride=6 VF=32 interleaving costs
A few more tuples are being queried after D111546. Might be good to model them,
They all require a lot of manual assembly surgery.
The only sched models that for cpu's that support avx2
but not avx512 are: haswell, broadwell, skylake, zen1-3
For load we have:
https://godbolt.org/z/YTeT9M7fW - for intels `Block RThroughput: <=212.0`; for ryzens, `Block RThroughput: <=64.0`
So could pick cost of `212`
For store we have:
https://godbolt.org/z/vc954KEGP - for intels `Block RThroughput: <=90.0`; for ryzens, `Block RThroughput: <=24.0`
So we could pick cost of `90`.
I'm directly using the shuffling asm the llc produced,
without any manual fixups that may be needed
to ensure sequential execution.
Reviewed By: RKSimon
Differential Revision: https://reviews.llvm.org/D111940
PeixinQiao [Sun, 17 Oct 2021 14:05:57 +0000 (22:05 +0800)]
This patch supports the following checks for THREADPRIVATE Directive:
```
[5.1] 2.21.2 THREADPRIVATE Directive
A variable that appears in a threadprivate directive must be declared in
the scope of a module or have the SAVE attribute, either explicitly or
implicitly.
A variable that appears in a threadprivate directive must not be an
element of a common block or appear in an EQUIVALENCE statement.
```
This patch supports the following checks for DECLARE TARGET Directive:
```
[5.1] 2.14.7 Declare Target Directive
A variable that is part of another variable (as an array, structure
element or type parameter inquiry) cannot appear in a declare
target directive.
A variable that appears in a declare target directive must be declared
in the scope of a module or have the SAVE attribute, either explicitly
or implicitly.
A variable that appears in a declare target directive must not be an
element of a common block or appear in an EQUIVALENCE statement.
```
As Fortran 2018 standard [8.5.16] states, a variable, common block, or
procedure pointer declared in the scoping unit of a main program,
module, or submodule implicitly has the SAVE attribute, which may be
confirmed by explicit specification.
Reviewed By: kiranchandramohan
Differential Revision: https://reviews.llvm.org/D109864
Aaron Ballman [Sun, 17 Oct 2021 13:22:29 +0000 (09:22 -0400)]
Bump the value of __STDC_VERSION__ in -std=c2x mode
Previously, we reported the same value as for C17, now we report 202000L, which
is the same value currently used by GCC.
Once C23 ships, this value will be bumped to the correct date.
David Green [Sun, 17 Oct 2021 12:21:28 +0000 (13:21 +0100)]
[InstCombine] Add some extra tests for truncated saturates. NFC
Aaron Ballman [Sun, 17 Oct 2021 11:54:48 +0000 (07:54 -0400)]
Lex arguments for __has_cpp_attribute and friends as expanded tokens
The C and C++ standards require the argument to __has_cpp_attribute and
__has_c_attribute to be expanded ([cpp.cond]p5). It would make little sense
to expand the argument to those operators but not expand the argument to
__has_attribute and __has_declspec, so those were both also changed in this
patch.
Note that it might make sense for the other builtins to also expand their
argument, but it wasn't as clear to me whether the behavior would be correct
there, and so they were left for a future revision.
David Truby [Wed, 13 Oct 2021 14:08:02 +0000 (14:08 +0000)]
[llvm][AArch64][SVE] Fold literals into math instructions
SVE has predicated literal forms of some instructions for specific
literals, which currently are generated correctly when using ACLE
but not when those instructions are generated directly.
This adds the patterns to generate those instructions when
generating from standard LLVM IR instructions.
Differential Revision: https://reviews.llvm.org/D99074
Dmitry Vyukov [Mon, 27 Sep 2021 12:57:18 +0000 (14:57 +0200)]
tsan: refactor trace tests
Instead of creating real threads for trace tests
create a new ThreadState in the main thread.
This makes the tests more unit-testy and will also
help with future trace tests that will need
more than 1 thread. Creating more than 1 real thread and
dispatching test actions across multiple threads in the
required deterministic order is painful.
This is resubmit of reverted D110546 with 2 changes:
1. The previous version patched ImitateTlsWrite to not
expect ThreadState to be allocated in TLS (the CHECK
failed for the fake test threads).
This added an ugly hack into production code and was still
logically wrong because we imitated write to the main
thread TLS/stack when we started the fake test thread
(which has nothing to do with the main thread TLS/stack).
This version uses ThreadType::Fiber instead of ThreadType::Regular
for the fake threads. This naturally makes ThreadStart skip
obtaining stack/tls and imitating writes to them.
2. This version still skips the tests on Darwin and PowerPC
to be on the safer side. Build bots reported failures for PowerPC
for the previous version.
Reviewed By: melver
Differential Revision: https://reviews.llvm.org/D111156
LLVM GN Syncbot [Sun, 17 Oct 2021 08:39:45 +0000 (08:39 +0000)]
[gn build] Port
ff13189c5d0d
Kito Cheng [Sun, 17 Oct 2021 08:38:53 +0000 (16:38 +0800)]
[RISCV][NFC] Fix build error
Kito Cheng [Wed, 23 Jun 2021 08:18:54 +0000 (16:18 +0800)]
[RISCV] Unify the arch string parsing logic to to RISCVISAInfo.
How many place you need to modify when implementing a new extension for RISC-V?
At least 7 places as I know:
- Add new SubtargetFeature at RISCV.td
- -march parser in RISCV.cpp
- RISCVTargetInfo::initFeatureMap@RISCV.cpp for handling feature vector.
- RISCVTargetInfo::getTargetDefines@RISCV.cpp for pre-define marco.
- Arch string parser for ELF attribute in RISCVAsmParser.cpp
- ELF attribute emittion in RISCVAsmParser.cpp, and make sure it's in
canonical order...
- ELF attribute emittion in RISCVTargetStreamer.cpp, and again, must in
canonical order...
And now, this patch provide an unified infrastructure for handling (almost)
everything of RISC-V arch string.
After this patch, you only need to update 2 places for implement an extension
for RISC-V:
- Add new SubtargetFeature at RISCV.td, hmmm, it's hard to avoid.
- Add new entry to RISCVSupportedExtension@RISCVISAInfo.cpp or
SupportedExperimentalExtensions@RISCVISAInfo.cpp .
Most codes are come from existing -march parser, but with few new feature/bug
fixes:
- Accept version for -march, e.g. -march=rv32i2p0.
- Reject version info with `p` but without minor version number like `rv32i2p`.
Differential Revision: https://reviews.llvm.org/D105168
Kazu Hirata [Sun, 17 Oct 2021 06:31:20 +0000 (23:31 -0700)]
Use llvm::erase_value (NFC)
David Blaikie [Sun, 17 Oct 2021 05:43:57 +0000 (22:43 -0700)]
Fix a few warnings (signed/unsigned comparison in gtest, and missing field initializers)
William S. Moses [Fri, 15 Oct 2021 19:34:23 +0000 (15:34 -0400)]
[MLIR][LLVM] Add memset intrinsic
Add memset intrinsic into LLVM dialect
Reviewed By: mehdi_amini
Differential Revision: https://reviews.llvm.org/D111906
Ben Shi [Sat, 16 Oct 2021 22:14:59 +0000 (22:14 +0000)]
Revert "[AArch64] Optimize add/sub with immediate"
This reverts commit
9bf6bef9951a1c230796ccad2c5c0195ce4c4dff.
Fangrui Song [Sat, 16 Oct 2021 22:03:14 +0000 (15:03 -0700)]
[Object] Simplify RELR decoding
Vitaly Buka [Sat, 16 Oct 2021 20:31:59 +0000 (13:31 -0700)]
[NFC][sanitizer] Add StackDepotTestOnlyUnmap
Vitaly Buka [Sat, 16 Oct 2021 20:31:59 +0000 (13:31 -0700)]
[NFC][sanitizer] Rename stack depot tests
Craig Topper [Sat, 16 Oct 2021 20:31:41 +0000 (13:31 -0700)]
[X86] Add DAG combine for negation of CMOV absolute value pattern.
This patch detects the absolute value pattern on the RHS of a
subtract. If we find it we swap the CMOV true/false values and
replace the subtract with an ADD.
There may be a more generic way to do this, but I'm not sure.
Targets that don't have legal or custom ISD::ABS use a generic
expand in DAG combiner already when it sees (neg (abs(x))). I
haven't checked what happens if the neg is a more general subtract.
Fixes PR50991 for X86.
Reviewed By: RKSimon, spatel
Differential Revision: https://reviews.llvm.org/D111858
Chris Lattner [Sat, 16 Oct 2021 20:01:13 +0000 (13:01 -0700)]
[Builders.h] Silence a warning by adding a cast.
The no-result version of createOrFold calls 'tryFold' but
ignores the result since it doesn't matter what it produced.
Explicitly cast to void to silence this warning:
../llvm/mlir/include/mlir/IR/Builders.h:454:5: warning: ignoring return value of function declared with 'nodiscard' attribute [-Wunused-result]
tryFold(op.getOperation(), unused);
^~~~~~~ ~~~~~~~~~~~~~~~~~~~~~~~~~
Differential Revision: https://reviews.llvm.org/D111951
Mehdi Amini [Sat, 16 Oct 2021 20:19:35 +0000 (20:19 +0000)]
Improve fatal error message when an Attribute or Type wasn't initialized by a dialect (NFC)
The existing message hints that the dialect may not be loaded, but there
is also the possibility that the dialect was loaded and the initialize()
method didn't include the Type/Attribute.
Arthur Eubanks [Sat, 16 Oct 2021 19:05:41 +0000 (12:05 -0700)]
Revert "[clang] Pass -clear-ast-before-backend in Clang::ConstructJob()"
This reverts commit
47eb99aa44ab1d20327d67a49d6c47163de76387.
This causes crashes with -print-stats: PR52193.
Nikita Popov [Sat, 16 Oct 2021 18:25:18 +0000 (20:25 +0200)]
[APInt] Fix 1-bit edge case in smul_ov()
The sdiv used to check for overflow can itself overflow if the
LHS is signed min and the RHS is -1. The code tried to account for
this by also checking the commuted version. However, for 1-bit
values, signed min and -1 are the same value, so both divisions
overflow. As such, the overflow for -1 * -1 was not detected
(which results in -1 rather than 1 for 1-bit values). Fix this by
explicitly checking for this case instead.
Noticed while adding exhaustive test coverage for smul_ov(),
which is also part of this commit.
Shilei Tian [Sat, 16 Oct 2021 16:58:11 +0000 (12:58 -0400)]
[OpenMP][deviceRTLs] Fix wrong return value of `__kmpc_is_spmd_exec_mode`
D110279 introduced a bug to the device runtime. In `__kmpc_parallel_51`, we detect
whether we are already in parallel region by `__kmpc_parallel_level() > __kmpc_is_spmd_exec_mode()`.
It is based on the assumption that:
- In SPMD mode, parallel level is initialized to 1.
- In generic mode, parallel level is initialized to 0.
- `__kmpc_is_spmd_exec_mode` returns `1` for SPMD mode, 0 otherwise.
Because the return value type of `__kmpc_is_spmd_exec_mode` is `int8_t`, there
was an implicit cast from `bool` to `int8_t`. We can make sure it is either 0 or
1 since C++14. In D110279, the return value is the result of an `and` operation,
which is 2 in SPMD mode. This breaks the assumption in `__kmpc_parallel_51`.
Reviewed By: carlo.bertolli, dpalermo
Differential Revision: https://reviews.llvm.org/D111905
Simon Pilgrim [Sat, 16 Oct 2021 16:27:52 +0000 (17:27 +0100)]
[TTI][X86] Add v8i16 -> 2 x v4i16 stride 2 interleaved load costs
Split SSE2 and SSSE3 costs to correctly handle PSHUFB lowering - as was noted on D111938
Mark de Wever [Sat, 16 Oct 2021 10:22:25 +0000 (12:22 +0200)]
[libc++][doc] Adds more issue status labels.
A followup to D111458 adding more labels to LWG-issues. This should add
the labels for the not completed chrono, format, ranges, and spaceship
issues.
Some minor formatting cleanups along the way.
Reviewed By: #libc, Quuxplusone
Differential Revision: https://reviews.llvm.org/D111935
Simon Pilgrim [Sat, 16 Oct 2021 15:21:37 +0000 (16:21 +0100)]
[TTI][X86] Add SSE2 sub-128bit vXi16/32 and v2i64 stride 2 interleaved load costs
These cases use the same codegen as AVX2 (pshuflw/pshufd) for the sub-128bit vector deinterleaving, and unpcklqdq for v2i64.
It's going to take a while to add full interleaved cost coverage, but since these are the same for SSE2 -> AVX2 it should be an easy win.
Fixes PR47437
Differential Revision: https://reviews.llvm.org/D111938
Roman Lebedev [Sat, 16 Oct 2021 14:48:09 +0000 (17:48 +0300)]
[NFC][X86][Codegen] Add missing interleaving tests after D111546
Kazu Hirata [Sat, 16 Oct 2021 14:52:21 +0000 (07:52 -0700)]
Use llvm::is_contained (NFC)
Martin Storsjö [Mon, 4 Oct 2021 21:03:57 +0000 (00:03 +0300)]
[Support] Add more Windows error codes to mapWindowsError
Also sort ERROR_BAD_NETPATH correctly.
Compared with the similar error code mapping in
libcxx/src/filesystem/operations.cpp, I'm leaving out
mappings for ERROR_NOT_SAME_DEVICE and ERROR_OPERATION_ABORTED.
They map nicely to std::errc::cross_device_link and
std::errc::operation_canceled, but those aren't available in
llvm::errc, as they aren't available across all platforms.
Also, the libcxx version maps ERROR_INVALID_NAME to
no_such_file_or_directory instead of invalid_argument.
Differential Revision: https://reviews.llvm.org/D111874
Simon Pilgrim [Sat, 16 Oct 2021 12:40:36 +0000 (13:40 +0100)]
[LV][X86] Add PR47437 test case
Raphael Isemann [Sat, 16 Oct 2021 11:46:21 +0000 (13:46 +0200)]
[lldb] Split ParseSingleMember into Obj-C property and normal member/ivar parsing code.
Right now DWARFASTParserClang::ParseSingleMember has two parts: One part parses
Objective-C properties and the other part parses C/C++ members/Objective-C
ivars. These parts are pretty much independent of each other (with one
historical exception, see below) and in practice they parse DIEs with different
tags/attributes: `DW_TAG_APPLE_property` and `DW_TAG_member`.
I don't see a good reason for keeping the different parsing code intertwined in
a single function, so instead split out the Objective-C property parser into its
own function.
Note that 90% of this commit is just unindenting nearly all of
`ParseSingleMember` which was inside a `if (tag == DW_TAG_member)` block. I.e.,
think of the old `ParseSingleMember` function as: The rest is just moving the
property parsing code into its own function and I added the ReportError
implementation in case we fail to resolve the property type (which before was
just a silent failure).
```
lang=c++
void DWARFASTParserClang::ParseSingleMember(...) {
[...]
if (tag == DW_TAG_member) {
[...] // This huge block got unindented in this patch as the `if` above is gone.
}
if (property) {
[...] // This is the property parsing code that is now its own function.
}
}
```
There is one exception to the rule that the parsers are independent. Before 2012
Objective-C properties were encoded as `DW_TAG_member` with
`DW_AT_APPLE_property*` attributes describing the property. In 2012 this has
changed in a series of commits (see for example
c0449635b35b057c5a877343b0c5f14506c7cf02 which updates the docs) so that
`DW_TAG_APPLE_property` is now used for properties. With the old format we first
created an ivar and afterwards used the `DW_AT_APPLE_property*` attributes to
create the respective property, but there doesn't seem to be any way to create
such debug info with any clang from the last 9 years. So this is technically not
NFC in case some finds debug info from that time and tries to use properties.
Reviewed By: aprantl
Differential Revision: https://reviews.llvm.org/D111632
Tomasz MiÄ…sko [Fri, 15 Oct 2021 18:43:55 +0000 (20:43 +0200)]
[Symbolize] Demangle Rust symbols
Add support for demangling Rust v0 symbols to LLVM symbolizer by reusing
nonMicrosoftDemangle which supports both Itanium and Rust mangling.
Reviewed By: dblaikie, jhenderson
Part of https://reviews.llvm.org/D110664
Tomasz MiÄ…sko [Fri, 15 Oct 2021 18:43:27 +0000 (20:43 +0200)]
[llvm-cxxfilt] Use nonMicrosoftDemangle for demangling NFC
Reviewed By: dblaikie, jhenderson
Part of https://reviews.llvm.org/D110664
Tomasz MiÄ…sko [Fri, 15 Oct 2021 18:41:35 +0000 (20:41 +0200)]
[Demangle] Extract nonMicrosoftDemangle from llvm::demangle
Introduce a new demangling function that supports symbols using Itanium
mangling and Rust v0 mangling, and is expected in the near future to
include support for D mangling as well.
Unlike llvm::demangle, the function does not accept extra underscore
decoration. The callers generally know exactly when symbols should
include the extra decoration and so they should be responsible for
stripping it.
Functionally the only intended change is to allow demangling Rust
symbols with an extra underscore decoration through llvm::demangle,
which matches the existing behaviour for Itanium symbols.
Reviewed By: dblaikie, jhenderson
Part of https://reviews.llvm.org/D110664
Frederic Cambus [Sat, 16 Oct 2021 11:20:10 +0000 (13:20 +0200)]
[docs] Mention DragonFlyBSD as a supported platform for LLVM.
Differential Revision: https://reviews.llvm.org/D111758
Simon Pilgrim [Sat, 16 Oct 2021 10:40:19 +0000 (11:40 +0100)]
[Analysis] Replace assert(isa)/dyn_cast with cast. NFC.
cast<> will perform the assertion for us.
Removes a static analysis null dereference warning.
Simon Pilgrim [Sat, 16 Oct 2021 10:20:07 +0000 (11:20 +0100)]
[LazyValueInfo] getPredicateAt - remove unnecessary null pointer check. NFC.
We already dereference the CxtI pointer several times before reaching the "if(CxtI)", we have no need to check it again.
Fixes a coverity warning.
Simon Pilgrim [Sat, 16 Oct 2021 10:11:48 +0000 (11:11 +0100)]
[ConstantFolding] ConstantFoldScalarCall2 - early-out if getLibFunc fails. NFC.
Simon Pilgrim [Sat, 16 Oct 2021 10:07:00 +0000 (11:07 +0100)]
[ConstantFolding] Use getValueAPF const ref value where possible. NFC.
Don't copy the value if we can avoid it.
Simon Pilgrim [Sat, 16 Oct 2021 10:02:13 +0000 (11:02 +0100)]
[ConstantFolding] ConstantFoldScalarCall1 - early-out if getLibFunc fails. NFC.
Roman Lebedev [Sat, 16 Oct 2021 09:25:08 +0000 (12:25 +0300)]
[X86][LV] X86 does *not* prefer vectorized addressing
And another attempt to start untangling this ball of threads around gather.
There's `TTI::prefersVectorizedAddressing()`hoop, which confusingly defaults to `true`,
which tells LV to try to vectorize the addresses that lead to loads,
but X86 generally can not deal with vectors of addresses,
the only instructions that support that are GATHER/SCATTER,
but even those aren't available until AVX2, and aren't really usable until AVX512.
This specializes the hook for X86, to return true only if we have AVX512 or AVX2 w/ fast gather.
Reviewed By: RKSimon
Differential Revision: https://reviews.llvm.org/D111546
Ben Shi [Tue, 12 Oct 2021 09:03:16 +0000 (09:03 +0000)]
[AArch64] Optimize add/sub with immediate
Optimize ([add|sub] r, imm) -> ([ADD|SUB] ([ADD|SUB] r, #imm0, lsl #12), #imm1),
if imm == (imm0<<12)+imm1. and both imm0 and imm1 are non-zero 12-bit unsigned
integers.
Optimize ([add|sub] r, imm) -> ([SUB|ADD] ([SUB|ADD] r, #imm0, lsl #12), #imm1),
if imm == -(imm0<<12)-imm1, and both imm0 and imm1 are non-zero 12-bit unsigned
integers.
Reviewed By: jaykang10, dmgreen
Differential Revision: https://reviews.llvm.org/D111034
Carlos Galvez [Tue, 28 Sep 2021 08:37:32 +0000 (08:37 +0000)]
[clang-tidy] Fix false positive in cppcoreguidelines-virtual-class-destructor
Incorrectly triggers for template classes that inherit
from a base class that has virtual destructor.
Any class inheriting from a base that has a virtual destructor
will have their destructor also virtual, as per the Standard:
https://timsong-cpp.github.io/cppwp/n4140/class.dtor#9
> If a class has a base class with a virtual destructor,
> its destructor (whether user- or implicitly-declared) is virtual.
Added unit tests to prevent regression.
Fixes bug https://bugs.llvm.org/show_bug.cgi?id=51912
Differential Revision: https://reviews.llvm.org/D110614
Matthias Springer [Sat, 16 Oct 2021 08:08:00 +0000 (17:08 +0900)]
[mlir][linalg][bufferize] Relax rules for extract_slice/insert_slice matching
The rules were too restrictive, causing out-of-place bufferization when the result of two ExtractSliceOp is fed into an InsertSliceOp.
Differential Revision: https://reviews.llvm.org/D111861
Craig Topper [Sat, 16 Oct 2021 07:26:59 +0000 (00:26 -0700)]
[TableGen] Replace static_cast with llvm's cast. NFC
These all appear next to an isa<> and cast<> is much more
common in these cases.
Juneyoung Lee [Sat, 16 Oct 2021 07:20:14 +0000 (16:20 +0900)]
Fix missing failures in clang-ppc64be* and retry fixing clang-x64-windows-msvc
Groverkss [Sat, 16 Oct 2021 06:45:31 +0000 (12:15 +0530)]
[MLIR] Generalize Affine dependence analysis using Affine Relations
This patch removes code very specific to affine dependence analysis and
refactors it as a FlatAfffineRelation.
A FlatAffineRelation represents a set of ordered pairs (domain -> range) where
"domain" and "range" are tuples of identifiers. These relations are used to
represent an "access relation" for memory access on a memref. An access
relation maps elements of an iteration domain to the element(s) of an array
domain accessed by that iteration of the associated statement through some
array reference. The dependence relation representing the dependence
constraints between two memory accesses can be built by composing the access
relation of the destination access by the inverse of the access relation of
source access.
This patch does not change the functionality of the existing dependence
analysis in checkMemrefAccessDependence, but refactors it to use
FlatAffineRelations to deduplicate code and enable code reuse for future
development of features like scheduling, value-based dependence analysis, etc.
Reviewed By: bondhugula
Differential Revision: https://reviews.llvm.org/D110563
Juneyoung Lee [Sat, 16 Oct 2021 05:33:59 +0000 (14:33 +0900)]
Fix lit test failures in clang-ppc* and clang-x64-windows-msvc
Juneyoung Lee [Sat, 16 Oct 2021 04:51:50 +0000 (13:51 +0900)]
Resolve lit failures in clang after 8ca4b3e's land
Juneyoung Lee [Fri, 15 Oct 2021 10:45:30 +0000 (19:45 +0900)]
[Clang/Test]: Rename enable_noundef_analysis to disable-noundef-analysis and turn it off by default (2)
This patch updates test files after D105169.
Autogenerated test codes are changed by `utils/update_cc_test_checks.py,` and non-autogenerated test codes are changed as follows:
(1) I wrote a python script that (partially) updates the tests using regex: {
F18594904} The script is not perfect, but I believe it gives hints about which patterns are updated to have `noundef` attached.
(2) The remaining tests are updated manually.
Reviewed By: eugenis
Differential Revision: https://reviews.llvm.org/D108453
Juneyoung Lee [Fri, 15 Oct 2021 10:26:07 +0000 (19:26 +0900)]
[Clang/Test]: Rename enable_noundef_analysis to disable-noundef-analysis and turn it off by default
Turning on `enable_noundef_analysis` flag allows better codegen by removing freeze instructions.
I modified clang by renaming `enable_noundef_analysis` flag to `disable-noundef-analysis` and turning it off by default.
Test updates are made as a separate patch: D108453
Reviewed By: eugenis
Differential Revision: https://reviews.llvm.org/D105169
Michael Kruse [Sat, 16 Oct 2021 02:11:23 +0000 (21:11 -0500)]
[Polly][docs] Fix Sphinx warning.
ReStructured Text is not Markdown.
Craig Topper [Sat, 16 Oct 2021 00:39:00 +0000 (17:39 -0700)]
[X86] Add more tests for D111858. NFC
Add tests with sub instead of neg.
Zhi An Ng [Sat, 16 Oct 2021 00:45:08 +0000 (17:45 -0700)]
[WebAssembly] Add prototype relaxed laneselect instructions
Add i8x16, i16x8, i32x4, i64x2 laneselect instructions. These are only
exposed as builtins, and require user opt-in.
Jacques Pienaar [Sat, 16 Oct 2021 00:30:17 +0000 (17:30 -0700)]
[mlir] Add folder for shape.add
Aart Bik [Fri, 15 Oct 2021 17:07:45 +0000 (10:07 -0700)]
[mlir][sparse] run less combinations of SpMM in test (to reduce runtime)
This revision also adds a few passes to the sparse compiler part to unify the transformation sequence with all other paths we currently use.
Reviewed By: nicolasvasilache
Differential Revision: https://reviews.llvm.org/D111900
Geoffrey Martin-Noble [Fri, 15 Oct 2021 22:40:42 +0000 (15:40 -0700)]
[MLIR][TOSA] Drop "OnTensors" suffix
This is the only lowering to Linalg Tosa has, so it's needlessly
verbose. Likely this was a carry over from IREE's usage where we
originally lowered to linalg on buffers (the only linalg that existed at
the time), so the everything on tensors needed the suffix. We're dropping
it in IREE also, having transitioned entirely to using Linalg on
tensors.
Reviewed By: sjarus
Differential Revision: https://reviews.llvm.org/D111911
Fangrui Song [Fri, 15 Oct 2021 22:36:30 +0000 (15:36 -0700)]
[ELF] Require two-dash form for --pack-dyn-relocs
LLD specific options can be more rigid.
Also add a test.
Matheus Izvekov [Thu, 14 Oct 2021 19:49:22 +0000 (21:49 +0200)]
[clang] fix typo correction not looking for candidates in base classes.
RecordMemberExprValidator was not looking through ElaboratedType
nodes when looking for candidates which occur in base classes.
Signed-off-by: Matheus Izvekov <mizvekov@gmail.com>
Reviewed By: rsmith
Differential Revision: https://reviews.llvm.org/D111830
Anshil Gandhi [Fri, 15 Oct 2021 22:15:45 +0000 (16:15 -0600)]
Revert "[HIP] [AlwaysInliner] Disable AlwaysInliner to eliminate undefined symbols"
This reverts commit
03375a3fb33b11e1249d9c88070b7f33cb97802a.
Lawrence D'\''Anna [Fri, 15 Oct 2021 22:05:46 +0000 (15:05 -0700)]
Fix Xcode project for debugserver
It seems StringConvert.cpp was moved, and the Xcode project file
wasn't updated.
Reviewed By: JDevlieghere
Differential Revision: https://reviews.llvm.org/D111910
Nikita Popov [Fri, 15 Oct 2021 19:25:39 +0000 (21:25 +0200)]
[ConstantRange] Compute precise shl range for single elements
For the common case where the shift amount is constant (a single
element range) we can easily compute a precise range (up to
unsigned envelope), so do that.
Anshil Gandhi [Fri, 15 Oct 2021 21:16:32 +0000 (15:16 -0600)]
[HIP] Relax conditions for address space cast in builtin args
Allow (implicit) address space casting between LLVM-equivalent
target address spaces.
Reviewed By: yaxunl, tra
Differential Revision: https://reviews.llvm.org/D111734
Arthur Eubanks [Fri, 15 Oct 2021 21:33:13 +0000 (14:33 -0700)]
[NFC] Make Assume2KnowledgeMap's typedef more precise
Sanjay Patel [Fri, 15 Oct 2021 21:09:02 +0000 (17:09 -0400)]
[InstCombine] generalize fold for mask-with-signbit-splat, part 2
This removes an over-specified fold. The more general transform
was added with:
727e642e970d
There's a difference on an existing test that shows a potentially
unnecessary use limit on an icmp fold.
That fold is in InstCombinerImpl::foldICmpSubConstant(), and IIRC
there was some back-and-forth on it and similar folds because they
could cause analysis/passes (SCEV, LSR?) to miss optimizations.
Differential Revision: https://reviews.llvm.org/D111410
Stanislav Mekhanoshin [Fri, 15 Oct 2021 20:50:23 +0000 (13:50 -0700)]
[AMDGPU] Precommit fused-bitlogic.ll test. NFC.
Nikita Popov [Fri, 15 Oct 2021 20:44:52 +0000 (22:44 +0200)]
[ConstantRange] Support checking optimality for subset of inputs (NFC)
We always want to check correctness, but for some operations we
can only guarantee optimality for a subset of inputs. Accept an
additional predicate that determines whether optimality for a
given pair of ranges should be checked.
Anshil Gandhi [Fri, 15 Oct 2021 20:41:41 +0000 (14:41 -0600)]
Revert "[HIP] Relax conditions for address space cast in builtin args"
This reverts commit
3b48e1170dc623a95ff13a1e34c839cc094bf321.
Sanjay Patel [Fri, 15 Oct 2021 20:22:59 +0000 (16:22 -0400)]
[InstCombine] generalize fold for mask-with-signbit-splat
(iN X s>> (N-1)) & Y --> (X < 0) ? Y : 0
https://alive2.llvm.org/ce/z/qeYhdz
I was looking at a missing abs() transform and found my way to this
generalization of an existing fold that was added with D67799.
As discussed in that review, we want to make sure codegen handles
this difference well, and for all of the targets/types that I
spot-checked, it looks good.
I am leaving the existing fold in place in this commit because
it covers a potentially missing icmp fold, but I plan to remove
that as a follow-up commit as suggested during review.
Differential Revision: https://reviews.llvm.org/D111410
Anshil Gandhi [Fri, 15 Oct 2021 19:44:38 +0000 (13:44 -0600)]
[HIP] Relax conditions for address space cast in builtin args
Allow (implicit) address space casting between LLVM-equivalent
target address spaces.
Reviewed By: yaxunl
Differential Revision: https://reviews.llvm.org/D111734
Nikita Popov [Fri, 15 Oct 2021 19:56:54 +0000 (21:56 +0200)]
[BasicAA] Rename ExtendedValue to CastedValue (NFC)
As suggested on D110977, rename ExtendedValue to CastedValue,
because it will contain more than just extensions in the future.
Nikita Popov [Fri, 15 Oct 2021 19:35:57 +0000 (21:35 +0200)]
[ConstantRange] Better diagnostic for correctness test failure (NFC)
Print a friendly error message including the inputs, result and
not-contained element if an exhaustive correctness test fails,
same as we do if the optimality test fails.
Volodymyr Sapsai [Sat, 9 Oct 2021 00:10:18 +0000 (17:10 -0700)]
[modules] Make a module map referenced by a system map a system one too.
Mimic the behavior of including headers where a system includer makes an
includee a system header too.
rdar://
84049469
Differential Revision: https://reviews.llvm.org/D111476
Florian Hahn [Fri, 15 Oct 2021 18:27:23 +0000 (19:27 +0100)]
[VectorCombine] Add option to only run scalarization transforms.
This patch adds a pass option to only run transforms that scalarize
vector operations and do not create new vector instructions.
When running VectorCombine early in the pipeline introducing new vector
operations can have negative effects, like blocking loop or SLP
vectorization. To avoid regressions, restrict the early VectorCombine
run (when using -enable-matrix) to only perform scalarization and not
introduce new vector operations.
This is done as option to the pass directly, which is then set when
adding the pass to the pipeline. This is done for the new pass manager
only.
Reviewed By: spatel
Differential Revision: https://reviews.llvm.org/D111800
Pirama Arumuga Nainar [Fri, 15 Oct 2021 18:56:16 +0000 (11:56 -0700)]
[compiler-rt/profile] Hide __llvm_profile_raw_version
Hide __llvm_profile_raw_version so as not to resolve reference from a
dependent shared object. Since libclang_rt.profile is added later in
the command line, a definition of __llvm_profile_raw_version is not
included if it is provided from an earlier object, e.g. from a shared
dependency.
This causes an extra dependence edge where if libA.so depends on libB.so
and both are coverage-instrumented, libA.so uses libB.so's definition of
__llvm_profile_raw_version. This leads to a runtime link failure if the
libB.so available at runtime does not provide this symbol (but provides
the other dependent symbols). Such a scenario can occur in Android's
mainline modules.
E.g.:
ld -o libB.so libclang_rt.profile-x86_64.a
ld -o libA.so -l B libclang_rt.profile-x86_64.a
libB.so has a global definition of __llvm_profile_raw_version. libA.so
uses libB.so's definition of __llvm_profile_raw_version. At runtime,
libB.so may not be coverage-instrumented (i.e. not export
__llvm_profile_raw_version) so runtime linking of libA.so will fail.
Marking this symbol as hidden forces each binary to use the definition
of __llvm_profile_raw_version from libclang_rt.profile.
Differential Revision: https://reviews.llvm.org/D111759
Sam Clegg [Thu, 7 Oct 2021 19:17:15 +0000 (12:17 -0700)]
[WebAssembly] Add import info to `dylink` section of shared libraries
See https://github.com/WebAssembly/tool-conventions/pull/175
Differential Revision: https://reviews.llvm.org/D111345
Mingming Liu [Fri, 15 Oct 2021 18:27:40 +0000 (11:27 -0700)]
[SelectionDAG] Fix typo in option help
Reviewed By: MaskRay
Differential Revision: https://reviews.llvm.org/D111867
Anshil Gandhi [Fri, 15 Oct 2021 17:13:12 +0000 (11:13 -0600)]
[HIP] [AlwaysInliner] Disable AlwaysInliner to eliminate undefined symbols
By default clang emits complete contructors as alias of base constructors if they are the same.
The backend is supposed to emit symbols for the alias, otherwise it causes undefined symbols.
@yaxunl observed that this issue is related to the llvm options `-amdgpu-early-inline-all=true`
and `-amdgpu-function-calls=false`. This issue is resolved by only inlining global values
with internal linkage. The `getCalleeFunction()` in AMDGPUResourceUsageAnalysis also had
to be extended to support aliases to functions. inline-calls.ll was corrected appropriately.
Reviewed By: yaxunl, #amdgpu
Differential Revision: https://reviews.llvm.org/D109707
Nico Weber [Thu, 14 Oct 2021 22:32:10 +0000 (18:32 -0400)]
[lld/mac] Mark private externs with GOT relocs as LOCAL in indirect symbtab
prepareSymbolRelocation() in Writer.cpp adds both symbols that need binding and
symbols relocated with a pointer relocation to the got.
Pointer relocations are emitted for non-movq GOTPCREL(%rip) loads. (movqs
become GOT_LOADs so that the linker knows they can be relaxed to leaqs, while
others, such as addq, become just GOT -- a pointer relocation -- since they
can't be relaxed in that way).
For example, this C file produces a private_extern GOT relocation when
compiled with -O2 with clang:
extern const char kString[];
const char* g(int a) { return kString + a; }
Linkers need to put pointer-relocated symbols into the GOT, but ld64 marks them
as LOCAL in the indirect symbol table. This matters, since `strip -x` looks at
the indirect symbol table when deciding what to strip.
The indirect symtab emitting code was assuming that only symbols that need
binding are in the GOT, but pointer relocations where there too. Hence, the
code needs to explicitly check if a symbol is a private extern.
Fixes https://crbug.com/1242638, which has some more information in comments 14
and 15. With this patch, the output of `nm -U` on Chromium Framework after
stripping now contains just two symbols when using lld, just like with ld64.
Differential Revision: https://reviews.llvm.org/D111852
Michael Liao [Thu, 14 Oct 2021 20:10:15 +0000 (16:10 -0400)]
[amdgpu] Fix a crash case when preserving MDT in SILowerControlFlow
- When a redundant MBB is being erased from MDT, check whether its
single successor is dominiated by it. If yes, update that successor's
idom before erasing MBB; otherwise, it implies MBB is a leaf node and
could be erased directly.
Reviewed By: foad
Differential Revision: https://reviews.llvm.org/D111831
Vitaly Buka [Fri, 15 Oct 2021 02:04:23 +0000 (19:04 -0700)]
[ubsan] Remove REQUIRED from some TestCases
It's not obvious why they are needed, and tests pass.
Reviewed By: lebedev.ri
Differential Revision: https://reviews.llvm.org/D111859
Arthur Eubanks [Wed, 6 Oct 2021 20:57:29 +0000 (13:57 -0700)]
[clang] Pass -clear-ast-before-backend in Clang::ConstructJob()
This clears the memory used for the Clang AST before we run LLVM passes.
https://llvm-compile-time-tracker.com/compare.php?from=
d0a5f61c4f6fccec87fd5207e3fcd9502dd59854&to=
b7437fee79e04464dd968e1a29185495f3590481&stat=max-rss
shows significant memory savings with no slowdown (in fact -O0 slightly speeds up).
For more background, see
https://lists.llvm.org/pipermail/cfe-dev/2021-September/068930.html.
Turn this off for the interpreter since it does codegen multiple times.
Differential Revision: https://reviews.llvm.org/D111270
Jonas Paulsson [Fri, 15 Oct 2021 15:43:39 +0000 (17:43 +0200)]
[SystemZ] Handle huge immediates in SystemZInstrInfo::loadImmediate().
This is needed during isel pseudo expansion in order not to crash on huge
immediates.
Review: Ulrich Weigand
Kazu Hirata [Fri, 15 Oct 2021 17:07:08 +0000 (10:07 -0700)]
[clang] Use llvm::is_contained (NFC)
Jessica Paquette [Fri, 15 Oct 2021 16:59:00 +0000 (09:59 -0700)]
NFC: Remove wayward MIR tests from lib/Target
These were put in lib/Target instead of tests.
Thankfully dupes of them already existed in the tests directory.
So, just delete them.
Raphael Isemann [Fri, 15 Oct 2021 16:48:17 +0000 (18:48 +0200)]
[lldb] Harden TestCompletion against new settings in 'target.process'
This test starts failing when people add a setting starting with
`target.process.t` which of course can easily happen. Make it a bit more
resistant by only requiring that `target.process.thr` has a unique completion.
Alexey Bataev [Fri, 15 Oct 2021 16:42:14 +0000 (09:42 -0700)]
[SLP]Add a test for shrink shuffle after reorder, NFC.
Ellis Hoag [Fri, 15 Oct 2021 16:37:12 +0000 (12:37 -0400)]
[DebugInfo] retainedTypes should not have subprograms
After D80369, the retainedTypes in CU's should not have any subprograms
so we should not handle that case when emitting debug info.
Differential Revision: https://reviews.llvm.org/D111593
Stephen Tozer [Tue, 21 Sep 2021 14:11:22 +0000 (15:11 +0100)]
[DebugInfo] Limit the size of DIExpressions that we will salvage up to
Fixes: https://bugs.llvm.org/show_bug.cgi?id=51841
This patch places an arbitrary limit on the size of DIExpressions that
we will produce via salvaging, for performance reasons. This helps to
fix a performance issue observed in the bug above, in which debug values
would be salvaged hundreds of times, producing expressions with over
1000 elements and causing the compiler to hang. Limiting the size of
debug values that we will produce to 128 largely fixes this issue.
Reviewed By: dblaikie, jmorse
Differential Revision: https://reviews.llvm.org/D110332
Aart Bik [Thu, 14 Oct 2021 01:33:53 +0000 (18:33 -0700)]
[mlir][sparse] implement sparse tensor init operation
Next step towards supporting sparse tensors outputs.
Also some minor refactoring of enum constants as well
as replacing tensor arguments with proper buffer arguments
(latter is required for more general sizes arguments for
the sparse_tensor.init operation, as well as more general
spares_tensor.convert operations later)
Reviewed By: wrengr
Differential Revision: https://reviews.llvm.org/D111771