[arm] Early split subdi3

This patch adds early splitting of subdi3 so that the individual
operations can be seen by the optimizers, particuarly combine.  This
should allow us to do at least as good a job as previously, but with
far fewer patterns in the machine description.

This is just the initial patch to add the early splitting.  The
cleanups will follow later.

A special trick is used to handle the 'reverse subtract and compare'
where a register is subtracted from a constant.  The natural
comparison

    (COMPARE (const) (reg))

is not canonical in this case and combine will never correctly
generate it (trying to swap the order of the operands.  To handle this
we write the comparison as

    (COMPARE (NOT (reg)) (~const)),

which has the same result for EQ, NE, LTU, LEU, GTU and GEU, which are
all the cases we are really interested in here.

Finally, we delete the negdi2 pattern.  The generic expanders will use
our new subdi3 expander if this pattern is missing and that can handle
the negate case just fine.

* config/arm/arm-modes.def (CC_RSB): New CC mode.
* config/arm/predicates.md (arm_borrow_operation): Handle CC_RSBmode.
* config/arm/arm.c (arm_select_cc_mode): Detect when we should
return CC_RSBmode.
(maybe_get_arm_condition_code): Handle CC_RSBmode.
* config/arm/arm.md (subsi3_carryin): Make this pattern available to
expand.
(subdi3): Rewrite to early-expand the sub-operations.
(rsb_im_compare): New pattern.
(negdi2): Delete.
(negdi2_insn): Delete.
(arm_negsi2): Correct type attribute to alu_imm.
(negsi2_0compare): New insn pattern.
(negsi2_carryin): New insn pattern.

From-SVN: r277169

[arm] fix constraints on addsi3_carryin_alt2

addsi3_carryin_alt2 has a more strict constraint than the predicate
when adding a constant.  This leads to sub-optimal code in some
circumstances.

* config/arm/arm.md (addsi3_carryin_alt2): Use arm_not_operand for
operand 2.

From-SVN: r277168

[arm] Rewrite addsi3_carryin_shift_<optab> in canonical form

The add-with-carry operation which involves a shift doesn't match at present
because it isn't matching the canonical form generated by combine.  Fixing
this is simply a matter of re-ordering the operands.

* config/arm/arm.md (addsi3_carryin_shift_<optab>): Reorder operands
to match canonical form.

From-SVN: r277167

[arm] Early split zero- and sign-extension

This patch changes the insn patterns for zero- and sign-extend into
define_expands that generate the appropriate word operations
immediately.

* config/arm/arm.md (zero_extend<mode>di2): Convert to define_expand.
(extend<mode>di2): Likewise.

From-SVN: r277166

[arm] Perform early splitting of adddi3.

This patch causes the expansion of adddi3 to split the operation
immediately for Arm and Thumb-2.  This is desirable as it frees up the
register allocator to pick what ever combination of registers suits
best and reduces the number of auxiliary patterns that we need in the
back-end.  Three of the testcases that we disabled earlier are already
fixed by this patch.  Finally, we add a new pattern to match the
canonicalization of add-with-carry when using an immediate of zero.

gcc:
* config/arm/arm-protos.h (arm_decompose_di_binop): New prototype.
* config/arm/arm.c (arm_decompose_di_binop): New function.
* config/arm/arm.md (adddi3): Also accept any const_int for op2.
If not generating Thumb-1 code, decompose the operation into 32-bit
pieces.
* add0si_carryin_<optab>: New pattern.

testsuite:
* gcc.target/arm/pr53447-1.c: Remove XFAIL.
* gcc.target/arm/pr53447-3.c: Remove XFAIL.
* gcc.target/arm/pr53447-4.c: Remove XFAIL.

From-SVN: r277165

[arm] Rip out DImode addition and subtraction splits.

The first step towards early splitting of addition and subtraction at
DImode is to rip out the old patterns that are designed to propagate
DImode through the RTL optimization passes and the do late splitting.

This patch does cause some code size regressions, but it should still
execute correctly.  We will progressively add back the optimizations
we had here in later patches.

A small number of tests in the Arm-specific testsuite do fail as a
result of this patch, but that's to be expected, since the
optimizations they are looking for have just been removed.  I've kept
the tests, but XFAILed them for now.

One small technical change is also done in this patch as part of the
cleanup: the uaddv<mode>4 expander is changed to use LTU as the branch
comparison.  This eliminates the need for CC_Cmode to recognize
somewhat bogus equality constraints.

gcc:
* arm.md (adddi3): Only accept register operands.
(arm_adddi3): Convert to simple insn with no split.  Do not accept
constants.
(adddi_sesidi_di): Delete patern.
(adddi_zesidi_di): Likewise.
(uaddv<mode>4): Use LTU as condition for branch.
(adddi3_compareV): Convert to simple insn with no split.
(addsi3_compareV_upper): Delete pattern.
(adddi3_compareC): Convert to simple insn with no split.  Correct
flags setting expression.
(addsi3_compareC_upper): Delete pattern.
(addsi3_compareC): Correct flags setting expression.
(subdi3_compare1): Convert to simple insn with no split.
(subsi3_carryin_compare): Delete pattern.
(arm_subdi3): Convert to simple insn with no split.
(subdi_zesidi): Delete pattern.
(subdi_di_sesidi): Delete pattern.
(subdi_zesidi_di): Delete pattern.
(subdi_sesidi_di): Delete pattern.
(subdi_zesidi_zesidi): Delete pattern.
(negvdi3): Use s_register_operand.
(negdi2_compare): Convert to simple insn with no split.
(negdi2_insn): Likewise.
(negsi2_carryin_compare): Delete pattern.
(negdi_zero_extendsidi): Delete pattern.
(arm_cmpdi_insn): Convert to simple insn with no split.
(negdi2): Don't call gen_negdi2_neon.
* config/arm/neon.md (adddi3_neon): Delete pattern.
(subdi3_neon): Delete pattern.
(negdi2_neon): Delete pattern.
(splits for negdi2_neon): Delete splits.

testsuite:
* gcc.target/arm/negdi-3.c: Add XFAILS.
* gcc.target/arm/pr3447-1.c: Likewise.
* gcc.target/arm/pr3447-3.c: Likewise.
* gcc.target/arm/pr3447-4.c: Likewise.

From-SVN: r277164

re PR fortran/69455 ([F08] Assembler error(s) when using intrinsic modules in two BLOCK)

2019-10-18  Steven G. Kargl  <kargl@gcc.gnu.org>

PR fortran/69455
* trans-decl.c (generate_local_decl): Avoid misconstructed
intrinsic modules in a BLOCK construct.

2019-10-18  Steven G. Kargl  <kargl@gcc.gnu.org>

PR fortran/69455
* gfortran.dg/pr69455_1.f90: New test.
* gfortran.dg/pr69455_2.f90: Ditto.

From-SVN: r277158

re PR middle-end/92153 (ICE / segmentation fault, use-after-free at gcc/ggc-page.c:1159)

PR middle-end/92153
* ggc-page.c (release_pages): Read g->alloc_size before free rather
than after it.

From-SVN: r277157

[Arm] Fix multilibs for Armv7-R

This patch maps multilibs using -march=armv7-r+vfpv3-d16-fp16 and
-march=armv7-r+vfpv3-d16-fp16+idiv to v7+fp.  This patch also adds a new
multilib for armv7-r+fp.sp and maps -march=armv7-r+fp.sp+idiv,
-march=armv7-r+vfpv3xd-fp16 and -march=armv7-r+vfpv3xd-fp16+idiv to it.

This patch also makes it so that the generated multilib header file is
regenerated if changes have been made to either t-multilib, t-aprofile or
t-rmprofile when doing incremental builds.

gcc/ChangeLog:
2019-10-18  Andre Vieira  <andre.simoesdiasvieira@arm.com>

* config/arm/t-multilib: Add rule to regenerate mutlilib header file
with any change to t-multilib, t-aprofile and t-rmprofile.  Also add
new multilib variants and new mappings.

gcc/testsuite/ChangeLog:
2019-10-18  Andre Vieira  <andre.simoesdiasvieira@arm.com>

* gcc.target/arm/multilib.exp: Add extra tests.

From-SVN: r277156

[C++ PATCH] anon type names

https://gcc.gnu.org/ml/gcc-patches/2019-10/msg01354.html
I noticed that we use a bitfield flag to note types with names for linkage
purposes:
  typedef struct {} foo;
but, we can infer this by comparing TYPE_STUB_DECL and TYPE_DECL of the
main variant.  It's only checked in two places -- the C++ parser
and the objective C++ encoder.
* cp-tree.h (struct lang_type): Remove was_anonymous.
(TYPE_WAS_UNNAMED): Implement by checking TYPE_DECL &
TYPE_STUB_DECL.
* decl.c (name_unnamed_type): Don't set TYPE_WAS_UNNAMED.

From-SVN: r277155

Fortran] PR91586 Fix ICE on invalid code with CLASS

        gcc/fortran/
        PR fortran/91586
        * class.c (gfc_find_derived_vtab): Return NULL
        instead of deref'ing NULL pointer.

        gcc/testsuite/
        PR fortran/91586
        * gfortran.dg/class_71.f90: New.

From-SVN: r277153

PR libstdc++/92143 adjust for OS X aligned_alloc behaviour

OS X 10.15 adds aligned_alloc but it has the same restriction as the AIX
version, namely that alignments smaller than sizeof(void*) are not
supported.

PR libstdc++/92143
* libsupc++/new_opa.cc (operator new) [__APPLE__]: Increase alignment
to at least sizeof(void*).

From-SVN: r277151

Implement std::ranges::less without std::less

* include/bits/range_cmp.h (ranges::less::operator()): Inline the
logic from std::less::operator() to remove the dependency on it.

From-SVN: r277150

re PR target/86040 ([avr]: RAMPZ is not always cleared after loading __flashN data)

PR target/86040
* config/avr/avr.c (avr_out_lpm): Do not shortcut-return.

From-SVN: r277143

Fix some fallout for small targets.

gcc/testsuite/
Fix some fallout for small targets.

PR testsuite/52641
* gcc.c-torture/execute/20190820-1.c:
Add dg-require-effective-target int32plus.
* gcc.c-torture/execute/pr85331.c
Add dg-require-effective-target double64plus.
* gcc.dg/pow-sqrt-1.c: Same.
* gcc.dg/pow-sqrt-2.c: Same.
* gcc.dg/pow-sqrt-3.c: Same.
* gcc.c-torture/execute/20190901-1.c: Same.
* gcc.c-torture/execute/user-printf.c [avr]: Skip.
* gcc.c-torture/execute/fprintf-2.c [avr]: Skip.
* gcc.c-torture/execute/printf-2.c [avr]: Skip.
* gcc.dg/Wlarger-than3.c [avr]: Skip.
* gcc.c-torture/execute/ieee/20041213-1.c (sqrt)
[avr,double=float]: Provide custom prototype.
* gcc.dg/pr36017.c: Same.
* gcc.c-torture/execute/pr90025.c: Use 32-bit int.
* gcc.dg/complex-7.c: Add dg-require-effective-target double64.
* gcc.dg/loop-versioning-1.c:
Add dg-require-effective-target size32plus.
* gcc.dg/loop-versioning-2.c: Same.

From-SVN: r277142

re PR target/86753 (gcc.target/aarch64/sve/vcond_[45].c fail after recent combine patch)

2019-10-18  Prathamesh Kulkarni  <prathamesh.kulkarni@linaro.org>
    Richard Sandiford  <richard.sandiford@arm.com>

PR target/86753
* tree-vectorizer.h (scalar_cond_masked_key): New struct,
and define hashmap traits for it.
(loop_vec_info::scalar_cond_masked_set): New member.
(vect_record_loop_mask): Adjust prototype.
* tree-vectorizer.c (scalar_cond_masked_key::get_cond_ops_from_tree):
Implement method.
* tree-vect-loop.c (vectorizable_reduction): Pass NULL as last arg to
vect_record_loop_mask.
(vectorizable_live_operation): Likewise.
(vect_record_loop_mask): New param scalar_mask. Add entry
cond, loop_mask to scalar_cond_masked_set if scalar_mask is non NULL.
* tree-vect-stmts.c (check_load_store_masking): New param scalar_mask.
Pass it as last arg to vect_record_loop_mask.
(vectorizable_call): Pass scalar_mask as last arg to
vect_record_loop_mask.
(vectorizable_store): Likewise.
(vectorizable_load): Likewise.
(vectorizable_condition): Check if another part of vectorized code
applies loop_mask to condition or to it's inverse, and if yes,
apply loop_mask to result of vector comparison.

testsuite/
* gcc.target/aarch64/sve/cond_cnot_2.c: Remove XFAIL
from { scan-assembler-not {\tsel\t}.
* gcc.target/aarch64/sve/cond_convert_1.c: Adjust to make
only one load conditional.
* gcc.target/aarch64/sve/cond_convert_4.c: Likewise.
* gcc.target/aarch64/sve/cond_unary_2.c: Likewise.
* gcc.target/aarch64/sve/vcond_4.c: Remove XFAIL's.
* gcc.target/aarch64/sve/vcond_5.c: Likewise.

Co-Authored-By: Richard Sandiford <richard.sandiford@arm.com>
From-SVN: r277141

Daily bump.

From-SVN: r277140

pa.c (pa_output_indirect_call): Fix typos in last change.

* config/pa/pa.c (pa_output_indirect_call): Fix typos in last change.

From-SVN: r277135

re PR tree-optimization/92056 (ice in expr_object_size, at tree-object-si ze.c:675 with -O3)

PR tree-optimization/92056
* tree-ssa-strlen.c (determine_min_objsize): Call init_object_sizes
before calling compute_builtin_object_size.

* gcc.dg/tree-ssa/pr92056.c: New test.

From-SVN: r277134

decl.c (grokfndecl): Remove redundant use of in_system_header_at.

/cp
2019-10-17  Paolo Carlini  <paolo.carlini@oracle.com>

* decl.c (grokfndecl): Remove redundant use of in_system_header_at.
(compute_array_index_type_loc): Likewise.
(grokdeclarator): Likewise.
* error.c (cp_printer): Likewise.
* lambda.c (add_default_capture): Likewise.
* parser.c (cp_parser_primary_expression): Likewise.
(cp_parser_selection_statement): Likewise.
(cp_parser_toplevel_declaration): Likewise.
(cp_parser_enumerator_list): Likewise.
(cp_parser_using_declaration): Likewise.
(cp_parser_member_declaration): Likewise.
(cp_parser_exception_specification_opt): Likewise.
(cp_parser_std_attribute_spec): Likewise.
* pt.c (do_decl_instantiation): Likewise.
(do_type_instantiation): Likewise.
* typeck.c (cp_build_unary_op): Likewise.

* decl.c (check_tag_decl): Pass to in_system_header_at the same
location used for the permerror.
(grokdeclarator): Likewise.

* decl.c (check_tag_decl): Use locations[ds_typedef] in error_at.

/testsuite
2019-10-17  Paolo Carlini  <paolo.carlini@oracle.com>

* g++.old-deja/g++.other/decl9.C: Check locations too.

From-SVN: r277133

[Darwin, PPC] Fix PR 65342.

The current Darwin load/store lo_sum patterns have neither predicate nor
constraint.  This means that most parts of the backend, which rely on
recog() to validate the rtx, can produce invalid combinations/selections.

For 32bit cases this isn't a problem since we can load/store to unaligned
addresses using D-mode insns.

Conversely, for 64bit instructions that use DS mode, this can manifest as
assemble errors (for an assembler that checks the LO14 relocations), or as
crashes caused by wrong offsets (or worse, wrong content for the two LSBs).

What we want to check for "Y" on Darwin is:
  - that the alignment of the Symbols' target is sufficient for DS mode
  - that the offset is suitable for DS mode.
(while looking through the Mach-O PIC unspecs).

So, the patch removes the Darwin-specific lo_sum patterns (we begin using
the movdi_internal64 patterns).  We also we need to extend the handling of the
mem_operand_gpr constraint to allow looking through Mach-O PIC UNSPECs in
the lo_sum cases.

gcc/ChangeLog:

2019-10-17  Iain Sandoe  <iain@sandoe.co.uk>

PR target/65342
* config/rs6000/darwin.md (movdi_low, movsi_low_st): Delete.
(movdi_low_st): Delete.
* config/rs6000/rs6000.c
(darwin_rs6000_legitimate_lo_sum_const_p): New.
(mem_operand_gpr): Validate Mach-O LO_SUM cases separately.
* config/rs6000/rs6000.md (movsi_low): Delete.

From-SVN: r277130

gitattributes: Avoid {} in filename pattern.

* .gitattributes: Avoid {} in filename pattern.

Brace-expansion is a bash feature, not part of glob(7).

From-SVN: r277129

cp-gimplify.c (cp_gimplify_expr): Use get_initialized_tmp_var.

* cp-gimplify.c (cp_gimplify_expr): Use get_initialized_tmp_var.

The comment for get_formal_tmp_var says that it shouldn't be used for
expressions whose value might change between initialization and use, and in
this case we're creating a temporary precisely because the value might
change, so we should use get_initialized_tmp_var instead.

I also noticed that many callers of get_initialized_tmp_var pass NULL for
post_p, so it seems appropriate to make it a default argument.

gcc/
* gimplify.h (get_initialized_tmp_var): Add default argument to
post_p.
* gimplify.c (gimplify_self_mod_expr, gimplify_omp_atomic): Remove
NULL post_p argument.
* targhooks (std_gimplify_va_arg_expr): Likewise.

From-SVN: r277128

tree-vectorizer.h (_stmt_vec_info::cond_reduc_code): Remove.

2019-10-17  Richard Biener  <rguenther@suse.de>

* tree-vectorizer.h (_stmt_vec_info::cond_reduc_code): Remove.
(STMT_VINFO_VEC_COND_REDUC_CODE): Likewise.
* tree-vectorizer.c (vec_info::new_stmt_vec_info): Do not
initialize STMT_VINFO_VEC_COND_REDUC_CODE.
* tree-vect-loop.c (vect_is_simple_reduction): Set
STMT_VINFO_REDUC_CODE.
(vectorizable_reduction): Remove dead and redundant code, use
STMT_VINFO_REDUC_CODE instead of STMT_VINFO_VEC_COND_REDUC_CODE.

From-SVN: r277126

Process new C++17 and C++20 headers with Doxygen

This won't do anything by default, because __cplusplus is set to 201402L
when Doxygen runs. If/when that changes, these headers should be
processed.

* doc/doxygen/user.cfg.in (INPUT): Add new C++17 and C++20 headers.

From-SVN: r277121

Define [range.cmp] comparisons for C++20

Define std::identity, std::ranges::equal_to, std::ranges::not_equal_to,
std::ranges::greater, std::ranges::less, std::ranges::greater_equal and
std::ranges::less_equal.

* include/Makefile.am: Add new header.
* include/Makefile.in: Regenerate.
* include/bits/range_cmp.h: New header for C++20 function objects.
* include/std/functional: Include new header.
* testsuite/20_util/function_objects/identity/1.cc: New test.
* testsuite/20_util/function_objects/range.cmp/equal_to.cc: New test.
* testsuite/20_util/function_objects/range.cmp/greater.cc: New test.
* testsuite/20_util/function_objects/range.cmp/greater_equal.cc: New
test.
* testsuite/20_util/function_objects/range.cmp/less.cc: New test.
* testsuite/20_util/function_objects/range.cmp/less_equal.cc: New test.
* testsuite/20_util/function_objects/range.cmp/not_equal_to.cc: New
test.

From-SVN: r277120

Fix breakage introduced by r276985.

* config/avr/avr.c (avr_option_override): Remove set of
PARAM_ALLOW_STORE_DATA_RACES.
* common/config/avr/avr-common.c (avr_option_optimization_table)
[OPT_LEVELS_ALL]: Turn on -fallow-store-data-races.

From-SVN: r277115

i386: Add clear_ratio to processor_costs

i386.h has

 #define CLEAR_RATIO(speed) ((speed) ? MIN (6, ix86_cost->move_ratio) : 2)

It is impossible to have CLEAR_RATIO > 6.  This patch adds clear_ratio
to processor_costs, sets it to the minimum of 6 and move_ratio in all
cost models and defines CLEAR_RATIO with clear_ratio.

* config/i386/i386.h (processor_costs): Add clear_ratio.
(CLEAR_RATIO): Remove MIN and use ix86_cost->clear_ratio.
* config/i386/x86-tune-costs.h: Set clear_ratio to the minimum
of 6 and move_ratio in all cost models.

From-SVN: r277114

PR libstdc++/92124 fix incorrect container move assignment

The container requirements say that for move assignment "All existing
elements of [the target] are either move assigned or destroyed". Some of
our containers currently use __make_move_if_noexcept which makes the
move depend on whether the element type is nothrow move constructible.
This is incorrect, because the standard says we must move assign, not
move or copy depending on the move constructor.

Use make_move_iterator instead so that we move unconditionally. This
ensures existing elements won't be copy assigned.

PR libstdc++/92124
* include/bits/forward_list.h
(_M_move_assign(forward_list&&, false_type)): Do not use
__make_move_if_noexcept, instead move unconditionally.
* include/bits/stl_deque.h (_M_move_assign2(deque&&, false_type)):
Likewise.
* include/bits/stl_list.h (_M_move_assign(list&&, false_type)):
Likewise.
* include/bits/stl_vector.h (_M_move_assign(vector&&, false_type)):
Likewise.
* testsuite/23_containers/vector/92124.cc: New test.

From-SVN: r277113

tree-vect-loop.c (check_reduction_path): Compute reduction operation here.

2019-10-17  Richard Biener  <rguenther@suse.de>

* tree-vect-loop.c (check_reduction_path): Compute reduction
operation here.
(vect_is_simple_reduction): Remove special-case of single-stmt
reduction path detection.

From-SVN: r277112

[arm] Add default FPU for Marvell-pj4

According to GAS, the Marvell PJ4 CPU has a VFPv3-D16 floating point
unit, but GCC's CPU configuration tables omits this meaning that
-mfpu=auto will not correctly select the FPU.  This patch fixes this
by adding the +fp option to the architecture specification for this
device.

* config/arm/arm-cpus.in (marvel-pj4): Add +fp to the architecture.

From-SVN: r277111

[AArch64][SVE2] Support for EOR3 and variants of BSL

2019-10-17  Yuliang Wang  <yuliang.wang@arm.com>

gcc/
* config/aarch64/aarch64-sve2.md (aarch64_sve2_eor3<mode>)
(aarch64_sve2_nor<mode>, aarch64_sve2_nand<mode>)
(aarch64_sve2_bsl<mode>, aarch64_sve2_nbsl<mode>)
(aarch64_sve2_bsl1n<mode>, aarch64_sve2_bsl2n<mode>):
New combine patterns.
* config/aarch64/iterators.md (BSL_DUP): New int iterator for the
above.
(bsl_1st, bsl_2nd, bsl_dup, bsl_mov): Attributes for the above.

gcc/testsuite/
* gcc.target/aarch64/sve2/eor3_1.c: New test.
* gcc.target/aarch64/sve2/nlogic_1.c: As above.
* gcc.target/aarch64/sve2/nlogic_2.c: As above.
* gcc.target/aarch64/sve2/bitsel_1.c: As above.
* gcc.target/aarch64/sve2/bitsel_2.c: As above.
* gcc.target/aarch64/sve2/bitsel_3.c: As above.
* gcc.target/aarch64/sve2/bitsel_4.c: As above.

From-SVN: r277110

Remove incorrect PR from ChangeLog.

From-SVN: r277108

re PR tree-optimization/92131 (incorrect assumption that (ao >= 0) is always false)

PR tree-optimization/92131
* tree-vrp.c (value_range_base::dump): Display +INF for both
pointers and integers when appropriate.

From-SVN: r277107

[vect] Be consistent in versioning threshold use

gcc/ChangeLog:
2019-10-17  Andre Vieira  <andre.simoesdiasvieira@arm.com>

* tree-vect-loop.c (vect_analyze_loop_2): Use same condition to decide
when to use versioning threshold.

From-SVN: r277105

[vect] Outline code into new function: determine_peel_for_niter

gcc/ChangeLog:
2019-10-17  Andre Vieira  <andre.simoesdiasvieira@arm.com>

* tree-vect-loop.c (determine_peel_for_niter): New function contained
outlined code from ...
(vect_analyze_loop_2): ... here.

From-SVN: r277103

[C++ PATCH] builtin fn creation

https://gcc.gnu.org/ml/gcc-patches/2019-10/msg01283.html
* decl.c (builtin_function_1): Merge into ...
(cxx_builtin_function): ... here.  Nadger the decl before maybe
copying it.  Set the context.
(cxx_builtin_function_ext_scope): Push to top level, then call
cxx_builtin_function.

From-SVN: r277102

[vect] Refactor versioning threshold

gcc/ChangeLog:
2019-10-17  Andre Vieira  <andre.simoesdiasvieira@arm.com>

* tree-vect-loop.c (vect_transform_loop): Move code from here...
* tree-vect-loop-manip.c (vect_loop_versioning): ... to here.
* tree-vectorizer.h (vect_loop_versioning): Remove unused parameters.

From-SVN: r277101

tree-vect-loop.c (needs_fold_left_reduction_p): Export.

2019-10-17  Richard Biener  <rguenther@suse.de>

* tree-vect-loop.c (needs_fold_left_reduction_p): Export.
(vect_is_simple_reduction): Move all validity checks ...
(vectorizable_reduction): ... here.  Compute whether we
need a fold-left reduction here.
* tree-vect-patterns.c (vect_reassociating_reduction_p): Merge
both overloads, check needs_fold_left_reduction_p directly.
* tree-vectorizer.h (needs_fold_left_reduction_p): Declare.

From-SVN: r277100

[ARM,testsuite] Fix typo in arm_arch_v8a_ok effective target.

The arm_arch_v8a_ok effective-target lacks a closing bracket in these
tests, resulting in it being ignored.

2019-10-17  Christophe Lyon  <christophe.lyon@linaro.org>

gcc/testsuite/
* gcc.target/arm/vseleqdf.c: Add missing closing bracket.
* gcc.target/arm/vseleqsf.c: Likewise.
* gcc.target/arm/vselgedf.c: Likewise.
* gcc.target/arm/vselgesf.c: Likewise.
* gcc.target/arm/vselgtdf.c: Likewise.
* gcc.target/arm/vselgtsf.c: Likewise.
* gcc.target/arm/vselledf.c: Likewise.
* gcc.target/arm/vsellesf.c: Likewise.
* gcc.target/arm/vselltdf.c: Likewise.
* gcc.target/arm/vselltsf.c: Likewise.
* gcc.target/arm/vselnedf.c: Likewise.
* gcc.target/arm/vselnesf.c: Likewise.
* gcc.target/arm/vselvcdf.c: Likewise.
* gcc.target/arm/vselvcsf.c: Likewise.
* gcc.target/arm/vselvsdf.c: Likewise.
* gcc.target/arm/vselvssf.c: Likewise.

From-SVN: r277099

tree-ssa-pre.c (create_component_ref_by_pieces_1): Fix TARGET_MEM_REF creation.

2019-10-17  Richard Biener  <rguenther@suse.de>

* tree-ssa-pre.c (create_component_ref_by_pieces_1): Fix
TARGET_MEM_REF creation.

From-SVN: r277098

Additional test cases for using automatic variables in equivalence statements.

From-SVN: r277097

progmem-error-1.cpp: Fix location of the expected diagnostic.

gcc/testsuite/
* gcc.target/avr/progmem-error-1.cpp: Fix location of the
expected diagnostic.

From-SVN: r277096

re PR testsuite/92125 (New test gcc.dg/ipa/pr91088.c introduced in r277054 fails)

PR testsuite/92125

2019-10-17  Feng Xue  <fxue@os.amperecomputing.com>

        PR testsuite/92125
        * gcc.dg/ipa/pr91088.c: Change char conversion to bitand.

From-SVN: r277095

re PR tree-optimization/92129 (ICE in vectorizable_reduction, at tree-vect-loop.c:5869)

2019-10-17  Richard Biener  <rguenther@suse.de>

PR tree-optimization/92129
* tree-vect-loop.c (vectorizable_reduction): Also fail
on GIMPLE_SINGLE_RHS.

From-SVN: r277094

re PR tree-optimization/92056 (ice in expr_object_size, at tree-object-si ze.c:675 with -O3)

PR tree-optimization/92056
* tree-object-size.c (cond_expr_object_size): Return early if then_
processing resulted in unknown size.

* gcc.c-torture/compile/pr92056.c: New test.

From-SVN: r277093

re PR tree-optimization/92115 (ICE in gimple_cond_get_ops_from_tree, at gimple-expr.c:577)

PR tree-optimization/92115
* tree-ssa-ifcombine.c (ifcombine_ifandif): Force condition into
temporary if it could trap.

* gcc.dg/pr92115.c: New test.

From-SVN: r277092

re PR fortran/87752 (ICE in omp_add_variable, at gimplify.c:6776)

PR fortran/87752
* gfortran.dg/gomp/pr87752.f90: New test.

From-SVN: r277091

re PR debug/91887 (-fdebug-types-section ICE building chromium)

2019-10-17  Richard Biener  <rguenther@suse.de>

PR debug/91887
* dwarf2out.c (gen_formal_parameter_die): Also try to match
context_die against a DW_TAG_GNU_formal_parameter_pack parent.

* g++.dg/debug/dwarf2/pr91887.C: New testcase.

From-SVN: r277090

Fix old file reference in gcc/cp/cp-gimplify.c

I've found this stale reference while looking at cp-gimplify.c. tree-gimple.c
no longer exists and its contents were merged into gimple.c.

Seems obvious enough.

gcc/cp/ChangeLog:

2019-10-16  Luis Machado  <luis.machado@linaro.org>

* cp-gimplify.c: Fix reference to non-existing tree-gimple.c file.

From-SVN: r277089

Daily bump.

From-SVN: r277088

decl.c (cxx_maybe_build_cleanup): When clearing location of cleanup...

* decl.c (cxx_maybe_build_cleanup): When clearing location of cleanup,
if cleanup is a nop, clear location of its operand too.

From-SVN: r277084

tree-ssa-strlen.c (maybe_invalidate): Use HOST_WIDE_INT_PRINT_UNSIGNED instead of "%zu".

* tree-ssa-strlen.c (maybe_invalidate): Use
HOST_WIDE_INT_PRINT_UNSIGNED instead of "%zu".

From-SVN: r277083

RISC-V: Include more registers in SIBCALL_REGS.

This finishes the part 1 of 2 patch submitted by Andrew Burgess on Aug 19.
This adds the argument registers but not t0 (aka x5) to SIBCALL_REGS.  It
also adds the missing riscv_regno_to_class change.

Tested with cross riscv32-elf and riscv64-linux toolchain build and check.
There were no regressions.  I see about a 0.01% code size reduction for the
C and libstdc++ libraries.

gcc/
* config/riscv/riscv.h (REG_CLASS_CONTENTS): Add argument passing
regs to SIBCALL_REGS.
* config/riscv/riscv.c (riscv_regno_to_class): Change argument
passing regs to SIBCALL_REGS.

Co-Authored-By: Jim Wilson <jimw@sifive.com>
From-SVN: r277082

PR tree-optimization/83821 - local aggregate initialization defeats strlen optimization

gcc/ChangeLog:

PR tree-optimization/83821
* tree-ssa-strlen.c (maybe_invalidate): Add argument.  Consider
the length of a string when available.
(handle_builtin_memset) Add argument.
(handle_store, strlen_check_and_optimize_call): Same.
(check_and_optimize_stmt): Same.  Pass it to callees.

gcc/testsuite/ChangeLog:

PR tree-optimization/83821
* c-c++-common/Warray-bounds-4.c: Remove XFAIL.
* gcc.dg/strlenopt-82.c: New test.
* gcc.dg/strlenopt-83.c: Same.
* gcc.dg/strlenopt-84.c: Same.
* gcc.dg/strlenopt-85.c: Same.
* gcc.dg/strlenopt-86.c: Same.
* gcc.dg/tree-ssa/calloc-4.c: Same.
* gcc.dg/tree-ssa/calloc-5.c: Same.

From-SVN: r277080

PR tree-optimization/91996 - fold non-constant strlen relational expressions

gcc/testsuite/ChangeLog:

PR tree-optimization/91996
* gcc.dg/strlenopt-80.c: New test.
* gcc.dg/strlenopt-81.c: New test.

gcc/ChangeLog:

PR tree-optimization/91996
* tree-ssa-strlen.c (maybe_warn_pointless_strcmp): Improve location
information.
(compare_nonzero_chars): Add an overload.
(count_nonzero_bytes): Add an argument.  Call overload above.
Handle non-constant lengths in some range.
(handle_store): Add an argument.
(check_and_optimize_stmt): Pass an argument to handle_store.

From-SVN: r277076

[arm] fix bootstrap failure due to uninitialized warning

The Arm port is failing bootstrap because GCC is now warning about an
unitialized array.

The code is complex enough that I certainly can't be sure the compiler
is wrong, so perhaps the best fix here is just to memset the entire
array before use.

* config/arm/arm.c (neon_valid_immediate): Clear bytes before use.

From-SVN: r277073

mips.c (mips_expand_builtin_insn): Force the operands which correspond to the same input-output register to have...

* config/mips/mips.c (mips_expand_builtin_insn): Force the
operands which correspond to the same input-output register to
have the same pseudo assigned to them.

* gcc.target/mips/msa-dpadd-dpsub.c: New test.

From-SVN: r277071

find_partition_fixes: remove unused bbs_in_cold_partition variable

gcc/ChangeLog:

2019-10-16  Ilya Leoshkevich  <iii@linux.ibm.com>

* cfgrtl.c (find_partition_fixes): Remove bbs_in_cold_partition.

From-SVN: r277070

[AArch64] Fix symbol offset limit

In aarch64_classify_symbol symbols are allowed large offsets on relocations.
This means the offset can use all of the +/-4GB offset, leaving no offset
available for the symbol itself.  This results in relocation overflow and
link-time errors for simple expressions like &global_array + 0xffffff00.

To avoid this, unless the offset_within_block_p is true, limit the offset
to +/-1MB so that the symbol needs to be within a 3.9GB offset from its
references.  For the tiny code model use a 64KB offset, allowing most of
the 1MB range for code/data between the symbol and its references.

    gcc/
* config/aarch64/aarch64.c (aarch64_classify_symbol):
Apply reasonable limit to symbol offsets.

    testsuite/
* gcc.target/aarch64/symbol-range.c: Improve testcase.
* gcc.target/aarch64/symbol-range-tiny.c: Likewise.

From-SVN: r277068

tree-vect-loop.c (vect_valid_reduction_input_p): Remove.

2019-10-16  Richard Biener  <rguenther@suse.de>

* tree-vect-loop.c (vect_valid_reduction_input_p): Remove.
(vect_is_simple_reduction): Delay checking to
vectorizable_reduction and relax the checking.
(vectorizable_reduction): Check we have a simple use.  Check
for bogus condition reductions.
* tree-vect-stmts.c (vect_transform_stmt): Make sure we
are looking at the last stmt in a pattern sequence when
filling in backedge PHI values.

* gcc.dg/vect/vect-cond-reduc-3.c: New testcase.
* gcc.dg/vect/vect-cond-reduc-4.c: Likewise.

From-SVN: r277067

In PR70010, a function is marked with target(no-vsx) to disable VSX code generation.

In PR70010, a function is marked with target(no-vsx) to disable VSX code
generation.  To avoid VSX code generation, this function should not be
inlined into VSX function.  To fix the bug, in the current logic when
checking whether the caller's ISA flags supports the callee's ISA flags, we
just need to add a test that enforces that the caller's ISA flags match
exactly the callee's flags, for those flags that were explicitly set in the
callee.  If caller without target attribute then using options from command
line.

gcc/
2019-10-16  Peter Bergner <bergner@linux.ibm.com>
    Jiufu Guo  <guojiufu@linux.ibm.com>

PR target/70010
* config/rs6000/rs6000.c (rs6000_can_inline_p): Prohibit inlining if
the callee explicitly disables some isa_flags the caller is using.

gcc.testsuite/
2019-10-16  Peter Bergner <bergner@linux.ibm.com>
    Jiufu Guo  <guojiufu@linux.ibm.com>

PR target/70010
* gcc.target/powerpc/pr70010.c: New test.
* gcc.target/powerpc/pr70010-1.c: New test.
* gcc.target/powerpc/pr70010-2.c: New test.
* gcc.target/powerpc/pr70010-3.c: New test.
* gcc.target/powerpc/pr70010-4.c: New test.

Co-Authored-By: Jiufu Guo <guojiufu@linux.ibm.com>
From-SVN: r277065

Assert for POINTER_TYPE_P in expr_callee_abi

2019-10-16  Richard Sandiford  <richard.sandiford@arm.com>

gcc/
* function-abi.cc (expr_callee_abi): Assert for POINTER_TYPE_P.

From-SVN: r277063

[AArch64] Add partial SVE vector modes

This patch adds extra vector modes that represent a half, quarter or
eighth of what an SVE vector can hold.  This is useful for describing
the memory vector involved in an extending load or truncating store.
It might also be useful in future for representing "unpacked" SVE
registers, i.e. registers that contain values in the low bits of a
wider containing element.

The new modes could have the same width as an Advanced SIMD mode for
certain -msve-vector-bits=N options, so we need to ensure that they
come later in the mode list and that Advanced SIMD modes always "win".

2019-10-16  Richard Sandiford  <richard.sandiford@arm.com>

gcc/
* genmodes.c (mode_data::order): New field.
(blank_mode): Update accordingly.
(VECTOR_MODES_WITH_PREFIX): Add an order parameter.
(make_vector_modes): Likewise.
(VECTOR_MODES): Update use accordingly.
(cmp_modes): Sort by the new order field ahead of sorting by size.
* config/aarch64/aarch64-modes.def (VNx2QI, VN2xHI, VNx2SI)
(VNx4QI, VNx4HI, VNx8QI): New partial vector modes.
* config/aarch64/aarch64.c (VEC_PARTIAL): New flag value.
(aarch64_classify_vector_mode): Handle the new partial modes.
(aarch64_vl_bytes): New function.
(aarch64_hard_regno_nregs): Use it instead of BYTES_PER_SVE_VECTOR
when counting the number of registers in an SVE mode.
(aarch64_class_max_nregs): Likewise.
(aarch64_hard_regno_mode_ok): Don't allow partial vectors
in registers yet.
(aarch64_classify_address): Treat partial vectors analogously
to full vectors.
(aarch64_print_address_internal): Consolidate the printing of
MUL VL addresses, using aarch64_vl_bytes as the number of
bytes represented by "VL".
(aarch64_vector_mode_supported_p): Reject partial vector modes.

From-SVN: r277062

[AArch64] Improve poly_int handling in aarch64_layout_frame

I'd used known_lt when converting these conditions to poly_int,
but on reflection that was a bad choice.  The code isn't just
doing a range check; it specifically needs constants that will
fit in a certain encoding.

2019-10-16  Richard Sandiford  <richard.sandiford@arm.com>

gcc/
* config/aarch64/aarch64.c (aarch64_layout_frame): Use is_constant
rather than known_lt when choosing frame layouts.

From-SVN: r277061

[AArch64] Add an assert to aarch64_layout_frame

This patch adds an assert that all the individual *_adjust allocations
add up to the full frame size.  With that safety net, it seemed slightly
clearer to use crtl->outgoing_args_size as the final adjustment where
appropriate, to match what's used in the comments.

This is a bit overkill on its own, but I need to add more cases for SVE.

2019-10-16  Richard Sandiford  <richard.sandiford@arm.com>

gcc/
* config/aarch64/aarch64.c (aarch64_layout_frame): Assert
that all the adjustments add up to the full frame size.
Use crtl->outgoing_args_size directly as the final adjustment
where appropriate.

From-SVN: r277060

[AArch64] Use frame reference in aarch64_layout_frame

Using the full path "cfun->machine->frame" in aarch64_layout_frame
led to awkward formatting in some follow-on patches, so it seemed
worth using a local reference instead.

2019-10-16  Richard Sandiford  <richard.sandiford@arm.com>

gcc/
* config/aarch64/aarch64.c (aarch64_layout_frame): Use a local
"frame" reference instead of always referring directly to
"cfun->machine->frame".

From-SVN: r277059

Only use GCC-specific __is_same_as built-in conditionally

Clang doesn't support __is_same_as but provides __is_same instead.
Restore the original implementation (pre r276891) when neither of those
built-ins is available.

* include/bits/c++config (_GLIBCXX_BUILTIN_IS_SAME_AS): Define to
one of __is_same_as or __is_same when available.
* include/std/concepts (__detail::__same_as): Use std::is_same_v.
* include/std/type_traits (is_same) [_GLIBCXX_BUILTIN_IS_SAME_AS]:
Use new macro instead of __is_same_as.
(is_same) [!_GLIBCXX_BUILTIN_IS_SAME_AS]: Restore partial
specialization.
(is_same_v) [_GLIBCXX_BUILTIN_IS_SAME_AS]: Use new macro.
(is_same_v) [!_GLIBCXX_BUILTIN_IS_SAME_AS]: Use std::is_same.

From-SVN: r277058

re PR tree-optimization/92119 (ICE: SIGSEGV in contains_struct_check (tree.h:3380) with -Os -fno-tree-dce -fno-tree-dse -ftree-slp-vectorize)

2019-10-16  Richard Biener  <rguenther@suse.de>

PR tree-optimization/92119
* tree-vect-patterns.c (vect_recog_rotate_pattern): Guard
against missing bswap lhs.

From-SVN: r277057

Deal with incoming POLY_INT_CST ranges (PR92033)

This patch makes value_range_base::set convert POLY_INT_CST bounds
into the worst-case INTEGER_CST bounds.  The main case in which this
gives useful ranges is a lower bound of A + B * X becoming A when B >= 0.
E.g.:

  [32 + 16X, 100] -> [32, 100]
  [32 + 16X, 32 + 16X] -> [32, MAX]

But the same thing can be useful for the upper bound with negative
X coefficients.

2019-10-16  Richard Sandiford  <richard.sandiford@arm.com>

gcc/
PR middle-end/92033
* poly-int.h (constant_lower_bound_with_limit): New function.
(constant_upper_bound_with_limit): Likewise.
* doc/poly-int.texi: Document them.
* tree-vrp.c (value_range_base::set): Convert POLY_INT_CST bounds
into the worst-case INTEGER_CST bounds.

From-SVN: r277056

Generalized IPA predicate on parameter reference

2019-10-16  Feng Xue  <fxue@os.amperecomputing.com>

        PR ipa/91088
        * doc/invoke.texi (ipa-max-param-expr-ops): Document new option.
        * params.def (PARAM_IPA_MAX_PARAM_EXPR_OPS): New.
        * ipa-predicat.h (struct expr_eval_op): New struct.
        (expr_eval_ops): New typedef.
        (struct condition): Add type and param_ops fields, remove size field.
        (add_condition): Replace size parameter with type parameter, add
        param_ops parameter.
        * ipa-predicat.c (expr_eval_ops_equal_p): New function.
        (predicate::add_clause): Add comparisons on type and param_ops.
        (dump_condition): Add debug dump for param_ops.
        (remap_after_inlining): Adjust call arguments to add_condition.
        (add_condition): Replace size parameter with type parameter, add
        param_ops parameter. Unshare constant value used in conditions.
        * ipa-fnsummary.c (evaluate_conditions_for_known_args): Fold
        parameter expressions using param_ops.
        (decompose_param_expr):  New function.
        (set_cond_stmt_execution_predicate): Use call to decompose_param_expr
        to replace call to unmodified_parm_or_parm_agg_item.
        (set_switch_stmt_execution_predicate): Likewise.
        (will_be_nonconstant_expr_predicate): Likewise. Replace usage of size
        with type.
        (inline_read_section): Read param_ops from summary stream.
        (ipa_fn_summary_write): Write param_ops to summary stream.

2019-10-16  Feng Xue  <fxue@os.amperecomputing.com>

        PR ipa/91088
        * gcc.dg/ipa/pr91088.c: New test.
        * gcc.dg/ipa/pr91089.c: Add sub-test for range analysis.
        * g++.dg/tree-ssa/ivopts-3.C: Force a function to be noinline.

From-SVN: r277054

[_GLIBCXX_DEBUG] Clarify constness and state <unknown> entries.

* src/c++11/debug.cc (print_field): Replace constness_names <unknown>
entry with <unknown constness>. Replace state_names <unknown> entry with
<unknown state>.

From-SVN: r277049

Daily bump.

From-SVN: r277033

genattrtab: Parenthesize expressions correctly (PR92107)

As PR92107 shows, genattrtab doesn't parenthesize expressions correctly
(or at all, even).  This fixes it.

PR rtl-optimization/92107
* genattrtab.c (write_attr_value) <do_operator>: Parenthesize the
expression written.

From-SVN: r277023

fptr.c (_dl_read_access_allowed): Change argument to unsigned int.

* config/pa/fptr.c (_dl_read_access_allowed): Change argument to
unsigned int.  Adjust callers.
(__canonicalize_funcptr_for_compare): Change plabel type to volatile
unsigned int *.  Load relocation offset before function pointer.
Add barrier to ensure ordering.

From-SVN: r277015

20191015-1.c: New test.

2019-10-15  Andrew Pinski  <apinski@marvell.com>

        * gcc.c-torture/compile/20191015-1.c: New test.
        * gcc.c-torture/compile/20191015-2.c: New test.

From-SVN: r277011

[Darwin] Clarify fix and continue support (NFC).

This updates the description of the support for fix and continue
debugging.

gcc/ChangeLog:

2019-10-15  Iain Sandoe  <iain@sandoe.co.uk>

* config/darwin.c: Update description of fix and continue.

From-SVN: r277010

[Darwin] Update darwin_binds_local_p.

The use of default_binds_local_p had got out of sync with the varasm
changes, this restores the call to be direct.  In practice, we add some
further tests to determine local binding - but this callback is used for
the initial assessments made by default_encode_section_info().

gcc/ChangeLog:

2019-10-15  Iain Sandoe  <iain@sandoe.co.uk>

* config/darwin.c (darwin_binds_local_p): Update to call
default_binds_local_p_3 () directly. amend comments.

From-SVN: r277009

PR testsuite/92016 - Excess errors in Wstringop-overflow-17.c

gcc/testsuite/ChangeLog:
* gcc.dg/Wstringop-overflow-17.c: Expect an additional warning.

From-SVN: r277008

lto-streamer-out.c (lto_variably_modified_type_p): New.

2019-10-15  Richard Biener  <rguenther@suse.de>

* lto-streamer-out.c (lto_variably_modified_type_p): New.
(tree_is_indexable): Use it.
* tree-streamer-out.c (pack_ts_type_common_value_fields):
Stream variably_modified_type_p as TYPE_LANG_FLAG_0.
* tree-streamer-in.c (unpack_ts_type_common_value_fields): Likewise.

From-SVN: r277005

[Fortran] OpenMP+OpenACC: Remove bogus contigous-pointer check

        gcc/fortran
        PR fortran/65438
        * openmp.c (check_array_not_assumed): Remove pointer check.

Co-Authored-By: Tobias Burnus <tobias@codesourcery.com>
From-SVN: r277000

re PR testsuite/92093 (New test case gcc.target/powerpc/pr91275.c from r276410 fails on BE)

2019-10-15  Bill Schmidt  <wschmidt@linux.ibm.com>

PR target/92093
* gcc.target/powerpc/pr91275.c: Fix type and endian issues.

From-SVN: r276999

[C++ PATCH] clone_function_decl breakup

https://gcc.gnu.org/ml/gcc-patches/2019-10/msg01083.html
This patch, from the modules branch, breaks out function cloning from the
method vector updating. We have a new function, build_clones,
which does the building, returning a count of the number of clones
(2 or 3). clone_function_decl separately adds them to the method
vector, if they should be added. I suppose this could have used
FOR_EVERY_CLONE, but I went with the counting scheme.

* class.c (build_clones): Break out of clone_function_decl.  Just
build the clones.
(clone_function_decl): Call build_clones, then maybe add them to
the method vector.

From-SVN: r276998

msp430.md (zero_extendqipsi2): New.

2019-10-15  Jozef Lawrynowicz  <jozef.l@mittosystems.com>

* config/msp430/msp430.md (zero_extendqipsi2): New.
(zero_extendqisi2): Optimize case where src register and base dst
register are the same.
(zero_extendhipsi2): Don't use 430X insn for rYs->r case.
(zero_extendpsisi2): Optimize r->m case.
Add unnamed insn patterns to catch insns combine searches for when
optimizing pointer manipulation.

From-SVN: r276997

msp430.md: Group zero_extend* insns together.

2019-10-15  Jozef Lawrynowicz  <jozef.l@mittosystems.com>

* config/msp430/msp430.md: Group zero_extend* insns together.

From-SVN: r276996

constraints.md: Allow post_inc operand for "Ya" constraint.

2019-10-15  Jozef Lawrynowicz  <jozef.l@mittosystems.com>

* config/msp430/constraints.md: Allow post_inc operand for "Ya"
constraint.
* config/msp430/msp430.c (msp430_legitimate_address_p): Handle
POST_INC.
(msp430_subreg): Likewise.
(msp430_split_addsi): Likewise.
(msp430_print_operand_addr): Likewise.
* config/msp430/msp430.h (HAVE_POST_INCREMENT): Define.
(USE_STORE_POST_INCREMENT): Define.
* config/msp430/msp430.md: Use the msp430_general_dst_operand or
msp430_general_dst_nonv_operand predicates for the lvalues of insns.
* config/msp430/predicates.md (msp430_nonpostinc_operand): New.
(msp430_general_dst_operand): New.
(msp430_general_dst_nonv_operand): New.
(msp430_nonsubreg_operand): Remove.
(msp430_nonsubreg_dst_operand): New.
(msp430_nonsubreg_or_imm_operand): Allow reg or mem operands in place
of defunct msp430_nonsubreg_operand.
(msp430_nonsubregnonpostinc_or_imm_operand): New.

From-SVN: r276995

[linemap PATCH] Constify lookup

https://gcc.gnu.org/ml/gcc-patches/2019-10/msg01080.html
looking up a line map takes a non-constant line_maps object, which is confusing.
This makes the caching fields mutable, so permits a constant object, as one might expect for a lookup.

* include/line-map.h (struct maps_info_ordinary): Make cache
mutable.
(struct maps_info_macro): Likewise.
(LINEMAPS_CACHE): Remove non-ref accessor. Constify ref accessor.
(LINEMAPS_ORDINARY_CACHE, LINEMAPS_MACRO_CACHE): Likewise.
(LINEMAPS_ORDINARY_MAP_AT, LINEMAPS_MACRO_MAP_AT): Use
LINEMAPS_USED and LINEMAPS_MAP_AT.
(linemap_lookup): Constify line_map arg.
linemap.c (linemap_ordinary_map_lookup, linemap_macro_map_lookup):
Constify line_map arg.

From-SVN: r276994

re PR debug/91929 (missing inline subroutine information in build using sin/cos)

2019-10-15  Richard Biener  <rguenther@suse.de>

PR tree-optimization/91929
* tree-ssa-pre.c (pre_expr_d::loc): New member.
(get_or_alloc_expr_for_name): Initialize it.
(get_or_alloc_expr_for_constant): Likewise.
(phi_translate_1): Copy it.
(create_expression_by_pieces): Use the original location
of the expression for the inserted stmt.
(compute_avail): Record the location of the stmt for the
expressions created.

From-SVN: r276993

[C++ PATCH] build_clone cleanup

https://gcc.gnu.org/ml/gcc-patches/2019-10/msg01069.html
build_clone is recursive when applied to a template, but I found the control flow confusing. this makes it clearer and moves some decls to their initializers.

* class.c (build_clone): Refactor to clarify recursiveness.

From-SVN: r276992

re PR target/92048 (armeb regression after r276645)

2019-10-15  Richard Biener  <rguenther@suse.de>

PR testsuite/92048
* gcc.dg/vect/fast-math-vect-pr29925.c: Avoid unrolling of
inner loop.

From-SVN: r276991

Fix unchecked use of tree_to_uhwi in tree-ssa-strlen.c

r273783 introduced an unchecked use of tree_to_uhwi.  This is
tested by the SVE ACLE patches, but could potentially trigger
in non-SVE cases too.

2019-10-15  Richard Sandiford  <richard.sandiford@arm.com>

gcc/
* tree-ssa-strlen.c (count_nonzero_bytes): Check tree_fits_uhwi_p
before using tree_to_uhwi.

From-SVN: r276990

[PATCH] S/390: Run %a0:DI splitters only after reload

gcc/ChangeLog:

2019-10-15  Ilya Leoshkevich  <iii@linux.ibm.com>

* config/s390/s390.md: Run %a0:DI splitters only after reload.

gcc/testsuite/ChangeLog:

2019-10-15  Ilya Leoshkevich  <iii@linux.ibm.com>

* gcc.target/s390/load-thread-pointer-once.c: New test.

From-SVN: r276989

Makefile.rtl (a-except.o): Put -O1 earlier so that it can be overriden if needed by other variables.

* Makefile.rtl (a-except.o): Put -O1 earlier so that it can be
overriden if needed by other variables.

From-SVN: r276988

re PR fortran/92094 (ice in vect_transform_stmt at tree-vect-stmts.c:10921)

2019-10-15  Richard Biener  <rguenther@suse.de>

PR tree-optimization/92094
* tree-vect-loop.c (vectorizable_reduction): For nested cycles
do not adjust the reduction definition def type.
* tree-vect-stmts.c (vect_transform_stmt): Verify the scalar stmt
defines the latch argument of the PHI.

* gfortran.dg/pr92094.f90: New testcase.

From-SVN: r276987

Add missing mask[z]_roundscale_[round]_s[d,s] intrinsics

gcc/
* config/i386/avx512fintrin.h (_mm_mask_roundscale_ss,
_mm_maskz_roundscale_ss, _mm_maskz_roundscale_round_ss,
_mm_maskz_roundscale_round_ss, _mm_mask_roundscale_sd,
_mm_maskz_roundscale_sd, _mm_mask_roundscale_round_sd,
_mm_maskz_roundscale_round_sd): New intrinsics.
(_mm_roundscale_ss, _mm_roundscale_round_ss): Use
__builtin_ia32_rndscales?_mask_round builtins instead of
__builtin_ia32_rndscales?_round.
* config/i386/i386-builtin.def (__builtin_ia32_rndscaless_round,
__builtin_ia32_rndscalesd_round): Remove.
(__builtin_ia32_rndscaless_mask_round,
__builtin_ia32_rndscalesd_mask_round): New intrinsics.
* config/i386/sse.md
(avx512f_rndscale<mode><round_saeonly_name>): Renamed to ...
(avx512f_rndscale<mode><mask_scalar_name><round_saeonly_scalar_name>):
 ... this, adjust and add subst atrributes to make it maskable.

gcc/testsuite/
* gcc.target/i386/avx512f-vrndscaless-1.c: Add scan-assembler-times
directives for newly expected instructions.
* gcc.target/i386/avx512f-vrndscalesd-1.c: Likewise.
* gcc.target/i386/avx512f-vrndscaless-2.c
(avx512f_test): Add tests for new intrinsics.
* gcc.target/i386/avx512f-vrndscalesd-2.c: Likewise.
* gcc.target/i386/avx-1.c (__builtin_ia32_rndscalefss_round,
__builtin_ia32_rndscalefsd_round): Remove.
(__builtin_ia32_rndscalefss_mask_round,
__builtin_ia32_rndscalefsd_mask_round): Define.
* gcc.target/i386/sse-13.c: Ditto.
* gcc.target/i386/sse-23.c: Ditto.

From-SVN: r276986

re PR middle-end/92046 (Command line options (that are per-functions) are affecting --params which are global.)

2019-10-15  Richard Biener  <rguenther@suse.de>

PR middle-end/92046
* common.opt (fallow-store-data-races): New.
* params.def (PARAM_ALLOW_STORE_DATA_RACES): Remove.
* params.h (ALLOW_STORE_DATA_RACES): Likewise.
* doc/invoke.texi (fallow-store-data-races): Document.
(--param allow-store-data-races): Remove docs.
* opts.c (default_options_table): Enable -fallow-store-data-races
at -Ofast.
(default_options_optimization): Do not enable --param
allow-store-data-races at -Ofast.
* tree-if-conv.c (ifcvt_memrefs_wont_trap): Use flag_store_data_races
instead of PARAM_ALLOW_STORE_DATA_RACES.
* tree-ssa-loop-im.c (execute_sm): Likewise.

* c-c++-common/cxxbitfields-3.c: Adjust.
* c-c++-common/cxxbitfields-6.c: Likewise.
* c-c++-common/simulate-thread/bitfields-1.c: Likewise.
* c-c++-common/simulate-thread/bitfields-2.c: Likewise.
* c-c++-common/simulate-thread/bitfields-3.c: Likewise.
* c-c++-common/simulate-thread/bitfields-4.c: Likewise.
* g++.dg/simulate-thread/bitfields-2.C: Likewise.
* g++.dg/simulate-thread/bitfields.C: Likewise.
* gcc.dg/lto/pr52097_0.c: Likewise.
* gcc.dg/simulate-thread/speculative-store-2.c: Likewise.
* gcc.dg/simulate-thread/speculative-store-3.c: Likewise.
* gcc.dg/simulate-thread/speculative-store-4.c: Likewise.
* gcc.dg/simulate-thread/speculative-store.c: Likewise.
* gcc.dg/tree-ssa/20050314-1.c: Likewise.

From-SVN: r276985

re PR tree-optimization/92085 (ICE: tree check: expected class 'type', have 'exceptional' (error_mark) in useless_type_conversion_p, at gimple-expr.c:86)

2019-10-15  Prathamesh Kulkarni  <prathamesh.kulkarni@linaro.org>

PR tree-optimization/92085
* tree-if-conv.c (ifcvt_local_dce): Call gsi_next in else clause,
instead of calling it unconditionally after
delete_dead_or_redundant_assignment and fix indentation.

testsuite/
* gcc.dg/tree-ssa/pr92085-1.c: New test.
* gcc.dg/tree-ssa/pr92085-2.c: Likewise.

From-SVN: r276984

re PR fortran/89943 (Submodule functions are not allowed to have C binding)

2019-10-14  Steven G. Kargl  <kargl@gcc.gnu.org>

PR fortran/89943
decl.c (gfc_match_function_decl): Ignore duplicate BIND(C) for function
declaration in submodule.  Implement at check for F2018 C1550.
(gfc_match_entry): Use temporary for locus, which allows removal of
one gfc_error_now().
(gfc_match_subroutine): Ignore duplicate BIND(C) for subroutine
declaration in submodule.  Implement at check for F2018 C1550.

2019-10-14  Steven G. Kargl  <kargl@gcc.gnu.org>

PR fortran/89943
* gfortran.dg/pr89943_1.f90: New test.
* gfortran.dg/pr89943_2.f90: Ditto.
* gfortran.dg/pr89943_3.f90: Ditto.
* gfortran.dg/pr89943_4.f90: Ditto.

From-SVN: r276983

Daily bump.

From-SVN: r276982

Rename attribute-related functions and productions in C parser.

The C2x attribute syntax, [[ ]], appears in different places in the
syntax from GNU __attribute__, and, where they can appear in the same
place in the syntax, they do not always appertain to the same entity.
(For example, in "int func(void) ATTRS;", GNU attributes appertain to
the declaration but C2x attributes appertain to the function type.)

Thus, the C parser needs to handle the two kinds of attributes
separately, with each place in the syntax accepting whatever kinds of
attributes are appropriate there and applying them to the relevant
entities.  This patch prepares for this by renaming parser functions
relating to attributes to make clear they are specifically about GNU
attributes and renaming syntax productions likewise to avoid confusing
with the C2x attributes syntax productions.

Where comments refer to attributes, this has only be changed where it
is clear that in the context they are referring specifically to the
gnu-attributes syntax.  There may be other places that also end up
changing to refer to gnu-attributes as part of the C2x attributes
implementation, if more detailed examination of those places shows
they are also specific to gnu-attributes.  (I do not expect code
dealing with semantics of attributes outside of the parser to need to
change; as for C++, it will be possible to use existing attributes
inside [[]] with the gnu:: form of the attribute name.)

Bootstrapped with no regressions on x86_64-pc-linux-gnu.

* c-parser.c (c_parser_attribute_any_word): Rename to
c_parser_gnu_attribute_any_word.  All callers changed.
(c_parser_attribute): Rename to c_parser_gnu_attribute.  All
callers changed.
(c_parser_attributes): Rename to c_parser_gnu_attributes.  All
callers changed.
(c_parser_declaration_or_fndef, c_parser_declspecs)
(c_parser_enum_specifier, c_parser_struct_or_union_specifier)
(c_parser_struct_declaration, c_parser_declarator)
(c_parser_gnu_attribute, c_parser_compound_statement)
(c_parser_label, c_parser_statement, c_parser_objc_method_decl)
(c_parser_transaction_attributes): Add "gnu-" prefix to names of
attribute-related syntax productions.

From-SVN: r276978