Michal Simek [Thu, 12 Aug 2021 10:30:36 +0000 (12:30 +0200)]
xilinx: common: Change board_info[] handling
Origin code was allocating only pointers to struct xilinx_board_description
and there was separate allocation for structure self and freeing in case of
failure.
The code is directly allocating space for all structures by one calloc to
simlify logic.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Fri, 23 Jul 2021 07:55:59 +0000 (09:55 +0200)]
xilinx: Use variable for passing board_name
Use variable which points to DEVICE_TREE by default. The reason for this
change is to enable DTB_RESELECT and MULTI_DTB_FIT where board detection
can be used for change DTB at run time. That's why there must be reference
in board_fit_config_name_match() via variable instead of hardcoding it
which is sufficient for that use case.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Thu, 12 Aug 2021 09:03:49 +0000 (11:03 +0200)]
xilinx: fru: Replace spaces with \0 in detected name
FRU spec expected \0 for unused symbols but unfortunately a lot of boards
are using spaces instead of \0. That's why after saving it to desc->name
name is checked again and all spaces are converted to \0. This will ensure
that names can be used for string manipulations like concatenation.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Thu, 21 Jan 2021 13:02:30 +0000 (14:02 +0100)]
xilinx: zynqmp: Enable gpio-key/button driver
Enable button uclass and also gpio-key driver by default.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Fri, 4 Dec 2020 09:37:38 +0000 (10:37 +0100)]
arm64: zynqmp: Enable sha1sum command
Enable it for TPM usage.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Ashok Reddy Soma [Tue, 10 Aug 2021 06:16:12 +0000 (00:16 -0600)]
watchdog: versal: Include header file needed for dev_ functions
dev_dbg, dev_err and dev_warn seems to be moved to different header file.
Include dm/device_compat.h file to compile properly.
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Wed, 28 Jul 2021 10:25:49 +0000 (12:25 +0200)]
xilinx: zynqmp: Add debug messages for boot mode
Add debug messages to see HW boot mode and also alternative boot mode in
logs directly.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Wed, 11 Aug 2021 10:01:25 +0000 (12:01 +0200)]
cmd: boot: Update reset usage message
The commit
573a3811edc8 ("sysreset: psci: support system reset in a generic
way with PSCI") has added support for warm reset via PSCI but this hasn't
been reflected in usage message and user has to look at the code how to run
it. That's why update usage text to make this clear.
Here is full help with updated usage:
ZynqMP> help reset
reset - Perform RESET of the CPU
Usage:
reset - cold boot without level specifier
reset -w - warm reset if implemented
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Igor Opaniuk <igor.opaniuk@foundries.io>
Michal Simek [Thu, 1 Jul 2021 09:44:51 +0000 (11:44 +0200)]
cmd: pwm: Remove additional pwm description
The first name is taken from command name that's why shouldn't be listed in
help. And commands shouldn't be listed with <> which means value but value
itself is command name.
Also add description for commands to make it clear what it does.
Before
pwm pwm <invert> <pwm_dev_num> <channel> <polarity>
pwm <config> <pwm_dev_num> <channel> <period_ns> <duty_ns>
...
After:
pwm invert <pwm_dev_num> <channel> <polarity> - invert polarity
pwm config <pwm_dev_num> <channel> <period_ns> <duty_ns> - config PWM
pwm enable <pwm_dev_num> <channel> - enable PWM output
pwm disable <pwm_dev_num> <channel> - disable PWM output
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
T Karthik Reddy [Tue, 10 Aug 2021 12:50:21 +0000 (06:50 -0600)]
xilinx: Enable config to display cpuinfo
Enable CONFIG_DISPLAY_CPUINFO to display SoC family & revision.
Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Reviewed-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
T Karthik Reddy [Tue, 10 Aug 2021 12:50:20 +0000 (06:50 -0600)]
xilinx: common: Add function to print SoC info
Add print_cpuinfo() to print SoC info like family & revision.
This function depends on CONFIG_DISPLAY_CPUINFO config.
Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Reviewed-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
T Karthik Reddy [Tue, 10 Aug 2021 12:50:19 +0000 (06:50 -0600)]
soc: xilinx: versal: Add soc_xilinx_versal driver
soc_xilinx_versal driver allows identification of family & revision
of versal SoC. This driver is selected by CONFIG_SOC_XILINX_VERSAL.
Probe this driver using platdata U_BOOT_DEVICE structure which is
defined at mach-versal/cpu.c.
Add this config to xilinx_versal_virt_defconfig &
xilinx_versal_mini_ospi_defconfig file to select this driver.
Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Reviewed-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
T Karthik Reddy [Tue, 10 Aug 2021 12:50:18 +0000 (06:50 -0600)]
soc: xilinx: zynqmp: Add soc_xilinx_zynqmp driver
soc_xilinx_zynqmp driver allows identification of family & revision
of zynqmp SoC. This driver is selected by CONFIG_SOC_XILINX_ZYNQMP.
Add this config to xilinx_zynqmp_virt_defconfig file.
Probe this driver using platdata U_BOOT_DEVICE structure which is
specified in mach-zynqmp/cpu.c.
Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Reviewed-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Tue, 10 Aug 2021 07:21:54 +0000 (09:21 +0200)]
fdt_support: Add kernel-doc for fdt_fixup_memory_banks()
Add kernel-doc description for fdt_fixup_memory_banks() because it is
implemented in one specific way and this information should be available
for others to decide if their SoC conforms to it.
If you don't want U-Boot to update your memory DT layout please disable
CONFIG_ARCH_FIXUP_FDT_MEMORY.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Michal Simek [Fri, 6 Aug 2021 12:09:32 +0000 (14:09 +0200)]
xilinx: Disable ARCH_FIXUP_FDT_MEMORY
Based on DT spec you can have one memory node which multiple ranges or
multiple nodes.
fdt_fixup_memory_banks() is not implemented in a correct way when multiple
memory nodes are present because all ranges are put it to the first memory
node found. And next memory nodes are kept in DT which ends up in the same
range specification in the same DT.
Here is what it is happening.
Origin DT.
memory@0 {
device_type = "memory";
reg = <0x0 0x0 0x0 0x80000000>;
};
memory@
800000000 {
device_type = "memory";
reg = <0x8 0x00000000 0x0 0x80000000>;
};
After fdt_fixup_memory_banks()
memory@0 {
device_type = "memory";
reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
};
memory@
800000000 {
device_type = "memory";
reg = <0x8 0x00000000 0x0 0x80000000>;
};
As is visible memory@0 node got second range but there is still
memory@
800000000 node present and 2G range is listed twice.
The solution can't be that second node is removed because it can be
referenced already that's why it is better for us to disable this option
for now.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Fri, 6 Aug 2021 11:30:11 +0000 (13:30 +0200)]
ARM: zynq: Enable smcc and nor for zc770-xm012
Enable cfi flash on zc770-xm012 configuration.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Fri, 6 Aug 2021 11:30:19 +0000 (13:30 +0200)]
ARM: zynq: Wire single qspi on couple of boards
Single configuration is working fine and no issue to enable it.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Sai Krishna Potthuri [Fri, 6 Aug 2021 07:41:46 +0000 (01:41 -0600)]
ARM: zynq: Replace 'io-standard' with 'power-source' property
Replace 'io-standard' property with 'power-source' property in all
zynq dts files to be in sync with Zynq Pinctrl driver.
Signed-off-by: Sai Krishna Potthuri <lakshmi.sai.krishna.potthuri@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Raju Kumar Pothuraju [Thu, 1 Jul 2021 08:45:11 +0000 (14:15 +0530)]
xilinx: Add jedec compatible string for QSPI (Zynq/ZynqMP)
Add missing "jedec, spi-nor" compatible string for QSPI flash node.
Spi-nor framework uses this compatibility string to probe &
initialize flash. With missing compatibility string we are observing
below error:
Zynq> sf probe 0 0 0
jedec_spi_nor spi_flash@0:0: unrecognized JEDEC id bytes:
00, 00, 00 Failed to initialize SPI flash at 0:0 (error -2)
Signed-off-by: Raju Kumar Pothuraju <raju.kumar-pothuraju@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Thu, 5 Aug 2021 06:28:46 +0000 (08:28 +0200)]
arm64: zynqmp: Update comment style sm-k26
Trivial style patch.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Fri, 6 Aug 2021 09:12:29 +0000 (11:12 +0200)]
arm64: zynqmp: Fix header alignment on kv260 boards
Fix header alignment.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Fri, 6 Aug 2021 09:12:56 +0000 (11:12 +0200)]
arm64: zynqmp: Fix node name for ds35/36 leds
By dt-binding specs led nodes should have -led suffix that's why add it.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Thu, 29 Jul 2021 12:22:05 +0000 (14:22 +0200)]
xilinx: zynqmp: Initialize usb and scsi via preboot
Based on thread
https://lists.denx.de/pipermail/u-boot/2021-June/451828.html
especially
"Overall we have a deficiency in the UEFI implementation in that we
cannot deal with block devices added or removed after initialization."
there is a need to deal with removable media as usb/scsi/sata.
That's why bridge this gap in EFI implementation by resetting usb and
scsi resets to get all disks before efi_init_obj_list() is called.
In our standard boot flow, where we use distro boot, order is fixed as
"jtag mmc0 mmc1 qspi0 nand0 usb0 usb1 scsi0 pxe dhcp" with prioritizing
boot device added by commit
2882b39d564b ("arm64: zynqmp: Setup the first
boot_target at run time").
When device has ESP partition all devices should be detected because then
efi_disk_register() in efi_init_obj_list() is called only once.
The first such a device is sd/emmc(mmc0/mmc1) and then disks on usb/sata
are not handled at all.
The commit
6bb577dbb30f ("arm64: zynqmp: Disable
EFI_CAPSULE_ON_DISK_EARLY") also pointed out on this issue but detection of
removable media wasn't solved that's why do it now via preboot command.
I have tested cases without usb and scsi and there is no problem with
calling resets without devices itself.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Fri, 6 Aug 2021 07:18:17 +0000 (09:18 +0200)]
arm64: zynqmp: Disable WDT_CDNS driver by default
Do not enable watchdog driver in default zynqmp configuration. The reason
is that not all distributions are handling watchdog properly and then
expires and system resets. If someone needs watchdog in their design please
enable it by hand.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Ashok Reddy Soma [Tue, 3 Aug 2021 05:20:46 +0000 (23:20 -0600)]
mmc: zynq_sdhci: Use set_control_reg from sdhci.c
Since set_control_reg is available in sdhci.c, use it and remove
arasan_sdhci_set_control_reg().
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
T Karthik Reddy [Tue, 3 Aug 2021 05:20:45 +0000 (23:20 -0600)]
mmc: zynq_sdhci: Wait till sd card detect state is stable
As per SD spec when SD host controller is reset, it takes 1000msec
to detect the card state. In case, if we enable the sd bus voltage &
card detect state is not stable, then host controller will disable
the sd bus voltage.
In case of warm/subsystem reboot, due to unstable card detect state
host controller is disabling the sd bus voltage to sd card causing
sd card timeout error. So we wait for a maximum of 1000msec to get
the card detect state stable before we enable the sd bus voltage.
This current fix is workaround for now, this needs to be analysed
further. Zynqmp platform should behave the same as Versal, but we
did not encounter this issue as of now. So we are fixing it for
Versal only.
Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Ashok Reddy Soma [Tue, 3 Aug 2021 05:20:44 +0000 (23:20 -0600)]
mmc: zynq_sdhci: Move setting tapdelay code to driver
Move tapdelay function calls to zynq_sdhci.c and make them static
inline. zynqmp_tap_delay.h has function prototypes for the functions
defined in tap_delays.c, which will not be needed anymore.
Remove tap_delays.c and zynqmp_tap_delay.h files.
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Ashok Reddy Soma [Tue, 3 Aug 2021 05:20:43 +0000 (23:20 -0600)]
mmc: zynq_sdhci: Add xilinx_pm_request() method to set tapdelays
Currently xilinx sdhci driver is using zynqmp_mmio_write() to set
tapdelay values and DLL resets. Continue to use this for SPL and mini
U-Boot where U-Boot will be executed at EL3 level.
Use firmware call xilinx_pm_request() using appropriate arguments to
set input/output tapdelays and also for DLL resets in regular flow(EL2).
Host driver should explicitly request DLL reset before ITAP (assert DLL)
and after OTAP (release DLL) to avoid issues in some cases. Also handle
error return where possible.
Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
T Karthik Reddy [Tue, 3 Aug 2021 05:20:42 +0000 (23:20 -0600)]
zynqmp_firmware: Add zynqmp firmware related enums
Add enums for pm node id's, pm ioctl id's, tapdelay types, dll reset types
Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Ashok Reddy Soma [Tue, 3 Aug 2021 05:20:41 +0000 (23:20 -0600)]
mmc: sdhci: Change prototype of set_delay to return errors
set_delay() has return type as void. If there are any errors while
setting tapdelay's it won't be able to return them.
Change the prototype of set_delay() in sdhci_ops structure and return
the errors from wherever it is called.
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Ashok Reddy Soma [Tue, 3 Aug 2021 05:20:40 +0000 (23:20 -0600)]
mmc: zynq_sdhci: Return errors from arasan_sdhci_set_tapdelay
Change return type of arasan_sdhci_set_tapdelay() to int, to facilitate
returning errors. Get return values from input and output set clock phase
functions inside arasan_sdhci_set_tapdelay() and return those errors.
Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Fri, 30 Jul 2021 06:00:10 +0000 (08:00 +0200)]
reset: zynqmp: Add reset controller for ZynqMP SoC
Add firmware based reset controller for Xilinx ZynqMP SoC to let other
drivers to call reset functions. Driver is only tested on Xilinx ZynqMP but
support for Xilinx Versal can be simply added. That's why reset_id and
nr_reset are assigned in probe folder.
Driver is inpired by driver from Linux kernel.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Thu, 29 Jul 2021 09:42:11 +0000 (11:42 +0200)]
xilinx: zynqmp: Enable CMD_RTC command with Zynqmp RTC driver
Enable RTC command to be able to check available.
And also enable ZynqMP RTC driver to be possible to use by default.
Here is the list when both drivers are enabled:
ZynqMP> rtc list
RTC #0 - rtc_emul
RTC #1 - rtc@
ffa60000
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Thu, 29 Jul 2021 08:39:08 +0000 (10:39 +0200)]
rtc: zynqmp: Add support for ZynqMP RTC
The whole driver logic is taken from Linux kernel but only set/get/reset
functions are implemented. When device is power off RTC is power out of
battery.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Thu, 29 Jul 2021 10:59:12 +0000 (12:59 +0200)]
cmd: date: rtc: Update command to read the first RTC with seq 0
RTCs are using sequence number defined in aliases node. Date command with
DM_RTC enabled is looking for the first RTC with index 0. But when
RTC_EMULATION is enabled it gets likely most of the time index 0 even when
system has rtc0 device via aliases node and gets sequence number 0.
That's why extend the code to look for sequence 0 number first. If this
fails continue to use existing device with index 0.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Thu, 29 Jul 2021 10:57:12 +0000 (12:57 +0200)]
dm: rtc: uclass: Add flag to control sequence numbering
RTCs are using aliases for sequences. That's why enable
DM_UC_FLAG_SEQ_ALIAS for exact RTC indentification.
The same flag is used by a lot of other uclasses like mmc, pci, serial,
spi, timer, tpm, etc.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Fri, 30 Jul 2021 05:59:29 +0000 (07:59 +0200)]
firmware: xilinx: Use explicit values for all enum values
Based on discussion at
https://lore.kernel.org/r/
20200318125003.GA2727094@kroah.com we got
recommendation to use explicit values for all enum values.
The patch is following this recommendation.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/daeb67ded45d8a8f6a96717d1fb9c84439dd2ae8.1612361627.git.michal.simek@xilinx.com
Michal Simek [Tue, 27 Jul 2021 14:19:18 +0000 (16:19 +0200)]
xilinx: zynqmp: Add support for runtime dfu_alt_info setup
The main reason for this to be implemented is capsule update.
Two memories are supported and tested which is MMC FAT based and QSPI
based.
For creating capsule these commands are used:
./tools/mkeficapsule --raw spl/boot.bin --index 1 capsule1.bin
./tools/mkeficapsule --raw u-boot.itb --index 2 capsule2.bin
Then transfer to SD card where these commands run:
load mmc 0
10000000 capsule1.bin
efidebug capsule update -v
10000000
load mmc 0
10000000 capsule2.bin
efidebug capsule update -v
10000000
Depends on the boot device used are binaries loaded to qspi or mmc fat
partition.
Also multiboot register is handled to make sure that the same location(id)
is used as image which is upgraded.
Two locations are used by purpose for SPL flow. If only boot.bin is used
create only one capsule.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Wed, 28 Jul 2021 10:43:53 +0000 (12:43 +0200)]
xilinx: zynqmp: Config non zero SYS_SPI_U_BOOT_OFFS
This variable is pointing to offset is qspi where u-boot image is placed.
In our case it is location of u-boot.itb file. Offset is the same as is
used by Xilinx Zynq SoC.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Tue, 27 Jul 2021 14:17:31 +0000 (16:17 +0200)]
xilinx: zynqmp: use zynqmp_mmio_read() in multi_boot()
When U-Boot runs in EL2 there is no access to csu_base registers that's why
this has to be done via firmware interface to find out multi boot register
value. Till now this function is called only from SPL in EL3.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Tue, 27 Jul 2021 12:05:27 +0000 (14:05 +0200)]
xilinx: zynqmp: Change multi_boot() to return value
Change multi_boot() to return multiboot value and move print out of this
function and let this function to be used by other functions without
duplicating message.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Wed, 28 Jul 2021 10:46:39 +0000 (12:46 +0200)]
xilinx: zynqmp: Free allocated field for target variable
When env_set() is called there is no need to allocate memory for variable
which is already saved that's why free it.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Tom Rini [Thu, 5 Aug 2021 01:18:33 +0000 (21:18 -0400)]
Merge branch '2021-08-04-assorted-minor-fixes'
- Assorted fixes
Adarsh Babu Kalepalli [Mon, 24 May 2021 08:05:39 +0000 (13:35 +0530)]
cmd:(cosmetic)Mentioned in 'chpart' command HELP text that it is for MTD devices
Modified the help text of 'chpart' command ,mentioning that it is
for MTD devices.
Signed-off-by: Adarsh Babu Kalepalli <opensource.kab@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Adarsh Babu Kalepalli [Wed, 30 Jun 2021 18:27:45 +0000 (23:57 +0530)]
cmd:Elaborate 'blkcache' cmd HELP statement
HELP description is provided for ‘configure’ sub-command
of ‘blkcache’.
Signed-off-by: Adarsh Babu Kalepalli <opensource.kab@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Heinrich Schuchardt [Thu, 29 Jul 2021 18:27:17 +0000 (20:27 +0200)]
config: MPC8548CDS: eliminate symbol CONFIG_SYS_ID_EEPROM
Symbol CONFIG_SYS_ID_EEPROM is defined in include/configs/MPC8548CDS.h
but never used. Remove it here and from the whitelist.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Tom Rini [Tue, 27 Jul 2021 17:01:44 +0000 (13:01 -0400)]
doc: Add basic information about running CI tests
Start out by documenting general expectations on when CI is run, how
anyone can run Azure pipelines, and how GitLab CI pipelines can be run.
Signed-off-by: Tom Rini <trini@konsulko.com>
Campbell Suter [Fri, 30 Apr 2021 04:45:46 +0000 (16:45 +1200)]
fs/squashfs: Fix some hardlinks reading the wrong inode
In SquashFS, the contents of a directory is stored by
squashfs_directory_entry structures which contain the file's name, inode
and position within the filesystem.
The inode number is not stored directly; instead each directory has one
or more headers which set a base inode number, and files store the
offset from that to the file's inode number.
In mksquashfs, each inode is allocated a number in the same order as
they are written to the directory table; thus the offset from the
header's base inode number to the file's inode number is usually
positive.
Hardlinks are simply stored with two directory entries referencing the
same file. This means the second entry will thus have an inode number
much lower than the surrounding files. Since the header's base inode
number comes from the first entry that uses the header, this delta will
usually be negative.
Previously, U-Boot's squashfs_directory_entry.inode_offset field was
declared as an unsigned value. Thus when a negative value was found, it
would either resolve to an invalid inode number or to that of an
unrelated file.
A squashfs image to test this can be created like so:
echo hi > sqfs_test_files/001-root-file
mkdir sqfs_test_files/002-subdir
touch sqfs_test_files/002-subdir/003-file
ln sqfs_test_files/{001-root-file,002-subdir/004-link}
mksquashfs sqfs_test_files/ test.sqfs -noappend
Note that squashfs sorts the files ASCIIbetacally, so we can use the
names to control the order they appear in. The ordering is important -
the first reference to the file must have a lower inode number than the
directory in which the second reference resides, and the second
reference cannot be the first file in the directory.
Listing this sample image in U-Boot results in:
=> sqfsls virtio 2 002-subdir
0 003-file
Inode not found.
0 004-link
Signed-off-by: Campbell Suter <campbell@snapit.group>
Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com>
John Keeping [Tue, 20 Apr 2021 18:19:44 +0000 (19:19 +0100)]
fit: Fix verification of images with external data
The "-E" option to mkimage generates a FIT with external data using the
data-size and data-offset properties which must both be ignored when
verifying a signature.
Add "data-offset" to the list of excluded properties for signature
verification; since the line is now too long, re-format the list to
one-per-line and make it static since the data is constant.
Signed-off-by: John Keeping <john@metanate.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tom Rini [Thu, 15 Jul 2021 18:24:25 +0000 (14:24 -0400)]
CI: Update to LLVM-12
The current stable release of LLVM is 12, update to that. While at it,
fix that we had not correctly upgraded to LLVM 11 previously.
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Tue, 3 Aug 2021 18:06:41 +0000 (14:06 -0400)]
Merge https://source.denx.de/u-boot/custodians/u-boot-spi
- SPI-NOR fix (Big Meng)
- XMC XM25QH64C flash (Reto Schneider)
Tom Rini [Tue, 3 Aug 2021 13:07:01 +0000 (09:07 -0400)]
Merge https://source.denx.de/u-boot/custodians/u-boot-samsung
Bin Meng [Fri, 30 Jul 2021 07:20:17 +0000 (15:20 +0800)]
mtd: spi-nor: Mask out fast read if not requested in DT
The DT bindings of "jedec,spi-nor" [1] defines "m25p,fast-read" property
to indicate that "fast read" opcode can be used to read data from the
chip instead of the usual "read" opcode.
If this property is not present in DT, mask out fast read in
spi_nor_init_params(). This change mirrors the same logic in
spi_nor_info_init_params() in drivers/mtd/spi-nor/core.c in
the Linux kernel v5.14-rc3.
[1] Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml in the kernel tree
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Bin Meng [Fri, 30 Jul 2021 07:20:16 +0000 (15:20 +0800)]
mtd: spi-nor: Respect flash's hwcaps in spi_nor_adjust_hwcaps()
The smart spi_nor_adjust_hwcaps() does not respect the SPI flash's
hwcaps, and only looks to the controller on what can be supported.
The flash's hwcaps needs to be AND'ed before checking.
Fixes:
71025f013ccb ("mtd: spi-nor-core: Rework hwcaps selection")
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Pratyush Yadav <p.yadav@ti.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Bin Meng [Wed, 28 Jul 2021 12:50:14 +0000 (20:50 +0800)]
spi: spi-mem-nodm: Fix read data size issue
When slave drivers don't set the max_read_size, the spi-mem should
directly use data.nbytes and not limit to any size. But current
logic will limit to the max_write_size.
This commit mirrors the same changes in the dm version done in
commit
535b1fdb8e5e ("spi: spi-mem: Fix read data size issue").
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Reto Schneider [Thu, 17 Jun 2021 16:26:51 +0000 (18:26 +0200)]
mtd: spi-nor-ids: Add support for XMC XM25QH64C
This chip has been (briefly) tested on the MediaTek MT7688 based GARDENA
smart gateway.
Datasheet: http://xmcwh.com/Uploads/2020-12-17/XM25QH64C_Ver1.1.pdf
Signed-off-by: Reto Schneider <reto.schneider@husqvarnagroup.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tom Rini [Tue, 3 Aug 2021 01:35:50 +0000 (21:35 -0400)]
Merge https://source.denx.de/u-boot/custodians/u-boot-x86
- Fixed broken ICH SPI driver in software sequencer mode
- Added "m25p,fast-read" to SPI flash node for x86 boards
- Drop ROM_NEEDS_BLOBS and BUILD_ROM for x86 ROM builds
- Define a default TSC timer frequency for all x86 boards
- x86 MTRR MSR programming codes bug fixes
- x86 "hob" command bug fixes
- Don't program MTRR for DRAM for FSP1
- Move INIT_PHASE_END_FIRMWARE to FSP2
- Use external graphics card by default on Intel Crown Bay
- tangier: Fix DMA controller IRQ polarity in CSRT
Tom Rini [Mon, 2 Aug 2021 17:32:20 +0000 (13:32 -0400)]
Merge branch '2021-08-02-numeric-input-cleanups'
- Merge in a series that cleans up and makes more consistent how we deal
with numeric input on the CLI. This saves a few bytes in a lot of
places.
Simon Glass [Sat, 24 Jul 2021 15:03:38 +0000 (09:03 -0600)]
lib: Allow using 0x when a decimal value is requested
U-Boot mostly uses hex for value input, largely because addresses are much
easier to understand in hex.
But in some cases a decimal value is requested, such as where the value is
small or hex does not make sense in the context. In these cases it is
sometimes useful to be able to provide a hex value in any case, if only to
resolve any ambiguity.
Add this functionality, for increased flexibility.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Sat, 24 Jul 2021 15:03:37 +0000 (09:03 -0600)]
doc: Add a note about number representation
Mention the default base of U-Boot in the command-line section. Add
examples for decimal and octal.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Sat, 24 Jul 2021 15:03:36 +0000 (09:03 -0600)]
doc: Convert command-line info to rST
Take this part of the README and put it into rST format.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Sat, 24 Jul 2021 15:03:35 +0000 (09:03 -0600)]
lib: Move common digit-parsing code into a function
The code to convert a character into a digit is repeated twice in this
file. Factor it out into a separate function. This also makes the code a
little easier to read.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Sat, 24 Jul 2021 15:03:34 +0000 (09:03 -0600)]
lib: Add octal tests for simple_strtoul/l()
This function support decoding octal but no tests are included yet.
Add some.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Sat, 24 Jul 2021 15:03:33 +0000 (09:03 -0600)]
lib: Add tests for simple_strtoull()
Add some tests that check the behaviour of this function. These are the
same as for simple_strtoul() but with a few longer values.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Sat, 24 Jul 2021 15:03:32 +0000 (09:03 -0600)]
lib: Drop unnecessary check for hex digit
If we see 0x then we can assume this is the start of a hex value. It
does not seem necessary to check for a hex digit after that since it will
happen when parsing the value anyway.
Drop this check to simplify the code and reduce size. Add a few more test
cases for when a 0x prefix is used.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Sat, 24 Jul 2021 15:03:31 +0000 (09:03 -0600)]
lib: Comment the base parameter with simple_strtoul/l()
This parameter is not documented properly since it does not cover the
meaning when the base is 0. Update this in both functions.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Sat, 24 Jul 2021 15:03:30 +0000 (09:03 -0600)]
global: Convert simple_strtoul() with decimal to dectoul()
It is a pain to have to specify the value 10 in each call. Add a new
dectoul() function and update the code to use it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Sat, 24 Jul 2021 15:03:29 +0000 (09:03 -0600)]
global: Convert simple_strtoul() with hex to hextoul()
It is a pain to have to specify the value 16 in each call. Add a new
hextoul() function and update the code to use it.
Add a proper comment to simple_strtoul() while we are here.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Sat, 24 Jul 2021 15:03:28 +0000 (09:03 -0600)]
hash: Ensure verification hex pairs are terminated
This function seems to assume that the chr[] variable contains zeros at
the start, which is not always true. Use strlcpy() to be safe.
Signed-off-by: Simon Glass <sjg@chromium.org>
Bin Meng [Mon, 2 Aug 2021 07:05:16 +0000 (15:05 +0800)]
x86: crownbay: Use external graphics card by default
The board routes the Integrated Graphics Device (IGD) to an LVDS
panel, which is less popular than a PCIe based graphics card.
Disable the IGD so that it does not show up in the PCI configuration
space as a VGA display controller, so we can use an external PCIe
graphics card with whatever cable we have.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Bin Meng [Mon, 2 Aug 2021 07:05:15 +0000 (15:05 +0800)]
x86: queensbay: Return directly if IGD / SDVO were already disabled
Initialize 'igd' and 'sdvo' to NULL so that we just need to test
them against NULL later, to be compatible with that case that IGD
and SDVO devices were already in disabled state.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Bin Meng [Mon, 2 Aug 2021 09:45:22 +0000 (17:45 +0800)]
x86: fsp: Only FSP2 has INIT_PHASE_END_FIRMWARE
For FSP1, there is no such INIT_PHASE_END_FIRMWARE.
Move board_final_cleanup() to fsp2 directory.
Fixes:
7c73cea44290 ("x86: Notify the FSP of the 'end firmware' event")
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested on chromebook_coral, chromebook_samus, chromebook_link, minnowmax
Tested-by: Simon Glass <sjg@chromium.org>
Bin Meng [Mon, 2 Aug 2021 09:45:21 +0000 (17:45 +0800)]
x86: fsp: Don't program MTRR for DRAM for FSP1
There are several outstanding issues as to why this does not apply
to FSP1:
* For FSP1, the system memory and reserved memory used by FSP are
already programmed in the MTRR by FSP.
* The 'mtrr_top' mistakenly includes TSEG memory range that has the
same RES_MEM_RESERVED resource type. Its address is programmed
and reported by FSP to be near the top of 4 GiB space, which is
not what we want for SDRAM.
* The call to mtrr_add_request() is not guaranteed to have its size
to be exactly the power of 2. This causes reserved bits of the
IA32_MTRR_PHYSMASK register to be written which generates #GP.
For FSP2, it seems this is necessary as without this, U-Boot boot
process on Chromebook Coral goes very slowly.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested on chromebook_coral, chromebook_samus, chromebook_link, minnowmax
Tested-by: Simon Glass <sjg@chromium.org>
Tom Rini [Mon, 2 Aug 2021 12:54:23 +0000 (08:54 -0400)]
Merge tag 'efi-2021-10-rc2' of https://source.denx.de/u-boot/custodians/u-boot-efi
Pull request for efi-2021-10-rc2
Documentation:
* handle 'make htmldocs' warnings as errors
* add missing board/ti/index.rst
Bug fixes:
* avoid buffer overrun in TrueType console
* lib: disable CONFIG_SPL_HEXDUMP by default
Tom Rini [Mon, 2 Aug 2021 12:53:58 +0000 (08:53 -0400)]
Merge tag 'mmc-2021-7-30' of https://source.denx.de/u-boot/custodians/u-boot-mmc
pl180_mmci update and cleanup
fix rpmb routing memory alignment
Bin Meng [Sat, 31 Jul 2021 08:45:28 +0000 (16:45 +0800)]
x86: cmd: hob: Fix display of resource type for system memory
The resource type for system memory is currently displayed as
"unknown", which is wrong.
Fixes:
51af144eb7a0 ("x86: Allow showing details about a HOB entry")
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested on chromebook_coral, chromebook_samus, chromebook_link, minnowmax
Tested-by: Simon Glass <sjg@chromium.org>
Bin Meng [Sat, 31 Jul 2021 08:45:27 +0000 (16:45 +0800)]
x86: cmd: hob: Fix the command usage and help messages
At present the hob command usage and help messages are messed up
in a single line. They should be separated.
This was a regression introduced when [seq] and [-v] were added
to the command.
Fixes:
d11544dfa9f4 ("x86: hob: Add way to show a single hob entry")
Fixes:
51af144eb7a0 ("x86: Allow showing details about a HOB entry")
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested on chromebook_coral, chromebook_samus, chromebook_link, minnowmax
Tested-by: Simon Glass <sjg@chromium.org>
Bin Meng [Sat, 31 Jul 2021 08:45:26 +0000 (16:45 +0800)]
x86: mtrr: Abort if requested size is not power of 2
The size parameter of mtrr_add_request() and mtrr_set_next_var()
shall be power of 2, otherwise the logic creates a mask that does
not meet the requirement of IA32_MTRR_PHYSMASK register.
Programming such a mask value to IA32_MTRR_PHYSMASK generates #GP.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested on chromebook_coral, chromebook_samus, chromebook_link, minnowmax
Tested-by: Simon Glass <sjg@chromium.org>
Bin Meng [Sat, 31 Jul 2021 08:45:25 +0000 (16:45 +0800)]
x86: mtrr: Skip MSRs that were already programmed in mtrr_commit()
At present mtrr_commit() programs the MTRR MSRs starting from
index 0, which may overwrite MSRs that were already programmed
by previous boot stage or FSP.
Switch to call mtrr_set_next_var() instead.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested on chromebook_coral, chromebook_samus, chromebook_link, minnowmax
Tested-by: Simon Glass <sjg@chromium.org>
Bin Meng [Sat, 31 Jul 2021 08:45:24 +0000 (16:45 +0800)]
x86: mtrr: Do not clear the unused ones in mtrr_commit()
Current mtrr_commit() logic assumes that MTRR MSRs are programmed
consecutively from index 0 to its maximum number, and whenever it
detects an unused one, it clears all other MTRRs starting from that
one. However this may not always be the case.
In fact, the clear is not much helpful because these MTRRs come out
of reset as disabled already. Drop the clear codes.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested on chromebook_coral, chromebook_samus, chromebook_link, minnowmax
Tested-by: Simon Glass <sjg@chromium.org>
Bin Meng [Wed, 28 Jul 2021 04:00:23 +0000 (12:00 +0800)]
x86: dts: Define a default TSC timer frequency
If for some reason, TSC timer frequency cannot be determined from
hardware, nor is it specified in the device tree, U-Boot will panic
resulting in endless reset during boot.
Let's define a default TSC timer frequency using the Kconfig value
CONFIG_X86_TSC_TIMER_FREQ (note: #include must be used instead of
/include/ otherwise the macro is not pre-processed).
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Bin Meng [Wed, 28 Jul 2021 04:00:22 +0000 (12:00 +0800)]
x86: tsc: Rename X86_TSC_TIMER_EARLY_FREQ to X86_TSC_TIMER_FREQ
Currently there are two places to specify the x86 TSC timer frequency
with one in Kconfig used for early timer and the other one in device
tree used when the frequency cannot be determined from hardware.
This may potentially create an inconsistent config where the 2 values
do not match. Let's use the one specified in Kconfig in the device
tree as well.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Bin Meng [Tue, 27 Jul 2021 15:15:39 +0000 (23:15 +0800)]
x86: kconfig: Drop ROM_NEEDS_BLOBS and BUILD_ROM
These 2 options are no longer needed as now binman is used to build
u-boot.rom.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Bin Meng [Tue, 27 Jul 2021 13:30:02 +0000 (21:30 +0800)]
x86: crownbay: Adjust VGA rom address
binman complains when binary blobs are present:
Node '/binman/rom/intel-vga': Offset 0xfff90000 (
4294508544) overlaps
with previous entry '/binman/rom/u-boot-dtb-with-ucode' ending at
0xfff9204c (
4294516812)
Adjust VGA rom address to 0xfffa0000 so that u-boot.rom image can be
successfully built again.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Andy Shevchenko [Fri, 30 Jul 2021 20:15:44 +0000 (23:15 +0300)]
x86: tangier: Fix DMA controller IRQ polarity in CSRT
IRQ polarity in CSRT has the same definition as by ACPI specification
chapter 19.6.64 "Interrupt (Interrupt Resource Descriptor Macro)", i.e.
ActiveHigh is 0, and ActiveLow is 1. On Intel Tangier the DMA controller
IRQ polarity is ActiveHigh.
Note, in DSDT (see southcluster.asl) it's described correctly.
Fixes:
5e99fde34a77 ("x86: tangier: Populate CSRT for shared DMA controller")
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Bin Meng [Thu, 29 Jul 2021 12:18:23 +0000 (20:18 +0800)]
x86: dts: Add "m25p,fast-read" to SPI flash node
Except ICH7 SPI, all SPI flashes connected to ICH9 / Fast SPI should
have "m25p,fast-read" property present in their DT nodes.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Bin Meng [Wed, 28 Jul 2021 10:28:57 +0000 (18:28 +0800)]
x86: crownbay: Disable CONFIG_SPI_FLASH_SMART_HWCAPS
Since commit
71025f013ccb ("mtd: spi-nor-core: Rework hwcaps selection")
SPI flash on Intel Crown Bay board does not work anymore.
Disable CONFIG_SPI_FLASH_SMART_HWCAPS until a proper fix is made to
the spi-nor core.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Bin Meng [Wed, 28 Jul 2021 10:28:56 +0000 (18:28 +0800)]
spi: ich: Limit slave->max_read_size
Since commit
43c145b8b3ee ("spi: ich: Correct max-size bug in ich_spi_adjust_size()")
(in v2020.04-rc1), SPI flash read no longer works with ICH SPI controller
in software sequencer mode.
ICH controller can only transfer a small number of bytes at once.
Before commit
43c145b8b3ee, the logic happens to make sure data.nbytes
is limited to slave->max_write_size but after commit
43c145b8b3ee
data.nbytes is no longer limited because slave->max_read_size is not
initialized with a valid number.
Fixes:
43c145b8b3ee ("spi: ich: Correct max-size bug in ich_spi_adjust_size()")
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Heinrich Schuchardt [Mon, 2 Aug 2021 06:21:12 +0000 (08:21 +0200)]
efi_loader: typo cerificate
%s/cerificate/certificate/
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Heinrich Schuchardt [Sun, 1 Aug 2021 21:29:20 +0000 (23:29 +0200)]
doc: add graphviz imagemagick as build dependencies
'make htmldocs' requires graphviz and imagemagick (at least with Sphinx
3.5.4).
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Heinrich Schuchardt [Sun, 1 Aug 2021 20:11:39 +0000 (22:11 +0200)]
doc: handle 'make htmldocs' warnings as errors
Parameter -W for sphinx-build turns build warnings into errors. This helps
us to avoid bad patches passing Gitlab CI.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Heinrich Schuchardt [Sun, 1 Aug 2021 20:09:44 +0000 (22:09 +0200)]
doc: add missing board/ti/index.rst
Commit
8baeeecbe305 ("doc: board: Move j721e document to doc/board/ti/
directory") introduced 'make htmldocs' build errors due to a missing
file board/ti/index.rst.
Fixes:
8baeeecbe305 ("doc: board: Move j721e document to doc/board/ti/ directory")
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Tom Rini [Sun, 1 Aug 2021 18:41:22 +0000 (14:41 -0400)]
Merge tag 'dm-pull-1aug21' of https://source.denx.de/u-boot/custodians/u-boot-dm
sandbox TPM-emulator improvements
rST documentation and fixes for moveconfig
handle empty 'ranges' property in dtoc
patman warning for invalid tag
clean-ups to 'fdt add' command
Simon Glass [Thu, 29 Jul 2021 01:23:11 +0000 (19:23 -0600)]
dtoc: Support widening a bool value
At present if we see 'ranges' property (with no value) we assume it is a
boolean, as per the devicetree spec.
But another node may define 'ranges' with a value, forcing us to widen it
to an int array. At present this is not supported and causes an error.
Fix this and add some test cases.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reported-by: Tom Rini <trini@konsulko.com>
Simon Glass [Thu, 29 Jul 2021 01:23:10 +0000 (19:23 -0600)]
dtoc: Fix widening an int array to an int
An int array can hold a single int so we should not need to do anything
in the widening operation. However due to a quirk in the code, an int[3]
widened with an int produced an int[4]. Fix this and add a test.
Fix a comment typo while we are here.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reported-by: Tom Rini <trini@konsulko.com>
Simon Glass [Thu, 29 Jul 2021 01:23:09 +0000 (19:23 -0600)]
dtoc: Rename is_wider_than() to reduce confusion
The current name is confusing because the logic is actually backwards from
what you might expect. Rename it to needs_widening() and update the
comments.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Sat, 24 Jul 2021 21:14:39 +0000 (15:14 -0600)]
sandbox: Reduce keyed autoboot delay
The autoboot tests are a recent addition to U-Boot, providing much-needed
coverage in this area.
A side effect of the keyed autoboot test is that this feature is enabled
in sandbox always. This changes the autoboot prompt and confuses the
pytests. Some tests become slower, for example the vboot tests take about
27s now instead of 3s.
We don't actually need this feature enabled to be able to run the tests.
Add a switch to allow sandbox to turn it on and off as needed. Use this
in the one test that needs it.
Add a command-line flag in case this is desired in normal use.
Signed-off-by: Simon Glass <sjg@chromium.org>
Fixes:
25c8b9f298e ("test: add first autoboot unit tests")
Reviewed-by: Steffen Jaeckel <jaeckel-floss@eyet-services.de>
Simon Glass [Thu, 22 Jul 2021 03:35:53 +0000 (21:35 -0600)]
moveconfig: Update to newer kconfiglib
Some of the more advanced features of this tool don't work anymore since
kconfiglib was update. Update the code accordingly.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Thu, 22 Jul 2021 03:35:52 +0000 (21:35 -0600)]
doc: Fix up outdated moveconfig docs
The examples here are a bit messed up since the command does not match
the documentation. Use a different example instead.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Thu, 22 Jul 2021 03:35:51 +0000 (21:35 -0600)]
doc: Add docs for the moveconfig tool
Move these docs into htmldocs so they can be read there.
Signed-off-by: Simon Glass <sjg@chromium.org>