Fred Riss [Fri, 8 May 2020 22:14:14 +0000 (15:14 -0700)]
[lldb/Driver] Support terminal resizing
Summary:
The comment in the Editine.h header made it sound like editline was
just unable to handle terminal resizing. We were not ever telling
editline that the terminal had changed size, which might explain why
it wasn't working.
This patch threads a `TerminalSizeChanged()` callback through the
IOHandler and invokes it from the SIGWINCH handler in the driver. Our
`Editline` class already had a `TerminalSizeChanged()` method which
was invoked only when editline was configured.
This patch also changes `Editline` to not apply the changes right away
in `TerminalSizeChanged()`, but instead defer that to the next
character read. During my testing, it happened once that the signal
was received while our `ConnectionFileDescriptor::Read` was allocating
memory. As `el_resize` seems to allocate memory too, this crashed.
Reviewers: labath, teemperor
Subscribers: lldb-commits
Tags: #lldb
Differential Revision: https://reviews.llvm.org/D79654
David Blaikie [Tue, 12 May 2020 18:39:01 +0000 (11:39 -0700)]
Avoid binding pointers to "auto&" (by dereferencing the pointer that's non-null anyway)
Based on @djtodoro's
2552dc5317e0
zoecarver [Tue, 12 May 2020 01:42:50 +0000 (18:42 -0700)]
[libcxx] Re-commit: shared_ptr changes from library fundamentals (P0414R2).
Implements P0414R2:
* Adds support for array types in std::shared_ptr.
* Adds reinterpret_pointer_cast for shared_ptr.
Re-committing now that the leaking tests are fixed.
Differential Revision: https://reviews.llvm.org/D62259
Kamau Bridgeman [Tue, 12 May 2020 18:15:06 +0000 (13:15 -0500)]
[PowerPC] Fold redundant load immediates of zero and delete if possible
This patch folds redundant load immediates into a zero for instructions
which recognise this as the value zero and not the register. If the load
immediate is no longer in use it is then deleted.
This is already done in earlier passes but the ppc-mi-peephole allows for
a more general implementation.
Differential Revision: https://reviews.llvm.org/D69168
Jonas Devlieghere [Tue, 12 May 2020 17:28:27 +0000 (10:28 -0700)]
[Reproducers] Serialize process arguments in ProcessInfo
While debugging why TestProcessList.py failed during passive replay, I
remembered that we don't serialize the arguments for ProcessInfo. This
is necessary to make the test pass and to make platform process list -v
behave the same during capture and replay.
Differential revision: https://reviews.llvm.org/D79646
Jan Korous [Fri, 8 May 2020 23:29:17 +0000 (16:29 -0700)]
[FileCollector][NFC] Add comments
Differential Revision: https://reviews.llvm.org/D78961
Juneyoung Lee [Mon, 20 Apr 2020 15:35:45 +0000 (00:35 +0900)]
[ValueTracking] Let propagatesPoison support binops/unaryops/cast/etc.
Summary:
This patch makes propagatesPoison be more accurate by returning true on
more bin ops/unary ops/casts/etc.
The changed test in ScalarEvolution/nsw.ll was introduced by
https://github.com/llvm/llvm-project/commit/
a19edc4d15b0dae0210b90615775edd76f021008 .
IIUC, the goal of the tests is to show that iv.inc's SCEV expression still has
no-overflow flags even if the loop isn't in the wanted form.
It becomes more accurate with this patch, so think this is okay.
Reviewers: spatel, lebedev.ri, jdoerfert, reames, nikic, sanjoy
Reviewed By: spatel, nikic
Subscribers: regehr, nlopes, efriedma, fhahn, javed.absar, llvm-commits, hiraditya
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D78615
Craig Topper [Tue, 12 May 2020 17:10:42 +0000 (10:10 -0700)]
[X86] Remove the v16i8->v16i16 path for MULHS with AVX2.
We have a couple main strategies for legalizing MULH.
-If the vXi16 type is legal, extend to do the full i16 multiply
and then shift and truncate the results.
-Use unpcks to split each 128 bit lane into high and low halves.a
For signed we have an extra case to split a v32i8 to v16i8 and then
use the extending to v16i16 strategy.
This patch proposes to use the unpck strategy instead. Which is
what we already do for unsigned.
This seems to be 1 instruction shorter when the RHS is constant
like the idiv case. It's 1 instruction longer for the smulo case.
But we're trading cross lane shuffles for inlane shuffles and a
shift.
Differential Revision: https://reviews.llvm.org/D79652
Dimitry Andric [Tue, 12 May 2020 10:33:15 +0000 (12:33 +0200)]
[arm] Add big-endian version of pcrel fixups for adr instructions
Summary:
In
2e24219d3cbf, a number of ARM pcrel fixups were resolved at assembly
time, to solve PR44929. This only covered little-endian ARM however, so
add similar fixups for big-endian ARM. Also extend the test case to
cover big-endian ARM.
Reviewers: hans, psmith, MaskRay
Reviewed By: psmith, MaskRay
Subscribers: kristof.beyls, hiraditya, danielkiss, emaste, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D79774
Austin Kerbow [Tue, 12 May 2020 03:30:10 +0000 (20:30 -0700)]
[AMDGPU] Add AGPRs to getRegClassForSizeOnBank
Differential Revision: https://reviews.llvm.org/D79761
Craig Topper [Tue, 12 May 2020 16:43:24 +0000 (09:43 -0700)]
[CodeGen] Use Align in MachineConstantPool.
Sanjay Patel [Tue, 12 May 2020 16:48:51 +0000 (12:48 -0400)]
[VectorCombine] add test to check for iterative improvements; NFC
Thomas Lively [Tue, 12 May 2020 16:39:01 +0000 (09:39 -0700)]
[WebAssembly] Implement pseudo-min/max SIMD instructions
Summary:
As proposed in https://github.com/WebAssembly/simd/pull/122. Since
these instructions are not yet merged to the SIMD spec proposal, this
patch makes them entirely opt-in by surfacing them only through LLVM
intrinsics and clang builtins. If these instructions are made
official, these intrinsics and builtins should be replaced with simple
instruction patterns.
Reviewers: aheejin
Subscribers: dschuff, sbc100, jgravelle-google, hiraditya, sunfish, cfe-commits, llvm-commits
Tags: #clang, #llvm
Differential Revision: https://reviews.llvm.org/D79742
Fangrui Song [Tue, 12 May 2020 16:21:19 +0000 (09:21 -0700)]
[gcov][test] Fix clang test
Fangrui Song [Tue, 12 May 2020 06:20:33 +0000 (23:20 -0700)]
[gcov] Default coverage version to '408*' and delete CC1 option -coverage-exit-block-before-body
gcov 4.8 (r189778) moved the exit block from the last to the second.
The .gcda format is compatible with 4.7 but
* decoding libgcov 4.7 produced .gcda with gcov [4.7,8) can mistake the
exit block, emit bogus `%s:'%s' has arcs from exit block\n` warnings,
and print wrong `" returned %s` for branch statistics (-b).
* decoding libgcov 4.8 produced .gcda with gcov 4.7 has similar issues.
Also, rename "return block" to "exit block" because the latter is the
appropriate term.
Whitney Tsang [Tue, 12 May 2020 15:56:14 +0000 (15:56 +0000)]
[PassBuilder] Moved ProfileSummaryAnalysis in buildInlinerPipeline.
Summary:
As commented in the code, ProfileSummaryAnalysis is required for inliner
pass to query, so this patch moved
RequireAnalysisPass<ProfileSummaryAnalysis> in the recently created
buildInlinerPipeline.
Reviewer: mtrofin, davidxl, tejohnson, dblaikie, jdoerfert, sstefan1
Reviewed By: mtrofin, davidxl, jdoerfert
Subscribers: hiraditya, steven_wu, dexonsmith, wuzish, llvm-commits,
jsji
Tag: LLVM
Differential Revision: https://reviews.llvm.org/D79696
Jay Foad [Fri, 17 Apr 2020 15:17:26 +0000 (16:17 +0100)]
[GlobalISel][IRTranslator] Fix <1 x Ty> handling in ConstantExprs
Summary:
ConstantExprs involving operations on <1 x Ty> could translate into MIR
that failed to verify with:
*** Bad machine code: Reading virtual register without a def ***
The problem was that translate(const Constant &C, Register Reg) had
recursive calls that passed the same Reg in for the translation of a
subexpression, but without updating VMap for the subexpression first as
translate(const Constant &C, Register Reg) expects.
Fix this by using the same translateCopy helper function that we use for
translating Instructions. In some cases this causes extra G_COPY
MIR instructions to be generated.
Fixes https://bugs.llvm.org/show_bug.cgi?id=45576
Reviewers: arsenm, volkan, t.p.northover, aditya_nandakumar
Subscribers: jvesely, wdng, nhaehnle, rovka, hiraditya, kerbowa, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D78378
Jay Foad [Fri, 17 Apr 2020 13:36:01 +0000 (14:36 +0100)]
[GlobalISel][IRTranslator] New helper function translateCopy. NFC.
Reviewers: arsenm, volkan, t.p.northover, aditya_nandakumar
Subscribers: wdng, rovka, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D78377
Florian Hahn [Tue, 12 May 2020 15:37:01 +0000 (16:37 +0100)]
[Matrix] Check non-dependent elt type before creating DepSizedMatrix.
We should check non-dependent element types before creating a
DependentSizedMatrixType. Otherwise we do not generate an error message
for dependent-sized matrix types with invalid non-dependent element
types, if the template is never instantiated. See the make5 struct in
the tests.
It also moves the SEMA template tests to
clang/test/SemaTemplate/matrix-type.cpp and introduces a few more test
cases.
Michael Kruse [Tue, 12 May 2020 14:44:34 +0000 (09:44 -0500)]
[docs] Corrected inaccuracies in Common Problems section.
Changed the language in LLVM_USE_LINKER to more strongly recommend LLD
and to specify that the GNU gold linker is only useful if LLD is
unavailable in binary form and it is the first build of LLVM. Added that
LLD will help when used on ELF-based platforms.
Corrected information in CMAKE_BUILD_TYPE regarding the Release build
type and enabling assertions.
Added option LLVM_ENABLE_ASSERTIONS and mentioned enabling this option
with a Release build as an alternative to using a Debug build.
Specified that the LLVM_OPTIMIZED_TABLEGEN
option is only for Debug builds, that the LLVM_USE_SPLIT_DWARF option
is only available on ELF host platforms, and that setting
CLANG_ENABLE_STATIC_ANALYZER to OFF only slightly improves build time.
These changes address comments made in D75425.
Reviewed By: Meinersbur
Differential Revision: https://reviews.llvm.org/D77346
Jez Ng [Fri, 24 Apr 2020 03:16:49 +0000 (20:16 -0700)]
[lld-macho] Add support for creating and reading reexported dylibs
This unblocks the linking of real programs, since many core system
functions are only available as sub-libraries of libSystem.
Differential Revision: https://reviews.llvm.org/D79228
Jez Ng [Tue, 12 May 2020 14:29:15 +0000 (07:29 -0700)]
[lld-macho] Re-add dylink-lazy test
This reverts commit
eb81de2de4003e3045fdf743e093f77e37aee9bf; the
test commands just needed to be run under llvm-lit.
James Y Knight [Tue, 12 May 2020 04:22:54 +0000 (00:22 -0400)]
Add comment for SelectionDAGBuilder::SL field.
Haojian Wu [Mon, 11 May 2020 09:02:34 +0000 (11:02 +0200)]
[clangd] Add metrics for selection tree and recovery expressions.
Reviewers: sammccall
Subscribers: ilya-biryukov, MaskRay, jkorous, arphaman, kadircet, usaxena95, cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D79701
Carl Ritson [Tue, 12 May 2020 14:02:05 +0000 (23:02 +0900)]
[AMDGPU] Order pos exports before param exports
Summary:
Modify export clustering DAG mutation to move position exports
before other exports types.
Reviewers: foad, arsenm, rampitec, nhaehnle
Reviewed By: foad
Subscribers: kzhuravl, jvesely, wdng, yaxunl, dstuttard, tpr, t-tye, hiraditya, kerbowa, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D79670
Matt Arsenault [Fri, 27 Mar 2020 16:28:24 +0000 (12:28 -0400)]
HIP: Merge builtin library handling
Merge with the new --rocm-path handling used for OpenCL. This looks
for a usable set of device libraries upfront, rather than giving a
generic "no such file or directory error". If any of the required
bitcode libraries are missing, this will now produce a "cannot find
ROCm installation." error. This differs from the existing hip specific
flags by pointing to a rocm root install instead of a single directory
with bitcode files.
This tries to maintain compatibility with the existing the
--hip-device-lib and --hip-device-lib-path flags, as well as the
HIP_DEVICE_LIB_PATH environment variable, or at least the range of
uses with testcases. The existing range of uses and behavior doesn't
entirely make sense to me, so some of the untested edge cases change
behavior. Currently the two path forms seem to have the double purpose
of a search path for an arbitrary --hip-device-lib, and for finding
the stock set of libraries. Since the stock set of libraries This also
changes the behavior when multiple paths are specified, and only takes
the last one (and the environment variable only handles a single
path).
If --hip-device-lib is used, it now only treats --hip-device-lib-path
as the search path for it, and does not attempt to find the rocm
installation. If not, --hip-device-lib-path and the environment
variable are used as the directory to search instead of the rocm root
based path.
This should also automatically fix handling of the options to use
wave64.
Matt Arsenault [Fri, 10 Apr 2020 16:56:20 +0000 (12:56 -0400)]
AMDGPU: Search for new ROCm bitcode library structure
The current install situation is a mess, but I'm working on fixing
it. Search for the target layout instead of one of the N options that
exist today.
Reid Kleckner [Mon, 11 May 2020 20:16:25 +0000 (13:16 -0700)]
[LLD] Rename iDTable -> idTable, NFC
The variable renaming change did not handle this variable well.
Benjamin Kramer [Tue, 12 May 2020 13:26:59 +0000 (15:26 +0200)]
Fold single-use variables into assert
This avoids unused variable warnings in Release builds.
Kristof Beyls [Thu, 7 May 2020 15:32:44 +0000 (17:32 +0200)]
Add Linux SVE Ptrace macros.
Differential Revision: https://reviews.llvm.org/D79623
Sam McCall [Tue, 12 May 2020 13:18:50 +0000 (15:18 +0200)]
Revert "[mlir] Revisit std.subview handling of static information."
This reverts commit
80d133b24f77d1b9d351251315606441c971ef9b.
Per Stephan Herhut: The canonicalizer pattern that was added creates
forms of the subview op that cannot be lowered.
This is shown by failing Tensorflow XLA tests such as:
tensorflow/compiler/xla/service/mlir_gpu/tests:abs.hlo.test
Will provide more details offline, they rely on logs from private CI.
Melanie Blower [Fri, 8 May 2020 15:05:34 +0000 (08:05 -0700)]
[PATCH] #pragma float_control should be permitted in namespace scope.
Summary: Erroneous error diagnostic observed in VS2017 <numeric> header
Also correction to propagate usesFPIntrin from template func to instantiation.
Reviewers: rjmccall, erichkeane (no feedback received)
Differential Revision: https://reviews.llvm.org/D79631
Simon Pilgrim [Tue, 12 May 2020 12:43:38 +0000 (13:43 +0100)]
[X86] combineX86ShuffleChain - use narrowShuffleMaskElts scale == 1 builtin handling. NFC.
narrowShuffleMaskElts already has the fast-path for scale == 1, no need to reimplement it here.
Yaxun (Sam) Liu [Fri, 24 Apr 2020 20:41:24 +0000 (16:41 -0400)]
[CUDA][HIP] Workaround for resolving host device function against wrong-sided function
recommit
c77a4078e01033aa2206c31a579d217c8a07569b with fix
https://reviews.llvm.org/D77954 caused regressions due to diagnostics in implicit
host device functions.
For now, it seems the most feasible workaround is to treat implicit host device function and explicit host
device function differently. Basically in device compilation for implicit host device functions, keep the
old behavior, i.e. give host device candidates and wrong-sided candidates equal preference. For explicit
host device functions, favor host device candidates against wrong-sided candidates.
The rationale is that explicit host device functions are blessed by the user to be valid host device functions,
that is, they should not cause diagnostics in both host and device compilation. If diagnostics occur, user is
able to fix them. However, there is no guarantee that implicit host device function can be compiled in
device compilation, therefore we need to preserve its overloading resolution in device compilation.
Differential Revision: https://reviews.llvm.org/D79526
Sam Parker [Tue, 12 May 2020 12:05:09 +0000 (13:05 +0100)]
[NFC][AArch64] More casts tests...
Don't use truncs are users because sometimes they're free too.
Simon Pilgrim [Tue, 12 May 2020 11:31:07 +0000 (12:31 +0100)]
[X86][AVX] Use X86ISD::VPERM2X128 for blend-with-zero if optimizing for size
Last part of PR22984 - avoid the zero-register dependency if optimizing for size
Simon Pilgrim [Sun, 10 May 2020 20:50:13 +0000 (21:50 +0100)]
FuzzerCLI.h - reduce StringRef.h include to forward declaration. NFC.
Simon Pilgrim [Sun, 10 May 2020 19:33:51 +0000 (20:33 +0100)]
DebugCounter.h - remove unused includes. NFC.
Added explicit StringRef.h include as we need the full definition for several inline functions in DebugCounter.h.
Pierre-vh [Wed, 8 Apr 2020 10:55:09 +0000 (11:55 +0100)]
[Target][ARM] Replace outdated getARMVPTBlockMask function
getARMVPTBlockMask was an outdated function that only handled basic
block masks: T, TT, TTT and TTTT. This worked fine before the MVE
VPT Block Insertion Pass improvements as it was the only kind of
masks that it could generate, but now it can generate more complex
masks that uses E predicates, so it's dangerous to use that function
to calculate VPT/VPST block masks.
I replaced it with 2 different functions:
- expandPredBlockMask, in ARMBaseInfo. This adds an "E" or "T" at
the end of an existing PredBlockMask.
- recomputeVPTBlockMask, in Thumb2InstrInfo. This takes an iterator
to a VPT/VPST instruction and recomputes its block mask by looking
at the predicated instructions that follows it. This should be
used to recompute a block mask after removing/adding a predicated
instruction to the block.
The expandPredBlockMask function is pretty much imported from the MVE
VPT Blocks pass.
I had to change the ARMLowOverheadLoops and MVEVPTBlocks passes as well
so they could use these new functions.
Differential Revision: https://reviews.llvm.org/D78201
Pierre-vh [Thu, 2 Apr 2020 14:24:14 +0000 (15:24 +0100)]
[Target][ARM] Replace re-uses of old VPR values with VPNOTs
Differential Revision: https://reviews.llvm.org/D76847
David Zarzycki [Tue, 12 May 2020 10:44:37 +0000 (06:44 -0400)]
[libcxx testing] Remove ALLOW_RETRIES from sleep_for.pass.cpp
Operating systems are best effort by default, so we cannot assume that
sleep-like APIs return as soon as we'd like.
Even if a sleep-like API returns when we want it to, the potential for
preemption means that attempts to measure time are subject to delays.
Sander de Smalen [Tue, 12 May 2020 10:23:38 +0000 (11:23 +0100)]
[CodeGen][SVE] Add patterns for whole vector predicate select
Added patterns to implement `select i1 %p, <vty> %a, <vty> %b`
Reviewed By: efriedma
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D79356
Jim Lin [Tue, 12 May 2020 10:49:17 +0000 (18:49 +0800)]
Revert "[RISCV] Make CanLowerReturn protected for downstream maintenance"
This reverts commit
d775841d7d6ee3e8bbf3a420590be9bb19433eaa.
Sam Parker [Tue, 12 May 2020 10:30:54 +0000 (11:30 +0100)]
[NFC][AArch64] More cast cost tests
Add truncating stores and casts with users.
Sander de Smalen [Tue, 12 May 2020 10:01:18 +0000 (11:01 +0100)]
[SveEmitter] Add builtins for svdup and svindex
Reviewed By: efriedma
Differential Revision: https://reviews.llvm.org/D79357
Petre-Ionut Tudor [Tue, 21 Apr 2020 13:11:13 +0000 (14:11 +0100)]
[ARM] Refactor lower to S[LR]I optimization
Summary:
The optimization has been refactored to fix certain bugs and
limitations. The condition for lowering to S[LR]I has been changed
to reflect the manual pseudocode description of SLI and SRI operation.
The optimization can now handle more cases of operand type and order.
Subscribers: kristof.beyls, hiraditya, danielkiss, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D79233
Sam Parker [Thu, 7 May 2020 12:21:31 +0000 (13:21 +0100)]
[ARM][CostModel] Improve getCastInstrCost
- Specifically check for sext/zext users which have 'long' form NEON
instructions.
- Add more entries to the table for sext/zexts so that we can report
more accurately the number of vmovls required for NEON.
- Pass the instruction to the pass implementation.
Differential Revision: https://reviews.llvm.org/D79561
Sam Parker [Tue, 12 May 2020 07:54:18 +0000 (08:54 +0100)]
[AArch64][CostModel] getCastInstrCost
Pass the instruction to the base implementation.
Differential Revision: https://reviews.llvm.org/D79562
Manoel Roemmer [Tue, 12 May 2020 08:05:00 +0000 (10:05 +0200)]
[Openmp][VE] Libomptarget plugin for NEC SX-Aurora
This patch adds a libomptarget plugin for the NEC SX-Aurora TSUBASA Vector
Engine (VE target). The code is largely based on the existing generic-elf
plugin and uses the NEC VEO and VEOSINFO libraries for offloading.
Differential Revision: https://reviews.llvm.org/D76843
Haojian Wu [Tue, 12 May 2020 08:16:30 +0000 (10:16 +0200)]
get rid of the NDEBUG usage in RecoveryExpr, NFC.
use the llvm::all_of, per dblaikie's suggestion.
Sam Parker [Tue, 12 May 2020 07:47:28 +0000 (08:47 +0100)]
[NFC][AArch64] Update tests
Add cost model tests for extending loads.
Eric Christopher [Tue, 12 May 2020 07:44:05 +0000 (00:44 -0700)]
Fix typos encountered while working on pass pipeline for O1.
Djordje Todorovic [Tue, 12 May 2020 07:40:47 +0000 (09:40 +0200)]
Revert "[NFC][DwarfDebug] Prefer explicit to auto type deduction"
This wasn't proposed by the LLVM Style Guide.
Please see https://reviews.llvm.org/D79624.
This reverts commit rG2552dc5317e0.
Djordje Todorovic [Tue, 12 May 2020 07:04:57 +0000 (09:04 +0200)]
Revert "[NFC][DwarfDebug] Avoid default capturing when using lambdas"
Reverting this because we found it isn't that useful.
Please see https://reviews.llvm.org/D79616.
This reverts commit rG45e5a32a8bd3.
Jonas Paulsson [Wed, 18 Mar 2020 17:11:56 +0000 (18:11 +0100)]
[SystemZ] Improve foldMemoryOperandImpl: vec->FP conversions
Use FP-mem instructions when folding reloads into single lane (W..) vector
instructions.
Only do this when all other operands of the instruction have already been
allocated to an FP (F0-F15) register.
Review: Ulrich Weigand
Differential Revision: https://reviews.llvm.org/D76705
David Sherwood [Tue, 5 May 2020 08:58:24 +0000 (09:58 +0100)]
[CodeGen] Fix incorrect uses of getVectorNumElements()
I have fixed up some places in SelectionDAG::getNode() where we
used to assert that the number of vector elements for two types
are the same. I have changed such cases to assert that the
element counts are the same instead. I've added new tests that
exercise the code paths for all the truncations. All the extend
operations are covered by this existing test:
CodeGen/AArch64/sve-sext-zext.ll
For the ISD::SETCC case I fixed this code path is exercised by
these existing tests:
CodeGen/AArch64/sve-fcmp.ll
CodeGen/AArch64/sve-intrinsics-int-compares-with-imm.ll
Differential Revision: https://reviews.llvm.org/D79399
Muhammad Omair Javaid [Tue, 12 May 2020 06:32:54 +0000 (11:32 +0500)]
[LLDB] Disable TestBasicEntryValues.py for arm
TestBasicEntryValues.py fails on arm 32 bit. Currently running on silent master here:
http://lab.llvm.org:8014/builders/lldb-arm-ubuntu/
Nathan Ridge [Sun, 10 May 2020 19:08:18 +0000 (15:08 -0400)]
[clangd] Have suppression comments take precedence over warning-as-error
Summary: This matches the clang-tidy behaviour.
Fixes https://github.com/clangd/clangd/issues/375
Subscribers: ilya-biryukov, MaskRay, jkorous, arphaman, kadircet, usaxena95, cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D79691
Eric Christopher [Tue, 12 May 2020 06:03:41 +0000 (23:03 -0700)]
Temporarily Revert "[mlir][shape] Tidy up shape.shape_of" as it's breaking a few tests.
This reverts commit
b6045448869a63dc7da3a4c87c124e85101220d7.
Followed up offline with a testcase.
Jim Lin [Tue, 12 May 2020 05:48:30 +0000 (13:48 +0800)]
[RISCV] Make CanLowerReturn protected for downstream maintenance
Summary: For the downstream RISCV maintenance, it would be easier to override and reuse CanLowerReturn for customizing.
Reviewers: asb, lenary, luismarques
Reviewed By: lenary
Subscribers: hiraditya, rbar, johnrusso, simoncook, sabuasal, niosHD, kito-cheng, shiva0217, jrtc27, MaskRay, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, s.egerton, pzheng, sameer.abuasal, apazos, evandro, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D78545
Qiu Chaofan [Tue, 12 May 2020 05:40:54 +0000 (13:40 +0800)]
[PowerPC] Add fma/fsqrt/fmax strict-fp intrinsics
This patch adds strict-fp intrinsics support for fma, fsqrt, fmaxnum and
fminnum on PowerPC.
Reviewed By: hfinkel
Differential Revision: https://reviews.llvm.org/D72749
zoecarver [Tue, 12 May 2020 05:42:49 +0000 (22:42 -0700)]
Revert "[libcxx] shared_ptr changes from library fundamentals (P0414R2)."
This reverts commit
e8c13c182a562f45287d6b8da612264d09027087.
Fangrui Song [Tue, 12 May 2020 05:30:49 +0000 (22:30 -0700)]
[gcov] Fix big-endian problems
In a big-endian .gcda file, the first four bytes are "gcda" instead of "adcg".
All 32-bit values are in big-endian.
With this change, libclang_rt.profile can hopefully produce gcov
compatible output.
Fangrui Song [Tue, 12 May 2020 05:08:07 +0000 (22:08 -0700)]
Revert part of D49132 "[gcov] Fix gcov profiling on big-endian machines"
D49132 is partially correct. For 64-bit values, the lower 32-bit part comes
before the higher 32-bit part (in a little-endian manner).
For 32-bit values, libgcov reads/writes 32-bit values in native endianness.
Martin Storsjö [Tue, 12 May 2020 05:20:34 +0000 (08:20 +0300)]
Partially revert "[CMake] Fix building with -DBUILD_SHARED_LIBS=ON on mingw"
This reverts parts of commit
609ef948387ba40e3693c2bd693d82ca34dcdc02,
as it caused build failures on windows if LLVM_BUILD_EXAMPLES was
enabled, due to Bye being added as a dependency of the lit tests.
Sourabh Singh Tomar [Mon, 27 Apr 2020 16:16:11 +0000 (21:46 +0530)]
[DWARF5]: Added support for dumping strx forms in llvm-dwarfdump
This patch adds support for dumping DW_MACRO_define_strx,
DW_MACRO_undef_strx in llvm-dwarfdump. These forms are currently
supported only in debug_macro section.
Reviewed By: ikudrin, dblaikie
Differential Revision: https://reviews.llvm.org/D78736
Fangrui Song [Tue, 12 May 2020 01:43:15 +0000 (18:43 -0700)]
[gcov] Emit GCOV_TAG_OBJECT_SUMMARY/GCOV_TAG_PROGRAM_SUMMARY correctly and fix llvm-cov's decoding of runcount
gcov 9 (r264462) started to use GCOV_TAG_OBJECT_SUMMARY. Before,
GCOV_TAG_PROGRAM_SUMMARY was used.
libclang_rt.profile should emit just one tag according to the version.
Another bug introduced by rL194499 is that the wrong runcount field was
selected.
Fix the two bugs so that gcov can correctly decode "Runs:" from
libclang_rt.profile produced .gcda files, and llvm-cov gcov can
correctly decode "Runs:" from libgcov produced .gcda files.
Wang, Pengfei [Tue, 12 May 2020 03:43:20 +0000 (11:43 +0800)]
[x86/SLH][NFC] Add a test to produce a failed generation.
aartbik [Tue, 12 May 2020 01:22:59 +0000 (18:22 -0700)]
[mlir] [VectorOps] Replace zero-scalar + splat into direct zero vector constant
Summary:
The scalar zero + splat yields more intermediate code than the direct
dense zero constant, and ultimately is lowered to exactly the same
LLVM IR operations, so no point wasting the intermediate code.
Reviewers: nicolasvasilache, andydavis1, reidtatge
Reviewed By: nicolasvasilache
Subscribers: mehdi_amini, rriddle, jpienaar, shauheen, antiagainst, nicolasvasilache, arpith-jacob, mgester, lucyrfox, liufengdb, stephenneuendorffer, Joonsoo, grosul1, frgossen, Kayjukh, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D79758
Jason Molenda [Tue, 12 May 2020 03:01:54 +0000 (20:01 -0700)]
Quote error string from qLaunchSuccess
If the error message from qLaunchSucess included a gdb RSP
metacharacter, it could crash lldb. Apply the binary
escaping to the string before sending it to lldb; lldb
promiscuously applies the binary escaping protocol on
packets it receives.
Also fix a small bug in cstring_to_asciihex_string where
a high bit character (eg utf-8 chars) would not be
quoted correctly due to signed char fun.
Differential Revision: https://reviews.llvm.org/D79614
rdar://problem/
62873581
Eric Christopher [Tue, 12 May 2020 03:02:54 +0000 (20:02 -0700)]
Fix a release+noasserts werror for unused variable.
Eric Christopher [Tue, 12 May 2020 02:46:06 +0000 (19:46 -0700)]
Temporarily Revert "[lld-macho] Re-add dylink-lazy test" as it
appears to be still failing.
This reverts commit
723c46e645dbe23942c926d2cb800ce020df6b8b.
zoecarver [Tue, 12 May 2020 01:42:50 +0000 (18:42 -0700)]
[libcxx] shared_ptr changes from library fundamentals (P0414R2).
Implements P0414R2:
* Adds support for array types in std::shared_ptr.
* Adds reinterpret_pointer_cast for shared_ptr.
Differential Revision: https://reviews.llvm.org/D62259
Joel E. Denny [Mon, 11 May 2020 13:57:37 +0000 (09:57 -0400)]
[FileCheck] Make invalid prefix diagnostics more precise
This will prove especially helpful after D79276, which introduces
comment prefixes. Specifically, identifying whether there's a
uniqueness violation will be helpful as prefixes will be required to
be unique across both check prefixes and comment prefixes.
Also, remove a related comment about `cl::list` that no longer seems
relevant now that FileCheck is also a library.
Reviewed By: jhenderson, thopre
Differential Revision: https://reviews.llvm.org/D79375
Austin Kerbow [Tue, 12 May 2020 00:24:03 +0000 (17:24 -0700)]
[AMDGPU][GlobalISel] Revise handling of wide loads in RegBankSelect
When splitting loads in RegBankSelect G_EXTRACT_VECTOR_ELT were being added
which could not be selected. Since invoking the legalizer will generate
instructions that split and combine wide loads, we can remove the redundant
repair instructions which are added by RegBankSelect.
Differential Revision: https://reviews.llvm.org/D75547
Nico Weber [Tue, 12 May 2020 00:57:46 +0000 (20:57 -0400)]
[gn build] Use relative paths in generated lit.site.cfg.py files for llvm and clang.
This ports
a16ba6fea2e554f to the GN build.
No intended behavior change.
Kazu Hirata [Mon, 11 May 2020 21:04:10 +0000 (14:04 -0700)]
[Inlining] Make shouldBeDeferred static (NFC)
Summary:
This patch makes shouldBeDeferred static because it is called only
from shouldInline in the same .cpp file.
Reviewers: davidxl, mtrofin
Reviewed By: mtrofin
Subscribers: hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D79750
Eli Friedman [Wed, 6 May 2020 19:06:29 +0000 (12:06 -0700)]
[SelectionDAG] Don't promote the alignment of allocas beyond the stack alignment.
allocas in LLVM IR have a specified alignment. When that alignment is
specified, the alloca has at least that alignment at runtime.
If the specified type of the alloca has a higher preferred alignment,
SelectionDAG currently ignores that specified alignment, and increases
the alignment. It does this even if it would trigger stack realignment.
I don't think this makes sense, so this patch changes that.
I was looking into this for SVE in particular: for SVE, overaligning
vscale'ed types is extra expensive because it requires realigning the
stack multiple times, or using dynamic allocation. (This currently isn't
implemented.)
I updated the expected assembly for a couple tests; in particular, for
arg-copy-elide.ll, the optimization in question does not increase the
alignment the way SelectionDAG normally would. For the rest, I just
increased the specified alignment on the allocas to match what
SelectionDAG was inferring.
Differential Revision: https://reviews.llvm.org/D79532
Saiyedul Islam [Fri, 10 Apr 2020 07:55:11 +0000 (07:55 +0000)]
[AMDGPU] Reserving VGPR for future SGPR Spill
Summary: One VGPR register is allocated to handle a future spill of SGPR if "--amdgpu-reserve-vgpr-for-sgpr-spill" option is used
Reviewers: arsenm, rampitec, msearles, cdevadas
Reviewed By: arsenm
Subscribers: madhur13490, qcolombet, kerbowa, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, hiraditya, llvm-commits
Tags: #amdgpu, #llvm
Differential Revision: https://reviews.llvm.org/D70379
Eli Friedman [Sat, 2 May 2020 03:58:49 +0000 (20:58 -0700)]
[AArch64][SVE] Add patterns for VSELECT of immediates.
This covers forms involving "CPY (immediate, zeroing)".
This doesn't handle the case where the operands are reversed, and the
condition is freely invertible. Not sure how to handle that. Maybe a
DAGCombine.
Differential Revision: https://reviews.llvm.org/D79598
Rahul Joshi [Mon, 11 May 2020 23:53:16 +0000 (16:53 -0700)]
[MLIR] Fix several misc issues in in Toy tutorial
Summary:
- Fix comments in several places
- Eliminate extra ' in AST dump and adjust tests accordingly
Differential Revision: https://reviews.llvm.org/D78399
Austin Kerbow [Thu, 7 May 2020 21:56:37 +0000 (14:56 -0700)]
[AMDGPU] Allow spilling FP to memory
If there are no available lanes in a reserved VGPR, no free SGPR, and no unused CSR
VGPR when trying to save the FP it needs to be spilled to memory as a last
resort. This can be done in the prolog/epilog if we manually add the spill
and manage exec.
Differential Revision: https://reviews.llvm.org/D79610
Joel E. Denny [Mon, 11 May 2020 23:40:15 +0000 (19:40 -0400)]
Revert "[FileCheck] Make invalid prefix diagnostics more precise"
This reverts commit
a78e13745d4ee4a42e41ebbe698159f651515fc5 to try to
fix a bot:
http://lab.llvm.org:8011/builders/llvm-clang-x86_64-expensive-checks-win/builds/23489
Joel E. Denny [Mon, 11 May 2020 23:39:49 +0000 (19:39 -0400)]
Revert "[FileCheck] Support comment directives"
This reverts commit
9a9a5f9893c8db05cebc8818eb8485bff61f7c74 to try to
fix a bot:
http://lab.llvm.org:8011/builders/llvm-clang-x86_64-expensive-checks-win/builds/23489
Nico Weber [Mon, 11 May 2020 23:31:26 +0000 (19:31 -0400)]
[gn build] Make paths in generated llvm-lit relative.
This ports
d4638cba and
e613f0ee to the GN build.
Since paths in the generated lit.site.cfg.py files still contain
absolute paths in the GN build, this isn't very useful yet.
No intended behavior change.
Davide Italiano [Mon, 11 May 2020 23:21:26 +0000 (16:21 -0700)]
[GlobalISel] Remove debug locations when emitting G_FCONSTANT.
<rdar://problem/
62991543>
Nico Weber [Mon, 11 May 2020 23:21:31 +0000 (19:21 -0400)]
[gn build] Make config_map computation in llvm-lit more table-driven.
No behavior change.
Nico Weber [Mon, 11 May 2020 23:04:28 +0000 (19:04 -0400)]
llvm-lit.in: Use a raw string for LLVM_SOURCE_DIR
In case the path from cmake build dir contains a backslash
escape on Windows (which uses \ as path separator).
While here, consistently use one form of quotes in this file.
No intended behavior change.
Jonas Devlieghere [Mon, 11 May 2020 21:41:38 +0000 (14:41 -0700)]
[YAMLTraits] Add trait for char
Add a YAML trait for char.
Differential revision: https://reviews.llvm.org/D79745
Eric Christopher [Mon, 11 May 2020 22:50:22 +0000 (15:50 -0700)]
Fix auto -> auto * clang tidy.
Evgenii Stepanov [Fri, 8 May 2020 23:32:33 +0000 (16:32 -0700)]
[hwasan] Fix allocator alignment.
Summary:
Fix hwasan allocator not respecting the requested alignment when it is
higher than a page, but still within primary (i.e. [2048, 65536]).
Reviewers: pcc, hctim, cryptoad
Subscribers: #sanitizers, llvm-commits
Tags: #sanitizers
Differential Revision: https://reviews.llvm.org/D79656
Hanhan Wang [Mon, 11 May 2020 22:41:12 +0000 (15:41 -0700)]
[mlir][StandardToSPIRV] Add support for lowering index_cast to SPIR-V.
Differential Revision: https://reviews.llvm.org/D79644
stevewan [Mon, 11 May 2020 22:33:55 +0000 (18:33 -0400)]
Add vendor macro to "lld"
Summary:
Add the vendor macro to "lld" for extended version output support,
such that it's able to print additional version info. This is
consistent with the Clang and LLVM version printer, and the
additional version message can be provided via PACKAGE_VENDOR.
Reviewers: hubert.reinterpretcast, kbarton, cebowleratibm, rzurob, ruiu
Reviewed By: hubert.reinterpretcast
Subscribers: emaste, mgorny, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D79026
Eric Christopher [Mon, 11 May 2020 22:32:18 +0000 (15:32 -0700)]
Fix a few clang-tidy warnings about auto * and const auto.
Stanislav Mekhanoshin [Mon, 11 May 2020 19:09:16 +0000 (12:09 -0700)]
[AMDGPU] Fix promote alloca which is already vector
Just do not touch loads and stores which are already vector.
Previously pass was just unable to see these loads and stores
because these were hidden bitcasts.
Differential Revision: https://reviews.llvm.org/D79738
Nicolas Vasilache [Mon, 11 May 2020 21:38:20 +0000 (17:38 -0400)]
[mlir] Revisit std.subview handling of static information.
Summary:
The main objective of this revision is to change the way static information is represented, propagated and canonicalized in the SubViewOp.
In the current implementation the issue is that canonicalization may strictly lose information because static offsets are combined in irrecoverable ways into the result type, in order to fit the strided memref representation.
The core semantics of the op do not change but the parser and printer do: the op always requires `rank` offsets, sizes and strides. These quantities can now be either SSA values or static integer attributes.
The result type is automatically deduced from the static information and more powerful canonicalizations (as powerful as the representation with sentinel `?` values allows). Previously static information was inferred on a best-effort basis from looking at the source and destination type.
Relevant tests are rewritten to use the idiomatic `offset: x, strides : [...]`-form. Bugs are corrected along the way that were not trivially visible in flattened strided memref form.
It is an open question, and a longer discussion, whether a better result type representation would be a nicer alternative. For now, the subview op carries the required semantic.
Reviewers: ftynse, mravishankar, antiagainst, rriddle!, andydavis1, timshen, asaadaldien, stellaraccident
Reviewed By: mravishankar
Subscribers: aartbik, bondhugula, mehdi_amini, rriddle, jpienaar, shauheen, antiagainst, arpith-jacob, mgester, lucyrfox, liufengdb, stephenneuendorffer, Joonsoo, bader, grosul1, frgossen, Kayjukh, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D79662
Reid Tatge [Mon, 11 May 2020 18:59:14 +0000 (11:59 -0700)]
[mlir][Vector] NFC - Rename vector.strided_slice into vector.extract_strided_slice
Differential Revision: https://reviews.llvm.org/D79734
Simon Pilgrim [Sun, 10 May 2020 18:48:29 +0000 (19:48 +0100)]
RISCVAttributeParser.h - remove unnecessary ScopedPrinter.h include. NFC.
All uses of ScopedPrinter are in terms of ELFAttributeParser which are handled by ELFAttributeParser.h
Craig Topper [Mon, 11 May 2020 20:28:41 +0000 (13:28 -0700)]
[X86] Add inline assembly load hardening mitigation for Load Value Injection (LVI)
Added code to X86AsmParser::emitInstruction() to add an LFENCE after each instruction that may load, and emit a warning if it encounters an instruction that may be vulnerable, but cannot be automatically mitigated.
Differential Revision: https://reviews.llvm.org/D76158
Martin Storsjö [Mon, 11 May 2020 20:41:08 +0000 (23:41 +0300)]
[CMake] Fix building with -DBUILD_SHARED_LIBS=ON on mingw
Set the right target name in clang/examples/Attribute.
Add a missing dependency in the TableGen GlobalISel sublibrary.
Skip building the Bye pass plugin example on windows; plugins
that should have undefined symbols that are found in the host
process aren't supported on windows - this matches what was done
for a unit test in
bc8e44218810c0db6328b9809c959ceb7d43e3f5.