Martin Liska [Fri, 5 Nov 2021 14:39:53 +0000 (15:39 +0100)]
gcov-profile: Filter test only for some targets [PR102945]
PR gcov-profile/102945
gcc/testsuite/ChangeLog:
* gcc.dg/gcov-info-to-gcda.c: Filter supported targets.
Richard Biener [Fri, 5 Nov 2021 09:10:46 +0000 (10:10 +0100)]
Split vector loop analysis into main and epilogue analysis
As discussed this splits the analysis loop into two, first settling
on a vector mode used for the main loop and only then analyzing
the epilogue of that for possible vectorization. That makes it
easier to put in support for unrolled main loops.
On the way I've realized some cleanup opportunities, namely caching
n_stmts in vec_info_shared (it's computed by dataref analysis)
avoiding to pass that around and setting/clearing loop->aux
during analysis - try_vectorize_loop_1 will ultimatively set it
on those we vectorize.
This also gets rid of the previously introduced callback in
vect_analyze_loop_1 in favor of making that advance the mode iterator.
I'm now pushing VOIDmode explicitely into the vector_modes array
which makes the re-start on the epilogue side a bit more
straight-forward. Note that will now use auto-detection of the
vector mode in case the main loop used it and we want to try
LOOP_VINFO_EPIL_USING_PARTIAL_VECTORS_P and the first mode from
the target array if not. I've added a comment that says we may
want to make sure we don't try vectorizing the epilogue with a
bigger vector size than the main loop but the situation isn't
very likely to appear in practice I guess (and it was also present
before this change).
In principle this change should not change vectorization decisions
but the way we handled re-analyzing epilogues as main loops makes
me only 99% sure that it does.
2021-11-05 Richard Biener <rguenther@suse.de>
* tree-vectorizer.h (vec_info_shared::n_stmts): Add.
(LOOP_VINFO_N_STMTS): Likewise.
(vec_info_for_bb): Remove unused function.
* tree-vectorizer.c (vec_info_shared::vec_info_shared):
Initialize n_stmts member.
* tree-vect-loop.c: Remove INCLUDE_FUNCTIONAL.
(vect_create_loop_vinfo): Do not set loop->aux.
(vect_analyze_loop_2): Do not get n_stmts as argument,
instead use LOOP_VINFO_N_STMTS. Set LOOP_VINFO_VECTORIZABLE_P
here.
(vect_analyze_loop_1): Remove callback, get the mode iterator
and autodetected_vector_mode as argument, advancing the
iterator and initializing autodetected_vector_mode here.
(vect_analyze_loop): Split analysis loop into two, first
processing main loops only and then epilogues.
Martin Jambor [Fri, 5 Nov 2021 13:04:42 +0000 (14:04 +0100)]
ipa: Do not require RECORD_TYPE for ancestor jump functions
The check this patch removes has remained from times when ancestor
jump functions have been only used for devirtualization and also
contained BINFOs. It is not necessary now and should have been
removed long time ago.
gcc/ChangeLog:
2021-11-04 Martin Jambor <mjambor@suse.cz>
* ipa-prop.c (compute_complex_assign_jump_func): Remove
unnecessary check for RECORD_TYPE.
Jonathan Wakely [Fri, 5 Nov 2021 11:25:27 +0000 (11:25 +0000)]
libstdc++: Add xfail to pretty printer tests that fail in C++20
For some reason the type printer for std::string doesn't work in C++20
mode, so std::basic_string<char, char_traits<char>, allocator<char> is
printed out in full rather than being shown as std::string. It's
probably related to the fact that the extern template declarations are
disabled for C++20, but I don't know why that affects GDB.
For now I'm just marking the relevant tests as XFAIL. That requires
adding support for target selectors to individual GDB directives such as
note-test and whatis-regexp-test.
libstdc++-v3/ChangeLog:
* testsuite/lib/gdb-test.exp: Add target selector support to the
dg-final directives.
* testsuite/libstdc++-prettyprinters/80276.cc: Add xfail for
C++20.
* testsuite/libstdc++-prettyprinters/libfundts.cc: Likewise.
* testsuite/libstdc++-prettyprinters/prettyprinters.exp: Tweak
comment.
Gerald Pfeifer [Fri, 5 Nov 2021 11:56:07 +0000 (12:56 +0100)]
include: Allow for our md5.h to defer to the system header
This came up in the context of libsanitizer, where platform-specific
support for FreeBSD relies on aspects provided by FreeBSD's own md5.h.
Address this by allowing GCC's md5.h to pull in the system header
instead, controlled by a new macro USE_SYSTEM_MD5.
2021-11-05 Gerald Pfeifer <gerald@pfeifer.com>
Jakub Jelinek <jakub@redhat.com>
include/
* md5.h (USE_SYSTEM_MD5): Introduce.
Gerald Pfeifer [Sun, 24 Oct 2021 09:48:29 +0000 (11:48 +0200)]
doc: No longer generate old.html
Commit
431d26e1dd18c1146d3d4dcd3b45a3b04f7f7d59 removed
doc/install-old.texi, alas we still tried to generate the
associated web page old.html - which then turned out empty.
Simplify remove this from the list of pages to be generated.
gcc:
* doc/install.texi2html: Do not generate old.html any longer.
Martin Liska [Mon, 1 Nov 2021 15:28:34 +0000 (16:28 +0100)]
Reset when -gtoggle is used in gcc_options.
PR debug/102955
gcc/ChangeLog:
* opts.c (finish_options): Reset flag_gtoggle when it is used.
gcc/testsuite/ChangeLog:
* g++.dg/pr102955.C: New test.
Jakub Jelinek [Fri, 5 Nov 2021 09:20:10 +0000 (10:20 +0100)]
dwarf2out: Fix up CONST_WIDE_INT handling once more [PR103046]
My last change to CONST_WIDE_INT handling in add_const_value_attribute broke
handling of CONST_WIDE_INT constants like ((__uint128_t) 1 << 120).
wi::min_precision (w1, UNSIGNED) in that case 121, but wide_int::from
creates a wide_int that has 0 and 0xff00000000000000ULL in its elts and
precision 121. When we output that, we output both elements and thus emit
0, 0xff00000000000000 instead of the desired 0, 0x0100000000000000.
IMHO we should actually pass machine_mode to add_const_value_attribute from
callers, so that we know exactly what precision we want. Because
hypothetically, if say mode is OImode and the CONST_WIDE_INT value fits into
128 bits or 192 bits, we'd emit just those 128 or 192 bits but debug info
users would expect 256 bits.
On
typedef unsigned __int128 U;
int
main ()
{
U a = (U) 1 << 120;
U b = 0xffffffffffffffffULL;
U c = ((U) 0xffffffff00000000ULL) << 64;
return 0;
}
vanilla gcc incorrectly emits 0, 0xff00000000000000 for a,
0xffffffffffffffff alone (DW_FORM_data8) for b and 0, 0xffffffff00000000
for c. gcc with the previously posted PR103046 patch emits
0, 0x0100000000000000 for a, 0xffffffffffffffff alone for b and
0, 0xffffffff00000000 for c. And with this patch we emit
0, 0x0100000000000000 for a, 0xffffffffffffffff, 0 for b and
0, 0xffffffff00000000 for c.
So, the patch below certainly causes larger debug info (well, 128-bit
integers are pretty rare), but in this case the question is if it isn't
more correct, as debug info consumers generally will not know if they
should sign or zero extend the value in DW_AT_const_value.
The previous code assumes they will always zero extend it...
2021-11-05 Jakub Jelinek <jakub@redhat.com>
PR debug/103046
* dwarf2out.c (add_const_value_attribute): Add MODE argument, use it
in CONST_WIDE_INT handling. Adjust recursive calls.
(add_location_or_const_value_attribute): Pass DECL_MODE (decl) to
new add_const_value_attribute argument.
(tree_add_const_value_attribute): Pass TYPE_MODE (type) to new
add_const_value_attribute argument.
Rasmus Villemoes [Tue, 2 Nov 2021 10:43:57 +0000 (11:43 +0100)]
gcc: vx-common.h: fix test for VxWorks7
The macro TARGET_VXWORKS7 is always defined (see vxworks-dummy.h).
Thus we need to test its value, not its definedness.
Fixes
aca124df (define NO_DOT_IN_LABEL only in vxworks6).
gcc/ChangeLog:
* config/vx-common.h: Test value of TARGET_VXWORKS7 rather
than definedness.
Richard Biener [Wed, 27 Oct 2021 11:14:41 +0000 (13:14 +0200)]
First refactor of vect_analyze_loop
This refactors the main loop analysis part in vect_analyze_loop,
re-purposing the existing vect_reanalyze_as_main_loop for this
to reduce code duplication. Failure flow is a bit tricky since
we want to extract info from the analyzed loop but I wanted to
share the destruction part. Thus I add some std::function and
lambda to funnel post-analysis for the case we want that
(when analyzing from the main iteration but not when re-analyzing
an epilogue as main).
In addition I split vect_analyze_loop_form into analysis and
vinfo creation so we can do the analysis only once, simplifying
the new vect_analyze_loop_1.
As discussed we probably want to change the loop over vector
modes to first only analyze things as the main loop, picking
the best (or simd VF) mode for the main loop and then analyze
for a vectorized epilogue. The unroll would then integrate
with the main loop vectorization. I think that currently
we may fail to analyze the epilogue with the same mode as
the main loop when using partial vectors since we increment
mode_i before doing that.
2021-11-04 Richard Biener <rguenther@suse.de>
* tree-vectorizer.h (struct vect_loop_form_info): New.
(vect_analyze_loop_form): Adjust.
(vect_create_loop_vinfo): New.
* tree-parloops.c (gather_scalar_reductions): Adjust for
vect_analyze_loop_form API change.
* tree-vect-loop.c: Include <functional>.
(vect_analyze_loop_form_1): Rename to vect_analyze_loop_form,
take struct vect_loop_form_info as output parameter and adjust.
(vect_analyze_loop_form): Rename to vect_create_loop_vinfo and
split out call to the original vect_analyze_loop_form_1.
(vect_reanalyze_as_main_loop): Rename to...
(vect_analyze_loop_1): ... this, factor out the call to
vect_analyze_loop_form and generalize to be able to use it twice ...
(vect_analyze_loop): ... here. Perform vect_analyze_loop_form
once only and here.
Xionghu Luo [Thu, 4 Nov 2021 01:23:03 +0000 (20:23 -0500)]
rs6000: Fix incorrect fusion constraint [PR102991]
gcc/ChangeLog:
2021-11-05 Xionghu Luo <luoxhu@linux.ibm.com>
PR target/102991
* config/rs6000/fusion.md: Regenerate.
* config/rs6000/genfusion.pl: Fix incorrect clobber constraint.
GCC Administrator [Fri, 5 Nov 2021 00:16:36 +0000 (00:16 +0000)]
Daily bump.
Jonathan Wakely [Thu, 4 Nov 2021 22:50:02 +0000 (22:50 +0000)]
libstdc++: Fix pretty printing of std::unique_ptr [PR103086]
Since std::tuple started using [[no_unique_address]] the tuple<T*, D>
member of std::unique_ptr<T, D> has two _M_head_impl subobjects, in
different base classes. That means this printer code is ambiguous:
tuple_head_type = tuple_impl_type.fields()[1].type # _Head_base
head_field = tuple_head_type.fields()[0]
if head_field.name == '_M_head_impl':
self.pointer = tuple_member['_M_head_impl']
In older versions of GDB it happened to work by chance, because GDB
returned the last _M_head_impl member and std::tuple's base classes are
stored in reverse order, so the last one was the T* element of the
tuple. Since GDB 11 it returns the first _M_head_impl, which is the
deleter element.
The fix is for the printer to stop using an ambiguous field name and
cast the tuple to the correct base class before accessing the
_M_head_impl member.
Instead of fixing this in both UniquePointerPrinter and StdPathPrinter a
new unique_ptr_get function is defined to do it correctly. That is
defined in terms of new tuple_get and _tuple_impl_get functions.
It would be possible to reuse _tuple_impl_get to access each element in
StdTuplePrinter._iterator.__next__, but that already does the correct
casting, and wouldn't be much simpler anyway.
libstdc++-v3/ChangeLog:
PR libstdc++/103086
* python/libstdcxx/v6/printers.py (_tuple_impl_get): New helper
for accessing the tuple element stored in a _Tuple_impl node.
(tuple_get): New function for accessing a tuple element.
(unique_ptr_get): New function for accessing a unique_ptr.
(UniquePointerPrinter, StdPathPrinter): Use unique_ptr_get.
* python/libstdcxx/v6/xmethods.py (UniquePtrGetWorker): Cast
tuple to its base class before accessing _M_head_impl.
Jonathan Wakely [Wed, 29 Sep 2021 20:18:42 +0000 (21:18 +0100)]
libstdc++: Deprecate std::unexpected and handler functions
These functions have been deprecated since C++11, and were removed in
C++17. The proposal P0323 wants to reuse the name std::unexpected for a
class template, so we will need to stop defining the current function
for C++23 anyway.
This marks them as deprecated for C++11 and up, to warn users they won't
continue to be available. It disables them for C++17 and up, unless the
_GLIBCXX_USE_DEPRECATED macro is defined.
The <unwind-cxx.h> header uses std::unexpected_handler in the public
API, but since that type is the same as std::terminate_handler we can
just use that instead, to avoid warnings about it being deprecated.
libstdc++-v3/ChangeLog:
* doc/xml/manual/evolution.xml: Document deprecations.
* doc/html/*: Regenerate.
* libsupc++/exception (unexpected_handler, unexpected)
(get_unexpected, set_unexpected): Add deprecated attribute.
Do not define without _GLIBCXX_USE_DEPRECATED for C++17 and up.
* libsupc++/eh_personality.cc (PERSONALITY_FUNCTION): Disable
deprecated warnings.
* libsupc++/eh_ptr.cc (std::rethrow_exception): Likewise.
* libsupc++/eh_terminate.cc: Likewise.
* libsupc++/eh_throw.cc (__cxa_init_primary_exception):
Likewise.
* libsupc++/unwind-cxx.h (struct __cxa_exception): Use
terminate_handler instead of unexpected_handler.
(struct __cxa_dependent_exception): Likewise.
(__unexpected): Likewise.
* testsuite/18_support/headers/exception/synopsis.cc: Add
dg-warning for deprecated warning.
* testsuite/18_support/exception_ptr/60612-unexpected.cc:
Disable deprecated warnings.
* testsuite/18_support/set_unexpected.cc: Likewise.
* testsuite/18_support/unexpected_handler.cc: Likewise.
gcc/testsuite/ChangeLog:
* g++.dg/cpp0x/lambda/lambda-eh2.C: Add dg-warning for new
deprecation warnings.
* g++.dg/cpp0x/noexcept06.C: Likewise.
* g++.dg/cpp0x/noexcept07.C: Likewise.
* g++.dg/eh/forced3.C: Likewise.
* g++.dg/eh/unexpected1.C: Likewise.
* g++.old-deja/g++.eh/spec1.C: Likewise.
* g++.old-deja/g++.eh/spec2.C: Likewise.
* g++.old-deja/g++.eh/spec3.C: Likewise.
* g++.old-deja/g++.eh/spec4.C: Likewise.
* g++.old-deja/g++.mike/eh33.C: Likewise.
* g++.old-deja/g++.mike/eh34.C: Likewise.
* g++.old-deja/g++.mike/eh50.C: Likewise.
* g++.old-deja/g++.mike/eh51.C: Likewise.
Andreas Krebbel [Thu, 4 Nov 2021 18:37:19 +0000 (19:37 +0100)]
IBM Z: Define STACK_CHECK_MOVING_SP
With -fstack-check the stack probes emitted access memory below the
stack pointer.
gcc/ChangeLog:
* config/s390/s390.h (STACK_CHECK_MOVING_SP): New macro
definition.
Jonathan Wakely [Thu, 4 Nov 2021 11:11:58 +0000 (11:11 +0000)]
libstdc++: Consolidate duplicate metaprogramming utilities
Currently std::variant uses __index_of<T, Types...> to find the first
occurence of a type in a pack, and __exactly_once<T, Types...> to check
that there is no other occurrence.
We can reuse the __find_uniq_type_in_pack<T, Types...>() function for
both tasks, and remove the recursive templates used to implement
__index_of and __exactly_once.
libstdc++-v3/ChangeLog:
* include/bits/utility.h (__find_uniq_type_in_pack): Move
definition to here, ...
* include/std/tuple (__find_uniq_type_in_pack): ... from here.
* include/std/variant (__detail__variant::__index_of): Remove.
(__detail::__variant::__exactly_once): Define using
__find_uniq_type_in_pack instead of __index_of.
(get<T>, get_if<T>, variant::__index_of): Likewise.
Jonathan Wakely [Thu, 4 Nov 2021 09:31:50 +0000 (09:31 +0000)]
libstdc++: Optimize std::tuple_element and std::tuple_size_v
This reduces the number of class template instantiations needed for code
using tuples, by reusing _Nth_type in tuple_element and specializing
tuple_size_v for tuple, pair and array (and const-qualified versions of
them).
Also define the _Nth_type primary template as a complete type (but with
no nested 'type' member). This avoids "invalid use of incomplete type"
errors for out-of-range specializations of tuple_element. Those errors
would probably be confusing and unhelpful for users. We already have
a user-friendly static assert in tuple_element itself.
Also ensure that tuple_size_v is available whenever tuple_size is (as
proposed by LWG 3387). We already do that for tuple_element_t.
libstdc++-v3/ChangeLog:
* include/bits/stl_pair.h (tuple_size_v): Define partial
specializations for std::pair.
* include/bits/utility.h (_Nth_type): Move definition here
and define primary template.
(tuple_size_v): Move definition here.
* include/std/array (tuple_size_v): Define partial
specializations for std::array.
* include/std/tuple (tuple_size_v): Move primary template to
<bits/utility.h>. Define partial specializations for
std::tuple.
(tuple_element): Change definition to use _Nth_type.
* include/std/variant (_Nth_type): Move to <bits/utility.h>.
(variant_alternative, variant): Adjust qualification of
_Nth_type.
* testsuite/20_util/tuple/element_access/get_neg.cc: Prune
additional errors from _Nth_type.
Tamar Christina [Thu, 4 Nov 2021 17:36:08 +0000 (17:36 +0000)]
AArch64: Lower intrinsics shift to GIMPLE when possible.
This lowers shifts to GIMPLE when the C interpretations of the shift operations
matches that of AArch64.
In C shifting right by BITSIZE is undefined, but the behavior is defined in
AArch64. Additionally negative shifts lefts are undefined for the register
variant of the instruction (SSHL, USHL) as being right shifts.
Since we have a right shift by immediate I rewrite those cases into right shifts
So:
int64x1_t foo3 (int64x1_t a)
{
return vshl_s64 (a, vdup_n_s64(-6));
}
produces:
foo3:
sshr d0, d0, 6
ret
instead of:
foo3:
mov x0, -6
fmov d1, x0
sshl d0, d0, d1
ret
This behavior isn't specifically mentioned for a left shift by immediate, but I
believe that only the case because we do have a right shift by immediate but not
a right shift by register. As such I do the same for left shift by immediate.
gcc/ChangeLog:
* config/aarch64/aarch64-builtins.c
(aarch64_general_gimple_fold_builtin): Add ashl, sshl, ushl, ashr,
ashr_simd, lshr, lshr_simd.
* config/aarch64/aarch64-simd-builtins.def (lshr): Use USHIFTIMM.
* config/aarch64/arm_neon.h (vshr_n_u8, vshr_n_u16, vshr_n_u32,
vshrq_n_u8, vshrq_n_u16, vshrq_n_u32, vshrq_n_u64): Fix type hack.
gcc/testsuite/ChangeLog:
* gcc.target/aarch64/advsimd-intrinsics/vshl-opt-1.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vshl-opt-2.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vshl-opt-3.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vshl-opt-4.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vshl-opt-5.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vshl-opt-6.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vshl-opt-7.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vshl-opt-8.c: New test.
* gcc.target/aarch64/signbit-2.c: New test.
Tamar Christina [Thu, 4 Nov 2021 17:32:09 +0000 (17:32 +0000)]
middle-end: convert negate + right shift into compare greater.
This turns an inversion of the sign bit + arithmetic right shift into a
comparison with 0.
i.e.
void fun1(int32_t *x, int n)
{
for (int i = 0; i < (n & -16); i++)
x[i] = (-x[i]) >> 31;
}
now generates:
.L3:
ldr q0, [x0]
cmgt v0.4s, v0.4s, #0
str q0, [x0], 16
cmp x0, x1
bne .L3
instead of:
.L3:
ldr q0, [x0]
neg v0.4s, v0.4s
sshr v0.4s, v0.4s, 31
str q0, [x0], 16
cmp x0, x1
bne .L3
gcc/ChangeLog:
* match.pd: New negate+shift pattern.
gcc/testsuite/ChangeLog:
* gcc.dg/signbit-2.c: New test.
* gcc.dg/signbit-3.c: New test.
* gcc.dg/signbit-4.c: New test.
* gcc.dg/signbit-5.c: New test.
* gcc.dg/signbit-6.c: New test.
* gcc.target/aarch64/signbit-1.c: New test.
Andrew MacLeod [Thu, 4 Nov 2021 15:07:28 +0000 (11:07 -0400)]
Treat undefined operands as varying in GORI.
If the LHS is UNDEFINED simply stop calculating. Treat op1 and op2
as VARYING if they are UNDEFINED.
PR tree-optimization/103079
gcc/
* gimple-range-gori.cc (gimple_range_calc_op1): Treat undefined as
varying.
(gimple_range_calc_op2): Ditto.
gcc/testsuite/
* gcc.dg/pr103079.c: New.
Martin Jambor [Thu, 4 Nov 2021 17:01:20 +0000 (18:01 +0100)]
ipa-sra: Improve debug info for removed parameters (PR 93385)
In spring I added code eliminating any statements using parameters
removed by IPA passes (to fix PR 93385). That patch fixed issues such
as divisions by zero that such code could perform but it only reset
all affected debug bind statements, this one updates them with
expressions which can allow the debugger to print the removed value -
see the added test-case for an example.
Even though I originally did not want to create DEBUG_EXPR_DECLs for
intermediate values, I ended up doing so, because otherwise the code
started creating statements like
# DEBUG __aD.198693 => &MEM[(const struct _Alloc_nodeD.171110 *)D#195]._M_tD.184726->_M_implD.171154
which not only is a bit scary but also gimple-fold ICEs on
it. Therefore I decided they are probably quite necessary.
The patch simply notes each removed SSA name present in a debug
statement and then works from it backwards, looking if it can
reconstruct the expression it represents (which can fail if a
non-degenerate PHI node is in the way). If it can, it populates two
hash maps with those expressions so that 1) removed assignments are
replaced with a debug bind defining a new intermediate debug_decl_expr
and 2) existing debug binds that refer to SSA names that are bing
removed now refer to corresponding debug_decl_exprs.
If a removed parameter is passed to another function, the debugging
information still cannot describe its value there - see the xfailed
test in the testcase. I sort of know what needs to be done but that
needs a little bit more of IPA infrastructure on top of this patch and
so I would like to get this patch reviewed first.
Bootstrapped and tested on x86_64-linux, i686-linux and (long time
ago) on aarch64-linux. Also LTO-bootstrapped and on x86_64-linux.
Perhaps it is good to go to trunk?
Thanks,
Martin
gcc/ChangeLog:
2021-03-29 Martin Jambor <mjambor@suse.cz>
PR ipa/93385
* ipa-param-manipulation.h (class ipa_param_body_adjustments): New
members remap_with_debug_expressions, m_dead_ssa_debug_equiv,
m_dead_stmt_debug_equiv and prepare_debug_expressions. Added
parameter to mark_dead_statements.
* ipa-param-manipulation.c: Include tree-phinodes.h and cfgexpand.h.
(ipa_param_body_adjustments::mark_dead_statements): New parameter
debugstack, push into it all SSA names used in debug statements,
produce m_dead_ssa_debug_equiv mapping for the removed param.
(replace_with_mapped_expr): New function.
(ipa_param_body_adjustments::remap_with_debug_expressions): Likewise.
(ipa_param_body_adjustments::prepare_debug_expressions): Likewise.
(ipa_param_body_adjustments::common_initialization): Gather and
procecc SSA which will be removed but are in debug statements. Simplify.
(ipa_param_body_adjustments::ipa_param_body_adjustments): Initialize
new members.
* tree-inline.c (remap_gimple_stmt): Create a debug bind when possible
when avoiding a copy of an unnecessary statement. Remap removed SSA
names in existing debug statements.
(tree_function_versioning): Do not create DEBUG_EXPR_DECL for removed
parameters if we have already done so.
gcc/testsuite/ChangeLog:
2021-03-29 Martin Jambor <mjambor@suse.cz>
PR ipa/93385
* gcc.dg/guality/ipa-sra-1.c: New test.
Sandra Loosemore [Mon, 1 Nov 2021 20:45:19 +0000 (13:45 -0700)]
Fortran manual: Remove old docs for never-implemented extensions.
2021-11-01 Sandra Loosemore <sandra@codesourcery.com>
gcc/fortran/
* gfortran.texi (Projects): Add bullet for helping with
incomplete standards compliance.
(Proposed Extensions): Delete section.
Sandra Loosemore [Mon, 1 Nov 2021 20:19:35 +0000 (13:19 -0700)]
Fortran manual: Update miscellaneous references to old standard versions.
2021-11-01 Sandra Loosemore <sandra@codesourcery.com>
gcc/fortran/
* intrinsic.texi (Introduction to Intrinsics): Genericize
references to standard versions.
* invoke.texi (-fall-intrinsics): Likewise.
(-fmax-identifier-length=): Likewise.
Sandra Loosemore [Mon, 1 Nov 2021 17:01:16 +0000 (10:01 -0700)]
Fortran manual: Update section on Interoperability with C
2021-11-01 Sandra Loosemore <sandra@codesourcery.com>
gcc/fortran/
* gfortran.texi (Interoperability with C): Copy-editing. Add
more index entries.
(Intrinsic Types): Likewise.
(Derived Types and struct): Likewise.
(Interoperable Global Variables): Likewise.
(Interoperable Subroutines and Functions): Likewise.
(Working with C Pointers): Likewise.
(Further Interoperability of Fortran with C): Likewise. Rewrite
to reflect that this is now fully supported by gfortran.
Sandra Loosemore [Fri, 29 Oct 2021 22:08:47 +0000 (15:08 -0700)]
Fortran manual: Revise introductory chapter.
Fix various bit-rot in the discussion of standards conformance, remove
material that is only of historical interest, copy-editing. Also move
discussion of preprocessing out of the introductory chapter.
2021-11-01 Sandra Loosemore <sandra@codesourcery.com>
gcc/fortran/
* gfortran.texi (About GNU Fortran): Consolidate material
formerly in other sections. Copy-editing.
(Preprocessing and conditional compilation): Delete, moving
most material to invoke.texi.
(GNU Fortran and G77): Delete.
(Project Status): Delete.
(Standards): Update.
(Fortran 95 status): Mention conditional compilation here.
(Fortran 2003 status): Rewrite to mention the 1 missing feature
instead of all the ones implemented.
(Fortran 2008 status): Similarly for the 2 missing features.
(Fortran 2018 status): Rewrite to reflect completion of TS29113
feature support.
* invoke.texi (Preprocessing Options): Move material formerly
in introductory chapter here.
Sandra Loosemore [Sat, 30 Oct 2021 00:16:40 +0000 (17:16 -0700)]
Fortran manual: Combine standard conformance docs in one place.
Discussion of conformance with various revisions of the
Fortran standard was split between two separate parts of the
manual. This patch moves it all to the introductory chapter.
2021-11-01 Sandra Loosemore <sandra@codesourcery.com>
gcc/fortran/
* gfortran.texi (Standards): Move discussion of specific
standard versions here....
(Fortran standards status): ...from here, and delete this node.
Jan Hubicka [Thu, 4 Nov 2021 16:07:44 +0000 (17:07 +0100)]
Workaround ICE in gimple_call_static_chain_flags
gcc/ChangeLog:
2021-11-04 Jan Hubicka <hubicka@ucw.cz>
PR ipa/103058
* gimple.c (gimple_call_static_chain_flags): Handle case when
nested function does not bind locally.
Jason Merrill [Sat, 23 Oct 2021 09:45:02 +0000 (05:45 -0400)]
c++: use range-for more
gcc/cp/ChangeLog:
* call.c (build_array_conv): Use range-for.
(build_complex_conv): Likewise.
* constexpr.c (clear_no_implicit_zero)
(reduced_constant_expression_p): Likewise.
* decl.c (cp_complete_array_type): Likewise.
* decl2.c (mark_vtable_entries): Likewise.
* pt.c (iterative_hash_template_arg):
(invalid_tparm_referent_p, unify)
(type_dependent_expression_p): Likewise.
* typeck.c (build_ptrmemfunc_access_expr): Likewise.
Jonathan Wright [Thu, 7 Oct 2021 15:08:33 +0000 (16:08 +0100)]
aarch64: Pass and return Neon vector-tuple types without a parallel
Neon vector-tuple types can be passed in registers on function call
and return - there is no need to generate a parallel rtx. This patch
adds cases to detect vector-tuple modes and generates an appropriate
register rtx.
This change greatly improves code generated when passing Neon vector-
tuple types between functions; many new test cases are added to
defend these improvements.
gcc/ChangeLog:
2021-10-07 Jonathan Wright <jonathan.wright@arm.com>
* config/aarch64/aarch64.c (aarch64_function_value): Generate
a register rtx for Neon vector-tuple modes.
(aarch64_layout_arg): Likewise.
gcc/testsuite/ChangeLog:
* gcc.target/aarch64/vector_structure_intrinsics.c: New code
generation tests.
Jonathan Wright [Thu, 14 Oct 2021 12:49:02 +0000 (13:49 +0100)]
gcc/lower_subreg.c: Prevent decomposition if modes are not tieable
Preventing decomposition if modes are not tieable is necessary to
stop AArch64 partial Neon structure modes being treated as packed in
registers.
This is a necessary prerequisite for a future AArch64 PCS change to
maintain good code generation.
gcc/ChangeLog:
2021-10-14 Jonathan Wright <jonathan.wright@arm.com>
* lower-subreg.c (simple_move): Prevent decomposition if
modes are not tieable.
Jonathan Wright [Mon, 9 Aug 2021 14:26:48 +0000 (15:26 +0100)]
aarch64: Add machine modes for Neon vector-tuple types
Until now, GCC has used large integer machine modes (OI, CI and XI)
to model Neon vector-tuple types. This is suboptimal for many
reasons, the most notable are:
1) Large integer modes are opaque and modifying one vector in the
tuple requires a lot of inefficient set/get gymnastics. The
result is a lot of superfluous move instructions.
2) Large integer modes do not map well to types that are tuples of
64-bit vectors - we need additional zero-padding which again
results in superfluous move instructions.
This patch adds new machine modes that better model the C-level Neon
vector-tuple types. The approach is somewhat similar to that already
used for SVE vector-tuple types.
All of the AArch64 backend patterns and builtins that manipulate Neon
vector tuples are updated to use the new machine modes. This has the
effect of significantly reducing the amount of boiler-plate code in
the arm_neon.h header.
While this patch increases the quality of code generated in many
instances, there is still room for significant improvement - which
will be attempted in subsequent patches.
gcc/ChangeLog:
2021-08-09 Jonathan Wright <jonathan.wright@arm.com>
Richard Sandiford <richard.sandiford@arm.com>
* config/aarch64/aarch64-builtins.c (v2x8qi_UP): Define.
(v2x4hi_UP): Likewise.
(v2x4hf_UP): Likewise.
(v2x4bf_UP): Likewise.
(v2x2si_UP): Likewise.
(v2x2sf_UP): Likewise.
(v2x1di_UP): Likewise.
(v2x1df_UP): Likewise.
(v2x16qi_UP): Likewise.
(v2x8hi_UP): Likewise.
(v2x8hf_UP): Likewise.
(v2x8bf_UP): Likewise.
(v2x4si_UP): Likewise.
(v2x4sf_UP): Likewise.
(v2x2di_UP): Likewise.
(v2x2df_UP): Likewise.
(v3x8qi_UP): Likewise.
(v3x4hi_UP): Likewise.
(v3x4hf_UP): Likewise.
(v3x4bf_UP): Likewise.
(v3x2si_UP): Likewise.
(v3x2sf_UP): Likewise.
(v3x1di_UP): Likewise.
(v3x1df_UP): Likewise.
(v3x16qi_UP): Likewise.
(v3x8hi_UP): Likewise.
(v3x8hf_UP): Likewise.
(v3x8bf_UP): Likewise.
(v3x4si_UP): Likewise.
(v3x4sf_UP): Likewise.
(v3x2di_UP): Likewise.
(v3x2df_UP): Likewise.
(v4x8qi_UP): Likewise.
(v4x4hi_UP): Likewise.
(v4x4hf_UP): Likewise.
(v4x4bf_UP): Likewise.
(v4x2si_UP): Likewise.
(v4x2sf_UP): Likewise.
(v4x1di_UP): Likewise.
(v4x1df_UP): Likewise.
(v4x16qi_UP): Likewise.
(v4x8hi_UP): Likewise.
(v4x8hf_UP): Likewise.
(v4x8bf_UP): Likewise.
(v4x4si_UP): Likewise.
(v4x4sf_UP): Likewise.
(v4x2di_UP): Likewise.
(v4x2df_UP): Likewise.
(TYPES_GETREGP): Delete.
(TYPES_SETREGP): Likewise.
(TYPES_LOADSTRUCT_U): Define.
(TYPES_LOADSTRUCT_P): Likewise.
(TYPES_LOADSTRUCT_LANE_U): Likewise.
(TYPES_LOADSTRUCT_LANE_P): Likewise.
(TYPES_STORE1P): Move for consistency.
(TYPES_STORESTRUCT_U): Define.
(TYPES_STORESTRUCT_P): Likewise.
(TYPES_STORESTRUCT_LANE_U): Likewise.
(TYPES_STORESTRUCT_LANE_P): Likewise.
(aarch64_simd_tuple_types): Define.
(aarch64_lookup_simd_builtin_type): Handle tuple type lookup.
(aarch64_init_simd_builtin_functions): Update frontend lookup
for builtin functions after handling arm_neon.h pragma.
(register_tuple_type): Manually set modes of single-integer
tuple types. Record tuple types.
* config/aarch64/aarch64-modes.def
(ADV_SIMD_D_REG_STRUCT_MODES): Define D-register tuple modes.
(ADV_SIMD_Q_REG_STRUCT_MODES): Define Q-register tuple modes.
(SVE_MODES): Give single-vector modes priority over vector-
tuple modes.
(VECTOR_MODES_WITH_PREFIX): Set partial-vector mode order to
be after all single-vector modes.
* config/aarch64/aarch64-simd-builtins.def: Update builtin
generator macros to reflect modifications to the backend
patterns.
* config/aarch64/aarch64-simd.md (aarch64_simd_ld2<mode>):
Use vector-tuple mode iterator and rename to...
(aarch64_simd_ld2<vstruct_elt>): This.
(aarch64_simd_ld2r<mode>): Use vector-tuple mode iterator and
rename to...
(aarch64_simd_ld2r<vstruct_elt>): This.
(aarch64_vec_load_lanesoi_lane<mode>): Use vector-tuple mode
iterator and rename to...
(aarch64_vec_load_lanes<mode>_lane<vstruct_elt>): This.
(vec_load_lanesoi<mode>): Use vector-tuple mode iterator and
rename to...
(vec_load_lanes<mode><vstruct_elt>): This.
(aarch64_simd_st2<mode>): Use vector-tuple mode iterator and
rename to...
(aarch64_simd_st2<vstruct_elt>): This.
(aarch64_vec_store_lanesoi_lane<mode>): Use vector-tuple mode
iterator and rename to...
(aarch64_vec_store_lanes<mode>_lane<vstruct_elt>): This.
(vec_store_lanesoi<mode>): Use vector-tuple mode iterator and
rename to...
(vec_store_lanes<mode><vstruct_elt>): This.
(aarch64_simd_ld3<mode>): Use vector-tuple mode iterator and
rename to...
(aarch64_simd_ld3<vstruct_elt>): This.
(aarch64_simd_ld3r<mode>): Use vector-tuple mode iterator and
rename to...
(aarch64_simd_ld3r<vstruct_elt>): This.
(aarch64_vec_load_lanesci_lane<mode>): Use vector-tuple mode
iterator and rename to...
(vec_load_lanesci<mode>): This.
(aarch64_simd_st3<mode>): Use vector-tuple mode iterator and
rename to...
(aarch64_simd_st3<vstruct_elt>): This.
(aarch64_vec_store_lanesci_lane<mode>): Use vector-tuple mode
iterator and rename to...
(vec_store_lanesci<mode>): This.
(aarch64_simd_ld4<mode>): Use vector-tuple mode iterator and
rename to...
(aarch64_simd_ld4<vstruct_elt>): This.
(aarch64_simd_ld4r<mode>): Use vector-tuple mode iterator and
rename to...
(aarch64_simd_ld4r<vstruct_elt>): This.
(aarch64_vec_load_lanesxi_lane<mode>): Use vector-tuple mode
iterator and rename to...
(vec_load_lanesxi<mode>): This.
(aarch64_simd_st4<mode>): Use vector-tuple mode iterator and
rename to...
(aarch64_simd_st4<vstruct_elt>): This.
(aarch64_vec_store_lanesxi_lane<mode>): Use vector-tuple mode
iterator and rename to...
(vec_store_lanesxi<mode>): This.
(mov<mode>): Define for Neon vector-tuple modes.
(aarch64_ld1x3<VALLDIF:mode>): Use vector-tuple mode iterator
and rename to...
(aarch64_ld1x3<vstruct_elt>): This.
(aarch64_ld1_x3_<mode>): Use vector-tuple mode iterator and
rename to...
(aarch64_ld1_x3_<vstruct_elt>): This.
(aarch64_ld1x4<VALLDIF:mode>): Use vector-tuple mode iterator
and rename to...
(aarch64_ld1x4<vstruct_elt>): This.
(aarch64_ld1_x4_<mode>): Use vector-tuple mode iterator and
rename to...
(aarch64_ld1_x4_<vstruct_elt>): This.
(aarch64_st1x2<VALLDIF:mode>): Use vector-tuple mode iterator
and rename to...
(aarch64_st1x2<vstruct_elt>): This.
(aarch64_st1_x2_<mode>): Use vector-tuple mode iterator and
rename to...
(aarch64_st1_x2_<vstruct_elt>): This.
(aarch64_st1x3<VALLDIF:mode>): Use vector-tuple mode iterator
and rename to...
(aarch64_st1x3<vstruct_elt>): This.
(aarch64_st1_x3_<mode>): Use vector-tuple mode iterator and
rename to...
(aarch64_st1_x3_<vstruct_elt>): This.
(aarch64_st1x4<VALLDIF:mode>): Use vector-tuple mode iterator
and rename to...
(aarch64_st1x4<vstruct_elt>): This.
(aarch64_st1_x4_<mode>): Use vector-tuple mode iterator and
rename to...
(aarch64_st1_x4_<vstruct_elt>): This.
(*aarch64_mov<mode>): Define for vector-tuple modes.
(*aarch64_be_mov<mode>): Likewise.
(aarch64_ld<VSTRUCT:nregs>r<VALLDIF:mode>): Use vector-tuple
mode iterator and rename to...
(aarch64_ld<nregs>r<vstruct_elt>): This.
(aarch64_ld2<mode>_dreg): Use vector-tuple mode iterator and
rename to...
(aarch64_ld2<vstruct_elt>_dreg): This.
(aarch64_ld3<mode>_dreg): Use vector-tuple mode iterator and
rename to...
(aarch64_ld3<vstruct_elt>_dreg): This.
(aarch64_ld4<mode>_dreg): Use vector-tuple mode iterator and
rename to...
(aarch64_ld4<vstruct_elt>_dreg): This.
(aarch64_ld<VSTRUCT:nregs><VDC:mode>): Use vector-tuple mode
iterator and rename to...
(aarch64_ld<nregs><vstruct_elt>): Use vector-tuple mode
iterator and rename to...
(aarch64_ld<VSTRUCT:nregs><VQ:mode>): Use vector-tuple mode
(aarch64_ld1x2<VQ:mode>): Delete.
(aarch64_ld1x2<VDC:mode>): Use vector-tuple mode iterator and
rename to...
(aarch64_ld1x2<vstruct_elt>): This.
(aarch64_ld<VSTRUCT:nregs>_lane<VALLDIF:mode>): Use vector-
tuple mode iterator and rename to...
(aarch64_ld<nregs>_lane<vstruct_elt>): This.
(aarch64_get_dreg<VSTRUCT:mode><VDC:mode>): Delete.
(aarch64_get_qreg<VSTRUCT:mode><VQ:mode>): Likewise.
(aarch64_st2<mode>_dreg): Use vector-tuple mode iterator and
rename to...
(aarch64_st2<vstruct_elt>_dreg): This.
(aarch64_st3<mode>_dreg): Use vector-tuple mode iterator and
rename to...
(aarch64_st3<vstruct_elt>_dreg): This.
(aarch64_st4<mode>_dreg): Use vector-tuple mode iterator and
rename to...
(aarch64_st4<vstruct_elt>_dreg): This.
(aarch64_st<VSTRUCT:nregs><VDC:mode>): Use vector-tuple mode
iterator and rename to...
(aarch64_st<nregs><vstruct_elt>): This.
(aarch64_st<VSTRUCT:nregs><VQ:mode>): Use vector-tuple mode
iterator and rename to aarch64_st<nregs><vstruct_elt>.
(aarch64_st<VSTRUCT:nregs>_lane<VALLDIF:mode>): Use vector-
tuple mode iterator and rename to...
(aarch64_st<nregs>_lane<vstruct_elt>): This.
(aarch64_set_qreg<VSTRUCT:mode><VQ:mode>): Delete.
(aarch64_simd_ld1<mode>_x2): Use vector-tuple mode iterator
and rename to...
(aarch64_simd_ld1<vstruct_elt>_x2): This.
* config/aarch64/aarch64.c (aarch64_advsimd_struct_mode_p):
Refactor to include new vector-tuple modes.
(aarch64_classify_vector_mode): Add cases for new vector-
tuple modes.
(aarch64_advsimd_partial_struct_mode_p): Define.
(aarch64_advsimd_full_struct_mode_p): Likewise.
(aarch64_advsimd_vector_array_mode): Likewise.
(aarch64_sve_data_mode): Change location in file.
(aarch64_array_mode): Handle case of Neon vector-tuple modes.
(aarch64_hard_regno_nregs): Handle case of partial Neon
vector structures.
(aarch64_classify_address): Refactor to include handling of
Neon vector-tuple modes.
(aarch64_print_operand): Print "d" for "%R" for a partial
Neon vector structure.
(aarch64_expand_vec_perm_1): Use new vector-tuple mode.
(aarch64_modes_tieable_p): Prevent tieing Neon partial struct
modes with scalar machines modes larger than 8 bytes.
(aarch64_can_change_mode_class): Don't allow changes between
partial and full Neon vector-structure modes.
* config/aarch64/arm_neon.h (vst2_lane_f16): Use updated
builtin and remove boiler-plate code for opaque mode.
(vst2_lane_f32): Likewise.
(vst2_lane_f64): Likewise.
(vst2_lane_p8): Likewise.
(vst2_lane_p16): Likewise.
(vst2_lane_p64): Likewise.
(vst2_lane_s8): Likewise.
(vst2_lane_s16): Likewise.
(vst2_lane_s32): Likewise.
(vst2_lane_s64): Likewise.
(vst2_lane_u8): Likewise.
(vst2_lane_u16): Likewise.
(vst2_lane_u32): Likewise.
(vst2_lane_u64): Likewise.
(vst2q_lane_f16): Likewise.
(vst2q_lane_f32): Likewise.
(vst2q_lane_f64): Likewise.
(vst2q_lane_p8): Likewise.
(vst2q_lane_p16): Likewise.
(vst2q_lane_p64): Likewise.
(vst2q_lane_s8): Likewise.
(vst2q_lane_s16): Likewise.
(vst2q_lane_s32): Likewise.
(vst2q_lane_s64): Likewise.
(vst2q_lane_u8): Likewise.
(vst2q_lane_u16): Likewise.
(vst2q_lane_u32): Likewise.
(vst2q_lane_u64): Likewise.
(vst3_lane_f16): Likewise.
(vst3_lane_f32): Likewise.
(vst3_lane_f64): Likewise.
(vst3_lane_p8): Likewise.
(vst3_lane_p16): Likewise.
(vst3_lane_p64): Likewise.
(vst3_lane_s8): Likewise.
(vst3_lane_s16): Likewise.
(vst3_lane_s32): Likewise.
(vst3_lane_s64): Likewise.
(vst3_lane_u8): Likewise.
(vst3_lane_u16): Likewise.
(vst3_lane_u32): Likewise.
(vst3_lane_u64): Likewise.
(vst3q_lane_f16): Likewise.
(vst3q_lane_f32): Likewise.
(vst3q_lane_f64): Likewise.
(vst3q_lane_p8): Likewise.
(vst3q_lane_p16): Likewise.
(vst3q_lane_p64): Likewise.
(vst3q_lane_s8): Likewise.
(vst3q_lane_s16): Likewise.
(vst3q_lane_s32): Likewise.
(vst3q_lane_s64): Likewise.
(vst3q_lane_u8): Likewise.
(vst3q_lane_u16): Likewise.
(vst3q_lane_u32): Likewise.
(vst3q_lane_u64): Likewise.
(vst4_lane_f16): Likewise.
(vst4_lane_f32): Likewise.
(vst4_lane_f64): Likewise.
(vst4_lane_p8): Likewise.
(vst4_lane_p16): Likewise.
(vst4_lane_p64): Likewise.
(vst4_lane_s8): Likewise.
(vst4_lane_s16): Likewise.
(vst4_lane_s32): Likewise.
(vst4_lane_s64): Likewise.
(vst4_lane_u8): Likewise.
(vst4_lane_u16): Likewise.
(vst4_lane_u32): Likewise.
(vst4_lane_u64): Likewise.
(vst4q_lane_f16): Likewise.
(vst4q_lane_f32): Likewise.
(vst4q_lane_f64): Likewise.
(vst4q_lane_p8): Likewise.
(vst4q_lane_p16): Likewise.
(vst4q_lane_p64): Likewise.
(vst4q_lane_s8): Likewise.
(vst4q_lane_s16): Likewise.
(vst4q_lane_s32): Likewise.
(vst4q_lane_s64): Likewise.
(vst4q_lane_u8): Likewise.
(vst4q_lane_u16): Likewise.
(vst4q_lane_u32): Likewise.
(vst4q_lane_u64): Likewise.
(vtbl3_s8): Likewise.
(vtbl3_u8): Likewise.
(vtbl3_p8): Likewise.
(vtbl4_s8): Likewise.
(vtbl4_u8): Likewise.
(vtbl4_p8): Likewise.
(vld1_u8_x3): Likewise.
(vld1_s8_x3): Likewise.
(vld1_u16_x3): Likewise.
(vld1_s16_x3): Likewise.
(vld1_u32_x3): Likewise.
(vld1_s32_x3): Likewise.
(vld1_u64_x3): Likewise.
(vld1_s64_x3): Likewise.
(vld1_f16_x3): Likewise.
(vld1_f32_x3): Likewise.
(vld1_f64_x3): Likewise.
(vld1_p8_x3): Likewise.
(vld1_p16_x3): Likewise.
(vld1_p64_x3): Likewise.
(vld1q_u8_x3): Likewise.
(vld1q_s8_x3): Likewise.
(vld1q_u16_x3): Likewise.
(vld1q_s16_x3): Likewise.
(vld1q_u32_x3): Likewise.
(vld1q_s32_x3): Likewise.
(vld1q_u64_x3): Likewise.
(vld1q_s64_x3): Likewise.
(vld1q_f16_x3): Likewise.
(vld1q_f32_x3): Likewise.
(vld1q_f64_x3): Likewise.
(vld1q_p8_x3): Likewise.
(vld1q_p16_x3): Likewise.
(vld1q_p64_x3): Likewise.
(vld1_u8_x2): Likewise.
(vld1_s8_x2): Likewise.
(vld1_u16_x2): Likewise.
(vld1_s16_x2): Likewise.
(vld1_u32_x2): Likewise.
(vld1_s32_x2): Likewise.
(vld1_u64_x2): Likewise.
(vld1_s64_x2): Likewise.
(vld1_f16_x2): Likewise.
(vld1_f32_x2): Likewise.
(vld1_f64_x2): Likewise.
(vld1_p8_x2): Likewise.
(vld1_p16_x2): Likewise.
(vld1_p64_x2): Likewise.
(vld1q_u8_x2): Likewise.
(vld1q_s8_x2): Likewise.
(vld1q_u16_x2): Likewise.
(vld1q_s16_x2): Likewise.
(vld1q_u32_x2): Likewise.
(vld1q_s32_x2): Likewise.
(vld1q_u64_x2): Likewise.
(vld1q_s64_x2): Likewise.
(vld1q_f16_x2): Likewise.
(vld1q_f32_x2): Likewise.
(vld1q_f64_x2): Likewise.
(vld1q_p8_x2): Likewise.
(vld1q_p16_x2): Likewise.
(vld1q_p64_x2): Likewise.
(vld1_s8_x4): Likewise.
(vld1q_s8_x4): Likewise.
(vld1_s16_x4): Likewise.
(vld1q_s16_x4): Likewise.
(vld1_s32_x4): Likewise.
(vld1q_s32_x4): Likewise.
(vld1_u8_x4): Likewise.
(vld1q_u8_x4): Likewise.
(vld1_u16_x4): Likewise.
(vld1q_u16_x4): Likewise.
(vld1_u32_x4): Likewise.
(vld1q_u32_x4): Likewise.
(vld1_f16_x4): Likewise.
(vld1q_f16_x4): Likewise.
(vld1_f32_x4): Likewise.
(vld1q_f32_x4): Likewise.
(vld1_p8_x4): Likewise.
(vld1q_p8_x4): Likewise.
(vld1_p16_x4): Likewise.
(vld1q_p16_x4): Likewise.
(vld1_s64_x4): Likewise.
(vld1_u64_x4): Likewise.
(vld1_p64_x4): Likewise.
(vld1q_s64_x4): Likewise.
(vld1q_u64_x4): Likewise.
(vld1q_p64_x4): Likewise.
(vld1_f64_x4): Likewise.
(vld1q_f64_x4): Likewise.
(vld2_s64): Likewise.
(vld2_u64): Likewise.
(vld2_f64): Likewise.
(vld2_s8): Likewise.
(vld2_p8): Likewise.
(vld2_p64): Likewise.
(vld2_s16): Likewise.
(vld2_p16): Likewise.
(vld2_s32): Likewise.
(vld2_u8): Likewise.
(vld2_u16): Likewise.
(vld2_u32): Likewise.
(vld2_f16): Likewise.
(vld2_f32): Likewise.
(vld2q_s8): Likewise.
(vld2q_p8): Likewise.
(vld2q_s16): Likewise.
(vld2q_p16): Likewise.
(vld2q_p64): Likewise.
(vld2q_s32): Likewise.
(vld2q_s64): Likewise.
(vld2q_u8): Likewise.
(vld2q_u16): Likewise.
(vld2q_u32): Likewise.
(vld2q_u64): Likewise.
(vld2q_f16): Likewise.
(vld2q_f32): Likewise.
(vld2q_f64): Likewise.
(vld3_s64): Likewise.
(vld3_u64): Likewise.
(vld3_f64): Likewise.
(vld3_s8): Likewise.
(vld3_p8): Likewise.
(vld3_s16): Likewise.
(vld3_p16): Likewise.
(vld3_s32): Likewise.
(vld3_u8): Likewise.
(vld3_u16): Likewise.
(vld3_u32): Likewise.
(vld3_f16): Likewise.
(vld3_f32): Likewise.
(vld3_p64): Likewise.
(vld3q_s8): Likewise.
(vld3q_p8): Likewise.
(vld3q_s16): Likewise.
(vld3q_p16): Likewise.
(vld3q_s32): Likewise.
(vld3q_s64): Likewise.
(vld3q_u8): Likewise.
(vld3q_u16): Likewise.
(vld3q_u32): Likewise.
(vld3q_u64): Likewise.
(vld3q_f16): Likewise.
(vld3q_f32): Likewise.
(vld3q_f64): Likewise.
(vld3q_p64): Likewise.
(vld4_s64): Likewise.
(vld4_u64): Likewise.
(vld4_f64): Likewise.
(vld4_s8): Likewise.
(vld4_p8): Likewise.
(vld4_s16): Likewise.
(vld4_p16): Likewise.
(vld4_s32): Likewise.
(vld4_u8): Likewise.
(vld4_u16): Likewise.
(vld4_u32): Likewise.
(vld4_f16): Likewise.
(vld4_f32): Likewise.
(vld4_p64): Likewise.
(vld4q_s8): Likewise.
(vld4q_p8): Likewise.
(vld4q_s16): Likewise.
(vld4q_p16): Likewise.
(vld4q_s32): Likewise.
(vld4q_s64): Likewise.
(vld4q_u8): Likewise.
(vld4q_u16): Likewise.
(vld4q_u32): Likewise.
(vld4q_u64): Likewise.
(vld4q_f16): Likewise.
(vld4q_f32): Likewise.
(vld4q_f64): Likewise.
(vld4q_p64): Likewise.
(vld2_dup_s8): Likewise.
(vld2_dup_s16): Likewise.
(vld2_dup_s32): Likewise.
(vld2_dup_f16): Likewise.
(vld2_dup_f32): Likewise.
(vld2_dup_f64): Likewise.
(vld2_dup_u8): Likewise.
(vld2_dup_u16): Likewise.
(vld2_dup_u32): Likewise.
(vld2_dup_p8): Likewise.
(vld2_dup_p16): Likewise.
(vld2_dup_p64): Likewise.
(vld2_dup_s64): Likewise.
(vld2_dup_u64): Likewise.
(vld2q_dup_s8): Likewise.
(vld2q_dup_p8): Likewise.
(vld2q_dup_s16): Likewise.
(vld2q_dup_p16): Likewise.
(vld2q_dup_s32): Likewise.
(vld2q_dup_s64): Likewise.
(vld2q_dup_u8): Likewise.
(vld2q_dup_u16): Likewise.
(vld2q_dup_u32): Likewise.
(vld2q_dup_u64): Likewise.
(vld2q_dup_f16): Likewise.
(vld2q_dup_f32): Likewise.
(vld2q_dup_f64): Likewise.
(vld2q_dup_p64): Likewise.
(vld3_dup_s64): Likewise.
(vld3_dup_u64): Likewise.
(vld3_dup_f64): Likewise.
(vld3_dup_s8): Likewise.
(vld3_dup_p8): Likewise.
(vld3_dup_s16): Likewise.
(vld3_dup_p16): Likewise.
(vld3_dup_s32): Likewise.
(vld3_dup_u8): Likewise.
(vld3_dup_u16): Likewise.
(vld3_dup_u32): Likewise.
(vld3_dup_f16): Likewise.
(vld3_dup_f32): Likewise.
(vld3_dup_p64): Likewise.
(vld3q_dup_s8): Likewise.
(vld3q_dup_p8): Likewise.
(vld3q_dup_s16): Likewise.
(vld3q_dup_p16): Likewise.
(vld3q_dup_s32): Likewise.
(vld3q_dup_s64): Likewise.
(vld3q_dup_u8): Likewise.
(vld3q_dup_u16): Likewise.
(vld3q_dup_u32): Likewise.
(vld3q_dup_u64): Likewise.
(vld3q_dup_f16): Likewise.
(vld3q_dup_f32): Likewise.
(vld3q_dup_f64): Likewise.
(vld3q_dup_p64): Likewise.
(vld4_dup_s64): Likewise.
(vld4_dup_u64): Likewise.
(vld4_dup_f64): Likewise.
(vld4_dup_s8): Likewise.
(vld4_dup_p8): Likewise.
(vld4_dup_s16): Likewise.
(vld4_dup_p16): Likewise.
(vld4_dup_s32): Likewise.
(vld4_dup_u8): Likewise.
(vld4_dup_u16): Likewise.
(vld4_dup_u32): Likewise.
(vld4_dup_f16): Likewise.
(vld4_dup_f32): Likewise.
(vld4_dup_p64): Likewise.
(vld4q_dup_s8): Likewise.
(vld4q_dup_p8): Likewise.
(vld4q_dup_s16): Likewise.
(vld4q_dup_p16): Likewise.
(vld4q_dup_s32): Likewise.
(vld4q_dup_s64): Likewise.
(vld4q_dup_u8): Likewise.
(vld4q_dup_u16): Likewise.
(vld4q_dup_u32): Likewise.
(vld4q_dup_u64): Likewise.
(vld4q_dup_f16): Likewise.
(vld4q_dup_f32): Likewise.
(vld4q_dup_f64): Likewise.
(vld4q_dup_p64): Likewise.
(vld2_lane_u8): Likewise.
(vld2_lane_u16): Likewise.
(vld2_lane_u32): Likewise.
(vld2_lane_u64): Likewise.
(vld2_lane_s8): Likewise.
(vld2_lane_s16): Likewise.
(vld2_lane_s32): Likewise.
(vld2_lane_s64): Likewise.
(vld2_lane_f16): Likewise.
(vld2_lane_f32): Likewise.
(vld2_lane_f64): Likewise.
(vld2_lane_p8): Likewise.
(vld2_lane_p16): Likewise.
(vld2_lane_p64): Likewise.
(vld2q_lane_u8): Likewise.
(vld2q_lane_u16): Likewise.
(vld2q_lane_u32): Likewise.
(vld2q_lane_u64): Likewise.
(vld2q_lane_s8): Likewise.
(vld2q_lane_s16): Likewise.
(vld2q_lane_s32): Likewise.
(vld2q_lane_s64): Likewise.
(vld2q_lane_f16): Likewise.
(vld2q_lane_f32): Likewise.
(vld2q_lane_f64): Likewise.
(vld2q_lane_p8): Likewise.
(vld2q_lane_p16): Likewise.
(vld2q_lane_p64): Likewise.
(vld3_lane_u8): Likewise.
(vld3_lane_u16): Likewise.
(vld3_lane_u32): Likewise.
(vld3_lane_u64): Likewise.
(vld3_lane_s8): Likewise.
(vld3_lane_s16): Likewise.
(vld3_lane_s32): Likewise.
(vld3_lane_s64): Likewise.
(vld3_lane_f16): Likewise.
(vld3_lane_f32): Likewise.
(vld3_lane_f64): Likewise.
(vld3_lane_p8): Likewise.
(vld3_lane_p16): Likewise.
(vld3_lane_p64): Likewise.
(vld3q_lane_u8): Likewise.
(vld3q_lane_u16): Likewise.
(vld3q_lane_u32): Likewise.
(vld3q_lane_u64): Likewise.
(vld3q_lane_s8): Likewise.
(vld3q_lane_s16): Likewise.
(vld3q_lane_s32): Likewise.
(vld3q_lane_s64): Likewise.
(vld3q_lane_f16): Likewise.
(vld3q_lane_f32): Likewise.
(vld3q_lane_f64): Likewise.
(vld3q_lane_p8): Likewise.
(vld3q_lane_p16): Likewise.
(vld3q_lane_p64): Likewise.
(vld4_lane_u8): Likewise.
(vld4_lane_u16): Likewise.
(vld4_lane_u32): Likewise.
(vld4_lane_u64): Likewise.
(vld4_lane_s8): Likewise.
(vld4_lane_s16): Likewise.
(vld4_lane_s32): Likewise.
(vld4_lane_s64): Likewise.
(vld4_lane_f16): Likewise.
(vld4_lane_f32): Likewise.
(vld4_lane_f64): Likewise.
(vld4_lane_p8): Likewise.
(vld4_lane_p16): Likewise.
(vld4_lane_p64): Likewise.
(vld4q_lane_u8): Likewise.
(vld4q_lane_u16): Likewise.
(vld4q_lane_u32): Likewise.
(vld4q_lane_u64): Likewise.
(vld4q_lane_s8): Likewise.
(vld4q_lane_s16): Likewise.
(vld4q_lane_s32): Likewise.
(vld4q_lane_s64): Likewise.
(vld4q_lane_f16): Likewise.
(vld4q_lane_f32): Likewise.
(vld4q_lane_f64): Likewise.
(vld4q_lane_p8): Likewise.
(vld4q_lane_p16): Likewise.
(vld4q_lane_p64): Likewise.
(vqtbl2_s8): Likewise.
(vqtbl2_u8): Likewise.
(vqtbl2_p8): Likewise.
(vqtbl2q_s8): Likewise.
(vqtbl2q_u8): Likewise.
(vqtbl2q_p8): Likewise.
(vqtbl3_s8): Likewise.
(vqtbl3_u8): Likewise.
(vqtbl3_p8): Likewise.
(vqtbl3q_s8): Likewise.
(vqtbl3q_u8): Likewise.
(vqtbl3q_p8): Likewise.
(vqtbl4_s8): Likewise.
(vqtbl4_u8): Likewise.
(vqtbl4_p8): Likewise.
(vqtbl4q_s8): Likewise.
(vqtbl4q_u8): Likewise.
(vqtbl4q_p8): Likewise.
(vqtbx2_s8): Likewise.
(vqtbx2_u8): Likewise.
(vqtbx2_p8): Likewise.
(vqtbx2q_s8): Likewise.
(vqtbx2q_u8): Likewise.
(vqtbx2q_p8): Likewise.
(vqtbx3_s8): Likewise.
(vqtbx3_u8): Likewise.
(vqtbx3_p8): Likewise.
(vqtbx3q_s8): Likewise.
(vqtbx3q_u8): Likewise.
(vqtbx3q_p8): Likewise.
(vqtbx4_s8): Likewise.
(vqtbx4_u8): Likewise.
(vqtbx4_p8): Likewise.
(vqtbx4q_s8): Likewise.
(vqtbx4q_u8): Likewise.
(vqtbx4q_p8): Likewise.
(vst1_s64_x2): Likewise.
(vst1_u64_x2): Likewise.
(vst1_f64_x2): Likewise.
(vst1_s8_x2): Likewise.
(vst1_p8_x2): Likewise.
(vst1_s16_x2): Likewise.
(vst1_p16_x2): Likewise.
(vst1_s32_x2): Likewise.
(vst1_u8_x2): Likewise.
(vst1_u16_x2): Likewise.
(vst1_u32_x2): Likewise.
(vst1_f16_x2): Likewise.
(vst1_f32_x2): Likewise.
(vst1_p64_x2): Likewise.
(vst1q_s8_x2): Likewise.
(vst1q_p8_x2): Likewise.
(vst1q_s16_x2): Likewise.
(vst1q_p16_x2): Likewise.
(vst1q_s32_x2): Likewise.
(vst1q_s64_x2): Likewise.
(vst1q_u8_x2): Likewise.
(vst1q_u16_x2): Likewise.
(vst1q_u32_x2): Likewise.
(vst1q_u64_x2): Likewise.
(vst1q_f16_x2): Likewise.
(vst1q_f32_x2): Likewise.
(vst1q_f64_x2): Likewise.
(vst1q_p64_x2): Likewise.
(vst1_s64_x3): Likewise.
(vst1_u64_x3): Likewise.
(vst1_f64_x3): Likewise.
(vst1_s8_x3): Likewise.
(vst1_p8_x3): Likewise.
(vst1_s16_x3): Likewise.
(vst1_p16_x3): Likewise.
(vst1_s32_x3): Likewise.
(vst1_u8_x3): Likewise.
(vst1_u16_x3): Likewise.
(vst1_u32_x3): Likewise.
(vst1_f16_x3): Likewise.
(vst1_f32_x3): Likewise.
(vst1_p64_x3): Likewise.
(vst1q_s8_x3): Likewise.
(vst1q_p8_x3): Likewise.
(vst1q_s16_x3): Likewise.
(vst1q_p16_x3): Likewise.
(vst1q_s32_x3): Likewise.
(vst1q_s64_x3): Likewise.
(vst1q_u8_x3): Likewise.
(vst1q_u16_x3): Likewise.
(vst1q_u32_x3): Likewise.
(vst1q_u64_x3): Likewise.
(vst1q_f16_x3): Likewise.
(vst1q_f32_x3): Likewise.
(vst1q_f64_x3): Likewise.
(vst1q_p64_x3): Likewise.
(vst1_s8_x4): Likewise.
(vst1q_s8_x4): Likewise.
(vst1_s16_x4): Likewise.
(vst1q_s16_x4): Likewise.
(vst1_s32_x4): Likewise.
(vst1q_s32_x4): Likewise.
(vst1_u8_x4): Likewise.
(vst1q_u8_x4): Likewise.
(vst1_u16_x4): Likewise.
(vst1q_u16_x4): Likewise.
(vst1_u32_x4): Likewise.
(vst1q_u32_x4): Likewise.
(vst1_f16_x4): Likewise.
(vst1q_f16_x4): Likewise.
(vst1_f32_x4): Likewise.
(vst1q_f32_x4): Likewise.
(vst1_p8_x4): Likewise.
(vst1q_p8_x4): Likewise.
(vst1_p16_x4): Likewise.
(vst1q_p16_x4): Likewise.
(vst1_s64_x4): Likewise.
(vst1_u64_x4): Likewise.
(vst1_p64_x4): Likewise.
(vst1q_s64_x4): Likewise.
(vst1q_u64_x4): Likewise.
(vst1q_p64_x4): Likewise.
(vst1_f64_x4): Likewise.
(vst1q_f64_x4): Likewise.
(vst2_s64): Likewise.
(vst2_u64): Likewise.
(vst2_f64): Likewise.
(vst2_s8): Likewise.
(vst2_p8): Likewise.
(vst2_s16): Likewise.
(vst2_p16): Likewise.
(vst2_s32): Likewise.
(vst2_u8): Likewise.
(vst2_u16): Likewise.
(vst2_u32): Likewise.
(vst2_f16): Likewise.
(vst2_f32): Likewise.
(vst2_p64): Likewise.
(vst2q_s8): Likewise.
(vst2q_p8): Likewise.
(vst2q_s16): Likewise.
(vst2q_p16): Likewise.
(vst2q_s32): Likewise.
(vst2q_s64): Likewise.
(vst2q_u8): Likewise.
(vst2q_u16): Likewise.
(vst2q_u32): Likewise.
(vst2q_u64): Likewise.
(vst2q_f16): Likewise.
(vst2q_f32): Likewise.
(vst2q_f64): Likewise.
(vst2q_p64): Likewise.
(vst3_s64): Likewise.
(vst3_u64): Likewise.
(vst3_f64): Likewise.
(vst3_s8): Likewise.
(vst3_p8): Likewise.
(vst3_s16): Likewise.
(vst3_p16): Likewise.
(vst3_s32): Likewise.
(vst3_u8): Likewise.
(vst3_u16): Likewise.
(vst3_u32): Likewise.
(vst3_f16): Likewise.
(vst3_f32): Likewise.
(vst3_p64): Likewise.
(vst3q_s8): Likewise.
(vst3q_p8): Likewise.
(vst3q_s16): Likewise.
(vst3q_p16): Likewise.
(vst3q_s32): Likewise.
(vst3q_s64): Likewise.
(vst3q_u8): Likewise.
(vst3q_u16): Likewise.
(vst3q_u32): Likewise.
(vst3q_u64): Likewise.
(vst3q_f16): Likewise.
(vst3q_f32): Likewise.
(vst3q_f64): Likewise.
(vst3q_p64): Likewise.
(vst4_s64): Likewise.
(vst4_u64): Likewise.
(vst4_f64): Likewise.
(vst4_s8): Likewise.
(vst4_p8): Likewise.
(vst4_s16): Likewise.
(vst4_p16): Likewise.
(vst4_s32): Likewise.
(vst4_u8): Likewise.
(vst4_u16): Likewise.
(vst4_u32): Likewise.
(vst4_f16): Likewise.
(vst4_f32): Likewise.
(vst4_p64): Likewise.
(vst4q_s8): Likewise.
(vst4q_p8): Likewise.
(vst4q_s16): Likewise.
(vst4q_p16): Likewise.
(vst4q_s32): Likewise.
(vst4q_s64): Likewise.
(vst4q_u8): Likewise.
(vst4q_u16): Likewise.
(vst4q_u32): Likewise.
(vst4q_u64): Likewise.
(vst4q_f16): Likewise.
(vst4q_f32): Likewise.
(vst4q_f64): Likewise.
(vst4q_p64): Likewise.
(vtbx4_s8): Likewise.
(vtbx4_u8): Likewise.
(vtbx4_p8): Likewise.
(vld1_bf16_x2): Likewise.
(vld1q_bf16_x2): Likewise.
(vld1_bf16_x3): Likewise.
(vld1q_bf16_x3): Likewise.
(vld1_bf16_x4): Likewise.
(vld1q_bf16_x4): Likewise.
(vld2_bf16): Likewise.
(vld2q_bf16): Likewise.
(vld2_dup_bf16): Likewise.
(vld2q_dup_bf16): Likewise.
(vld3_bf16): Likewise.
(vld3q_bf16): Likewise.
(vld3_dup_bf16): Likewise.
(vld3q_dup_bf16): Likewise.
(vld4_bf16): Likewise.
(vld4q_bf16): Likewise.
(vld4_dup_bf16): Likewise.
(vld4q_dup_bf16): Likewise.
(vst1_bf16_x2): Likewise.
(vst1q_bf16_x2): Likewise.
(vst1_bf16_x3): Likewise.
(vst1q_bf16_x3): Likewise.
(vst1_bf16_x4): Likewise.
(vst1q_bf16_x4): Likewise.
(vst2_bf16): Likewise.
(vst2q_bf16): Likewise.
(vst3_bf16): Likewise.
(vst3q_bf16): Likewise.
(vst4_bf16): Likewise.
(vst4q_bf16): Likewise.
(vld2_lane_bf16): Likewise.
(vld2q_lane_bf16): Likewise.
(vld3_lane_bf16): Likewise.
(vld3q_lane_bf16): Likewise.
(vld4_lane_bf16): Likewise.
(vld4q_lane_bf16): Likewise.
(vst2_lane_bf16): Likewise.
(vst2q_lane_bf16): Likewise.
(vst3_lane_bf16): Likewise.
(vst3q_lane_bf16): Likewise.
(vst4_lane_bf16): Likewise.
(vst4q_lane_bf16): Likewise.
* config/aarch64/geniterators.sh: Modify iterator regex to
match new vector-tuple modes.
* config/aarch64/iterators.md (insn_count): Extend mode
attribute with vector-tuple type information.
(nregs): Likewise.
(Vendreg): Likewise.
(Vetype): Likewise.
(Vtype): Likewise.
(VSTRUCT_2D): New mode iterator.
(VSTRUCT_2DNX): Likewise.
(VSTRUCT_2DX): Likewise.
(VSTRUCT_2Q): Likewise.
(VSTRUCT_2QD): Likewise.
(VSTRUCT_3D): Likewise.
(VSTRUCT_3DNX): Likewise.
(VSTRUCT_3DX): Likewise.
(VSTRUCT_3Q): Likewise.
(VSTRUCT_3QD): Likewise.
(VSTRUCT_4D): Likewise.
(VSTRUCT_4DNX): Likewise.
(VSTRUCT_4DX): Likewise.
(VSTRUCT_4Q): Likewise.
(VSTRUCT_4QD): Likewise.
(VSTRUCT_D): Likewise.
(VSTRUCT_Q): Likewise.
(VSTRUCT_QD): Likewise.
(VSTRUCT_ELT): New mode attribute.
(vstruct_elt): Likewise.
* genmodes.c (VECTOR_MODE): Add default prefix and order
parameters.
(VECTOR_MODE_WITH_PREFIX): Define.
(make_vector_mode): Add mode prefix and order parameters.
gcc/testsuite/ChangeLog:
* gcc.target/aarch64/advsimd-intrinsics/bf16_vldN_lane_2.c:
Relax incorrect register number requirement.
* gcc.target/aarch64/sve/pcs/struct_3_256.c: Accept
equivalent codegen with fmov.
Jonathan Wright [Mon, 11 Oct 2021 22:02:16 +0000 (23:02 +0100)]
gcc/expmed.c: Ensure vector modes are tieable before extraction
Extracting a bitfield from a vector can be achieved by casting the
vector to a new type whose elements are the same size as the desired
bitfield, before generating a subreg. However, this is only an
optimization if the original vector can be accessed in the new
machine mode without first being copied - a condition denoted by the
TARGET_MODES_TIEABLE_P hook.
This patch adds a check to make sure that the vector modes are
tieable before attempting to generate a subreg. This is a necessary
prerequisite for a subsequent patch that will introduce new machine
modes for Arm Neon vector-tuple types.
gcc/ChangeLog:
2021-10-11 Jonathan Wright <jonathan.wright@arm.com>
* expmed.c (extract_bit_field_1): Ensure modes are tieable.
Jonathan Wright [Mon, 11 Oct 2021 17:37:32 +0000 (18:37 +0100)]
gcc/expr.c: Remove historic workaround for broken SIMD subreg
A long time ago, using a parallel to take a subreg of a SIMD register
was broken. This temporary fix[1] (from 2003) spilled these registers
to memory and reloaded the appropriate part to obtain the subreg.
The fix initially existed for the benefit of the PowerPC E500 - a
platform for which GCC removed support a number of years ago.
Regardless, a proper mechanism for taking a subreg of a SIMD register
exists now anyway.
This patch removes the workaround thus preventing SIMD registers
being dumped to memory unnecessarily - which sometimes can't be fixed
by later passes.
[1] https://gcc.gnu.org/pipermail/gcc-patches/2003-April/102099.html
gcc/ChangeLog:
2021-10-11 Jonathan Wright <jonathan.wright@arm.com>
* expr.c (emit_group_load_1): Remove historic workaround.
Jonathan Wright [Fri, 10 Sep 2021 15:48:02 +0000 (16:48 +0100)]
aarch64: Move Neon vector-tuple type declaration into the compiler
Declare the Neon vector-tuple types inside the compiler instead of in
the arm_neon.h header. This is a necessary first step before adding
corresponding machine modes to the AArch64 backend.
The vector-tuple types are implemented using a #pragma. This means
initialization of builtin functions that have vector-tuple types as
arguments or return values has to be delayed until the #pragma is
handled.
gcc/ChangeLog:
2021-09-10 Jonathan Wright <jonathan.wright@arm.com>
* config/aarch64/aarch64-builtins.c (aarch64_init_simd_builtins):
Factor out main loop to...
(aarch64_init_simd_builtin_functions): This new function.
(register_tuple_type): Define.
(aarch64_scalar_builtin_type_p): Define.
(handle_arm_neon_h): Define.
* config/aarch64/aarch64-c.c (aarch64_pragma_aarch64): Handle
pragma for arm_neon.h.
* config/aarch64/aarch64-protos.h (aarch64_advsimd_struct_mode_p):
Declare.
(handle_arm_neon_h): Likewise.
* config/aarch64/aarch64.c (aarch64_advsimd_struct_mode_p):
Remove static modifier.
* config/aarch64/arm_neon.h (target): Remove Neon vector
structure type definitions.
H.J. Lu [Thu, 4 Nov 2021 14:37:18 +0000 (07:37 -0700)]
x86: Check leal/addl gcc.target/i386/amxtile-3.c for x32
Check leal and addl for x32 to fix:
FAIL: gcc.target/i386/amxtile-3.c scan-assembler addq[ \\t]+\\$12
FAIL: gcc.target/i386/amxtile-3.c scan-assembler leaq[ \\t]+4
FAIL: gcc.target/i386/amxtile-3.c scan-assembler leaq[ \\t]+8
* gcc.target/i386/amxtile-3.c: Check leal/addl for x32.
Aldy Hernandez [Thu, 4 Nov 2021 11:37:16 +0000 (12:37 +0100)]
path solver: Prefer range_of_expr instead of range_on_edge.
The range_of_expr method provides better caching than range_on_edge.
If we have a statement, we can just it and avoid the range_on_edge
dance. Plus we can use all the range_of_expr fanciness.
Tested on x86-64 and ppc64le Linux with the usual regstrap. I also
verified that the before and after number of threads was the same or
greater in a suite of .ii files from a bootstrap.
gcc/ChangeLog:
PR tree-optimization/102943
* gimple-range-path.cc (path_range_query::range_on_path_entry):
Prefer range_of_expr unless there are no statements in the BB.
Aldy Hernandez [Thu, 4 Nov 2021 10:34:55 +0000 (11:34 +0100)]
Avoid repeating calculations in threader.
We already attempt to resolve the current path on entry to
find_paths_to_name(), so there's no need to do so again for each
exported range since nothing has changed.
Removing this redundant calculation avoids 22% of calls into the path
solver.
Tested on x86-64 and ppc64le Linux with the usual regstrap. I also
verified that the before and after number of threads was the same
in a suite of .ii files from a bootstrap.
gcc/ChangeLog:
PR tree-optimization/102943
* tree-ssa-threadbackward.c (back_threader::find_paths_to_names):
Avoid duplicate calculation of paths.
Aldy Hernandez [Wed, 3 Nov 2021 07:23:25 +0000 (08:23 +0100)]
path solver: Only compute relations for imports.
We are currently calculating implicit PHI relations for all PHI
arguments. This creates unecessary work, as we only care about SSA
names in the import bitmap. Similarly for inter-path relationals. We
can avoid things not in the bitmap.
Tested on x86-64 and ppc64le Linux with the usual regstrap. I also
verified that the before and after number of threads was the same
in a suite of .ii files from a bootstrap.
gcc/ChangeLog:
PR tree-optimization/102943
* gimple-range-path.cc (path_range_query::compute_phi_relations):
Only compute relations for SSA names in the import list.
(path_range_query::compute_outgoing_relations): Same.
* gimple-range-path.h (path_range_query::import_p): New.
H.J. Lu [Thu, 4 Nov 2021 14:17:44 +0000 (07:17 -0700)]
libffi: Add --enable-cet to configure
When --enable-cet is used to configure GCC, enable Intel CET in libffi.
* Makefile.am (AM_CFLAGS): Add $(CET_FLAGS).
(AM_CCASFLAGS): Likewise.
* configure.ac (CET_FLAGS): Add GCC_CET_FLAGS and AC_SUBST.
* Makefile.in: Regenerate.
* aclocal.m4: Likewise.
* configure: Likewise.
* include/Makefile.in: Likewise.
* man/Makefile.in: Likewise.
* testsuite/Makefile.in: Likewise.
Martin Liska [Thu, 4 Nov 2021 13:58:27 +0000 (14:58 +0100)]
Add -v option for git_check_commit.py.
Doing so, one can see:
$ git gcc-verify
a50914d2111c72d2cd5cb8cf474133f4f85a25f6 -v
Checking
a50914d2111c72d2cd5cb8cf474133f4f85a25f6: FAILED
ERR: unchanged file mentioned in a ChangeLog: "gcc/common.opt"
ERR: unchanged file mentioned in a ChangeLog (did you mean "gcc/testsuite/g++.dg/pr102955.C"?): "gcc/testsuite/gcc.dg/pr102955.c"
- gcc/testsuite/gcc.dg/pr102955.c
? ^^ ^
+ gcc/testsuite/g++.dg/pr102955.C
? ^^ ^
contrib/ChangeLog:
* gcc-changelog/git_check_commit.py: Add -v option.
* gcc-changelog/git_commit.py: Print verbose diff for wrong
filename.
Tamar Christina [Thu, 4 Nov 2021 13:43:36 +0000 (13:43 +0000)]
testsuite: Add more guards to complex tests
This test hopefully fixes all the remaining target specific test issues by
1: Unrolling all add testcases by 16 using pragma GCC unroll
2. On armhf use Adv.SIMD instead of MVE to test. MVE's autovec is too incomplete
to be a general test target.
3. Add appropriate vect_<type> and float<size> guards on testcases.
gcc/testsuite/ChangeLog:
PR testsuite/103042
* gcc.dg/vect/complex/bb-slp-complex-add-pattern-int.c: Update guards.
* gcc.dg/vect/complex/bb-slp-complex-add-pattern-long.c: Likewise.
* gcc.dg/vect/complex/bb-slp-complex-add-pattern-short.c: Likewise.
* gcc.dg/vect/complex/bb-slp-complex-add-pattern-unsigned-int.c:
Likewise.
* gcc.dg/vect/complex/bb-slp-complex-add-pattern-unsigned-long.c:
Likewise.
* gcc.dg/vect/complex/bb-slp-complex-add-pattern-unsigned-short.c:
Likewise.
* gcc.dg/vect/complex/complex-add-pattern-template.c: Likewise.
* gcc.dg/vect/complex/complex-add-template.c: Likewise.
* gcc.dg/vect/complex/complex-operations-run.c: Likewise.
* gcc.dg/vect/complex/fast-math-bb-slp-complex-add-double.c: Likewise.
* gcc.dg/vect/complex/fast-math-bb-slp-complex-add-float.c: Likewise.
* gcc.dg/vect/complex/fast-math-bb-slp-complex-add-half-float.c:
Likewise.
* gcc.dg/vect/complex/fast-math-bb-slp-complex-add-pattern-double.c:
Likewise.
* gcc.dg/vect/complex/fast-math-bb-slp-complex-add-pattern-float.c:
Likewise.
* gcc.dg/vect/complex/fast-math-bb-slp-complex-add-pattern-half-float.c:
Likewise.
* gcc.dg/vect/complex/fast-math-bb-slp-complex-mla-double.c: Likewise.
* gcc.dg/vect/complex/fast-math-bb-slp-complex-mla-float.c: Likewise.
* gcc.dg/vect/complex/fast-math-bb-slp-complex-mla-half-float.c:
Likewise.
* gcc.dg/vect/complex/fast-math-bb-slp-complex-mls-double.c: Likewise.
* gcc.dg/vect/complex/fast-math-bb-slp-complex-mls-float.c: Likewise.
* gcc.dg/vect/complex/fast-math-bb-slp-complex-mls-half-float.c:
Likewise.
* gcc.dg/vect/complex/fast-math-bb-slp-complex-mul-double.c: Likewise.
* gcc.dg/vect/complex/fast-math-bb-slp-complex-mul-float.c: Likewise.
* gcc.dg/vect/complex/fast-math-bb-slp-complex-mul-half-float.c:
Likewise.
* gcc.dg/vect/complex/fast-math-complex-add-double.c: Likewise.
* gcc.dg/vect/complex/fast-math-complex-add-float.c: Likewise.
* gcc.dg/vect/complex/fast-math-complex-add-half-float.c: Likewise.
* gcc.dg/vect/complex/fast-math-complex-add-pattern-double.c: Likewise.
* gcc.dg/vect/complex/fast-math-complex-add-pattern-float.c: Likewise.
* gcc.dg/vect/complex/fast-math-complex-add-pattern-half-float.c:
Likewise.
* gcc.dg/vect/complex/fast-math-complex-mla-double.c: Likewise.
* gcc.dg/vect/complex/fast-math-complex-mla-float.c: Likewise.
* gcc.dg/vect/complex/fast-math-complex-mla-half-float.c: Likewise.
* gcc.dg/vect/complex/fast-math-complex-mls-double.c: Likewise.
* gcc.dg/vect/complex/fast-math-complex-mls-float.c: Likewise.
* gcc.dg/vect/complex/fast-math-complex-mls-half-float.c: Likewise.
* gcc.dg/vect/complex/fast-math-complex-mul-double.c: Likewise.
* gcc.dg/vect/complex/fast-math-complex-mul-float.c: Likewise.
* gcc.dg/vect/complex/fast-math-complex-mul-half-float.c: Likewise.
* gcc.dg/vect/complex/vect-complex-add-pattern-byte.c: Likewise.
* gcc.dg/vect/complex/vect-complex-add-pattern-int.c: Likewise.
* gcc.dg/vect/complex/vect-complex-add-pattern-long.c: Likewise.
* gcc.dg/vect/complex/vect-complex-add-pattern-short.c: Likewise.
* gcc.dg/vect/complex/vect-complex-add-pattern-unsigned-byte.c:
Likewise.
* gcc.dg/vect/complex/vect-complex-add-pattern-unsigned-int.c:
Likewise.
* gcc.dg/vect/complex/vect-complex-add-pattern-unsigned-long.c:
Likewise.
* gcc.dg/vect/complex/vect-complex-add-pattern-unsigned-short.c:
Likewise.
David Malcolm [Thu, 9 Sep 2021 18:32:14 +0000 (14:32 -0400)]
analyzer: fix ICE in sm_state_map::dump when dumping trees
gcc/analyzer/ChangeLog:
* program-state.cc (sm_state_map::dump): Use default_tree_printer
as format decoder.
Signed-off-by: David Malcolm <dmalcolm@redhat.com>
Richard Biener [Thu, 4 Nov 2021 08:17:18 +0000 (09:17 +0100)]
rtl-optimization/103075 - avoid ICEing on unfolded int-to-float converts
The following avoids asserting in exact_int_to_float_conversion_p that
the argument is not constant which it in fact can be with
-frounding-math and inexact int-to-float conversions. Say so.
2021-11-04 Richard Biener <rguenther@suse.de>
PR rtl-optimization/103075
* simplify-rtx.c (exact_int_to_float_conversion_p): Return
false for a VOIDmode operand.
* gcc.dg/pr103075.c: New testcase.
Richard Sandiford [Thu, 4 Nov 2021 12:31:17 +0000 (12:31 +0000)]
aarch64: Move more code into aarch64_vector_costs
This patch moves more code into aarch64_vector_costs and reuses
some of the information that is now available in the base class.
I'm planing to significantly rework this code, with more hooks
into the vectoriser, but this seemed worth doing as a first step.
gcc/
* config/aarch64/aarch64.c (aarch64_vector_costs): Make member
variables private and add "m_" to their names. Remove is_loop.
(aarch64_record_potential_advsimd_unrolling): Replace with...
(aarch64_vector_costs::record_potential_advsimd_unrolling): ...this.
(aarch64_analyze_loop_vinfo): Replace with...
(aarch64_vector_costs::analyze_loop_vinfo): ...this.
Move initialization of (m_)vec_flags to add_stmt_cost.
(aarch64_analyze_bb_vinfo): Delete.
(aarch64_count_ops): Replace with...
(aarch64_vector_costs::count_ops): ...this.
(aarch64_vector_costs::add_stmt_cost): Set m_vec_flags,
using m_costing_for_scalar to test whether we're costing
scalar or vector code.
(aarch64_adjust_body_cost_sve): Replace with...
(aarch64_vector_costs::adjust_body_cost_sve): ...this.
(aarch64_adjust_body_cost): Replace with...
(aarch64_vector_costs::adjust_body_cost): ...this.
(aarch64_vector_costs::finish_cost): Use m_vinfo instead of is_loop.
Richard Sandiford [Thu, 4 Nov 2021 12:31:17 +0000 (12:31 +0000)]
vect: Convert cost hooks to classes
The current vector cost interface has a quite a bit of redundancy
built in. Each target that defines its own hooks has to replicate
the basic unsigned[3] management. Currently each target also
duplicates the cost adjustment for inner loops.
This patch instead defines a vector_costs class for holding
the scalar or vector cost and allows targets to subclass it.
There is then only one costing hook: to create a new costs
structure of the appropriate type. Everything else can be
virtual functions, with common concepts implemented in the
base class rather than in each target's derivation.
This might seem like excess C++-ification, but it shaves
~100 LOC. I've also got some follow-on changes that become
significantly easier with this patch. Maybe it could help
with things like weighting blocks based on frequency too.
This will clash with Andre's unrolling patches. His patches
have priority so this patch should queue behind them.
The x86 and rs6000 parts fully convert to a self-contained class.
The equivalent aarch64 changes are more complex, so this patch
just does the bare minimum. A later patch will rework the
aarch64 bits.
gcc/
* target.def (targetm.vectorize.init_cost): Replace with...
(targetm.vectorize.create_costs): ...this.
(targetm.vectorize.add_stmt_cost): Delete.
(targetm.vectorize.finish_cost): Likewise.
(targetm.vectorize.destroy_cost_data): Likewise.
* doc/tm.texi.in (TARGET_VECTORIZE_INIT_COST): Replace with...
(TARGET_VECTORIZE_CREATE_COSTS): ...this.
(TARGET_VECTORIZE_ADD_STMT_COST): Delete.
(TARGET_VECTORIZE_FINISH_COST): Likewise.
(TARGET_VECTORIZE_DESTROY_COST_DATA): Likewise.
* doc/tm.texi: Regenerate.
* tree-vectorizer.h (vec_info::vec_info): Remove target_cost_data
parameter.
(vec_info::target_cost_data): Change from a void * to a vector_costs *.
(vector_costs): New class.
(init_cost): Take a vec_info and return a vector_costs.
(dump_stmt_cost): Remove data parameter.
(add_stmt_cost): Replace vinfo and data parameters with a vector_costs.
(add_stmt_costs): Likewise.
(finish_cost): Replace data parameter with a vector_costs.
(destroy_cost_data): Delete.
* tree-vectorizer.c (dump_stmt_cost): Remove data argument and
don't print it.
(vec_info::vec_info): Remove the target_cost_data parameter and
initialize the member variable to null instead.
(vec_info::~vec_info): Delete target_cost_data instead of calling
destroy_cost_data.
(vector_costs::add_stmt_cost): New function.
(vector_costs::finish_cost): Likewise.
(vector_costs::record_stmt_cost): Likewise.
(vector_costs::adjust_cost_for_freq): Likewise.
* tree-vect-loop.c (_loop_vec_info::_loop_vec_info): Update
call to vec_info::vec_info.
(vect_compute_single_scalar_iteration_cost): Update after above
changes to costing interface.
(vect_analyze_loop_operations): Likewise.
(vect_estimate_min_profitable_iters): Likewise.
(vect_analyze_loop_2): Initialize LOOP_VINFO_TARGET_COST_DATA
at the start_over point, where it needs to be recreated after
trying without slp. Update retry code accordingly.
* tree-vect-slp.c (_bb_vec_info::_bb_vec_info): Update call
to vec_info::vec_info.
(vect_slp_analyze_operation): Update after above changes to costing
interface.
(vect_bb_vectorization_profitable_p): Likewise.
* targhooks.h (default_init_cost): Replace with...
(default_vectorize_create_costs): ...this.
(default_add_stmt_cost): Delete.
(default_finish_cost, default_destroy_cost_data): Likewise.
* targhooks.c (default_init_cost): Replace with...
(default_vectorize_create_costs): ...this.
(default_add_stmt_cost): Delete, moving logic to vector_costs instead.
(default_finish_cost, default_destroy_cost_data): Delete.
* config/aarch64/aarch64.c (aarch64_vector_costs): Inherit from
vector_costs. Add a constructor.
(aarch64_init_cost): Replace with...
(aarch64_vectorize_create_costs): ...this.
(aarch64_add_stmt_cost): Replace with...
(aarch64_vector_costs::add_stmt_cost): ...this. Use record_stmt_cost
to adjust the cost for inner loops.
(aarch64_finish_cost): Replace with...
(aarch64_vector_costs::finish_cost): ...this.
(aarch64_destroy_cost_data): Delete.
(TARGET_VECTORIZE_INIT_COST): Replace with...
(TARGET_VECTORIZE_CREATE_COSTS): ...this.
(TARGET_VECTORIZE_ADD_STMT_COST): Delete.
(TARGET_VECTORIZE_FINISH_COST): Likewise.
(TARGET_VECTORIZE_DESTROY_COST_DATA): Likewise.
* config/i386/i386.c (ix86_vector_costs): New structure.
(ix86_init_cost): Replace with...
(ix86_vectorize_create_costs): ...this.
(ix86_add_stmt_cost): Replace with...
(ix86_vector_costs::add_stmt_cost): ...this. Use adjust_cost_for_freq
to adjust the cost for inner loops.
(ix86_finish_cost, ix86_destroy_cost_data): Delete.
(TARGET_VECTORIZE_INIT_COST): Replace with...
(TARGET_VECTORIZE_CREATE_COSTS): ...this.
(TARGET_VECTORIZE_ADD_STMT_COST): Delete.
(TARGET_VECTORIZE_FINISH_COST): Likewise.
(TARGET_VECTORIZE_DESTROY_COST_DATA): Likewise.
* config/rs6000/rs6000.c (TARGET_VECTORIZE_INIT_COST): Replace with...
(TARGET_VECTORIZE_CREATE_COSTS): ...this.
(TARGET_VECTORIZE_ADD_STMT_COST): Delete.
(TARGET_VECTORIZE_FINISH_COST): Likewise.
(TARGET_VECTORIZE_DESTROY_COST_DATA): Likewise.
(rs6000_cost_data): Inherit from vector_costs.
Add a constructor. Drop loop_info, cost and costing_for_scalar
in favor of the corresponding vector_costs member variables.
Add "m_" to the names of the remaining member variables and
initialize them.
(rs6000_density_test): Replace with...
(rs6000_cost_data::density_test): ...this.
(rs6000_init_cost): Replace with...
(rs6000_vectorize_create_costs): ...this.
(rs6000_update_target_cost_per_stmt): Replace with...
(rs6000_cost_data::update_target_cost_per_stmt): ...this.
(rs6000_add_stmt_cost): Replace with...
(rs6000_cost_data::add_stmt_cost): ...this. Use adjust_cost_for_freq
to adjust the cost for inner loops.
(rs6000_adjust_vect_cost_per_loop): Replace with...
(rs6000_cost_data::adjust_vect_cost_per_loop): ...this.
(rs6000_finish_cost): Replace with...
(rs6000_cost_data::finish_cost): ...this. Group loop code
into a single if statement and pass the loop_vinfo down to
subroutines.
(rs6000_destroy_cost_data): Delete.
Martin Liska [Thu, 4 Nov 2021 12:26:58 +0000 (13:26 +0100)]
libsanitizer: update LOCAL_PATCHES
libsanitizer/ChangeLog:
* LOCAL_PATCHES: Update git revision.
H.J. Lu [Tue, 20 Jul 2021 17:46:51 +0000 (10:46 -0700)]
libsanitizer: Apply local patches
Martin Liska [Thu, 4 Nov 2021 08:26:30 +0000 (09:26 +0100)]
lisanitizer: Apply autoreconf.
Martin Liska [Thu, 4 Nov 2021 08:20:14 +0000 (09:20 +0100)]
Aldy Hernandez [Thu, 4 Nov 2021 08:23:24 +0000 (09:23 +0100)]
Convert arrays in ssa pointer_equiv_analyzer to auto_vec's.
The problem in this PR is an off-by-one bug. We should've allocated
num_ssa_names + 1. However, in fixing this, I noticed that
num_ssa_names can change between queries, so I have replaced the array
with an auto_vec and added code to grow the vector as necessary.
Tested on x86-64 Linux.
PR tree-optimization/103062
gcc/ChangeLog:
PR tree-optimization/103062
* value-pointer-equiv.cc (ssa_equiv_stack::ssa_equiv_stack):
Increase size of allocation by 1.
(ssa_equiv_stack::push_replacement): Grow as needed.
(ssa_equiv_stack::get_replacement): Same.
(pointer_equiv_analyzer::pointer_equiv_analyzer): Same.
(pointer_equiv_analyzer::~pointer_equiv_analyzer): Remove delete.
(pointer_equiv_analyzer::set_global_equiv): Grow as needed.
(pointer_equiv_analyzer::get_equiv): Same.
(pointer_equiv_analyzer::get_equiv_expr): Remove const.
* value-pointer-equiv.h (class pointer_equiv_analyzer): Remove
const markers. Use auto_vec instead of tree *.
gcc/testsuite/ChangeLog:
* gcc.dg/pr103062.c: New test.
Jonathan Wakely [Tue, 2 Nov 2021 21:07:37 +0000 (21:07 +0000)]
libstdc++: Refactor emplace-like functions in std::variant
libstdc++-v3/ChangeLog:
* include/std/variant (__detail::__variant::__emplace): New
function template.
(_Copy_assign_base::operator=): Reorder conditions to match
bulleted list of effects in the standard. Use __emplace instead
of _M_reset followed by _Construct.
(_Move_assign_base::operator=): Likewise.
(__construct_by_index): Remove.
(variant::emplace): Use __emplace instead of _M_reset followed
by __construct_by_index.
(variant::swap): Hoist valueless cases out of visitor. Use
__emplace to replace _M_reset followed by _Construct.
Jonathan Wakely [Wed, 3 Nov 2021 00:21:38 +0000 (00:21 +0000)]
libstdc++: Optimize std::variant traits and improve diagnostics
By defining additional partial specializations of _Nth_type we can
reduce the number of recursive instantiations needed to get from N to 0.
We can also use _Nth_type in variant_alternative, to take advantage of
that new optimization.
By adding a static_assert to variant_alternative we get a nicer error
than 'invalid use of incomplete type'.
By defining partial specializations of std::variant_size_v for the
common case we can avoid instantiating the std::variant_size class
template.
The __tuple_count class template and __tuple_count_v variable template
can be simplified to a single variable template, __count.
By adding a deleted constructor to the _Variant_union primary template
we can (very slightly) improve diagnostics for invalid attempts to
construct a std::variant with an out-of-range index. Instead of a
confusing error about "too many initializers for ..." we get a call to a
deleted function.
By using _Nth_type instead of variant_alternative (for cv-unqualified
variant types) we avoid instantiating variant_alternative.
By adding deleted overloads of variant::emplace we get better
diagnostics for emplace<invalid-index> or emplace<invalid-type>. Instead
of getting errors explaining why each of the four overloads wasn't
valid, we just get one error about calling a deleted function.
libstdc++-v3/ChangeLog:
* include/std/variant (_Nth_type): Define partial
specializations to reduce number of instantiations.
(variant_size_v): Define partial specializations to avoid
instantiations.
(variant_alternative): Use _Nth_type. Add static assert.
(__tuple_count, __tuple_count_v): Replace with ...
(__count): New variable template.
(_Variant_union): Add deleted constructor.
(variant::__to_type): Use _Nth_type.
(variant::emplace): Use _Nth_type. Add deleted overloads for
invalid types and indices.
Jonathan Wakely [Wed, 3 Nov 2021 13:51:45 +0000 (13:51 +0000)]
libstdc++: Fix handling of const types in std::variant [PR102912]
Prior to r12-4447 (implementing P2231R1 constexpr changes) we didn't
construct the correct member of the union in __variant_construct_single,
we just plopped an object in the memory occupied by the union:
void* __storage = std::addressof(__lhs._M_u);
using _Type = remove_reference_t<decltype(__rhs_mem)>;
::new (__storage) _Type(std::forward<decltype(__rhs_mem)>(__rhs_mem));
We didn't care whether we had variant<int, const int>, we would just
place an int (or const int) into the storage, and then set the _M_index
to say which one it was.
In the new constexpr-friendly code we use std::construct_at to construct
the union object, which constructs the active member of the right type.
But now we need to know exactly the right type. We have to distinguish
between alternatives of type int and const int, and we have to be able
to find a const int (or const std::string, as in the OP) among the
alternatives. So my change from remove_reference_t<decltype(__rhs_mem)>
to remove_cvref_t<_Up> was wrong. It strips the const from const int,
and then we can't find the index of the const int alternative.
But just using remove_reference_t doesn't work either. When the copy
assignment operator of std::variant<int> uses __variant_construct_single
it passes a const int& as __rhs_mem, but if we don't strip the const
then we try to find const int among the alternatives, and *that* fails.
Similarly for the copy constructor, which also uses a const int& as the
initializer for a non-const int alternative.
The root cause of the problem is that __variant_construct_single doesn't
know the index of the type it's supposed to construct, and the new
_Variant_storage::__index_of<_Type> helper doesn't work if __rhs_mem and
the alternative being constructed have different const-qualification. We
need to replace __variant_construct_single with something that knows the
index of the alternative being constructed. All uses of that function do
actually know the index, but that context is lost by the time we call
__variant_construct_single. This patch replaces that function and
__variant_construct, inlining their effects directly into the callers.
libstdc++-v3/ChangeLog:
PR libstdc++/102912
* include/std/variant (_Variant_storage::__index_of): Remove.
(__variant_construct_single): Remove.
(__variant_construct): Remove.
(_Copy_ctor_base::_Copy_ctor_base(const _Copy_ctor_base&)): Do
construction directly instead of using __variant_construct.
(_Move_ctor_base::_Move_ctor_base(_Move_ctor_base&&)): Likewise.
(_Move_ctor_base::_M_destructive_move()): Remove.
(_Move_ctor_base::_M_destructive_copy()): Remove.
(_Copy_assign_base::operator=(const _Copy_assign_base&)): Do
construction directly instead of using _M_destructive_copy.
(variant::swap): Do construction directly instead of using
_M_destructive_move.
* testsuite/20_util/variant/102912.cc: New test.
Richard Biener [Wed, 3 Nov 2021 14:01:44 +0000 (15:01 +0100)]
VN/PRE TLC
This removes an always true parameter of vn_nary_op_insert_into and moves
valueization to the two callers of vn_nary_op_compute_hash instead of doing it
therein where this function name does not suggest such thing.
Also remove extra valueization from PRE phi-translation.
2021-11-03 Richard Biener <rguenther@suse.de>
* tree-ssa-sccvn.c (vn_nary_op_insert_into): Remove always
true parameter and inline valueization.
(vn_nary_op_lookup_1): Inline valueization from ...
(vn_nary_op_compute_hash): ... here and remove it here.
* tree-ssa-pre.c (phi_translate_1): Do not valueize
before vn_nary_lookup_pieces.
(get_representative_for): Mark created SSA representatives
as visited.
Jiufu Guo [Thu, 4 Nov 2021 06:47:52 +0000 (14:47 +0800)]
Update dg-require-effective-target for pr101145 cases
For test cases pr101145*.c, some types are not able to be
vectorized on some targets. This patch updates
dg-require-effective-target according to test cases.
gcc/testsuite/ChangeLog:
* gcc.dg/vect/pr101145_1.c: Update case.
* gcc.dg/vect/pr101145_2.c: Update case.
* gcc.dg/vect/pr101145_3.c: Update case.
Martin Liska [Thu, 4 Nov 2021 08:53:38 +0000 (09:53 +0100)]
Disable warning for an ASAN test-case.
gcc/testsuite/ChangeLog:
* g++.dg/asan/asan_test.C: Disable one warning.
Richard Sandiford [Thu, 4 Nov 2021 08:28:44 +0000 (08:28 +0000)]
simplify-rtx: Fix vec_select index check
Vector lane indices follow memory (array) order, so lane 0 corresponds
to the high element rather than the low element on big-endian targets.
This was causing quite a few execution failures on aarch64_be,
such as gcc.c-torture/execute/pr47538.c.
gcc/
* simplify-rtx.c (simplify_context::simplify_gen_vec_select): Assert
that the operand has a vector mode. Use subreg_lowpart_offset
to test whether an index corresponds to the low part.
gcc/testsuite/
* gcc.dg/rtl/aarch64/big-endian-cse-1.c: New test.
Richard Sandiford [Thu, 4 Nov 2021 08:28:44 +0000 (08:28 +0000)]
Fix RTL frontend handling of const_vectors
The RTL frontend makes sure that CONST_INTs use shared rtxes where
appropriate. We should do the same thing for CONST_VECTORs,
reusing CONST0_RTX, CONST1_RTX and CONSTM1_RTX. This also has
the effect of setting CONST_VECTOR_NELTS_PER_PATTERN and
CONST_VECTOR_NPATTERNS.
While looking at where to add that, I noticed we had some dead #includes
in read-rtl.c. Some of the stuff that read-rtl-function.c does was once
in that file instead.
gcc/
* read-rtl.c: Remove dead !GENERATOR_FILE block.
* read-rtl-function.c (function_reader::consolidate_singletons):
Generate canonical CONST_VECTORs.
liuhongt [Wed, 3 Nov 2021 08:32:22 +0000 (16:32 +0800)]
Extend vternlog define_insn_and_split to memory_operand to enable more optimziation.
gcc/ChangeLog:
PR target/101989
* config/i386/predicates.md (reg_or_notreg_operand): Rename to ..
(regmem_or_bitnot_regmem_operand): .. and extend to handle
memory_operand.
* config/i386/sse.md (*<avx512>_vpternlog<mode>_1): Force_reg
the operands which are required to be register_operand.
(*<avx512>_vpternlog<mode>_2): Ditto.
(*<avx512>_vpternlog<mode>_3): Ditto.
(*<avx512>_vternlog<mode>_all): Disallow embeded broadcast for
vector HFmodes since it's not a real AVX512FP16 instruction.
gcc/testsuite/ChangeLog:
* gcc.target/i386/pr101989-3.c: New test.
liuhongt [Wed, 3 Nov 2021 08:07:34 +0000 (16:07 +0800)]
Simplify (trunc)copysign((extend)a, (extend)b) to .COPYSIGN (a,b).
a and b are same type as the truncation type and has less precision
than extend type.
gcc/ChangeLog:
PR target/102464
* match.pd: simplify (trunc)copysign((extend)a, (extend)b) to
.COPYSIGN (a,b) when a and b are same type as the truncation
type and has less precision than extend type.
gcc/testsuite/ChangeLog:
* gcc.target/i386/pr102464-copysign-1.c: New test.
Richard Biener [Thu, 4 Nov 2021 07:37:49 +0000 (08:37 +0100)]
Update TARGET_MEM_REF documentation
This updates the internals manual documentation of TARGET_MEM_REF
and amends MEM_REF. The former was seriously out of date.
2021-11-04 Richard Biener <rguenther@suse.de>
gcc/
* doc/generic.texi: Update TARGET_MEM_REF and MEM_REF
documentation.
Hongyu Wang [Tue, 26 Oct 2021 05:07:31 +0000 (13:07 +0800)]
i386: Auto vectorize sdot_prod, usdot_prod with VNNI instruction.
AVX512VNNI/AVXVNNI has vpdpwssd for HImode, vpdpbusd for QImode, so
Adjust HImode sdot_prod expander and add QImode usdot_prod expander
to enhance vectorization for dotprod.
gcc/ChangeLog:
* config/i386/sse.md (VI2_AVX512VNNIBW): New mode iterator.
(VI1_AVX512VNNI): Likewise.
(SDOT_VPDP_SUF): New mode_attr.
(VI1SI): Likewise.
(vi1si): Likewise.
(sdot_prod<mode>): Use VI2_AVX512F iterator, expand to
vpdpwssd when VNNI targets available.
(usdot_prod<mode>): New expander for vector QImode.
gcc/testsuite/ChangeLog:
* gcc.target/i386/vnni-auto-vectorize-1.c: New test.
* gcc.target/i386/vnni-auto-vectorize-2.c: Ditto.
Hongyu Wang [Wed, 3 Nov 2021 05:58:52 +0000 (13:58 +0800)]
i386: Fix wrong result for AMX-TILE intrinsic when parsing expression.
_tile_loadd, _tile_stored, _tile_streamloadd intrinsics are defined by
macro, so the parameters should be wrapped by parentheses to accept
expressions.
gcc/ChangeLog:
* config/i386/amxtileintrin.h (_tile_loadd_internal): Add
parentheses to base and stride.
(_tile_stream_loadd_internal): Likewise.
(_tile_stored_internal): Likewise.
gcc/testsuite/ChangeLog:
* gcc.target/i386/amxtile-3.c: New test.
Marek Polacek [Thu, 4 Nov 2021 00:39:32 +0000 (20:39 -0400)]
testsuite: Fix g++.dg/opt/pr102970.C
This test uses a generic lambda, only available since C++14, so don't
run it in earlier modes.
gcc/testsuite/ChangeLog:
* g++.dg/opt/pr102970.C: Only run in C++14 and up.
GCC Administrator [Thu, 4 Nov 2021 00:16:32 +0000 (00:16 +0000)]
Daily bump.
Maciej W. Rozycki [Wed, 3 Nov 2021 17:04:19 +0000 (17:04 +0000)]
MAINTAINERS: Clarify the policy WRT the Write After Approval list
* MAINTAINERS: Clarify the policy WRT the Write After Approval
list.
Maciej W. Rozycki [Wed, 3 Nov 2021 17:04:19 +0000 (17:04 +0000)]
RISC-V: Fix register class subset checks for CLASS_MAX_NREGS
Fix the register class subset checks in the determination of the maximum
number of consecutive registers needed to hold a value of a given mode.
The number depends on whether a register is a general-purpose or a
floating-point register, so check whether the register class requested
is a subset (argument 1 to `reg_class_subset_p') rather than superset
(argument 2) of GR_REGS or FP_REGS class respectively.
gcc/
* config/riscv/riscv.c (riscv_class_max_nregs): Swap the
arguments to `reg_class_subset_p'.
Jonathan Wakely [Tue, 2 Nov 2021 10:21:01 +0000 (10:21 +0000)]
libstdc++: Fix regression in std::list::sort [PR66742]
The standard does not require const-correct comparisons in list::sort.
libstdc++-v3/ChangeLog:
PR libstdc++/66742
* include/bits/list.tcc (list::sort): Use mutable iterators for
comparisons.
* include/bits/stl_list.h (_Scratch_list::_Ptr_cmp): Likewise.
* testsuite/23_containers/list/operations/66742.cc: Check
non-const comparisons.
Joseph Myers [Wed, 3 Nov 2021 14:58:25 +0000 (14:58 +0000)]
c: Fold implicit integer-to-floating conversions in static initializers with -frounding-math [PR103031]
Recent fixes to avoid inappropriate folding of some conversions to
floating-point types with -frounding-math also prevented such folding
in C static initializers, when folding (in the default rounding mode,
exceptions discarded) is required for correctness.
Folding for static initializers is handled via functions in
fold-const.c calling START_FOLD_INIT and END_FOLD_INIT to adjust flags
such as flag_rounding_math that should not apply in static initializer
context, but no such function was being called for the folding of
these implicit conversions to the type of the object being
initialized, only for explicit conversions as part of the initializer.
Arrange for relevant folding (a fold call in convert, in particular)
to use this special initializer handling (via a new fold_init
function, in particular).
Because convert is used by language-independent code but defined in
each front end, this isn't as simple as just adding a new default
argument to it. Instead, I added a new convert_init function; that
then gets called by c-family code, and C and C++ need convert_init
implementations (the C++ one does nothing different from convert and
will never actually get called because the new convert_and_check
argument will never be true from C++), but other languages don't.
Bootstrapped with no regressions for x86_64-pc-linux-gnu.
gcc/
PR c/103031
* fold-const.c (fold_init): New function.
* fold-const.h (fold_init): New prototype.
gcc/c-family/
PR c/103031
* c-common.c (convert_and_check): Add argument init_const. Call
convert_init if init_const.
* c-common.h (convert_and_check): Update prototype.
(convert_init): New prototype.
gcc/c/
PR c/103031
* c-convert.c (c_convert): New function, based on convert.
(convert): Make into wrapper of c_convert.
(convert_init): New function.
* c-typeck.c (enum impl_conv): Add ic_init_const.
(convert_for_assignment): Handle ic_init_const like ic_init. Add
new argument to convert_and_check call.
(digest_init): Pass ic_init_const to convert_for_assignment for
initializers required to be constant.
gcc/cp/
PR c/103031
* cvt.c (convert_init): New function.
gcc/testsuite/
PR c/103031
* gcc.dg/init-rounding-math-1.c: New test.
Andrew MacLeod [Wed, 3 Nov 2021 01:26:44 +0000 (21:26 -0400)]
Switch vrp2 to ranger.
This patch flips the default for the VRP2 pass to execute ranger vrp rather
than the assert_expr version of VRP.
* params.opt (param_vrp2_mode): Make ranger the default for VRP2.
Andrew MacLeod [Mon, 1 Nov 2021 20:20:23 +0000 (16:20 -0400)]
Testcase adjustments for pass vrp1.
Unify testcases for the vrp1 pass so they will work with the output from either
VRP or ranger.
gcc/testsuite/
* gcc.dg/tree-ssa/pr23744.c: Tweak output checks.
* gcc.dg/tree-ssa/vrp07.c: Ditto.
* gcc.dg/tree-ssa/vrp08.c: Ditto.
* gcc.dg/tree-ssa/vrp09.c: Ditto.
* gcc.dg/tree-ssa/vrp20.c: Ditto.
* gcc.dg/tree-ssa/vrp92.c: Ditto.
* jit.dg/test-sum-of-squares.c: Ditto.
Andrew MacLeod [Tue, 2 Nov 2021 13:46:53 +0000 (09:46 -0400)]
For ranges, PHIs don't need to process arg == def.
If an argument of a phi is the same as the DEF of the phi, then the range
on the incoming edge doesn't need to be taken into account since it can't
be anything other than itself.
* gimple-range-fold.cc (fold_using_range::range_of_phi): Don't import
a range from edge if arg == phidef.
Andrew MacLeod [Mon, 1 Nov 2021 20:20:59 +0000 (16:20 -0400)]
Check for constant builtin value first.
The original code imported from EVRP for evaluating built_in_constant_p
didn't check to see if the value was a constant before checking the
inlining flag. Now we check for a constant first.
* gimple-range-fold.cc (fold_using_range::range_of_builtin_call): Test
for constant before any other processing.
Andrew MacLeod [Mon, 1 Nov 2021 20:40:45 +0000 (16:40 -0400)]
Fix --param=ranger-debug=all to include a trace.
A recent change made each debug flag its own value, but the 'all' value was
not adjusted properly and 'trace' was left out.
* flag-types.h (RANGER_DEBUG_ALL): Fix values.
Andrew MacLeod [Mon, 1 Nov 2021 17:32:11 +0000 (13:32 -0400)]
Provide some context to folding via ranger.
Provide an internal mechanism to supply context to range_of_expr for calls
to ::fold_stmt.
* gimple-range.cc (gimple_ranger::gimple_ranger): Initialize current_bb.
(gimple_ranger::range_of_expr): Pick up range_on_entry when there is
no explcit context and current_bb is set.
(gimple_ranger::fold_stmt): New.
* gimple-range.h (current_bb, fold_stmt): New.
* tree-vrp.c (rvrp_folder::fold_stmt): Call ranger's fold_stmt.
Richard Biener [Wed, 3 Nov 2021 12:26:48 +0000 (13:26 +0100)]
tree-optimization/102970 - remap cliques when translating over backedges
The following makes sure to remap (or rather drop for simplicity)
dependence info encoded in MR_DEPENDENCE_CLIQUE when PRE PHI translation
translates a reference over a backedge since that ends up interleaving
two different loop iterations which boils down to two different
inline copies.
2021-11-03 Richard Biener <rguenther@suse.de>
PR tree-optimization/102970
* tree-ssa-pre.c (phi_translate_1): Drop clique and base
when translating a MEM_REF over a backedge.
* g++.dg/opt/pr102970.C: New testcase.
Philipp Tomsich [Thu, 20 May 2021 19:57:48 +0000 (21:57 +0200)]
aarch64: enable Ampere-1 CPU
This adds support and a basic turning model for the Ampere Computing
"Ampere-1" CPU.
The Ampere-1 implements the ARMv8.6 architecture in A64 mode and is
modelled as a 4-wide issue (as with all modern micro-architectures,
the chosen issue rate is a compromise between the maximum dispatch
rate and the maximum rate of uops issued to the scheduler).
This adds the -mcpu=ampere1 command-line option and the relevant cost
information/tuning tables for the Ampere-1.
gcc/ChangeLog:
* config/aarch64/aarch64-cores.def (AARCH64_CORE): New Ampere-1 core.
* config/aarch64/aarch64-tune.md: Regenerate.
* config/aarch64/aarch64-cost-tables.h: Add extra costs for Ampere-1.
* config/aarch64/aarch64.c: Add tuning structures for Ampere-1.
* doc/invoke.texi: Add documentation for Ampere-1 core.
Wilco Dijkstra [Wed, 3 Nov 2021 12:51:41 +0000 (12:51 +0000)]
AArch64: Improve GOT addressing
Improve GOT addressing by treating the instructions as a pair. This reduces
register pressure and improves code quality significantly. SPECINT2017
improves by 0.6% with -fPIC and codesize is 0.73% smaller. Perlbench has
0.9% smaller codesize, 1.5% fewer executed instructions and is 1.8% faster
on Neoverse N1.
ChangeLog:
2021-11-02 Wilco Dijkstra <wdijkstr@arm.com>
* config/aarch64/aarch64.md (movsi): Add alternative for GOT accesses.
(movdi): Likewise.
(ldr_got_small_<mode>): Remove pattern.
(ldr_got_small_sidi): Likewise.
* config/aarch64/aarch64.c (aarch64_load_symref_appropriately): Keep
GOT accesses as moves.
(aarch64_print_operand): Correctly print got_lo12 in L specifier.
(aarch64_mov_operand_p): Make GOT accesses valid move operands.
* config/aarch64/constraints.md: Add new constraint Usw for GOT access.
Martin Liska [Wed, 3 Nov 2021 13:30:01 +0000 (14:30 +0100)]
gcov: Remove dead variable.
gcc/ChangeLog:
* gcov.c (read_line): Remove dead variable.
Martin Liska [Wed, 3 Nov 2021 09:38:21 +0000 (10:38 +0100)]
Rename predicate class to ipa_predicate
PR bootstrap/102828
gcc/ChangeLog:
* ipa-fnsummary.c (edge_predicate_pool): Rename predicate class to ipa_predicate.
(ipa_fn_summary::account_size_time): Likewise.
(edge_set_predicate): Likewise.
(set_hint_predicate): Likewise.
(add_freqcounting_predicate): Likewise.
(evaluate_conditions_for_known_args): Likewise.
(evaluate_properties_for_edge): Likewise.
(remap_freqcounting_preds_after_dup): Likewise.
(ipa_fn_summary_t::duplicate): Likewise.
(set_cond_stmt_execution_predicate): Likewise.
(set_switch_stmt_execution_predicate): Likewise.
(compute_bb_predicates): Likewise.
(will_be_nonconstant_expr_predicate): Likewise.
(will_be_nonconstant_predicate): Likewise.
(phi_result_unknown_predicate): Likewise.
(predicate_for_phi_result): Likewise.
(analyze_function_body): Likewise.
(compute_fn_summary): Likewise.
(summarize_calls_size_and_time): Likewise.
(estimate_calls_size_and_time): Likewise.
(ipa_call_context::estimate_size_and_time): Likewise.
(remap_edge_summaries): Likewise.
(remap_freqcounting_predicate): Likewise.
(ipa_merge_fn_summary_after_inlining): Likewise.
(ipa_update_overall_fn_summary): Likewise.
(read_ipa_call_summary): Likewise.
(inline_read_section): Likewise.
* ipa-fnsummary.h (struct ipa_freqcounting_predicate): Likewise.
* ipa-predicate.c (predicate::add_clause): Likewise.
(ipa_predicate::add_clause): Likewise.
(predicate::or_with): Likewise.
(ipa_predicate::or_with): Likewise.
(predicate::evaluate): Likewise.
(ipa_predicate::evaluate): Likewise.
(predicate::probability): Likewise.
(ipa_predicate::probability): Likewise.
(dump_condition): Likewise.
(dump_clause): Likewise.
(predicate::dump): Likewise.
(ipa_predicate::dump): Likewise.
(predicate::debug): Likewise.
(ipa_predicate::debug): Likewise.
(predicate::remap_after_duplication): Likewise.
(ipa_predicate::remap_after_duplication): Likewise.
(predicate::remap_after_inlining): Likewise.
(ipa_predicate::remap_after_inlining): Likewise.
(predicate::stream_in): Likewise.
(ipa_predicate::stream_in): Likewise.
(predicate::stream_out): Likewise.
(ipa_predicate::stream_out): Likewise.
(add_condition): Likewise.
* ipa-predicate.h (class predicate): Likewise.
(class ipa_predicate): Likewise.
(add_condition): Likewise.
Richard Biener [Wed, 3 Nov 2021 08:57:21 +0000 (09:57 +0100)]
Make sbitmap bitmap_set_bit and bitmap_clear_bit return changed state
The following adjusts the sbitmap bitmap_set_bit and bitmap_clear_bit
APIs to match that of bitmap by returning a bool indicating whether
the bitmap was changed. I've also changed bitmap_bit_p to return
a bool rather than an int and made use of the sbitmap bitmap_set_bit
API change in one place.
2021-11-03 Richard Biener <rguenther@suse.de>
* bitmap.h (bitmap_bit_p): Change the return type to bool.
* bitmap.c (bitmap_bit_p): Likewise.
* sbitmap.h (bitmap_bit_p): Likewise.
(bitmap_set_bit): Return whether the bit changed.
(bitmap_clear_bit): Likewise.
* tree-ssa.c (verify_vssa): Make use of the changed state
from bitmap_set_bit.
Richard Biener [Wed, 3 Nov 2021 10:10:19 +0000 (11:10 +0100)]
middle-end/103033 - drop native_interpret_expr with .DEFERRED_INIT expansion
This drops the use of native_interpret_expr which can fail even though
can_native_interpret_expr_p returns true in favor of simply folding
the VIEW_CONVERT_EXPR punning.
2021-11-03 Richard Biener <rguenther@suse.de>
PR middle-end/103033
* internal-fn.c (expand_DEFERRED_INIT): Elide the
native_interpret_expr path in favor of folding the
VIEW_CONVERT_EXPR generated when punning the RHS.
Stefan Schulze Frielinghaus [Wed, 3 Nov 2021 08:39:27 +0000 (09:39 +0100)]
IBM Z: Free bbs in s390_loop_unroll_adjust
gcc/ChangeLog:
* config/s390/s390.c (s390_loop_unroll_adjust): In case of early
exit free bbs.
Jan Hubicka [Wed, 3 Nov 2021 00:45:47 +0000 (01:45 +0100)]
Fix wrong code caulsed by retslot EAF flags propagation [PR103040]
Fixe (quite nasty) thinko in how I propagate EAF flags from callee
to caller. In this case some flags needs to be changed. In particular
- EAF_NOT_RETURNED in callee does not really mean EAF_NOT_RETURNED in caller
since we speak of different return values
- if callee escapes the parametr, we caller may return it
- for retslot the rewritting is even bit more funny, since escaping to of
return slot to return slot is not really an escape, however escape of
argument to itself is.
This patch should correct all of the cases above and does fix the testcase from PR103040.
Bootstrapped/regtested x86_64 with all languages. Also lto-bootstrapped.
gcc/ChangeLog:
PR ipa/103040
* ipa-modref.c (callee_to_caller_flags): New function.
(modref_eaf_analysis::analyze_ssa_name): Use it.
(ipa_merge_modref_summary_after_inlining): Fix whitespace.
gcc/testsuite/ChangeLog:
* g++.dg/torture/pr103040.C: New test.
GCC Administrator [Wed, 3 Nov 2021 00:16:30 +0000 (00:16 +0000)]
Daily bump.
Jonathan Wakely [Mon, 1 Nov 2021 19:11:47 +0000 (19:11 +0000)]
libstdc++: Add some noexcept to std::valarray
libstdc++-v3/ChangeLog:
* include/std/valarray (valarray::valarray()): Add noexcept.
(valarray::operator[]): Likewise.
Jan Hubicka [Tue, 2 Nov 2021 22:07:15 +0000 (23:07 +0100)]
Revert accidental commit.
2021-11-02 Jan Hubicka <hubicka@ucw.cz>
* ipa-modref.c (modref_eaf_analysis::analyze_ssa_name): Revert
accidental commit.
Roger Sayle [Tue, 2 Nov 2021 21:58:32 +0000 (21:58 +0000)]
x86_64: Improved implementation of TImode rotations.
This simple patch improves the implementation of 128-bit (TImode)
rotations on x86_64 (a missed optimization opportunity spotted
during the recent V1TImode improvements).
Currently, the function:
unsigned __int128 rotrti3(unsigned __int128 x, unsigned int i) {
return (x >> i) | (x << (128-i));
}
produces:
rotrti3:
movq %rsi, %r8
movq %rdi, %r9
movl %edx, %ecx
movq %rdi, %rsi
movq %r9, %rax
movq %r8, %rdx
movq %r8, %rdi
shrdq %r8, %rax
shrq %cl, %rdx
xorl %r8d, %r8d
testb $64, %cl
cmovne %rdx, %rax
cmovne %r8, %rdx
negl %ecx
andl $127, %ecx
shldq %r9, %rdi
salq %cl, %rsi
xorl %r9d, %r9d
testb $64, %cl
cmovne %rsi, %rdi
cmovne %r9, %rsi
orq %rdi, %rdx
orq %rsi, %rax
ret
with this patch, GCC will now generate the much nicer:
rotrti3:
movl %edx, %ecx
movq %rdi, %rdx
shrdq %rsi, %rdx
shrdq %rdi, %rsi
andl $64, %ecx
movq %rdx, %rax
cmove %rsi, %rdx
cmovne %rsi, %rax
ret
Even I wasn't expecting the optimizer's choice of the final three
instructions; a thing of beauty. For rotations larger than 64,
the lowpart and the highpart (%rax and %rdx) are transposed, and
it would be nice to have a conditional swap/exchange. The inspired
solution the compiler comes up with is to store/duplicate the same
value in both %rax/%rdx, and then use complementary conditional moves
to either update the lowpart or highpart, which cleverly avoids the
potential decode-stage pipeline stall (on some microarchitectures)
from having multiple instructions conditional on the same condition.
See X86_TUNE_ONE_IF_CONV_INSN, and notice there are two such stalls
in the original expansion of rot[rl]ti3.
2021-11-02 Roger Sayle <roger@nextmovesoftware.com>
Uroš Bizjak <ubizjak@gmail.com>
* config/i386/i386.md (<any_rotate>ti3): Provide expansion for
rotations by non-constant amounts.
Jan Hubicka [Tue, 2 Nov 2021 21:08:56 +0000 (22:08 +0100)]
ipa-modref cleanup
A small refactoring of ipa-modref to make it bit more
C++y by moving logic analyzing ssa name flags to a class
and I also moved the anonymous namespace markers so we do not
export unnecessary stuff. There are no functional changes.
Bootstrapped/regtested x86_64-linux, will commit it shortly.
gcc/ChangeLog:
* ipa-modref.c: Fix anonymous namespace placement.
(class modref_eaf_analysis): New class.
(analyze_ssa_name_flags): Turn to ...
(modref_eaf_analysis::analyze_ssa_name): ... this one.
(merge_call_lhs_flags): Turn to ...
(modref_eaf_analysis::merge_call_lhs_flags): .. this one
(modref_eaf_analysis::merge_with_ssa_name): New member function.
(record_escape_points): Turn to ...
(modref_eaf_analysis::record_escape_points): ... this one.
(analyze_parms): Updat
(ipa_merge_modref_summary_after_inlining): Move to the end of file.
Jan Hubicka [Tue, 2 Nov 2021 17:57:51 +0000 (18:57 +0100)]
Static chain support in ipa-modref
Teach ipa-modref about the static chain that is, like
retslot, a hiden argument. The patch is pretty much symemtric to what
was done for retslot handling and I verified it does the intended job
for Ada LTO bootstrap.
gcc/ChangeLog:
* gimple.c (gimple_call_static_chain_flags): New function.
* gimple.h (gimple_call_static_chain_flags): Declare
* ipa-modref.c (modref_summary::modref_summary): Initialize
static_chain_flags.
(modref_summary_lto::modref_summary_lto): Likewise.
(modref_summary::useful_p): Test static_chain_flags.
(modref_summary_lto::useful_p): Likewise.
(struct modref_summary_lto): Add static_chain_flags.
(modref_summary::dump): Dump static_chain_flags.
(modref_summary_lto::dump): Likewise.
(struct escape_point): Add static_cahin_arg.
(analyze_ssa_name_flags): Use gimple_call_static_chain_flags.
(analyze_parms): Handle static chains.
(modref_summaries::duplicate): Duplicate static_chain_flags.
(modref_summaries_lto::duplicate): Likewise.
(modref_write): Stream static_chain_flags.
(read_section): Likewise.
(modref_merge_call_site_flags): Handle static_chain_flags.
* ipa-modref.h (struct modref_summary): Add static_chain_flags.
* tree-ssa-structalias.c (handle_rhs_call): Use
gimple_static_chain_flags.
gcc/testsuite/ChangeLog:
* gcc.dg/ipa/modref-3.c: New test.
Richard Biener [Tue, 2 Nov 2021 17:47:14 +0000 (18:47 +0100)]
tree-optimization/103029 - ensure vect loop versioning constraint on PHIs
PHI nodes in vectorizer loop versioning need to maintain the same
order of PHI arguments to not disturb SLP discovery. The following
adds an assertion and mitigation in case loop versioning breaks this
which happens more often after the recent reorg.
2021-11-02 Richard Biener <rguenther@suse.de>
PR tree-optimization/103029
* tree-vect-loop-manip.c (vect_loop_versioning): Ensure
the PHI nodes in the loop maintain their original operand
order.
Jan Hubicka [Tue, 2 Nov 2021 17:43:17 +0000 (18:43 +0100)]
addS EAF_NOT_RETURNED_DIRECTLY
addS EAF_NOT_RETURNED_DIRECTLY which works similarly as
EAF_NODIRECTESCAPE. Values pointed to by a given argument may be returned but
not the argument itself. This helps PTA quite noticeably because we mostly
care about tracking points to which given memory location can escape.
gcc/ChangeLog:
* tree-core.h (EAF_NOT_RETURNED_DIRECTLY): New flag.
(EAF_NOREAD): Renumber.
* ipa-modref.c (dump_eaf_flags): Dump EAF_NOT_RETURNED_DIRECTLY.
(remove_useless_eaf_flags): Handle EAF_NOT_RETURNED_DIRECTLY
(deref_flags): Likewise.
(modref_lattice::init): Likewise.
(modref_lattice::merge): Likewise.
(merge_call_lhs_flags): Likewise.
(analyze_ssa_name_flags): Likewise.
(modref_merge_call_site_flags): Likewise.
* tree-ssa-structalias.c (handle_call_arg): Likewise.
gcc/testsuite/ChangeLog:
* g++.dg/ipa/modref-1.C: Update template.
* gcc.dg/tree-ssa/modref-10.c: New test.
Maciej W. Rozycki [Tue, 2 Nov 2021 16:05:00 +0000 (16:05 +0000)]
RISC-V: Fix build errors with shNadd/shNadd.uw patterns in zba cost model
Fix a build regression from commit
04a9b554ba1a ("RISC-V: Cost model
for zba extension."):
.../gcc/config/riscv/riscv.c: In function 'bool riscv_rtx_costs(rtx, machine_mode, int, int, int*, bool)':
.../gcc/config/riscv/riscv.c:2018:11: error: 'and' of mutually exclusive equal-tests is always 0 [-Werror]
2018 | && IN_RANGE (INTVAL (XEXP (XEXP (x, 0), 0)), 1, 3))
| ^~
.../gcc/config/riscv/riscv.c:2047:17: error: unused variable 'ashift_lhs' [-Werror=unused-variable]
2047 | rtx ashift_lhs = XEXP (and_lhs, 0);
| ^~~~~~~~~~
by correcting a CONST_INT_P check referring the wrong operand and
getting rid of the unused variable.
gcc/
* config/riscv/riscv.c (riscv_rtx_costs): Correct a CONST_INT_P
check and remove an unused local variable with shNadd/shNadd.uw
pattern handling.
Stefan Schulze Frielinghaus [Tue, 2 Nov 2021 14:54:08 +0000 (15:54 +0100)]
IBM Z: ldist-{rawmemchr,strlen} tests require vector extensions
The tests require vector extensions which are only available for z13 and
later while using the z/Architecture.
gcc/testsuite/ChangeLog:
* gcc.dg/tree-ssa/ldist-rawmemchr-1.c: For IBM Z set arch to z13
and use z/Architecture since the tests require vector extensions.
* gcc.dg/tree-ssa/ldist-rawmemchr-2.c: Likewise.
* gcc.dg/tree-ssa/ldist-strlen-1.c: Likewise.
* gcc.dg/tree-ssa/ldist-strlen-3.c: Likewise.
Tamar Christina [Tue, 2 Nov 2021 13:26:36 +0000 (13:26 +0000)]
middle-end: Fix PR103007, add missing check on complex fms detection.
The complex FMS detection is missing a check on if the nodes of the VEC_PERM
has the amount of children we expect before it recurses.
This check is there on MUL and FMA but was missing for FMS, due to this the
compiler goes on further than it should and hits an assert.
gcc/ChangeLog:
PR tree-optimization/103007
* tree-vect-slp-patterns.c (complex_fms_pattern::matches): Add elem
check.
gcc/testsuite/ChangeLog:
PR tree-optimization/103007
* g++.dg/pr103007.C: New test.
Richard Biener [Tue, 2 Nov 2021 08:58:00 +0000 (09:58 +0100)]
middle-end/103038 - avoid ICE with -ftrivial-auto-var-init=pattern
This avoids ICEing with expanding a VIEW_CONVERT_EXRP of a SSA name
on the LHS by making sure we can native-interpret OFFSET_TYPE and
by never building such a LHS but instead view-converting the RHS
for SSA LHS.
2021-11-02 Richard Biener <rguenther@suse.de>
PR middle-end/103038
* fold-const.c (native_interpret_expr): Handle OFFSET_TYPE.
(can_native_interpret_type_p): Likewise.
* internal-fn.c (expand_DEFERRED_INIT): View-convert the
RHS if the LHS is an SSA name.
* g++.dg/pr103038.C: New testcase.
Richard Sandiford [Tue, 2 Nov 2021 10:51:23 +0000 (10:51 +0000)]
Add a simulate_record_decl lang hook
This patch adds a lang hook for defining a struct/RECORD_TYPE
“as if” it had appeared directly in the source code. It follows
the similar existing hook for enums.
It's the caller's responsibility to create the fields
(as FIELD_DECLs) but the hook's responsibility to create
and declare the associated RECORD_TYPE.
For now the hook is hard-coded to do the equivalent of:
typedef struct NAME { FIELDS } NAME;
but this could be controlled by an extra parameter if some callers
want a different behaviour in future.
The motivating use case is to allow the long list of struct
definitions in arm_neon.h to be provided by the compiler,
which in turn unblocks various arm_neon.h optimisations.
gcc/
* langhooks.h (lang_hooks_for_types::simulate_record_decl): New hook.
* langhooks-def.h (lhd_simulate_record_decl): Declare.
(LANG_HOOKS_SIMULATE_RECORD_DECL): Define.
(LANG_HOOKS_FOR_TYPES_INITIALIZER): Include it.
* langhooks.c (lhd_simulate_record_decl): New function.
gcc/c/
* c-tree.h (c_simulate_record_decl): Declare.
* c-objc-common.h (LANG_HOOKS_SIMULATE_RECORD_DECL): Override.
* c-decl.c (c_simulate_record_decl): New function.
gcc/cp/
* decl.c: Include langhooks-def.h.
(cxx_simulate_record_decl): New function.
* cp-objcp-common.h (cxx_simulate_record_decl): Declare.
(LANG_HOOKS_SIMULATE_RECORD_DECL): Override.
Andrew Burgess [Tue, 2 Nov 2021 09:27:44 +0000 (09:27 +0000)]
update my email address
Update my email address, and move myself into the Write After Approval
list - I've not done any ARC work for years now.
/
* MAINTAINERS (Reviewers, arc): Remove my entry.
(Write After Approval): Add an entry for myself.
Martin Liska [Tue, 2 Nov 2021 09:27:27 +0000 (10:27 +0100)]
Fix flake8 errors.
contrib/ChangeLog:
* check-internal-format-escaping.py: Fix flake8 errors.
Jakub Jelinek [Tue, 2 Nov 2021 08:44:24 +0000 (09:44 +0100)]
ia32: Disallow mode(V1TI) [PR103020]
As discussed in the PR, TImode isn't supported for -m32 on x86 (for the same
reason as on most 32-bit targets, no support for > 2 * BITS_PER_WORD
precision integers), but since PR32280 V1TImode is allowed with -msse in SSE
regs, V2TImode with -mavx or V4TImode with -mavx512f.
typedef __int128 V __attribute__((vector_size ({16,32,64}));
will not work, neither typedef int I __attribute__((mode(TI)));
but mode(V1TI), mode(V2TI) etc. are accepted with a warning when those
ISAs are enabled. But they are certainly not fully supported, for some
optabs maybe, but most of them will not. And, veclower lowering those ops
to TImode scalar operations will not work either because TImode isn't
supported.
So, this patch keeps V1TImode etc. in VALID*_MODE macros so that we can use
it in certain instructions, but disallows it in
targetm.vector_mode_supported_p, so that we don't offer those modes to the
user as supported.
2021-11-02 Jakub Jelinek <jakub@redhat.com>
PR target/103020
* config/i386/i386.c (ix86_vector_mode_supported_p): Reject vector
modes with TImode inner mode if 32-bit.
* gcc.target/i386/pr103020.c: New test.