Fangrui Song [Tue, 9 Feb 2021 08:43:10 +0000 (00:43 -0800)]
[ELF] Drop Android specific workaround -m aarch64_elf64_le_vec
`extern const bfd_target aarch64_elf64_le_vec;` is a variable in BFD.
It was somehow misused as an emulation by Android.
```
% aarch64-linux-gnu-ld -m aarch64_elf64_le_vec a.o
aarch64-linux-gnu-ld: unrecognised emulation mode: aarch64_elf64_le_vec
Supported emulations: aarch64linux aarch64elf aarch64elf32 aarch64elf32b aarch64elfb armelf armelfb aarch64linuxb aarch64linux32 aarch64linux32b armelfb_linux_eabi armelf_linux_eabi
```
Acked by Stephen Hines, who removed the flag from Android a while back.
Valeriy Savchenko [Mon, 8 Feb 2021 15:47:21 +0000 (18:47 +0300)]
[-Wcompletion-handler] Support checks with builtins
It is very common to check callbacks and completion handlers for null.
This patch supports such checks using built-in functions:
* __builtin_expect
* __builtin_expect_with_probablity
* __builtin_unpredictable
rdar://
73455388
Differential Revision: https://reviews.llvm.org/D96268
Hongtao Yu [Sat, 6 Feb 2021 01:56:45 +0000 (17:56 -0800)]
[ELF] Rewriting the path of sample profile file for --reproduce response.txt
Rewritting the path of the sample profile file in response.txt to be relative to the repro tar.
Reviewed By: MaskRay
Differential Revision: https://reviews.llvm.org/D96193
Chuanqi Xu [Tue, 9 Feb 2021 07:52:11 +0000 (15:52 +0800)]
[NFC] [Coroutine] Remove Unused Variables
Hsiangkai Wang [Tue, 9 Feb 2021 06:43:10 +0000 (14:43 +0800)]
[RISCV] Use whole register load/store for generic load/store.
In vector v0.10, there are whole vector register load/store
instructions. I suggest to use the whole register load/store
instructions for generic load/store for scalable vector types. It could
save up vset{i}vl{i} for these load/store.
For fractional LMUL, I keep to use vle{eew}.v/vse{eew}.v instructions to
load/store partial vector registers.
Differential Revision: https://reviews.llvm.org/D95853
Zakk Chen [Tue, 9 Feb 2021 07:43:32 +0000 (23:43 -0800)]
[Docs] Fix Typo
Matthias Springer [Tue, 9 Feb 2021 07:43:04 +0000 (16:43 +0900)]
[MLIR][AVX512] Add integration test for vp2intersect
Differential Revision: https://reviews.llvm.org/D96306
Fangrui Song [Tue, 9 Feb 2021 07:36:37 +0000 (23:36 -0800)]
[test] Drop redundant REQUIRES: x86-registered-target
Fangrui Song [Tue, 9 Feb 2021 07:34:41 +0000 (23:34 -0800)]
[test] Add REQUIRES: x86-registered-target to DebugInfo/Symbolize/ELF llvm-mc tests
Douglas Yung [Tue, 9 Feb 2021 06:47:14 +0000 (22:47 -0800)]
Mark 4 tests added in
6d766c8bf9df as requiring an x86 backend as they fail when it is not present.
This should fix buildbot failures like http://lab.llvm.org:8011/#/builders/107/builds/4469
Kazu Hirata [Tue, 9 Feb 2021 06:33:53 +0000 (22:33 -0800)]
[Transforms] Use range-based for loops (NFC)
Kazu Hirata [Tue, 9 Feb 2021 06:33:51 +0000 (22:33 -0800)]
[TableGen] Use ListSeparator (NFC)
Kazu Hirata [Tue, 9 Feb 2021 06:33:49 +0000 (22:33 -0800)]
[Transforms/Utils] Drop unnecessary const from a return type (NFC)
Identified with const-return-type.
Max Kazantsev [Tue, 9 Feb 2021 04:00:12 +0000 (11:00 +0700)]
Return "[Test] Add failing test for PR49087"
Another attempt, this time with tripple fix.
George [Tue, 9 Feb 2021 03:54:19 +0000 (19:54 -0800)]
[MLIR] Add C API for navigating up the IR tree
Reviewed By: mehdi_amini
Differential Revision: https://reviews.llvm.org/D96301
Sam Clegg [Tue, 9 Feb 2021 01:12:23 +0000 (17:12 -0800)]
[lld][WebAssembly] Fix typo in function name
addOptionalGlobalSymbols should be addOptionalGlobalSymbol.
Also, remove unnecessary additional argument to make the signature match
the sibling function: addOptionalDataSymbol.
Differential Revision: https://reviews.llvm.org/D96305
Yaxun (Sam) Liu [Tue, 19 Jan 2021 22:35:23 +0000 (17:35 -0500)]
[CUDA][HIP] Add -fuse-cuid
This patch added a distinct CUID for each input file, which is represented by InputAction.
clang initially creates an InputAction for each input file for the host compilation. In CUDA/HIP action
builder, each InputAction is given a CUID and cloned for each GPU arch, and the CUID is also cloned. In this way,
we guarantee the corresponding device and host compilation for the same file shared the
same CUID. On the other hand, different compilation units have different CUID.
-fuse-cuid=random|hash|none is added to control the method to generate CUID. The default
is hash. -cuid=X is also added to specify CUID explicitly, which overrides -fuse-cuid.
Reviewed by: Artem Belevich
Differential Revision: https://reviews.llvm.org/D95007
Dave Lee [Tue, 9 Feb 2021 01:33:53 +0000 (17:33 -0800)]
[lldb] Fix crash in FormatEntity for mangled-name
Check a `Block` pointer before dereferencing.
Using `function.mangled-name` led to a crash for a frame where the symbol
context had no block info. In my case, the frame's function was a system frame.
Differential Revision: https://reviews.llvm.org/D96307
Jinsong Ji [Tue, 9 Feb 2021 02:12:54 +0000 (02:12 +0000)]
Revert "[CostModel] Remove VF from IntrinsicCostAttributes"
This reverts commit
502a67dd7f23901834e05071ab253889f671b5d9.
This expose a failure in test-suite build on PowerPC,
revert to unblock buildbot first,
Dave will re-commit in https://reviews.llvm.org/D96287.
Thanks Dave.
Richard Smith [Tue, 9 Feb 2021 01:58:05 +0000 (17:58 -0800)]
PR48606: The lifetime of a constexpr heap allocation always started
during the same evaluation.
It looks like the only case for which this matters is determining
whether mutable subobjects of a heap allocation can be modified during
constant evaluation.
Richard Smith [Tue, 9 Feb 2021 01:32:52 +0000 (17:32 -0800)]
PR48587: is_constant_evaluated() should not evaluate to true during a
variable's destruction if it didn't do so during construction.
The standard doesn't give any guidance as to what to do here, but this
approach seems reasonable and conservative, and has been proposed to the
standard committee.
Fangrui Song [Tue, 9 Feb 2021 01:22:22 +0000 (17:22 -0800)]
[llvm-objcopy][test] Stablize build-id-link-dir.test
LLVM GN Syncbot [Tue, 9 Feb 2021 01:14:44 +0000 (01:14 +0000)]
[gn build] Port
87104faac433
Greg McGary [Sat, 26 Sep 2020 20:00:22 +0000 (13:00 -0700)]
[lld-macho] Add ARM64 target arch
This is an initial base commit for ARM64 target arch support. I don't represent that it complete or bug-free, but wish to put it out for review now that some basic things like branch target & load/store address relocs are working.
I can add more tests to this base commit, or add them in follow-up commits.
It is not entirely clear whether I use the "ARM64" (Apple) or "AArch64" (non-Apple) naming convention. Guidance is appreciated.
Differential Revision: https://reviews.llvm.org/D88629
Sam Clegg [Mon, 8 Feb 2021 02:51:42 +0000 (18:51 -0800)]
[MC][WebAssembly] Fix provisional values for data alias relocations
When calculating the symbol offsets to write as provisitonal values
in object files we are only interested in the offset of the symbol
itself. For aliases this offset already includes the offset of the
base symbol.
The testin question was added back in https://reviews.llvm.org/D87407
but I believe the expectations here were incorrect. sym_a lives
at offset 4 and sym_b lives 4 bytes into that (should be 8).
The addresses of the 3 symbosl in this object file are:
foo : 0
sym_a: 4
sym_b: 8
Differential Revision: https://reviews.llvm.org/D96234
Craig Topper [Tue, 9 Feb 2021 00:25:18 +0000 (16:25 -0800)]
[TableGen] Use return value from EmitVBRValue instead of calling GetVBRSize on the same value. Consistently use unsigned for child sizes. NFCI
getSize and setSize both use unsigned. So size_t doesn't
increase range here and might get truncated if passed to
setSize.
Also not sure why EmitVBRValue was returning uint64_t, but used
an unsigned to supply the value.
Uday Bondhugula [Sun, 7 Feb 2021 06:30:22 +0000 (12:00 +0530)]
[MLIR][NFC] Fix std.copysign op documentation
Fix std.copysign op documentation. NFC.
Differential Revision: https://reviews.llvm.org/D96217
Yaxun (Sam) Liu [Tue, 9 Feb 2021 00:27:17 +0000 (19:27 -0500)]
Fix failure in cuda-external-tools.cu
-fgpu-rdc is output in different order
LemonBoy [Tue, 9 Feb 2021 00:23:38 +0000 (19:23 -0500)]
[SPARC] Recognize and handle the %lm(sym) operator
Reviewed By: joerg
Differential Revision: https://reviews.llvm.org/D77737
Jameson Nash [Tue, 9 Feb 2021 00:11:08 +0000 (19:11 -0500)]
Revert "Renovate CMake files in the `llvm-exegesis` tool."
This reverts commit
549a1e2e59508d4aeaf9a93912b479798954bd5e.
I see some buildbot failures, so reverting while I look into them.
Argyrios Kyrtzidis [Mon, 8 Feb 2021 08:24:31 +0000 (00:24 -0800)]
Make sure a module file with errors produced via '-fallow-pcm-with-compiler-errors' can be loaded when using implicit modules
A module with errors would be marked as out-of-date, then the `compilerModule` action would produce it, but due to the error it would be treated as failure and the resulting PCM would not get used.
rdar://
74087062
Differential Revision: https://reviews.llvm.org/D96246
Yaxun (Sam) Liu [Mon, 8 Feb 2021 23:51:31 +0000 (18:51 -0500)]
[CUDA][HIP] Pass -fgpu-rdc to host clang -cc1
Currently -fgpu-rdc is not passed to host clang -cc1.
This causes issue because -fgpu-rdc affects shadow
variable linkage in host compilation.
Reviewed by: Artem Belevich
Differential Revision: https://reviews.llvm.org/D96105
Eric Schweitz [Mon, 8 Feb 2021 21:47:16 +0000 (13:47 -0800)]
[flang][fir] Add OpaqueAttr.
Add the opaque attribute class used in flang.
https://github.com/flang-compiler/f18-llvm-project/pull/402
Differential Revision: https://reviews.llvm.org/D96293
Jameson Nash [Mon, 8 Feb 2021 23:20:16 +0000 (18:20 -0500)]
Renovate CMake file for the `llvm-cfi-verify` tool
Hopefully this is the non-problematic part from https://reviews.llvm.org/rL342148, which later got reverted in r342336 (
b09a8c9bd9b819741b38071a7ccd95042ef2643a) due to problems with the llvm-exegesis part of the change. That part would also still be desirable, but currently appears not to be possible (https://reviews.llvm.org/D81922).
I think this should replace https://reviews.llvm.org/D44650, per Keno's comment there.
Reviewed By: hctim
Differential Revision: https://reviews.llvm.org/D90969
Jameson Nash [Mon, 8 Feb 2021 23:03:23 +0000 (18:03 -0500)]
Renovate CMake files in the `llvm-exegesis` tool.
This attempts to move all tools over to using `add_llvm_library` for
better consistency. After doing this, I noticed it ended up as nearly a
reimplementation of https://reviews.llvm.org/rL342148, which later got
reverted in r342336 (
b09a8c9bd9b819741b38071a7ccd95042ef2643a).
With ccache and ninja on a large core machine (40), I haven't run into
build errors, so I'm hopeful it's better now, though it doesn't seem to
be any different / new.
Reviewed By: stephenneuendorffer
Differential Revision: https://reviews.llvm.org/D90970
Hsiangkai Wang [Wed, 27 Jan 2021 07:00:46 +0000 (15:00 +0800)]
[RISCV] Initial support of LoopVectorizer for RISC-V Vector.
Define an option -riscv-vector-bits-max to specify the maximum vector
bits for vectorizer. Loop vectorizer will use the value to check if it
is safe to use the whole vector registers to vectorize the loop.
It is not the optimum solution for loop vectorizing for scalable vector.
It assumed the whole vector registers will be used to vectorize the code.
If it is possible, we should configure vl to do vectorize instead of
using whole vector registers.
We only consider LMUL = 1 in this patch.
This patch just an initial work for loop vectorizer for RISC-V Vector.
Differential Revision: https://reviews.llvm.org/D95659
Matt Arsenault [Mon, 8 Feb 2021 21:53:42 +0000 (16:53 -0500)]
GlobalISel: Use correct calling convention in handleAssignments
This was using the calling convention of the calling function, not the
callee. Avoids regressions in a future patch.
Matt Arsenault [Sun, 7 Feb 2021 17:12:09 +0000 (12:12 -0500)]
AMDGPU: Stop adding stack passed wide arguments to call conv handler
The generated calling convention code shouldn't see these types since
we split large types into 32-bit chunks before the calling convention
code is triggered.
GlobalISel ends up directly calls the generated CC code before
checking for the register count breakdown. Arguably this difference is
a bug, but this was dead code for the DAG anyway.
Matt Arsenault [Sun, 7 Feb 2021 21:15:08 +0000 (16:15 -0500)]
AMDGPU/GlobalISel: Remove dead check prefixes
Arthur Eubanks [Mon, 8 Feb 2021 21:52:14 +0000 (13:52 -0800)]
[NVPTX][NewPM] Re-enable NVVMReflectPass
Disabled alongside NVVMIntrRangePass in https://reviews.llvm.org/D96166,
but turns out NVVMIntrRangePass was the issue.
Reviewed By: tra
Differential Revision: https://reviews.llvm.org/D96291
Eric Schweitz [Mon, 8 Feb 2021 21:49:16 +0000 (13:49 -0800)]
[flang][NFC] Add comment.
Fangrui Song [Mon, 8 Feb 2021 21:44:29 +0000 (13:44 -0800)]
[test] Fix unused check prefixes
Fangrui Song [Mon, 8 Feb 2021 21:37:03 +0000 (13:37 -0800)]
[FileCheck] Default --allow-unused-prefixes to false
Link: https://lists.llvm.org/pipermail/llvm-dev/2020-October/146162.html
If a downstream project using lit needs time for transition,
add the following to `lit.local.cfg`:
```
from lit.llvm.subst import ToolSubst
fc = ToolSubst('FileCheck', unresolved='fatal')
config.substitutions.insert(0, (fc.regex, 'FileCheck --allow-unused-prefixes'))
```
Differential Revision: https://reviews.llvm.org/D95849
Fangrui Song [Mon, 8 Feb 2021 21:31:05 +0000 (13:31 -0800)]
[Verifier] Allow DW_TAG_class_type/DW_TAG_union_type to have no filename
`clang/lib/CodeGen/CGOpenMPRuntime.cpp` synthesized union
(`distinct !DICompositeType(tag: DW_TAG_union_type, name: "kmp_cmplrdata_t", size: 64, elements: <0x62b690>)`)
does not have meaningful filename/line number.
D94735 dropped the previously arbitrary and untested filename/line from the union and caused a verifier error here.
This fixes `check-libarcher` failures.
Differential Revision: https://reviews.llvm.org/D96212
David Green [Mon, 8 Feb 2021 21:24:32 +0000 (21:24 +0000)]
[ARM] One-off identity shuffle
A One-Off Identity mask is a shuffle that is mostly an identity mask
from as single source but contains a single element out-of-place, either
from a different vector or from another position in the same vector. As
opposed to lowering this via a ARMISD::BUILD_VECTOR we can generate an
extract/insert pair directly. Under ARM with individually accessible
lane elements this often becomes a simple lane move.
This also alters the LowerVECTOR_SHUFFLEUsingMovs code to use v4f32 (not
v4i32), a more natural type for lane moves.
Differential Revision: https://reviews.llvm.org/D95551
Arthur Eubanks [Mon, 8 Feb 2021 20:52:20 +0000 (12:52 -0800)]
[SimpleLoopUnswitch] Don't non-trivially unswitch loops that are unsafe to clone
Non-trivial unswitching can clone loops.
The legacy -loop-unswitch pass also checks for this.
Fixes PR49085.
Reviewed By: asbirlea
Differential Revision: https://reviews.llvm.org/D96288
Nico Weber [Mon, 8 Feb 2021 21:10:59 +0000 (16:10 -0500)]
[gn build] reformat all gn files
$ git ls-files '*.gn' '*.gni' | xargs llvm/utils/gn/gn.py format
Markus Böck [Mon, 8 Feb 2021 21:04:04 +0000 (23:04 +0200)]
[CMake] [MinGW] Enable use of LLVM_USE_SANITIZER in a MinGW environment
Currently using LLVM_USE_SANITIZER with a MinGW target leads to a fatal
configuration error due to an unsupported platform. MinGW targets on
clang however implement a few sanitizers, currently ASAN and UBSAN.
This patch enables LLVM_USE_SANITIZER in a MinGW environment as well.
Differential Revision: https://reviews.llvm.org/D95750
Amara Emerson [Wed, 3 Feb 2021 18:33:48 +0000 (10:33 -0800)]
[AArch64][GlobalISel] Support the 'returned' parameter attribute.
On AArch64 (which seems to be the only target that supports it), this
attribute allows codegen to avoid saving/restoring the value in x0
across a call.
Gives a 0.1% geomean -Os code size improvement on CTMark.
Differential Revision: https://reviews.llvm.org/D96099
Nico Weber [Mon, 8 Feb 2021 20:46:29 +0000 (15:46 -0500)]
Revert "[Test] Add failing test for PR49087"
This reverts commit
0fc1738eb75d613b9e16143b83e7cb80512e84eb.
The test passes (unexpectedly, due to the XFAIL: *) when x86 isn't
the default triple (such as on an arm machine).
Martin Storsjö [Mon, 8 Feb 2021 13:24:42 +0000 (15:24 +0200)]
[AArch64] Use '//' as comment string for MSVC assembly
As the actual MSVC toolset doesn't use the GAS-style assembly that
Clang/LLVM produces and consumes, there's no reference for what
string to use for e.g. comments when building with a MSVC triple.
This frees up the use of semicolon as separator string, just like
was done for GNU targets in
23413195649d0cf6f3860ae8b5fb115b35032075.
(Previously, both the separator and comment strings were set to
the same, a semicolon.)
Compiler-rt extensively uses separator chars in its assembly,
and that assembly should be buildable with clang-cl for MSVC too.
Differential Revision: https://reviews.llvm.org/D96259
Fangrui Song [Mon, 8 Feb 2021 20:29:11 +0000 (12:29 -0800)]
DebugInfo/Symbolize: Allow STT_NOTYPE/STT_GNU_IFUNC symbols for .symtab symbolization
In assembly files, omitting `.type foo,@function` is common. Such functions have
type `STT_NOTYPE` and llvm-symbolizer reports `??` for them.
An ifunc symbol usually has an associated resolver symbol which is defined at
the same address. Returning either one is fine for symbolization. The resolver
symbol may not end up in the symbol table if (object file) `.L` is used (linked
image) .symtab is stripped while .dynsym is retained.
This patch allows ELF STT_NOTYPE/STT_GNU_IFUNC symbols for .symtab symbolization.
I have left TODO in the test files for an unimplemented STT_FILE heuristic.
Differential Revision: https://reviews.llvm.org/D95916
Roland McGrath [Thu, 4 Feb 2021 03:28:29 +0000 (19:28 -0800)]
[scudo/standalone] Use .arch_extension memtag, not mte
GNU binutils accepts only `.arch_extension memtag` while Clang
accepts either that or `.arch_extension mte` to mean the same thing.
Reviewed By: pcc
Differential Revision: https://reviews.llvm.org/D95996
Eric Schweitz [Mon, 8 Feb 2021 20:10:43 +0000 (12:10 -0800)]
[flang][NFC] Update comments.
Jon Chesterfield [Mon, 8 Feb 2021 20:07:51 +0000 (20:07 +0000)]
[libomptarget][amdgcn] Fix language linkage post D95300, drop use of assert
Jianzhou Zhao [Fri, 5 Feb 2021 21:50:15 +0000 (21:50 +0000)]
[dfsan] Refactor visitCallBase
To simplify the review of https://reviews.llvm.org/D95835.
Reviewed-by: morehouse
Differential Revision: https://reviews.llvm.org/D96177
Jez Ng [Mon, 8 Feb 2021 19:50:13 +0000 (14:50 -0500)]
[lld-macho] Try to make ubsan happy
Summary: We should avoid passing a null pointer to memcpy.
Craig Topper [Mon, 8 Feb 2021 19:25:50 +0000 (11:25 -0800)]
[RISCV] Use _COMMUTABLE fma pseudos for fixed vectors.
This matches what we do in the VLMAX SDNode patterns.
Mitch Phillips [Mon, 8 Feb 2021 18:46:45 +0000 (10:46 -0800)]
[GWP-ASan] Add aligned allocations.
Adds a new allocation API to GWP-ASan that handles size+alignment
restrictions.
Reviewed By: cryptoad, eugenis
Differential Revision: https://reviews.llvm.org/D94830
Mircea Trofin [Mon, 8 Feb 2021 19:21:56 +0000 (11:21 -0800)]
Revert "[Utils] Add a switch controlling prefix warnings in UpdateTestChecks"
This reverts commit
87f8a08ce36e5bc72f11129d2cf36b5848f86f63.
Craig Topper [Mon, 8 Feb 2021 18:59:38 +0000 (10:59 -0800)]
[RISCV] Add support for splat fixed length build_vectors using RVV.
Building on the fixed vector support from D95705
I've added ISD nodes for vmv.v.x and vfmv.v.f and switched to
lowering the intrinsics to it. This allows us to share the same
isel patterns for both.
This doesn't handle splats of i64 on RV32 yet. The build_vector
gets converted to a vXi32 build_vector+bitcast during type
legalization. Not sure the best way to handle this at the moment.
Differential Revision: https://reviews.llvm.org/D96108
Craig Topper [Mon, 8 Feb 2021 18:45:45 +0000 (10:45 -0800)]
[RISCV] Add support for fixed vector FMA.
Follow up to D95705. Does not include the commuting support from D95800.
Differential Revision: https://reviews.llvm.org/D96103
Nicolas Vasilache [Mon, 8 Feb 2021 15:28:29 +0000 (15:28 +0000)]
[mlir][Linalg] Fix padding related bugs.
This revision fixes the fact that the padding transformation did not have enough information to set the proper type for the padding value.
Additionally, the verifier for Yield in the presence of PadTensorOp is fixed to properly report incorrect number of results or operands. Previously, the error would be silently ignored which made the core issue difficult to debug.
Differential Revision: https://reviews.llvm.org/D96264
Jez Ng [Mon, 8 Feb 2021 18:47:34 +0000 (13:47 -0500)]
[lld-macho] Emit LSDA info in compact unwind
The LSDA pointers are encoded as offsets from the image base,
and arranged in one big contiguous array. Each second-level page records
the offset within that LSDA array which corresponds to the LSDA for its
first CU entry.
Reviewed By: clayborg
Differential Revision: https://reviews.llvm.org/D95810
Jez Ng [Mon, 8 Feb 2021 18:47:33 +0000 (13:47 -0500)]
[lld-macho] Emit personalities in compact unwind
Note that there is a triple indirection involved with
personalities and compact unwind:
1. Two bits of each CU encoding are used as an offset into the
personality array.
2. Each entry of the personality array is an offset from the image base.
The resulting address (after adding the image base) should point within the
GOT.
3. The corresponding GOT entry contains the actual pointer to the
personality function.
To further complicate things, when the personality function is in the
object file (as opposed to a dylib), its references in
`__compact_unwind` may refer to it via a section + offset relocation
instead of a symbol relocation. Since our GOT implementation can only
create entries for symbols, we have to create a synthetic symbol at the
given section offset.
Reviewed By: clayborg
Differential Revision: https://reviews.llvm.org/D95809
Craig Topper [Mon, 8 Feb 2021 18:32:32 +0000 (10:32 -0800)]
[RISCV] Add initial support for converting fixed vectors to scalable vectors during lowering to use RVV instructions.
This is an alternative to D95563.
This is modeled after a similar feature for AArch64's SVE that uses
predicated scalable vector instructions.a
Rather than use predication, this patch uses an explicit VL operand.
I've limited it to always use LMUL=1 for now, but we can improve this
in the future.
This requires a bunch of new ISD opcodes to carry the VL operand.
I think we can probably lower intrinsics to these ISD opcodes to
cut down on the size of the isel table. Which is why I've added
patterns for all integer/float types and not just LMUL=1.
I'm only testing one vector width right now, but the width is
programmable via the command line.
Reviewed By: frasercrmck
Differential Revision: https://reviews.llvm.org/D95705
Fangrui Song [Mon, 8 Feb 2021 18:34:57 +0000 (10:34 -0800)]
[ELF] Inspect -EL & -EB for OUTPUT_FORMAT(default, big, little)
Choose big if -EB is specified, little if -EL is specified, or default if neither is specified.
The new behavior matches GNU ld.
Fixes: https://github.com/ClangBuiltLinux/linux/issues/1025
Differential Revision: https://reviews.llvm.org/D96214
Alex Zinenko [Mon, 8 Feb 2021 17:22:23 +0000 (18:22 +0100)]
[mlir] Drop deprecated syntax for LLVM dialect types
After the LLVM dialect types were ported to use built-in types, the parser kept
supporting the old syntax for LLVM dialect types to produce built-in types for
compatibility. Drop this support.
Reviewed By: mehdi_amini
Differential Revision: https://reviews.llvm.org/D96275
Florian Hahn [Mon, 8 Feb 2021 17:28:34 +0000 (17:28 +0000)]
[ConstraintElimination] Decompose a few more GEP indices.
This patch adds handling for zero-extended GEP indices.
Craig Topper [Mon, 8 Feb 2021 17:56:47 +0000 (09:56 -0800)]
[RISCV] Make scalable vector FMA commutable for register allocation.
This adds support for commuting operands and converting between
vfmadd and vfmacc to avoid register copies.
To avoid messing up intrinsic behavior, I've added new pseudo
instructions that have the isCommutable flag set. These pseudos also
force a tail agnostic policy. The intrinsic version still use
the tail undisturbed policy.
For best results it looks like we need to start with fmadd and only
pick fmacc if its beneficial. MachineCSE commutes without contraining
the operands and then commutes back if it didn't help with CSE. So
I've made sure that when the operand choice isn't constrained, we
will keep fmadd for MachineCSE and when it does the second commute,
we get back the original instruction.
Reviewed By: frasercrmck
Differential Revision: https://reviews.llvm.org/D95800
Julian Lettner [Sat, 6 Feb 2021 05:31:22 +0000 (21:31 -0800)]
[Sanitizer] Fix failing sanitizer tests
The new pass manager was enabled by default [1].
The commit message states the following relevant differences:
* The inliner works slightly differently
* -O1 does some amount of inlining
These tests are affected because they specify `-O1` and then check the
reported stack trace.
[1] https://reviews.llvm.org/D95380
Differential Revision: https://reviews.llvm.org/D96198
Craig Topper [Mon, 8 Feb 2021 17:48:25 +0000 (09:48 -0800)]
[RISCV] Use SplatPat/SplatPat_simm5 to handle PseudoVMV_V_X_/PseudoVMV_V_I_ selection as well.
This ensures that we'll match immediates consistently regardless
of whether we match them as a standalone splat or as part of
another operation.
While I was there I added complexities to the simm5/uimm5 patterns so
we didn't have to assume that the 1 on the non-immediate was lower
than what tablegen inferred.
I had to make a minor tweak to tablegen to fix one place that
didn't expect to see a ComplexPattern that wasn't a "leaf".
Reviewed By: frasercrmck
Differential Revision: https://reviews.llvm.org/D96199
Jay Foad [Mon, 8 Feb 2021 17:34:27 +0000 (17:34 +0000)]
[AMDGPU] Use named unified buffer format constant. NFC.
Michał Górny [Thu, 28 Jan 2021 11:23:54 +0000 (12:23 +0100)]
[lldb] [Process/FreeBSDRemote] Introduce mips64 support
Introduce mips64 support to match the legacy FreeBSD plugin. Similarly
to the legacy plugin, the code does not support FPU registers at the
moment. The support for them will be submitted separately as it
requires changes to the register context shared by both plugins.
This also includes software single-stepping support that is moved from
the Linux plugin into a common Utility class. The FreeBSD code also
starts explicitly ignoring EINVAL from PT_CLEARSTEP since this is easier
to implement than checking whether hardware single-stepping were used.
Differential Revision: https://reviews.llvm.org/D95802
Frederik Gossen [Mon, 8 Feb 2021 17:08:47 +0000 (18:08 +0100)]
[LLDB] Fix `Wunused-result` warning
Fangrui Song [Mon, 8 Feb 2021 16:55:28 +0000 (08:55 -0800)]
[ELF] Support aarch64_be
This patch adds
* Big-endian values for `R_AARCH64_{ABS,PREL}{16,32,64}` and `R_AARCH64_PLT32`
* aarch64elfb & aarch64linuxb BFD emulations
* elf64-bigaarch64 output format (bfdname)
Link: https://github.com/ClangBuiltLinux/linux/issues/1288
Differential Revision: https://reviews.llvm.org/D96188
Fangrui Song [Mon, 8 Feb 2021 16:50:25 +0000 (08:50 -0800)]
[llvm-objdump] Support PLT decoding for aarch64_be
Reviewed By: jhenderson
Differential Revision: https://reviews.llvm.org/D96211
Eric Schweitz [Fri, 5 Feb 2021 22:40:10 +0000 (14:40 -0800)]
[flang][fir] Update FIR's character type.
Upstream the changes made to the !fir.char type.
https://github.com/flang-compiler/f18-llvm-project/pull/269
https://github.com/flang-compiler/f18-llvm-project/pull/557
Author: Eric Schweitz, Jean Perier
Differention Revision: https://reviews.llvm.org/D96183
Xiangling Liao [Mon, 8 Feb 2021 16:14:23 +0000 (11:14 -0500)]
[FE] Manipulate the first byte of guard variable type in both load and store operation
As Itanium ABI[http://itanium-cxx-abi.github.io/cxx-abi/abi.html#once-ctor]
points out:
"The size of the guard variable is 64 bits. The first byte (i.e. the byte at
the address of the full variable) shall contain the value 0 prior to
initialization of the associated variable, and 1 after initialization is complete."
Differential Revision: https://reviews.llvm.org/D95822
Anastasia Stulova [Mon, 8 Feb 2021 16:01:44 +0000 (16:01 +0000)]
[OpenCL] Fix pipe type printing in arg info metadata
Pipe element type spelling for arg info metadata
should follow the same behavior as normal type spelling.
We should only use the canonical type spelling in the
base type field.
This patch also removed duplication in type handling.
Tags: #clang
Differential Revision: https://reviews.llvm.org/D96151
Sander de Smalen [Mon, 8 Feb 2021 14:33:05 +0000 (14:33 +0000)]
[AArch64AsmParser] Fix type-limits warning for VectorIndex.
Making VectorIndex an `int` instead of `unsigned`, silences the warning:
comparison of unsigned expression in ‘>= 0’ is always true
in:
template <int Min, int Max>
DiagnosticPredicate isVectorIndex() const {
...
if (VectorIndex.Val >= Min && VectorIndex.Val <= Max)
return DiagnosticPredicateTy::Match;
...
}
when Min is 0.
Louis Dionne [Mon, 8 Feb 2021 15:04:38 +0000 (10:04 -0500)]
[libc++] Add a wait step in the BuildKite pipeline to shield macOS builders
We don't have many of those and they are rather slow, so we'd rather not run
those jobs if we know other jobs in the pipeline failed anyway.
Tim Northover [Mon, 8 Feb 2021 14:47:14 +0000 (14:47 +0000)]
AArch64: use a constpool for blockaddress(...) on MachO
More MachO madness for everyone. MachO relocations are only 32-bits, which
means the ARM64_RELOC_ADDEND one only actually has 24 (signed) bits for the
actual addend. This is a problem when calculating the address of a basic block;
because it has no symbol of its own, the sequence
adrp x0, Ltmp0@PAGE
add x0, x0, x0 Ltmp0@PAGEOFF
is represented by relocation with an addend that contains the offset from the
function start to Ltmp, and so the largest function where this is guaranteed to
work is 8MB. That's not quite big enough that we can call it user error (IMO).
So this patch puts the any blockaddress into a constant-pool, where the addend
is instead stored in the (x)word being relocated, which is obviously big enough
for any function.
Jamie Schmeiser [Mon, 8 Feb 2021 15:09:34 +0000 (10:09 -0500)]
Introduce -print-changed=[diff | diff-quiet] which show changes in patch-like format
Summary:
Introduce base classes that hold a textual represent of the IR
based on basic blocks and a base class for comparing this
representation. A new change printer is introduced that uses these
classes to save and compare representations of the IR before and after
each pass. It only reports when changes are made by a pass (similar to
-print-changed) except that the changes are shown in a patch-like format
with those lines that are removed shown in red prefixed with '-' and those
added shown in green with '+'. This functionality was introduced in my
tutorial at the 2020 virtual developer's meeting.
Author: Jamie Schmeiser <schmeise@ca.ibm.com>
Reviewed By: aeubanks (Arthur Eubanks)
Differential Revision: https://reviews.llvm.org/D91890
Simon Pilgrim [Mon, 8 Feb 2021 13:46:31 +0000 (13:46 +0000)]
[DAG] visitVECTOR_SHUFFLE - move shuffle legality check into MergeInnerShuffle lamda. NFCI.
This is going to be necessary for a future reuse of MergeInnerShuffle
Mikael Holmen [Mon, 8 Feb 2021 13:30:48 +0000 (14:30 +0100)]
[RISCV] Use std::make_tuple to make some toolchains happy again
My toolchain (LLVM 8.0, libstdc++ 5.4.0) complained with:
12:38:19 ../lib/Target/RISCV/RISCVISelLowering.cpp:1717:12: error: chosen constructor is explicit in copy-initialization
12:38:19 return {RISCVISD::VECREDUCE_FADD, Op.getOperand(0),
12:38:19 ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
12:38:19 /proj/flexasic/app/llvm/8.0/bin/../lib/gcc/x86_64-unknown-linux-gnu/5.4.0/../../../../include/c++/5.4.0/tuple:479:19: note: explicit constructor declared here
12:38:19 constexpr tuple(_UElements&&... __elements)
12:38:19 ^
12:38:19 ../lib/Target/RISCV/RISCVISelLowering.cpp:1720:12: error: chosen constructor is explicit in copy-initialization
12:38:19 return {RISCVISD::VECREDUCE_SEQ_FADD, Op.getOperand(1), Op.getOperand(0)};
12:38:19 ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
12:38:19 /proj/flexasic/app/llvm/8.0/bin/../lib/gcc/x86_64-unknown-linux-gnu/5.4.0/../../../../include/c++/5.4.0/tuple:479:19: note: explicit constructor declared here
12:38:19 constexpr tuple(_UElements&&... __elements)
12:38:19 ^
12:38:19 2 errors generated.
This commit adds explicit calls to std::make_tuple to work around
the problem.
Nicholas Guy [Thu, 28 Jan 2021 17:22:21 +0000 (17:22 +0000)]
[CodeGen][AArch64] Add TargetInstrInfo hook to modify the TailDuplicateSize default threshold
Different targets might handle branch performance differently, so this patch allows for
targets to specify the TailDuplicateSize threshold. Said threshold defines how small a branch
can be and still be duplicated to generate straight-line code instead.
This patch also specifies said override values for the AArch64 subtarget.
Differential Revision: https://reviews.llvm.org/D95631
KareemErgawy-TomTom [Mon, 8 Feb 2021 11:45:11 +0000 (12:45 +0100)]
[MLIR][SPIRV] NFC: Split serialization code among multiple files.
Following up on https://reviews.llvm.org/D94360, this patch splits the
serialization code into multiple source files to provide a better
structure and allow parallel compilation.
Reviewed By: antiagainst
Differential Revision: https://reviews.llvm.org/D95855
Florian Hahn [Mon, 8 Feb 2021 12:28:52 +0000 (12:28 +0000)]
[ConstraintElimination] Improve index handing during constraint building.
This patch improves the index management during constraint building.
Previously, the code rejected constraints which used values that were not
part of Value2Index, but after combining the coefficients of the new
indices were 0 (if ShouldAdd was 0).
In those cases, no new indices need to be added. Instead of adding to
Value2Index directly, add new indices to the NewIndices map. The caller
can then check if it needs to add any new indices.
This enables checking constraints like `a + x <= a + n` to `x <= n`,
even if there is no constraint for `a` directly.
Jay Foad [Fri, 5 Feb 2021 15:03:04 +0000 (15:03 +0000)]
[AMDGPU] Generate test checks and add GFX10 test coverage
Differential Revision: https://reviews.llvm.org/D96143
Jeremy Morse [Mon, 8 Feb 2021 12:33:56 +0000 (12:33 +0000)]
Revert "Re-land D94976 after revert in
e29552c5aff6"
Maskray has reported a fault with .debug_gnu_pubnames in the comments on
D94976, caused by this patch, reverting to investigate.
This reverts commit
8998f5843503773c2f51fd475e2c77c687a65ee6.
Jeremy Morse [Mon, 8 Feb 2021 11:37:53 +0000 (11:37 +0000)]
Revert "DebugInfo: Temporarily work around -gsplit-dwarf + LTO .debug_gnu_pubnames regression after D94976"
Backing out this workaround to focus on fixing whatever's wrong with
.debug_gnu_pubnames, I'll revert the cause, (
8998f584) in the next commit.
This reverts commit
56fa34ae3570a34fd0f4c2cf1bfaf095da01a959.
einvbri [Mon, 8 Feb 2021 12:38:31 +0000 (06:38 -0600)]
Revert "[Sema] Fix -Warray-bounds false negative when casting an out-of-bounds array item"
This reverts commit
e48f444751cf781c42934b242b81f549da77bad0.
thakis noticed false reports, so reverting this change for now until
those can be sorted out.
See https://reviews.llvm.org/D71714
Kadir Cetinkaya [Wed, 3 Feb 2021 11:45:46 +0000 (12:45 +0100)]
[clang][CodeComplete] Fix crash on ParenListExprs
Fixes https://github.com/clangd/clangd/issues/676.
Differential Revision: https://reviews.llvm.org/D95935
Jan Svoboda [Mon, 8 Feb 2021 09:38:01 +0000 (10:38 +0100)]
Reapply "[clang][cli] Report result of ParseLangArgs"
This reverts commit
6039f821 and reapplies
bff6d9bb.
Clang's Index/implicit-attrs.m test invokes c-index-test with -fobjc-arc. This flag is not compatible with -fobjc-runtime=gcc, which gets implied on Linux.
The original commit uncovered this by correctly reporting issues when parsing -cc1 command line.
This commit fixes the test to explicitly provide ObjectiveC runtime compatible with ARC.
Tatyana Krasnukha [Wed, 3 Feb 2021 22:02:31 +0000 (01:02 +0300)]
[lldb/tests] Removed add_test_categories decorator for python API tests, NFC
There is a .categories file in the python_api directory that makes all nested tests
belong to the category "pyapi". The decorator is unnecessary for these tests.
Tatyana Krasnukha [Wed, 3 Feb 2021 20:35:35 +0000 (23:35 +0300)]
[lldb/tests] Un-skip TestGuiBasicDebug.py on Arm and AArch64
The test was timing out because of https://reviews.llvm.org/D92164, it should pass now.
Tatyana Krasnukha [Fri, 18 Dec 2020 13:36:15 +0000 (16:36 +0300)]
Reland "[lldb] Make CommandInterpreter's execution context the same as debugger's one"
Tatyana Krasnukha [Mon, 1 Feb 2021 19:24:30 +0000 (22:24 +0300)]
[lldb] Debugger: reuse ExecutionContextRef to create ExecutionContext from Target
The Debugger didn't take the Process's run lock, that causes deadlocks and races
after applying https://reviews.llvm.org/D92164 revision. Since ExecutionContextRef
does the same job correctly, Debugger::GetSelectedExecutionContext just can use it
to build execution context upon the selected target.
Thomas Symalla [Tue, 2 Feb 2021 17:01:48 +0000 (18:01 +0100)]
[AMDGPU]: Fixes an invalid clamp selection pattern.
When running the tests on PowerPC and x86, the lit test GlobalISel/trunc.ll fails at the memory sanitize step. This seems to be due to wrong invalid logic (which matches even if it shouldn't) and likely missing variable initialisation."
Reviewed By: arsenm
Differential Revision: https://reviews.llvm.org/D95878