Mehdi Amini [Mon, 7 Nov 2022 21:26:21 +0000 (21:26 +0000)]
Fix MLIR doc build
Mehdi Amini [Thu, 3 Nov 2022 20:12:14 +0000 (20:12 +0000)]
Apply clang-tidy fixes for performance-unnecessary-value-param in LinalgOps.cpp (NFC)
Mehdi Amini [Thu, 3 Nov 2022 20:10:11 +0000 (20:10 +0000)]
Apply clang-tidy fixes for performance-move-const-arg in IndexOps.cpp (NFC)
Arthur Eubanks [Mon, 7 Nov 2022 21:20:09 +0000 (13:20 -0800)]
[NFC] clang-format part of TypePrinter.cpp
Fixes weird clang-format indentation with an upcoming patch.
Matthias Braun [Fri, 4 Nov 2022 23:19:18 +0000 (16:19 -0700)]
Explicitly initialize opaque pointer mode in CodeGenAction
Explicitly call `LLVMContext::setOpaquePointers` in `CodeGenAction`
before loading any IR files. With this we use the mode specified on the
command-line rather than lazily initializing it based on the contents of
the IR.
This helps when using `-fthinlto-index` which may end up mixing files
with typed and opaque pointer types which fails when the first file
happened to use typed pointers since we cannot downgrade IR with opaque
pointer types to typed pointer types.
Differential Revision: https://reviews.llvm.org/D137475
Emilio Cota [Mon, 7 Nov 2022 19:21:06 +0000 (14:21 -0500)]
[bazel][mlir] NVGPUToNVVM fixes for
708185f03ff
Mircea Trofin [Mon, 7 Nov 2022 19:10:58 +0000 (11:10 -0800)]
[NFC] Comment in MLInlineAdvisor as to why use std::map for FPICache
Michael Jones [Thu, 3 Nov 2022 22:21:30 +0000 (15:21 -0700)]
[libc][obvious] fix printf failing to stop on %\0
Previously, the printf parser would treat "%\0" as a conversion with the
name "\0", and advance past the null byte causing a buffer overflow.
This patch corrects that in both printf and scanf.
Reviewed By: sivachandra
Differential Revision: https://reviews.llvm.org/D137367
Matt Arsenault [Mon, 31 Oct 2022 23:49:43 +0000 (16:49 -0700)]
AMDGPU: Fix DivergenceAnalysis for llvm.read_register
This was treating all calls as uniform by default, which
is wrong if used to read a VGPR.
Arthur Eubanks [Fri, 4 Nov 2022 21:02:11 +0000 (14:02 -0700)]
[NFC][lldb] Remove unnecessary branch in TypeSystemClang::DumpTypeDescription()
Reviewed By: Michael137
Differential Revision: https://reviews.llvm.org/D137464
Nathan James [Mon, 7 Nov 2022 18:25:46 +0000 (18:25 +0000)]
[clang][NFC] Use c++17 style variable type traits
This was done as a test for D137302 and it makes sense to push these changes
Reviewed By: shafik
Differential Revision: https://reviews.llvm.org/D137491
Fangrui Song [Mon, 7 Nov 2022 18:07:10 +0000 (10:07 -0800)]
[LTO] Make local linkage GlobalValue in non-prevailing COMDAT available_externally
For a local linkage GlobalObject in a non-prevailing COMDAT, it remains defined while its
leader has been made available_externally. This violates the COMDAT rule that
its members must be retained or discarded as a unit.
To fix this, update the regular LTO change D34803 to track local linkage
GlobalValues, and port the code to ThinLTO (GlobalAliases are not handled.)
This fixes two problems.
(a) `__cxx_global_var_init` in a non-prevailing COMDAT group used to
linger around (unreferenced, hence benign), and is now correctly discarded.
```
int foo();
inline int v = foo();
```
(b) Fix https://github.com/llvm/llvm-project/issues/58215:
as a size optimization, we place private `__profd_` in a COMDAT with a
`__profc_` key. When FuncImport.cpp makes `__profc_` available_externally due to
a non-prevailing COMDAT, `__profd_` incorrectly remains private. This change
makes the `__profd_` available_externally.
```
cat > c.h <<'eof'
extern void bar();
inline __attribute__((noinline)) void foo() {}
eof
cat > m1.cc <<'eof'
#include "c.h"
int main() {
bar();
foo();
}
eof
cat > m2.cc <<'eof'
#include "c.h"
__attribute__((noinline)) void bar() {
foo();
}
eof
clang -O2 -fprofile-generate=./t m1.cc m2.cc -flto -fuse-ld=lld -o t_gen
rm -fr t && ./t_gen && llvm-profdata show -function=foo t/default_*.profraw
clang -O2 -fprofile-generate=./t m1.cc m2.cc -flto=thin -fuse-ld=lld -o t_gen
rm -fr t && ./t_gen && llvm-profdata show -function=foo t/default_*.profraw
```
If a GlobalAlias references a GlobalValue which is just changed to
available_externally, change the GlobalAlias as well (e.g. C5/D5 comdats due to
cc1 -mconstructor-aliases). The GlobalAlias may be referenced by other
available_externally functions, so it cannot easily be removed.
Depends on D137441: we use available_externally to mark a GlobalAlias in a
non-prevailing COMDAT, similar to how we handle GlobalVariable/Function.
GlobalAlias may refer to a ConstantExpr, not changing GlobalAlias to
GlobalVariable gives flexibility for future extensions (the use case is niche.
For simplicity we don't handle it yet). In addition, available_externally
GlobalAlias is the most straightforward implementation and retains the aliasee
information to help optimizers.
Reviewed By: tejohnson
Differential Revision: https://reviews.llvm.org/D135427
Peiming Liu [Mon, 7 Nov 2022 17:10:01 +0000 (17:10 +0000)]
[mlir][sparse] support parallel for/reduction in sparsification.
This patch fix the re-revert D135927 (which caused a windows build failure) to re-enable parallel for/reduction. It also fix a warning caused by D137442.
Reviewed By: aartbik
Differential Revision: https://reviews.llvm.org/D137565
Kazu Hirata [Mon, 7 Nov 2022 17:54:10 +0000 (09:54 -0800)]
[mlir] Fix a warning (NFC)
This patch fixes:
mlir/lib/Dialect/SparseTensor/IR/SparseTensorDialect.cpp:717:48:
error: comparison of integers of different signs: 'int64_t' (aka
'long') and 'uint64_t' (aka 'unsigned long')
[-Werror,-Wsign-compare]
yijiagu [Mon, 7 Nov 2022 17:47:53 +0000 (09:47 -0800)]
[mlir] Lower async.func with async.coro and async.runtime operations
Lower async.func with async.coro and async.runtime operations
- This patch modifies AsyncToAsyncRuntime pass to add lowering async.func ops with coroutine cfg.
Example:
```
async.func @foo() -> !async.value<f32> {
%cst = arith.constant 42.0 : f32
return %cst: f32
}
```
After lowering:
```
func.func @foo() -> !async.value<f32> attributes {passthrough = ["presplitcoroutine"]} {
%0 = async.runtime.create : !async.value<f32>
%1 = async.coro.id
%2 = async.coro.begin %1
cf.br ^bb1
^bb1: // pred: ^bb0
%cst = arith.constant 4.200000e+01 : f32
async.runtime.store %cst, %0 : <f32>
async.runtime.set_available %0 : !async.value<f32>
cf.br ^bb2
^bb2: // pred: ^bb1
async.coro.free %1, %2
cf.br ^bb3
^bb3: // pred: ^bb2
async.coro.end %2
return %0 : !async.value<f32>
}
```
Reviewed By: ezhulenev
Differential Revision: https://reviews.llvm.org/D137462
Jay Foad [Mon, 7 Nov 2022 07:36:11 +0000 (07:36 +0000)]
[AMDGPU] Merge GlobalISel tests into SelectionDAG tests. NFC.
Remove GlobalISel test files that only contained RUN lines running the
code from the SelectionDAG version of the same test.
Differential Revision: https://reviews.llvm.org/D137533
Stella Stamenova [Mon, 7 Nov 2022 17:34:10 +0000 (09:34 -0800)]
Revert "[mlir][sparse] extend foreach operation to accept reduction arguments."
This reverts commit
53d5d3401120f2aa741a73a5a9ba0ce012ca532c.
This is causing a build failure on the windows mlir bot that was previously hidden by another sparse tensor change that caused failures:
https://lab.llvm.org/buildbot/#/builders/13/builds/28006
Hans Wennborg [Sat, 5 Nov 2022 03:37:45 +0000 (04:37 +0100)]
[lld] Check errors from expanding response files
Previously the response file expansion code would print the error, but
lld would not exit, which was odd.
lld does response file expansion in the different drivers, but it's also
done in main() first, so it's enough to check there.
By checking for these errors we would have caught when D136090
introduced a bug that made lld print errors for response files which
contained "-rpath @foo".
Differental revision: https://reviews.llvm.org/D137477
Hans Wennborg [Mon, 7 Nov 2022 17:22:05 +0000 (18:22 +0100)]
Use double hashes for non-run/check lines in lld/test/ELF/basic.s
Slava Zakharin [Mon, 7 Nov 2022 17:05:27 +0000 (09:05 -0800)]
[flang] Configure FirOpBuilder based on math driver options.
Added MathOptionsBase to share fastmath config between different
components. Frontend driver translates LangOptions into MathOptionsBase.
FirConverter configures FirOpBuilder using MathOptionsBase
config passed to it via LoweringOptions.
Depends on D137390
Reviewed By: jeanPerier
Differential Revision: https://reviews.llvm.org/D137391
Valentin Clement [Mon, 7 Nov 2022 17:23:22 +0000 (18:23 +0100)]
[flang] Allow fir.class as fir.save_result operand #0
Reviewed By: jeanPerier, PeteSteinfeld
Differential Revision: https://reviews.llvm.org/D137546
Michał Górny [Mon, 7 Nov 2022 13:46:58 +0000 (14:46 +0100)]
[cmake] Add missing CMakePushCheckState include to FindLibEdit.cmake
Add the missing include to fix an error when `cmake_push_check_state()`
is called and incidentally the CMakePushCheckState module is not loaded
by any other check running prior to `FindLibEdit.cmake`:
CMake Error at /var/no-tmpfs/portage/dev-util/lldb-15.0.4/work/cmake/Modules/FindLibEdit.cmake:24 (cmake_push_check_state):
Unknown CMake command "cmake_push_check_state".
Call Stack (most recent call first):
cmake/modules/LLDBConfig.cmake:52 (find_package)
cmake/modules/LLDBConfig.cmake:59 (add_optional_dependency)
CMakeLists.txt:28 (include)
Gentoo Bug: https://bugs.gentoo.org/880065
Differential Revision: https://reviews.llvm.org/D137555
Miguel Saldivar [Mon, 7 Nov 2022 16:26:30 +0000 (11:26 -0500)]
[InstCombine] Avoid passing pow attributes to sqrt
As described in issue #58475, we could pass the attributes of pow to sqrt and crash.
Differential Revision: https://reviews.llvm.org/D137454
Sanjay Patel [Sun, 6 Nov 2022 15:44:54 +0000 (10:44 -0500)]
[VectorCombine] add test with non-canonical shuffle mask; NFC
D137341
Slava Zakharin [Mon, 7 Nov 2022 16:25:19 +0000 (08:25 -0800)]
[flang] Initial support for FastMathAttr setup in FirOpBuilder.
Provide FirOpBuilder::setFastMathFlags() to configure FastMathFlags
for the builder. Set FastMathAttr for operations based on FirOpBuilder
configuration via mlir::OpBuilder::Listener.
This is a little bit hacky solution, because we lose the ability
to hook other listeners to FirOpBuilder. There are also potential
issues with OpBuilder::clone() - the hook will be invoked for cloned
operations and will effectively overwrite FastMathAttr with the ones
configured in FirOpBuilder, which should not be happening.
We should teach mlir::OpBuilder about FastMathAttr setup in future.
Reviewed By: jeanPerier, kiranchandramohan
Differential Revision: https://reviews.llvm.org/D137390
Fangrui Song [Mon, 7 Nov 2022 17:03:23 +0000 (09:03 -0800)]
[IR] Allow available_externally GlobalAlias
GlobalVariable and Function can be available_externally. GlobalAlias is used
similarly. Allowing available_externally is a natural extension and helps
ThinLTO discard GlobalAlias in a non-prevailing COMDAT (see D135427).
For now, available_externally GlobalAlias must point to an
available_externally GlobalValue (not ConstantExpr).
Differential Revision: https://reviews.llvm.org/D137441
Stella Stamenova [Mon, 7 Nov 2022 17:00:08 +0000 (09:00 -0800)]
Revert "[mlir][sparse] fix sparse tensor rewriting patterns that do not propagate sparse tensor SSA properly."
This reverts commit
70508b614e6478ba2c3fc79e935e2c68e2d79b71.
This change depends on a reverted change that broke the windows mlir buildbot; reverting to bring remaining mlir bots to green
Matt Arsenault [Mon, 17 Oct 2022 19:20:02 +0000 (12:20 -0700)]
InstCombine: Add baseline checks for fdiv
Stella Stamenova [Mon, 7 Nov 2022 16:48:52 +0000 (08:48 -0800)]
Revert "[mlir][sparse] support Parallel for/reduction."
This reverts commit
838389780e56f1a198a94f66ea436359466bf5ed.
This broke the windows mlir buildbot: https://lab.llvm.org/buildbot/#/builders/13/builds/27934
Matt Arsenault [Mon, 17 Oct 2022 05:27:36 +0000 (22:27 -0700)]
InstSimplify: Fold fdiv nnan ninf x, 0 -> poison
https://alive2.llvm.org/ce/z/JxX5in
Matt Arsenault [Mon, 17 Oct 2022 05:26:13 +0000 (22:26 -0700)]
InstSimplify: Add new baseline tests for fdiv
Christopher Bate [Sat, 5 Nov 2022 15:43:24 +0000 (09:43 -0600)]
[mlir][NVGPU] Add support for structured sparsity MMA variants
This change adds a new NVGPU operation that targets the PTX `mma.sp.sync`
instruction variants. A lowering to NVVM is provided using inline
assembly.
Reviewed By: ThomasRaoux, manishucsd
Differential Revision: https://reviews.llvm.org/D137202
Nikita Popov [Mon, 7 Nov 2022 16:40:30 +0000 (17:40 +0100)]
[Clang] Update test after wasm intrinsics attribute change (NFC)
I missed this test in
d35fcf0e97e7bb02381506a71e61ec282b292c50.
Alexey Bataev [Mon, 7 Nov 2022 16:33:41 +0000 (08:33 -0800)]
Revert "[SLP]Redesign vectorization of the gather nodes."
This reverts commit
8ddd1ccdf89317be1c40fa9183e214878a56151e to fix
buildbots failures reported in https://lab.llvm.org/buildbot#builders/74/builds/14839
bixia1 [Mon, 7 Nov 2022 16:18:53 +0000 (08:18 -0800)]
[mlir][sparse] Add sparse_tensor.sort_coo operator.
Reviewed By: aartbik
Differential Revision: https://reviews.llvm.org/D137442
Nikita Popov [Mon, 7 Nov 2022 14:50:05 +0000 (15:50 +0100)]
[WebAssembly] Use default attributes for intrinsics
This switches wasm intrinsics to use default attributes,
i.e. nofree, nosync, nocallback and willreturn. Especially
willreturn will be required to avoid optimization regressions
in the future.
The attributes are omitted from the trapping fptoi intrinsics
(where I assume trapping is considered well-defined, and as such
these aren't willreturn), the throw/rethrow intrinsics (which
will unwind) and the atomic intrinsics (which aren't nosync).
Differential Revision: https://reviews.llvm.org/D137551
Nikita Popov [Mon, 7 Nov 2022 16:02:19 +0000 (17:02 +0100)]
[InstCombine] Handle load smaller than one byte in memset forward
APInt::getSplat() requires that the new size is >= the original
one. If we're loading less than 8 bits, truncate instead.
Fixes https://github.com/llvm/llvm-project/issues/58845.
Mingming Liu [Fri, 4 Nov 2022 05:07:58 +0000 (22:07 -0700)]
[NFC][BlockPlacement]Add an option to renumber blocks based on function layout order.
Use case:
- When block layout is visualized after MBP pass, the basic blocks are labeled in layout order; meanwhile blocks could be numbered in a different order.
- As a result, it's hard to map between the graph and pass output. With this option on, the basic blocks are renumbered in function layout order.
This option is only useful when a function is to be visualized (i.e., when view options are on) to make it debugging only.
Use https://godbolt.org/z/5WTW36bMr as an example:
- As MBP pass output (shown in godbolt output window), `func2` is in a basic block numbered `2` (`bb.2`), and `func1` is in a basic block numbered `3` (`bb.3`);
`bb.3` is a block with higher block frequency than `bb.2`, and `bb.3` is placed before `bb.2` in the functin layout.
- Use [1] to get the dot graph (graph uploaded in [2]), the blocks are re-numbered.
- `func1` is in 'if.end' block, and labeled `1` in visualized dot; `func2` is in 'if.then' blocks, and labeled `3` --> the labeled number and bb number won't map.
- [[ https://github.com/llvm/llvm-project/blob/
b5626ae9751f0d82aa04791a21689b289721738e/llvm/lib/CodeGen/MachineBlockFrequencyInfo.cpp#L127 | DOTGraphTraits<MachineBlockFrequencyInfo *>::getNodeLabel ]] is where labeled numbers are based on function layout number, and [[ https://github.com/llvm/llvm-project/blob/
a8d93783f37c042ace67069ae4ca6f8fd849c2d0/llvm/include/llvm/Support/GraphWriter.h#L209
| called by graph writer ]].
So call 'MachineFunction::RenumberBlocks' would make labeled number (in dot graph) and block number (in pass output) consistent with each other.
[1] `./bin/clang++ -O3 -S -mllvm -view-block-layout-with-bfi=count -mllvm -view-bfi-func-name=_Z9func_loopv -mllvm -print-after=block-placement -mllvm -filter-print-funcs=_Z9func_loopv test.c`
[2] {
F25201785}
Reviewed By: davidxl
Differential Revision: https://reviews.llvm.org/D137467
David Sherwood [Tue, 1 Nov 2022 17:11:47 +0000 (17:11 +0000)]
[AArch64][SVE2] Add the SVE2.1 quadword variants of ld1w/ld1d/st1w/st1d
This patch adds the assembly/disassembly for the following instructions:
st1w: Contiguous store words from vector (128-bit vector elements)
st1d: Contiguous store doublewords from vector (128-bit vector elements)
ld1w: Contiguous load unsigned words to vector (128-bit vector elements)
ld1d: Contiguous load unsigned doublewords to vector (128-bit vector elements)
The reference can be found here:
https://developer.arm.com/documentation/ddi0602/2022-09
Differential Revision: https://reviews.llvm.org/D137245
Matt Devereau [Wed, 12 Oct 2022 09:20:05 +0000 (09:20 +0000)]
[InstCombine] Remove redundant splats in InstCombineVectorOps
Splatting the first vector element of the result of a BinOp, where any of the
BinOp's operands are the result of a first vector element splat can be simplified to
splatting the first vector element of the result of the BinOp
Differential Revision: https://reviews.llvm.org/D135876
bixia1 [Mon, 7 Nov 2022 02:46:49 +0000 (18:46 -0800)]
[mlir][sparse] Improve the non-stable sort implementation.
Replace the quick sort partition method with one that is more similar to the
method used by C++ std quick sort. This improves the runtime for sorting
sk_2005.mtx by more than 10x.
Reviewed By: aartbik
Differential Revision: https://reviews.llvm.org/D137290
David Sherwood [Wed, 2 Nov 2022 14:58:34 +0000 (14:58 +0000)]
[AArch64][SVE2] Add the SVE2.1 BF16 instructions
This patch adds the new FEAT_B16B16 feature as well as the
assembly/disassembly for all of the B16B16 instructions:
bfadd: BFloat16 floating-point add vectors
bfsub: BFloat16 floating-point subtract vectors
bfmul: BFloat16 floating-point multiply vectors
bfclamp: BFloat16 floating-point clamp to minimum/maximum number
bfmax: BFloat16 floating-point maximum
bfmaxnm: BFloat16 floating-point maximum number
bfmin: BFloat16 floating-point minimum
bfminnm: BFloat16 floating-point minimum number
bfmla: BFloat16 floating-point fused multiply-add vectors
bfmls: BFloat16 floating-point fused multiply-subtract vectors
The reference can be found here:
https://developer.arm.com/documentation/ddi0602/2022-09
Differential Revision: https://reviews.llvm.org/D137321
Simon Pilgrim [Mon, 7 Nov 2022 15:17:23 +0000 (15:17 +0000)]
[X86] Folded MOVDDUPrm has the same sched behaviour as MOVSHDUPrm/MOVSLDUPrm on Haswell/IceLake
There can be a difference for MOVDDUPrr but not the load folded broadcast that is purely on Port23
Fixes an old TODO (inherited from SkylakeServer which was fixed at
c7662dc3e52801ec824d8473278fb976107d3e57)
Confirmed on Agner + uops.info
Matt Arsenault [Fri, 4 Nov 2022 01:26:59 +0000 (18:26 -0700)]
InstCombine: Fold compare with smallest normal if input denormals are flushed
Try to simplify comparisons with the smallest normalized value. If
denormals will be treated as 0, we can simplify by using an equality
comparison with 0.
fcmp olt fabs(x), smallest_normalized_number -> fcmp oeq x, 0.0
fcmp ult fabs(x), smallest_normalized_number -> fcmp ueq x, 0.0
fcmp oge fabs(x), smallest_normalized_number -> fcmp one x, 0.0
fcmp ult fabs(x), smallest_normalized_number -> fcmp ueq x, 0.0
The device libraries have a few range checks that look like
this for denormal handling paths.
Matt Arsenault [Fri, 4 Nov 2022 01:27:47 +0000 (18:27 -0700)]
InstCombine: Add baseline tests for fcmp and select on denormal range
A future change will try to fold (if input denormals are treated as 0)
fcmp olt fabs(x), smallest_normalized_number -> fcmp oeq x, 0.0
fcmp ult fabs(x), smallest_normalized_number -> fcmp ueq x, 0.0
fcmp oge fabs(x), smallest_normalized_number -> fcmp one x, 0.0
fcmp ult fabs(x), smallest_normalized_number -> fcmp ueq x, 0.0
OCHyams [Mon, 7 Nov 2022 15:12:18 +0000 (15:12 +0000)]
[NFC] Move getDebugValueLoc from static in Local.cpp to DebugInfo.h
Move getDebugValueLoc so that it can be accessed from DebugInfo.h for the
Assignment Tracking patch stack and remove redundant parameter Src.
Reviewed By: jryans
Differential Revision: https://reviews.llvm.org/D132357
Alexey Bataev [Fri, 16 Sep 2022 20:57:04 +0000 (13:57 -0700)]
[SLP]Redesign vectorization of the gather nodes.
Gather nodes are vectorized as simply vector of the scalars instead of
relying on the actual node. It leads to the fact that in some cases
we may miss incorrect transformation (non-matching set of scalars is
just ended as a gather node instead of possible vector/gather node).
Better to rely on the actual nodes, it allows to improve stability and
better detect missed cases.
Differential Revision: https://reviews.llvm.org/D135174
OCHyams [Mon, 7 Nov 2022 12:47:11 +0000 (12:47 +0000)]
[Assignment Tracking][5.1/*] Add deleteAssignmentMarkers function
deleteAssignmentMarkers(const Instruction *Inst) does exactly as you'd expect -
it deletes any dbg.assign intrinsics linked to Inst.
Reviewed By: jmorse
Differential Revision: https://reviews.llvm.org/D133576
David Sherwood [Thu, 3 Nov 2022 11:25:41 +0000 (11:25 +0000)]
[AArch64] Add SME2.1 target feature for Armv9-A 2022 Architecture Extension
First patch in a series adding MC layer support for SME2.1.
This patch adds the following feature:
sme2p1
The reference can be found here:
https://developer.arm.com/documentation/ddi0602/2022-09
Differential Revision: https://reviews.llvm.org/D137410
Nikita Popov [Thu, 13 Oct 2022 14:45:37 +0000 (16:45 +0200)]
[MemCpyOpt] Move lifetime marker before call to enable call slot optimization
Currently call slot optimization may be prevented because the
lifetime markers for the destination only start after the call.
In this case, rather than aborting the transform, we should move
the lifetime.start before the call to enable the transform.
Differential Revision: https://reviews.llvm.org/D135886
Oleg Shyshkov [Mon, 7 Nov 2022 13:40:09 +0000 (14:40 +0100)]
[mlir][NFC] Remove unnecessary attr name getters from StructuredOpsUtils.h.
Those methods were added long time ago. Now we get the same methods generated by tablegen, so there is no need for duplicates.
Differential Revision: https://reviews.llvm.org/D137544
Daniel Grumberg [Mon, 7 Nov 2022 13:33:59 +0000 (13:33 +0000)]
Revert "Only add targetFallback if target is not in defined in current product"
This was an accidental addition of a non-reviewed change.
This reverts commit
f63db9159bbbb0db98e13cb4440fdaa5c40e219b.
Daniel Grumberg [Tue, 25 Oct 2022 10:16:20 +0000 (11:16 +0100)]
Only add targetFallback if target is not in defined in current product
Daniel Grumberg [Fri, 21 Oct 2022 14:34:57 +0000 (15:34 +0100)]
[clang][ExtractAPI] Add targetFallback to relationships in symbol graph
Adds a 'targetFallback' field to relationships in symbol graph that
contains the plain name of the relationship target. This is useful for
clients when the relationship target symbol is not available.
Differential Revision: https://reviews.llvm.org/D136455
Dmitry Preobrazhensky [Mon, 7 Nov 2022 12:52:55 +0000 (15:52 +0300)]
[AMDGPU][MC][GFX11][NFC] Correct VINTERP src operands
Differential Revision: https://reviews.llvm.org/D137238
Dmitry Preobrazhensky [Mon, 7 Nov 2022 12:45:55 +0000 (15:45 +0300)]
[AMDGPU][MC][GFX10+] Enable literal operands with permlane16/permlanex16
Differential Revision: https://reviews.llvm.org/D137332
OCHyams [Mon, 7 Nov 2022 12:33:23 +0000 (12:33 +0000)]
Fix warning: comparison of integers of different signs
Buildbot failure:
https://lab.llvm.org/buildbot/#/builders/36/builds/26925
Review & commit:
https://reviews.llvm.org/D132224
https://reviews.llvm.org/rG171f7024cc82e8702abebdedb699d37b50574be7
Simon Pilgrim [Mon, 7 Nov 2022 12:27:02 +0000 (12:27 +0000)]
[X86] Flatten WriteShift/Rotate SchedRW defs
Some "inner" defs were being overriding "outer" SchedRW defs, making it very tricky to track what schedule was being used.
Noticed as I'm trying to remove a lot of unnecessary shift/rotate RMW overrides from the scheduler models
OCHyams [Mon, 7 Nov 2022 11:56:36 +0000 (11:56 +0000)]
[Assignment Tracking][5/*] Add core infrastructure for instruction reference
The Assignment Tracking debug-info feature is outlined in this RFC:
https://discourse.llvm.org/t/
rfc-assignment-tracking-a-better-way-of-specifying-variable-locations-in-ir
Overview
It's possible to find intrinsics linked to an instruction by looking at the
MetadataAsValue uses of the attached DIAssignID. That covers instruction ->
intrinsic(s) lookup. Add a global DIAssignID -> instruction(s) map which gives
us the ability to perform intrinsic -> instruction(s) lookup. Add plumbing to
keep the map up to date through optimisations and add utility functions
including two that perform those lookups. Finally, add a unittest.
Details
In llvm/lib/IR/LLVMContextImpl.h add AssignmentIDToInstrs which maps DIAssignID
* attachments to Instruction *s. Because the DIAssignID * is the key we can't
use a TrackingMDNodeRef for it, and therefore cannot easily update the mapping
when a temporary DIAssignID is replaced.
Temporary DIAssignID's are only used in IR parsing to deal with metadata
forward references. Update llvm/lib/AsmParser/LLParser.cpp to avoid using
temporary DIAssignID's for attachments.
In llvm/lib/IR/Metadata.cpp add Instruction::updateDIAssignIDMapping which is
called to remove or add an entry (or both) to AssignmentIDToInstrs. Call this
from Instruction::setMetadata and add a call to setMetadata in Intruction's
dtor that explicitly unsets the DIAssignID so that the mappging gets updated.
In llvm/lib/IR/DebugInfo.cpp and DebugInfo.h add utility functions:
getAssignmentInsts(const DbgAssignIntrinsic *DAI)
getAssignmentMarkers(const Instruction *Inst)
RAUW(DIAssignID *Old, DIAssignID *New)
deleteAll(Function *F)
These core utils are tested in llvm/unittests/IR/DebugInfoTest.cpp.
Reviewed By: jmorse
Differential Revision: https://reviews.llvm.org/D132224
Christian Kandeler [Tue, 21 Jun 2022 13:56:21 +0000 (15:56 +0200)]
[clangd] Add "usedAsMutablePointer" highlighting modifier
Counterpart to "usedAsMutableReference". Just as for references, there
are const and non-const pointer parameters, and it's valuable to be able
to have different highlighting for the two cases at the call site.
We could have re-used the existing modifier, but having a dedicated one
maximizes client flexibility.
Reviewed By: nridge
Differential Revision: https://reviews.llvm.org/D130015
OCHyams [Mon, 7 Nov 2022 09:31:45 +0000 (09:31 +0000)]
[Assignment Tracking][4/*] Add llvm.dbg.assign intrinsic boilerplate
The Assignment Tracking debug-info feature is outlined in this RFC:
https://discourse.llvm.org/t/
rfc-assignment-tracking-a-better-way-of-specifying-variable-locations-in-ir
Add the llvm.dbg.assign intrinsic boilerplate. This updates the textual-bitcode
roundtrip test to also check that round-tripping with the intrinsic works.
The intrinsic marks the position of a source level assignment.
The llvm.dbg.assign interface looks like this (each parameter is wrapped in
MetadataAsValue, and Value * type parameters are first wrapped in
ValueAsMetadata):
void @llvm.dbg.assign(Value *Value,
DIExpression *ValueExpression,
DILocalVariable *Variable,
DIAssignID *ID,
Value *Address,
DIExpression *AddressExpression)
The first three parameters look and behave like an llvm.dbg.value. ID is a
reference to a store. The intrinsic is "linked to" instructions in the same
function that use the same ID as an attachment. That is mostly conceptual at
this point; the two-way link infrastructure will come in another patch. Address
is the destination address of the store and it is modified by
AddressExpression. LLVM currently encodes variable fragment information in
DIExpressions, so as an implementation quirk the FragmentInfo for Variable is
contained within ValueExpression only.
Reviewed By: jmorse
Differential Revision: https://reviews.llvm.org/D132223
David Green [Mon, 7 Nov 2022 10:03:18 +0000 (10:03 +0000)]
[InstSimplify] (~A & B) | ~(A | B) --> ~A with logical and
According to https://alive2.llvm.org/ce/z/opsdrb, it is valid to convert
(~A & B) | ~(A | B) --> ~A even if the And is a Logical And. This came
up from the vector masking of predicated blocks.
Differential Revision: https://reviews.llvm.org/D137435
Thomas Preud'homme [Fri, 21 Oct 2022 14:42:56 +0000 (15:42 +0100)]
[SWP] Recognize mem carried dep with different base
The loop-carried dependency detection logic in isLoopCarriedDep relies
on the load and store using the same definition for the base register.
This misses the case of post-increment loads and stores whose base
register are different PHI initialized from the same initial value.
This commit extends the logic to accept the load and store having
different PHI base address provided that they had the same initial value
when entering the loop and are incremented by the same amount in each
loop.
Reviewed By: bcahoon
Differential Revision: https://reviews.llvm.org/D136463
Chen Zheng [Mon, 7 Nov 2022 09:10:06 +0000 (04:10 -0500)]
[PowerPC][NFC] fix the LIT regressions
This is to fix the wrong checking introdued in D64195.
`std {{[0-9]+}}, 16(1)` is the store for the lr register. It breaks
previous testing point before D64195.
chenglin.bi [Mon, 7 Nov 2022 09:15:59 +0000 (17:15 +0800)]
Recommit [AArch64] Improve codegen for shifted mask op
The original change compares `APInt` to check the constant is the same or not. But shift amount may have different constant types.
So, this patch change to use `getZExtValue` to compare constant value.
Original comment:
The special case for bit extraction pattern is `((x >> C) & mask) << C`.
It can be combined to `x & (mask << C)` by return true in isDesirableToCommuteWithShift.
Fix: #56427
Reviewed By: dmgreen
Differential Revision: https://reviews.llvm.org/D136014
OCHyams [Thu, 3 Nov 2022 09:50:31 +0000 (09:50 +0000)]
[Assignment Tracking][3/*] Add DIAssignID metadata boilerplate
The Assignment Tracking debug-info feature is outlined in this RFC:
https://discourse.llvm.org/t/
rfc-assignment-tracking-a-better-way-of-specifying-variable-locations-in-ir
Add the DIAssignID metadata attachment boilerplate. Includes a textual-bitcode
roundtrip test and tests that the verifier and parser catch badly formed IR.
This piece of metadata links together stores (used as an attachment) and the
yet-to-be-added llvm.dbg.assign debug intrinsic (used as an operand).
Reviewed By: jmorse
Differential Revision: https://reviews.llvm.org/D132222
Phoebe Wang [Mon, 7 Nov 2022 08:36:26 +0000 (16:36 +0800)]
[X86] Add missing `IntrArgMemOnly` for intrinsics
Reviewed By: nikic
Differential Revision: https://reviews.llvm.org/D137406
David Green [Mon, 7 Nov 2022 09:04:06 +0000 (09:04 +0000)]
[InstSimplify] Add tests for (~A & B) | ~(A | B) --> ~A with logical And. NFC
Timm Bäder [Mon, 31 Oct 2022 08:08:20 +0000 (09:08 +0100)]
[clang][Interp][NFC] Replace dyn_cast_or_null with _if_present
... in Descriptor.h
Timm Bäder [Mon, 31 Oct 2022 07:33:30 +0000 (08:33 +0100)]
[clang][Interp][NFC] Simplify visitReturnStmt()
Timm Bäder [Sun, 30 Oct 2022 09:22:44 +0000 (10:22 +0100)]
[clang][Interp][NFC] Remove unused function
Timm Bäder [Mon, 31 Oct 2022 11:58:27 +0000 (12:58 +0100)]
[clang][Interp][NFC] Avoid a getSource() call in the common case
In the common (successful) case, we don't need the getSource() call, so
move it to the two if statement bodies instead.
Nathan Ridge [Mon, 31 Oct 2022 07:22:29 +0000 (03:22 -0400)]
[clangd] Fix a small inconsistency in system-include-extractor.test
Also add an explanatory comment
Differential Revision: https://reviews.llvm.org/D137056
Adrian Kuegel [Mon, 7 Nov 2022 08:23:07 +0000 (09:23 +0100)]
[mlir] Apply two ClangTidy findings.
- argument name 'isLastOutput' in comment does not match parameter name
'hasOutput'.
- override is redundant since the function is already declared 'final'.
Timm Bäder [Sun, 30 Oct 2022 09:05:42 +0000 (10:05 +0100)]
[clang][Interp][NFCI] Cleanup emitConst()
Before, when emitting a regular integer constant, we went:
Int -> APInt -> int -> emit
Fix this by using regular integer constants in emitConst() and instead
converting APInt to those once.
Serguei Katkov [Mon, 7 Nov 2022 07:37:54 +0000 (14:37 +0700)]
[Greedy RegAlloc] Add a test for single block split with statepoint uses.
The test shows redundant usage of callee saved register in case
basic block has only one non-statepoint use.
Timm Bäder [Sat, 22 Oct 2022 07:27:21 +0000 (09:27 +0200)]
[clang][Interp][NFC] Handle discarded ArraySubscriptExprs
This is not exactly a common case, so just pop the pointer at the end if
necessary.
Tobias Hieta [Mon, 7 Nov 2022 07:34:40 +0000 (08:34 +0100)]
[clang-format] Handle object instansiation in if-statements
Before this patch code like this:
```
if (Class* obj{getObject()}) { }
```
would be mis-formated since the * would be annotated as a
binaryoperator.
This patch changes the * to become a PointerOrReference instead
and fixes the formatting issues.
Reviewed By: HazardyKnusperkeks
Differential Revision: https://reviews.llvm.org/D137327
Timm Bäder [Fri, 21 Oct 2022 13:43:42 +0000 (15:43 +0200)]
[clang][Interp][NFC] Make InitField() not pop the pointer
This was confusing. InitElem peeks a pointer, while InitElemPop will
pop the pointer. However, for fields, InitField would pop the pointer
and no InitFieldPop exists. At least make InitField and InitElem behave
the same.
Chen Zheng [Mon, 7 Nov 2022 07:03:48 +0000 (02:03 -0500)]
[PowerPC][NFC] use script to generate check lines
Timm Bäder [Fri, 21 Oct 2022 10:26:05 +0000 (12:26 +0200)]
[clang][Interp][NFC] Use StorePop for assignments with DiscardResult
If we don't need the result anyway, use StorePop, instead of a Store+Pop
combination. That way we save one instruction and not using the result
is the common case anyway.
Timm Bäder [Thu, 13 Oct 2022 08:09:36 +0000 (10:09 +0200)]
[clang][Interp] Support pointer arithmethic in binary operators
Differential Revision: https://reviews.llvm.org/D135858
Timm Bäder [Mon, 7 Nov 2022 06:22:30 +0000 (07:22 +0100)]
[clang][Interp] Add a test case for #58754
This works in the new interpreter but is rejected by the current one.
Make sure it keeps working.
Matt Arsenault [Sat, 5 Nov 2022 18:23:27 +0000 (11:23 -0700)]
AMDGPU: Fix faulty divergence analysis tests
These were supposed to be checking that atomics were treated
as divergence sources. However, they were using function arguments
which are always treated as divergent, so they could have
been found divergent for the wrong reason.
Matt Arsenault [Sat, 5 Nov 2022 18:20:41 +0000 (11:20 -0700)]
AMDGPU: Fix missing divergence tests for csub intrinsics
Matt Arsenault [Sat, 5 Nov 2022 19:33:43 +0000 (12:33 -0700)]
GlobalISel: Pass through AA metadata for target memory intrinsics
The corresponding change for the DAG was done in
fa4aac7335ac7ecabbb634d134bd4897783bf62b
Matt Arsenault [Sat, 5 Nov 2022 19:16:56 +0000 (12:16 -0700)]
AMDGPU: Add new test for target intrinsic aliasing metadata
The intrinsic used for the test will soon be removed, so move
the test to use another one.
Replaces test added in
fa4aac7335ac7ecabbb634d134bd4897783bf62b
Timm Bäder [Fri, 4 Nov 2022 10:55:18 +0000 (11:55 +0100)]
[clang][Interp][NFC] Remove an unused include
And an unnecessary private marker.
Kazu Hirata [Mon, 7 Nov 2022 05:09:20 +0000 (21:09 -0800)]
[clang] Use llvm::reverse (NFC)
Kazu Hirata [Mon, 7 Nov 2022 04:48:55 +0000 (20:48 -0800)]
[clang-tidy] Use structured bindings (NFC)
Kazu Hirata [Mon, 7 Nov 2022 04:04:53 +0000 (20:04 -0800)]
[Sema] Use llvm::is_contained (NFC)
Kazu Hirata [Mon, 7 Nov 2022 03:58:51 +0000 (19:58 -0800)]
[flang] Use llvm::is_contained (NFC)
Kazu Hirata [Mon, 7 Nov 2022 03:56:15 +0000 (19:56 -0800)]
[mlir] Use llvm::is_contained (NFC)
Kazu Hirata [Mon, 7 Nov 2022 03:53:02 +0000 (19:53 -0800)]
[PowerPC] Use llvm::is_contained (NFC)
Sean Cross [Mon, 7 Nov 2022 03:02:08 +0000 (19:02 -0800)]
[builtins] Check __SIZEOF_INT128__ for CRT_HAS_128BIT
When building libstd on Rust for a riscv32 target, `compiler-rt` fails to build with the following error:
```
running: "riscv-none-elf-gcc" "-O3" "-ffunction-sections" "-fdata-sections" "-fPIC" "-march=rv32imac" "-mabi=ilp32" "-mcmodel=medany" "-fno-builtin" "-fvisibility=hidden" "-ffreestanding" "-fomit-frame-pointer" "-ffile-prefix-map=E:\\Code\\Xous\\rust-next\\src\\llvm-project\\compiler-rt=." "-DVISIBILITY_HIDDEN" "-o" "E:\\Code\\Xous\\rust-next\\target\\riscv32imac-unknown-xous-elf\\release\\build\\compiler_builtins-
b0d7dd25c6999904\\out\\absvdi2.o" "-c" "E:\\Code\\Xous\\rust-next\\src\\llvm-project\\compiler-rt\\lib/builtins\\absvdi2.c"
cargo:warning=In file included from E:\Code\Xous\rust-next\src\llvm-project\compiler-rt\lib/builtins\int_lib.h:99,
cargo:warning= from E:\Code\Xous\rust-next\src\llvm-project\compiler-rt\lib/builtins\absvdi2.c:13:
cargo:warning=E:\Code\Xous\rust-next\src\llvm-project\compiler-rt\lib/builtins\int_types.h:79:1: error: unable to emulate 'TI'
cargo:warning= 79 | typedef int ti_int __attribute__((mode(TI)));
cargo:warning= | ^~~~~~~
cargo:warning=E:\Code\Xous\rust-next\src\llvm-project\compiler-rt\lib/builtins\int_types.h:80:1: error: unable to emulate 'TI'
cargo:warning= 80 | typedef unsigned tu_int __attribute__((mode(TI)));
cargo:warning= | ^~~~~~~
exit code: 1
```
This is because 128-bit support is gated on the `__riscv` compiler macro which is valid for both rv32 and rv64. However, only rv64 has 128-bit support, so this fails when building for rv32.
Add a check for `__SIZEOF_INT128__` to ensure that 128-bit support is only enabled on targets that support it.
Reviewed By: MaskRay
Differential Revision: https://reviews.llvm.org/D137485
wangpc [Mon, 7 Nov 2022 02:40:19 +0000 (10:40 +0800)]
[RISCV] Support -mcpu/mtune=native
We may need hosted Clang/LLVM to compile and `getHostCpuName`
can be used for native detection.
Tests are added in riscv-cpus.c just like what AArch64/PPC
have done.
Reviewed By: kito-cheng
Differential Revision: https://reviews.llvm.org/D136930
Fangrui Song [Mon, 7 Nov 2022 01:38:57 +0000 (17:38 -0800)]
[test] Canonicalize PowerPC detection macros to __powerpc__
Fangrui Song [Mon, 7 Nov 2022 01:34:04 +0000 (17:34 -0800)]
[builtins] Canonicalize PowerPC detection macros to __powerpc__
The lowercase __ppc__ is not defined by Linux GCC, therefore it lures
users to write code which is not portable to GCC. Migrate to __powerpc__ in
preparation for undefining __ppc__. __powerpc__ is much more common than
__PPC__.
Fangrui Song [Mon, 7 Nov 2022 01:29:44 +0000 (17:29 -0800)]
Canonicalize PowerPC detection macros to __powerpc__
Fangrui Song [Mon, 7 Nov 2022 00:16:50 +0000 (16:16 -0800)]
[PowerPC] Replace __ppc64__ with __powerpc64__
The lowercase __ppc64__ is not defined by non-darwin GCC, therefore it lures
users to write code which is not portable to GCC. Migrate to __powerpc64__ in
preparation for undefining __ppc64__. __powerpc64__ is much more common than
__PPC64__.