Sergei Grechanik [Wed, 5 May 2021 15:33:19 +0000 (08:33 -0700)]
[mlir][Affine][Vector] Support vectorizing reduction loops
This patch adds support for vectorizing loops with 'iter_args'
implementing known reductions along the vector dimension. Comparing to
the non-vector-dimension case, two additional things are done during
vectorization of such loops:
- The resulting vector returned from the loop is reduced to a scalar
using `vector.reduce`.
- In some cases a mask is applied to the vector yielded at the end of
the loop to prevent garbage values from being written to the
accumulator.
Vectorization of reduction loops is disabled by default. To enable it, a
map from loops to array of reduction descriptors should be explicitly passed to
`vectorizeAffineLoops`, or `vectorize-reductions=true` should be passed
to the SuperVectorize pass.
Current limitations:
- Loops with a non-unit step size are not supported.
- n-D vectorization with n > 1 is not supported.
Reviewed By: nicolasvasilache
Differential Revision: https://reviews.llvm.org/D100694
Jinsong Ji [Wed, 5 May 2021 16:10:28 +0000 (16:10 +0000)]
[clang][Driver] Add -fintegrate-as to debug-pass-structure test
CGProfilePass is not always on, it will be disabled when using
non-intergrated assemblers.
// Only enable CGProfilePass when using integrated assembler, since
// non-integrated assemblers don't recognize .cgprofile section.
PMBuilder.CallGraphProfile = !CodeGenOpts.DisableIntegratedAS;
Add -fintegrate-as to make sure the output don't rely on the platform default.
Reviewed By: evgeny777
Differential Revision: https://reviews.llvm.org/D101918
Sushma Unnibhavi [Wed, 5 May 2021 16:07:22 +0000 (21:37 +0530)]
Added a faster method to clone llvm project [DOCS]
Reviewed By: xgupta, amccarth
Differential Revision: https://reviews.llvm.org/D101433
Pooja Yadav [Wed, 5 May 2021 15:57:24 +0000 (21:27 +0530)]
[docs] Update the llvm/example section
Added details about the llvm/example section.
Reviewed By: xgupta
Differential Revision: https://reviews.llvm.org/D101284
Jessica Clarke [Wed, 5 May 2021 16:00:40 +0000 (17:00 +0100)]
Revert "[SelectionDAG][Mips][PowerPC][RISCV][WebAssembly] Teach computeKnownBits/ComputeNumSignBits about atomics"
This seems to have broken sanitizers, giving lots of
Assertion `NumBits <= MAX_INT_BITS && "bitwidth too large"' failed.
failures across multiple targets (currently X86 and PowerPC). Reverting
until I have a chance to reproduce and debug.
This reverts commit
6e876f9dedf00b24a96b8781e3b39d5282c43e91.
Guillaume Chatelet [Wed, 5 May 2021 15:52:42 +0000 (15:52 +0000)]
[libc] Normalize LIBC_TARGET_MACHINE
Current implementation defines LIBC_TARGET_MACHINE with the use of CMAKE_SYSTEM_PROCESSOR.
Unfortunately CMAKE_SYSTEM_PROCESSOR is OS dependent and can produce different results.
An evidence of this is the various matchers used to detect whether the architecture is x86.
This patch normalizes LIBC_TARGET_MACHINE and renames it LIBC_TARGET_ARCHITECTURE.
I've added many architectures but we may want to limit ourselves to x86 and ARM.
Differential Revision: https://reviews.llvm.org/D101524
Fraser Cormack [Wed, 5 May 2021 15:40:28 +0000 (16:40 +0100)]
[RISCV][NFC] Fix up pseudoinstruction name in comment
Jessica Clarke [Wed, 5 May 2021 14:32:34 +0000 (15:32 +0100)]
[SelectionDAG][Mips][PowerPC][RISCV][WebAssembly] Teach computeKnownBits/ComputeNumSignBits about atomics
Unlike normal loads these don't have an extension field, but we know
from TargetLowering whether these are sign-extending or zero-extending,
and so can optimise away unnecessary extensions.
This was noticed on RISC-V, where sign extensions in the calling
convention would result in unnecessary explicit extension instructions,
but this also fixes some Mips inefficiencies. PowerPC sees churn in the
tests as all the zero extensions are only for promoting 32-bit to
64-bit, but these zero extensions are still not optimised away as they
should be, likely due to i32 being a legal type.
This also simplifies the WebAssembly code somewhat, which currently
works around the lack of target-independent combines with some ugly
patterns that break once they're optimised away.
Reviewed By: RKSimon, atanasyan
Differential Revision: https://reviews.llvm.org/D101342
Vang Thao [Tue, 4 May 2021 23:43:07 +0000 (16:43 -0700)]
[GlobalISel] Fix buildZExtInReg creating new register.
Fix a bug where buildZExtInReg will create and use a new register instead of using the register from parameter DstOp Res.
Reviewed By: arsenm, foad
Differential Revision: https://reviews.llvm.org/D101871
Sanjay Patel [Wed, 5 May 2021 14:29:52 +0000 (10:29 -0400)]
[InstCombine] improve readability; NFC
Simon Pilgrim [Wed, 5 May 2021 14:55:53 +0000 (15:55 +0100)]
[MIPS][MSA] Regenerate immediates tests. NFCI.
Simplifies an upcoming patch diff
Simon Pilgrim [Wed, 5 May 2021 14:52:44 +0000 (15:52 +0100)]
[MIPS][MSA] Regenerate i5-b tests. NFCI.
Simplifies an upcoming patch diff
Simon Pilgrim [Wed, 5 May 2021 14:52:03 +0000 (15:52 +0100)]
[MIPS][MSA] Regenerate bitwise tests. NFCI.
Simplifies an upcoming patch diff
Baptiste Saleil [Wed, 5 May 2021 14:56:40 +0000 (10:56 -0400)]
[AMDGPU] Fix llc pipeline lit test for bots enabling expensive checks
Tobias Gysi [Wed, 5 May 2021 13:58:57 +0000 (13:58 +0000)]
[mlir][linalg] Fix bug in the fusion on tensors index op handling.
The old index op handling let the new index operations point back to the
producer block. As a result, after fusion some index operations in the
fused block had back references to the old producer block resulting in
illegal IR. The patch now relies on a block and value mapping to avoid
such back references.
Differential Revision: https://reviews.llvm.org/D101887
Pushpinder Singh [Wed, 5 May 2021 12:02:25 +0000 (12:02 +0000)]
[AMDGPU][OpenMP] Fix clang driver crash when provided -c
The offload action is used in four different ways as explained
in Driver.cpp:4495. When -c is present, the final phase will be
assemble (linker when -c is not present). However, this phase
is skipped according to D96769 for amdgcn. So, offload action
arrives into following situation,
compile (device) ---> offload ---> offload
without -c the chain looks like,
compile (device) ---> offload ---> linker (device)
---> offload
The former situation creates an unhandled case which causes
problem. The solution presented in this patch delays the D96769
logic until job creation time. This keeps the offload action
in the 1 of the 4 specified situations.
Reviewed By: JonChesterfield
Differential Revision: https://reviews.llvm.org/D101901
Anirudh Prasad [Wed, 5 May 2021 14:21:27 +0000 (10:21 -0400)]
[AsmParser][SystemZ][z/OS] Reject character and string literals for HLASM
- As per the HLASM support we are providing, i.e. support only for the first parameter of the inline asm block, only pertaining to Z machine instructions defined in LLVM, character literals and string literals are not supported (see Figure 4 - https://www-01.ibm.com/servers/resourcelink/svc00100.nsf/pages/zOSV2R3sc264940/$file/asmr1023.pdf for more information)
- This patch explicitly rejects the usage of char literals and string literals (for example "abc 'a'") when the relevant field is set
- This is achieved by introducing a field called `LexHLASMStrings` in MCAsmLexer similar to `LexMasmStrings`
Reviewed By: abhina.sreeskantharajan, Kai
Differential Revision: https://reviews.llvm.org/D101660
Stelios Ioannou [Wed, 5 May 2021 10:02:33 +0000 (11:02 +0100)]
[AArch64] Fix for the pre-indexed paired load/store optimization.
This patch fixes an issue where a pre-indexed store e.g.,
STR x1, [x0, #24]! with a store like STR x0, [x0, #8] are
merged into a single store: STP x1, x0, [x0, #24]!
. They shouldn’t be merged because the second store uses
x0 as both the stored value and the address and so it needs to be using the updated x0.
Therefore, it should not be folded into a STP <>pre.
Additionally a new test case is added to verify this fix.
Differential Revision: https://reviews.llvm.org/D101888
Change-Id: I26f1985ac84e970961e2cdca23c590fa6773851a
Anastasia Stulova [Wed, 5 May 2021 12:18:00 +0000 (13:18 +0100)]
[OpenCL] Add clang extension for non-portable kernel parameters.
Added __cl_clang_non_portable_kernel_param_types extension that
allows using non-portable types as kernel parameters. This allows
bypassing the portability guarantees from the restrictions specified
in C++ for OpenCL v1.0 s2.4.
Currently this only disables the restrictions related to the data
layout. The programmer should ensure the compiler generates the same
layout for host and device or otherwise the argument should only be
accessed on the device side. This extension could be extended to other
case (e.g. permitting size_t) if desired in the future.
Patch by olestrohm (Ole Strohm)!
https://reviews.llvm.org/D101168
Jinsong Ji [Wed, 5 May 2021 13:51:02 +0000 (13:51 +0000)]
[DebugInfo][test][MIPS] Use mtriple in tests
Mips tests are using -march in RUN lines,
this will fail on AIX OS , when we get the mips-ibm-aix triple.
This is caused/exposed recently due to https://reviews.llvm.org/D101194 changed the default getMultiarchTriple in toolchain.
Update the tests to use -mtriple instead to avoid unintended failures.
Reviewed By: atanasyan
Differential Revision: https://reviews.llvm.org/D101863
Abhina Sreeskantharajan [Wed, 5 May 2021 13:41:45 +0000 (09:41 -0400)]
[SystemZ][z/OS] Fix return values in AutoConversion functions
My previous patch https://reviews.llvm.org/rG1527a5e4b4834e65678f9c30f786a2f4c17932bf incorrectly set int return values instead of std::error_code. This patch correctly returns and std::error_code value.
Reviewed By: fanbo-meng, Jonathan.Crowther
Differential Revision: https://reviews.llvm.org/D101904
Andrew Savonichev [Thu, 29 Apr 2021 16:34:39 +0000 (19:34 +0300)]
[AArch64] Fix scalar imm variants of SIMD shift left instructions
This issue was reported in PR50057: Cannot select:
t10: i64 = AArch64ISD::VSHL t2, Constant:i32<2>
Shift intrinsics (llvm.aarch64.neon.ushl.i64 and sshl) with a constant
shift operand are lowered into AArch64ISD::VSHL in tryCombineShiftImm.
VSHL has i64 and v1i64 patterns for a right shift, but only v1i64 for
a left shift.
This patch adds the missing i64 pattern for AArch64ISD::VSHL, and LIT
tests to cover scalar variants (i64 and v1i64) of all shift
intrinsics (only ushl and sshl cases fail without the patch, others
were just not covered).
Differential Revision: https://reviews.llvm.org/D101580
Bjorn Pettersson [Tue, 4 May 2021 17:08:58 +0000 (19:08 +0200)]
Make dependency between certain analysis passes transitive (reapply)
LazyBlockFrequenceInfoPass, LazyBranchProbabilityInfoPass and
LoopAccessLegacyAnalysis all cache pointers to their nestled required
analysis passes. One need to use addRequiredTransitive to describe
that the nestled passes can't be freed until those analysis passes
no longer are used themselves.
There is still a bit of a mess considering the getLazyBPIAnalysisUsage
and getLazyBFIAnalysisUsage functions. Those functions are used from
both Transform, CodeGen and Analysis passes. I figure it is OK to
use addRequiredTransitive also when being used from Transform and
CodeGen passes. On the other hand, I figure we must do it when
used from other Analysis passes. So using addRequiredTransitive should
be more correct here. An alternative solution would be to add a
bool option in those functions to let the user tell if it is a
analysis pass or not. Since those lazy passes will be obsolete when
new PM has conquered the world I figure we can leave it like this
right now.
Intention with the patch is to fix PR49950. It at least solves the
problem for the reproducer in PR49950. However, that reproducer
need five passes in a specific order, so there are lots of various
"solutions" that could avoid the crash without actually fixing the
root cause.
This is a reapply of commit
3655f0757f2b4b, that was reverted in
33ff3c20498ef5c2057 due to problems with assertions in the polly
lit tests. That problem is supposed to be solved by also adjusting
ScopPass to explicitly preserve LazyBlockFrequencyInfo and
LazyBranchProbabilityInfo (it already preserved
OptimizationRemarkEmitter which depends on those lazy passes).
Differential Revision: https://reviews.llvm.org/D100958
Simon Pilgrim [Wed, 5 May 2021 11:21:30 +0000 (12:21 +0100)]
[X86][SSE] Move unpack(hop,hop) fold from foldShuffleOfHorizOp to combineTargetShuffle
By moving this after more of the shuffle canonicalization we reduce the demanded vector elts, avoiding a few unnecessary copies/moves etc.
Martin Storsjö [Wed, 5 May 2021 12:23:14 +0000 (15:23 +0300)]
Revert "[Passes] Enable the relative lookup table converter pass on aarch64"
This reverts commit
57b259a852a6383880f5d0875d848420bb3c2945.
The relative lookup table converter pass seems to cause problems
for chromium on Windows/ARM64, see https://crbug.com/1204788.
Fraser Cormack [Wed, 5 May 2021 12:11:11 +0000 (13:11 +0100)]
[RISCV][VP][NFC] Add tests for VP_SREM and VP_UREM
As agreed in D101826, these are follow-up tests for the RISC-V VP
support.
Jay Foad [Wed, 5 May 2021 12:05:38 +0000 (13:05 +0100)]
[AMDGPU] Autogenerate checks for a clustering test and add GFX10
Fraser Cormack [Wed, 5 May 2021 12:08:11 +0000 (13:08 +0100)]
[RISCV][VP][NFC] Add tests for VP_MUL and VP_[US]DIV
As agreed in D101826, these are follow-up tests for the RISC-V VP
support.
Alexey Bataev [Tue, 4 May 2021 14:48:06 +0000 (07:48 -0700)]
[X86]Fix a crash trying to convert indices to proper type.
Need to perfortm a bitcast on IndicesVec rather than subvector extract
if the original size of the IndicesVec is the same as the size of the
destination type.
Differential Revision: https://reviews.llvm.org/D101838
Uday Bondhugula [Wed, 5 May 2021 07:47:33 +0000 (13:17 +0530)]
[MLIR] Rename free function `verify` on OffsetSizeAndStrideOpInterface
Using a free function verify(<Op>) is error prone. Rename it.
Differential Revision: https://reviews.llvm.org/D101886
Fraser Cormack [Wed, 5 May 2021 12:01:04 +0000 (13:01 +0100)]
[RISCV][VP][NFC] Add tests for VP_SHL and VP_LSHR
As agreed in D101826, these are follow-up tests for the RISC-V VP
support. Tests for VP_ASHR were landed as part of D101826.
Fraser Cormack [Wed, 5 May 2021 11:56:16 +0000 (12:56 +0100)]
[RISCV][VP][NFC] Add tests for VP_AND, VP_XOR, VP_OR
As agreed in D101826, these are follow-up tests for the RISC-V VP
support.
Fraser Cormack [Thu, 29 Apr 2021 15:58:56 +0000 (16:58 +0100)]
[RISCV][VP] Lower VP ISD nodes to RVV instructions
This patch supports all of the current set of VP integer binary
intrinsics by lowering them to to RVV instructions. It does so by using
the existing RISCVISD *_VL custom nodes as an intermediate layer. Both
scalable and fixed-length vectors are supported by using this method.
One notable change to the existing vector codegen strategy is that
scalable all-ones and all-zeros mask SPLAT_VECTORs are now lowered to
RISCVISD VMSET_VL and VMCLR_VL nodes to match their fixed-length
BUILD_VECTOR counterparts. This allows them to reuse the existing
"all-ones" VL patterns.
To reduce the size of the phabricator diff, some tests are intentionally
left out and will be added later if the patch is accepted.
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D101826
Alexander Belyaev [Wed, 5 May 2021 09:02:24 +0000 (11:02 +0200)]
[mlir] Use ReassociationIndices instead of affine maps in linalg.reshape.
Differential Revision: https://reviews.llvm.org/D101861
Sushma Unnibhavi [Wed, 5 May 2021 10:11:23 +0000 (15:41 +0530)]
[DOCS] Added example for G_EXTRACT and G_INSERT
Reviewed By: xgupta, gargaroff
Differential Revision: https://reviews.llvm.org/D101227
Hans Wennborg [Wed, 5 May 2021 09:42:16 +0000 (11:42 +0200)]
Require asserts for clang/test/Headers/wasm.c
The test doesn't pass in no-asserts builds, see comment on
https://reviews.llvm.org/D101805
Fraser Cormack [Tue, 4 May 2021 14:18:28 +0000 (15:18 +0100)]
[RISCV] Cap legal fixed-length vectors to 256-element types
Previously, RISC-V would make legal all fixed-length vectors types whose
size are less than or equal to some function of the minimum value of
VLEN and the maximum-permissible LMUL grouping.
Due to vector legalization issues, this patch instead caps the legal
fixed-length vector types to those with 256 elements. This value was
chosen because it is the longest vector length which has corresponding
MVTs across all supported element types.
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D101839
Julien Pagès [Wed, 5 May 2021 07:53:59 +0000 (08:53 +0100)]
[AMDGPU] Select V_CVT_*16_F16 more often
Improve the code generation of fp_to_sint
and fp_to_uint for integer on 16-bits.
Differential Revision: https://reviews.llvm.org/D101481
Patch by Julien Pagès!
Javier Setoain [Wed, 5 May 2021 07:38:50 +0000 (09:38 +0200)]
[mlir][ArmSVE] Add basic arithmetic operations
While we figure out how to best add Standard support for scalable
vectors, these instructions provide a workaround for basic arithmetic
between scalable vectors.
Reviewed By: nicolasvasilache
Differential Revision: https://reviews.llvm.org/D100837
Fangrui Song [Wed, 5 May 2021 07:20:41 +0000 (00:20 -0700)]
[llvm-objdump] Add -M {att,intel} & deprecate --x86-asm-syntax={att,intel}
The internal `cl::opt` option --x86-asm-syntax sets the AsmParser and AsmWriter
dialect. The option is used by llc and llvm-mc tests to set the AsmWriter dialect.
This patch adds -M {att,intel} as GNU objdump compatible aliases (PR43413).
Note: the dialect is initialized when the MCAsmInfo is constructed.
`MCInstPrinter::applyTargetSpecificCLOption` is called too late and its MCAsmInfo
reference is const, so changing the `cl::opt` in
`MCInstPrinter::applyTargetSpecificCLOption` is not an option, at least without
large amount of refactoring.
Reviewed By: hoy, jhenderson, thakis
Differential Revision: https://reviews.llvm.org/D101695
Yang Fan [Wed, 5 May 2021 06:44:48 +0000 (14:44 +0800)]
[clang][TargetCXXABI] Fix -Wreturn-type warning (NFC)
GCC warning:
```
In file included from /llvm-project/clang/include/clang/Basic/LangOptions.h:22,
from /llvm-project/clang/include/clang/Frontend/CompilerInvocation.h:16,
from /llvm-project/clang/lib/Frontend/CompilerInvocation.cpp:9:
/llvm-project/clang/include/clang/Basic/TargetCXXABI.h: In static member function ‘static bool clang::TargetCXXABI::isSupportedCXXABI(const llvm::Triple&, clang::TargetCXXABI::Kind)’:
/llvm-project/clang/include/clang/Basic/TargetCXXABI.h:114:3: warning: control reaches end of non-void function [-Wreturn-type]
114 | };
| ^
```
Med Ismail Bennani [Wed, 5 May 2021 06:01:50 +0000 (06:01 +0000)]
[lldb/Test] Disable testBreakpointByLineAndColumnNearestCode on Windows
Signed-off-by: Med Ismail Bennani <medismail.bennani@gmail.com>
Jianzhou Zhao [Wed, 5 May 2021 05:30:53 +0000 (05:30 +0000)]
[dfsan] Turn off all dfsan test cases on non x86_64 OSs
https://reviews.llvm.org/D101666 enables sanitizer allocator.
This broke all test cases on non x86-64.
Med Ismail Bennani [Wed, 5 May 2021 04:28:28 +0000 (04:28 +0000)]
[lldb/Symbol] Fix column breakpoint `move_to_nearest_code` match
This patch fixes the column symbol resolution when creating a breakpoint
with the `move_to_nearest_code` flag set.
In order to achieve this, the patch adds column information handling in
the `LineTable`'s `LineEntry` finder. After experimenting a little, it
turns out the most natural approach in case of an inaccurate column match,
is to move backward and match the previous `LineEntry` rather than going
forward like we do with simple line breakpoints.
The patch also reflows the function to reduce code duplication.
Finally, it updates the `BreakpointResolver` heuristic to align it with
the `LineTable` method.
rdar://
73218201
Differential Revision: https://reviews.llvm.org/D101221
Signed-off-by: Med Ismail Bennani <medismail.bennani@gmail.com>
LLVM GN Syncbot [Wed, 5 May 2021 04:57:55 +0000 (04:57 +0000)]
[gn build] Port
600686d75f55
Brad Smith [Wed, 5 May 2021 04:55:36 +0000 (00:55 -0400)]
Fix typo, arvm7 -> armv7
zoecarver [Fri, 23 Apr 2021 18:23:22 +0000 (11:23 -0700)]
[libcxx][ranges] Add ranges::ssize CPO.
Based on D101079.
Differential Revision: https://reviews.llvm.org/D101189
zoecarver [Thu, 22 Apr 2021 16:29:02 +0000 (09:29 -0700)]
[libcxx][ranges] Add ranges::size CPO.
The begining of [range.prim].
Differential Revision: https://reviews.llvm.org/D101079
Juneyoung Lee [Tue, 4 May 2021 01:16:21 +0000 (10:16 +0900)]
[InstCombine] Fold more select of selects using isImpliedCondition
This is a simple folding that does these:
```
select x_inv, true, (select y, x, false)
=>
select x_inv, true, y
```
https://alive2.llvm.org/ce/z/-STJ2d
```
select (select y, x, false), true, x_inv
=>
select y, true, x_inv
```
https://alive2.llvm.org/ce/z/6ruYt6
Reviewed By: spatel
Differential Revision: https://reviews.llvm.org/D101807
Juneyoung Lee [Tue, 4 May 2021 01:14:02 +0000 (10:14 +0900)]
[InstCombine] Precommit tests for D101807 (NFC)
zoecarver [Sat, 24 Apr 2021 00:11:44 +0000 (17:11 -0700)]
[libcxx][ranges] Add `random_access_{iterator,range}`.
Differential Revision: https://reviews.llvm.org/D101316
William S. Moses [Mon, 3 May 2021 23:20:10 +0000 (19:20 -0400)]
[MLIR][SCF] Combine adjacent scf.if with same condition
Differential Revision: https://reviews.llvm.org/D101798
Serguei Katkov [Tue, 4 May 2021 03:56:00 +0000 (10:56 +0700)]
[GreedyRA] Add support for invoke statepoint with tied-defs.
statepoint instruction uses tied-def registers to represent live gc value which
is use and def at the same time on a call.
At the same time invoke statepoint instruction is a last split point which can throw and
jump to landing pad.
As a result we have instructon which is last split point with tied-defs registers and
we need to teach Greedy RA to work with it.
The option -use-registers-for-gc-values-in-landing-pad controls whether statepoint lowering
will generate tied-defs for invoke statepoint and is off by default now.
To resolve all issues the following changes has been done.
1) Last Split point for invoke statepoint should be statepoint itself
If statepoint has a def it is a relocated gc pointer and it should be available in landing pad.
So we cannot split interval after statepoint at end of basic block.
2) Do not split interval on tied-def
If end of interval for overlap utility is a use which has tied-def we
should not split interval on this instruction due to in this case use
and def may have different registers and it breaks tied-def property.
3) Take into account Last Split Point for enterIntvAtEnd
If the use after Last Split Point is a def so it should be tied-def and
we can take the def of the tied-use as ParentVNI and thus
tied-use and tied-def will be live in resulting interval.
4) Handle the case when def is after LIP in InlineSpiller
If def of LI is after last insertion point of basic block we cannot hoist in this BB.
The example of such instruction is invoke statepoint where def represents the
relocated live gc pointer. Invoke is a last insertion point and its def is located after it.
In this case there is no place to insert spill and we bail out.
5) Fix removeBackCopies to account empty copies
RegAssignMap cannot hold empty interval, so do not set stop
to kill value if it produces empty interval.
This can happen if we remove back-copy and right before that we have another
back-copy.
For example, for parent %0 we can get
%1 = COPY %0
%2 = COPY %0
while we removing %2 we cannot set kill for %1 due to its empty.
6) Do not hoist copy to BB if its def is after LSP
If the parent def is a LastSplitPoint or later we cannot hoist copy to this basic block
because inserted copy (or re-materialization) will be located before the def.
All parts have been reviewed separately as follows:
https://reviews.llvm.org/D100747
https://reviews.llvm.org/D100748
https://reviews.llvm.org/D100750
https://reviews.llvm.org/D100927
https://reviews.llvm.org/D100945
https://reviews.llvm.org/D101028
Reviewers: reames, rnk, void, MatzeB, wmi, qcolombet
Reviewed By: reames, qcolombet
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D101150
LLVM GN Syncbot [Wed, 5 May 2021 03:54:38 +0000 (03:54 +0000)]
[gn build] Port
f2018d6c16d1
Lang Hames [Wed, 28 Apr 2021 18:21:59 +0000 (11:21 -0700)]
[ORC] Reintroduce the ORC C API test.
This test was removed in
51495fd285 due to broken bots. Its reintroduction is
expected to trigger failures on some builders. The test has been modified to
print error messages in full, which should aid in tracking these down.
Walter Erquinigo [Mon, 3 May 2021 14:55:35 +0000 (07:55 -0700)]
[trace] Dedup different source lines when dumping instructions + refactor
When dumping the traced instructions in a for loop, like this one
4: for (int a = 0; a < n; a++)
5: do something;
there might be multiple LineEntry objects for line 4, but with different address ranges. This was causing the dump command to dump something like this:
```
a.out`main + 11 at main.cpp:4
[1] 0x0000000000400518 movl $0x0, -0x8(%rbp)
[2] 0x000000000040051f jmp 0x400529 ; <+28> at main.cpp:4
a.out`main + 28 at main.cpp:4
[3] 0x0000000000400529 cmpl $0x3, -0x8(%rbp)
[4] 0x000000000040052d jle 0x400521 ; <+20> at main.cpp:5
```
which is confusing, as main.cpp:4 appears twice consecutively.
This diff fixes that issue by making the line entry comparison strictly about the line, column and file name. Before it was also comparing the address ranges, which we don't need because our output is strictly about what the user sees in the source.
Besides, I've noticed that the logic that traverses instructions and calculates symbols and disassemblies had too much coupling, and made my changes harder to implement, so I decided to decouple it. Now there are two methods for iterating over the instruction of a trace. The existing one does it on raw load addresses, but the one provides a SymbolContext and an InstructionSP, and does the calculations efficiently (not as efficient as possible for now though), so the caller doesn't need to care about these details. I think I'll be using that iterator to reconstruct the call stacks.
I was able to fix a test with this change.
Differential Revision: https://reviews.llvm.org/D100740
Jianzhou Zhao [Wed, 5 May 2021 00:57:34 +0000 (00:57 +0000)]
Revert "[sanitizer_common] Recycle StackDepot memory"
This reverts commit
78804e6b20943f218f4b4a1867f600cf4744ffbd.
Jianzhou Zhao [Fri, 30 Apr 2021 21:19:45 +0000 (21:19 +0000)]
[dfsan] Add a DFSan allocator
This is a part of https://reviews.llvm.org/D101204
Reviewed By: morehouse
Differential Revision: https://reviews.llvm.org/D101666
Jianzhou Zhao [Sat, 6 Feb 2021 10:01:17 +0000 (10:01 +0000)]
[sanitizer_common] Recycle StackDepot memory
This relates to https://reviews.llvm.org/D95835.
In DFSan origin tracking we use StackDepot to record
stack traces and origin traces (like MSan origin tracking).
For at least two reasons, we wanted to control StackDepot's memory cost
1) We may use DFSan origin tracking to monitor programs that run for
many days. This may eventually use too much memory for StackDepot.
2) DFSan supports flush shadow memory to reduce overhead. After flush,
all existing IDs in StackDepot are not valid because no one will
refer to them.
Med Ismail Bennani [Wed, 5 May 2021 00:38:41 +0000 (00:38 +0000)]
[lldb/Symbol] Fix typo in SymbolFilePDBTests (NFC)
Signed-off-by: Med Ismail Bennani <medismail.bennani@gmail.com>
Med Ismail Bennani [Wed, 5 May 2021 00:34:19 +0000 (00:34 +0000)]
[lldb/Symbol] Update SymbolFilePDB unitest with SourceLocationSpec
This patch should fix the windows test failure following `
3e2ed7440569`.
It makes use of a `SourceLocationSpec` object when resolving a symbol
context from `SymbolFilePDB` file.
Signed-off-by: Med Ismail Bennani <medismail.bennani@gmail.com>
Fangrui Song [Wed, 5 May 2021 00:30:57 +0000 (17:30 -0700)]
[llvm-objcopy] --dump-section: error if '=' is missing or filename is empty
Fix PR45416: the diagnostic when '=' is missing is misleading.
`FileOutputBuffer::create` returns successfully when the filename is empty
(the temporary file is `.tmp%%%%%%%`), but `FileOutputBuffer::commit` will error when
renaming `.tmp%%%%%%%` to the empty name).
Reviewed By: jhenderson
Differential Revision: https://reviews.llvm.org/D101697
Giorgis Georgakoudis [Wed, 5 May 2021 00:12:32 +0000 (17:12 -0700)]
Revert "[OpenMP][NFC] Refactor Clang OpenMP tests using update_cc_test_checks"
This reverts commit
956cae2f09b21429dbcb02066c99e35a239aa4bf.
Aart Bik [Tue, 4 May 2021 03:55:12 +0000 (20:55 -0700)]
[mlir][sparse] Introduce proper sparsification passes
This revision migrates more code from Linalg into the new permanent home of
SparseTensor. It replaces the test passes with proper compiler passes.
NOTE: the actual removal of the last glue and clutter in Linalg will follow
Reviewed By: bixia
Differential Revision: https://reviews.llvm.org/D101811
Han Zhu [Tue, 9 Feb 2021 01:24:25 +0000 (17:24 -0800)]
[loop-idiom] Hoist loop memcpys to loop preheader
For a simple loop like:
```
struct S {
int x;
int y;
char b;
};
unsigned foo(S* __restrict__ a, S* b, int n) {
for (int i = 0; i < n; i++)
a[i] = b[i];
return sizeof(a[0]);
}
```
We could eliminate the loop and convert it to a large memcpy of 12*n bytes. Currently this is not handled. Output of `opt -loop-idiom -S < memcpy_before.ll`
```
%struct.S = type { i32, i32, i8 }
define dso_local i32 @_Z3fooP1SS0_i(%struct.S* noalias nocapture %a, %struct.S* nocapture readonly %b, i32 %n) local_unnamed_addr {
entry:
%cmp7 = icmp sgt i32 %n, 0
br i1 %cmp7, label %for.body.preheader, label %for.cond.cleanup
for.body.preheader: ; preds = %entry
br label %for.body
for.cond.cleanup.loopexit: ; preds = %for.body
br label %for.cond.cleanup
for.cond.cleanup: ; preds = %for.cond.cleanup.loopexit, %entry
ret i32 12
for.body: ; preds = %for.body, %for.body.preheader
%i.08 = phi i32 [ %inc, %for.body ], [ 0, %for.body.preheader ]
%idxprom = zext i32 %i.08 to i64
%arrayidx = getelementptr inbounds %struct.S, %struct.S* %b, i64 %idxprom
%arrayidx2 = getelementptr inbounds %struct.S, %struct.S* %a, i64 %idxprom
%0 = bitcast %struct.S* %arrayidx2 to i8*
%1 = bitcast %struct.S* %arrayidx to i8*
call void @llvm.memcpy.p0i8.p0i8.i64(i8* nonnull align 4 dereferenceable(12) %0, i8* nonnull align 4 dereferenceable(12) %1, i64 12, i1 false)
%inc = add nuw nsw i32 %i.08, 1
%cmp = icmp slt i32 %inc, %n
br i1 %cmp, label %for.body, label %for.cond.cleanup.loopexit
}
; Function Attrs: argmemonly nofree nosync nounwind willreturn
declare void @llvm.memcpy.p0i8.p0i8.i64(i8* noalias nocapture writeonly, i8* noalias nocapture readonly, i64, i1 immarg) #0
attributes #0 = { argmemonly nofree nosync nounwind willreturn }
```
The loop idiom pass currently only handles load and store instructions. Since struct S is too big to fit in a register, the loop body contains a memcpy intrinsic.
With this change, re-run `opt -loop-idiom -S < memcpy_before.ll`. The loop memcpy is promoted to loop preheader. For this trivial case, the loop is dead and will be removed by another pass.
```
%struct.S = type { i32, i32, i8 }
define dso_local i32 @_Z3fooP1SS0_i(%struct.S* noalias nocapture %a, %struct.S* nocapture readonly %b, i32 %n) local_unnamed_addr {
entry:
%a1 = bitcast %struct.S* %a to i8*
%b2 = bitcast %struct.S* %b to i8*
%cmp7 = icmp sgt i32 %n, 0
br i1 %cmp7, label %for.body.preheader, label %for.cond.cleanup
for.body.preheader: ; preds = %entry
%0 = zext i32 %n to i64
%1 = mul nuw nsw i64 %0, 12
call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 %a1, i8* align 4 %b2, i64 %1, i1 false)
br label %for.body
for.cond.cleanup.loopexit: ; preds = %for.body
br label %for.cond.cleanup
for.cond.cleanup: ; preds = %for.cond.cleanup.loopexit, %entry
ret i32 12
for.body: ; preds = %for.body, %for.body.preheader
%i.08 = phi i32 [ %inc, %for.body ], [ 0, %for.body.preheader ]
%idxprom = zext i32 %i.08 to i64
%arrayidx = getelementptr inbounds %struct.S, %struct.S* %b, i64 %idxprom
%arrayidx2 = getelementptr inbounds %struct.S, %struct.S* %a, i64 %idxprom
%2 = bitcast %struct.S* %arrayidx2 to i8*
%3 = bitcast %struct.S* %arrayidx to i8*
%inc = add nuw nsw i32 %i.08, 1
%cmp = icmp slt i32 %inc, %n
br i1 %cmp, label %for.body, label %for.cond.cleanup.loopexit
}
; Function Attrs: argmemonly nofree nosync nounwind willreturn
declare void @llvm.memcpy.p0i8.p0i8.i64(i8* noalias nocapture writeonly, i8* noalias nocapture readonly, i64, i1 immarg) #0
attributes #0 = { argmemonly nofree nosync nounwind willreturn }
```
Reviewed By: zino
Differential Revision: https://reviews.llvm.org/D97667
Giorgis Georgakoudis [Tue, 4 May 2021 19:17:42 +0000 (12:17 -0700)]
[OpenMP][NFC] Refactor Clang OpenMP tests using update_cc_test_checks
This patch refactors a subset of Clang OpenMP tests, generating checklines using the update_cc_test_checks script. This refactoring facilitates updating the Clang OpenMP code generation codebase by automating test generation.
Reviewed By: jdoerfert
Differential Revision: https://reviews.llvm.org/D101849
Thomas Lively [Tue, 4 May 2021 23:11:00 +0000 (16:11 -0700)]
[WebAssembly] Add codegen test for wasm_simd128.h
We previously did not have tests demonstrating that the intrinsics in
wasm_simd128.h lower to reasonable LLVM IR. This commit adds such a test.
Differential Revision: https://reviews.llvm.org/D101805
Med Ismail Bennani [Tue, 4 May 2021 23:03:10 +0000 (23:03 +0000)]
[lldb] Refactor argument group by SourceLocationSpec (NFCI)
This patch refactors a good part of the code base turning the usual
FileSpec, Line, Column, CheckInlines, ExactMatch arguments into a
SourceLocationSpec object.
This change is required for a following patch that will add handling of the
column line information when doing symbol resolution.
Differential Revision: https://reviews.llvm.org/D100965
Signed-off-by: Med Ismail Bennani <medismail.bennani@gmail.com>
Jianzhou Zhao [Tue, 4 May 2021 21:19:00 +0000 (21:19 +0000)]
[dfsan] move dfsan_flags.h to cc files
D101666 needs this change.
Reviewed By: morehouse
Differential Revision: https://reviews.llvm.org/D101857
Leonard Chan [Tue, 4 May 2021 22:52:17 +0000 (15:52 -0700)]
[clang][test] Update -fc++-abi tests
This attempts to move driver tests out of Frontend and to Driver, separates
RUNs that should fail from RUNs that should succeed, and prevent creating
output files or dumping output.
Differential Revision: https://reviews.llvm.org/D101867
Louis Dionne [Tue, 4 May 2021 22:48:16 +0000 (18:48 -0400)]
[libc++] Revert the std::to_address change to avoid relying on element_type.
This reverts commit
da456167, which broke the Clang build. I'm able to
reproduce it but I want to give myself a bit more time to investigate.
Differential Revision: https://reviews.llvm.org/D101638
Baptiste Saleil [Tue, 4 May 2021 22:27:02 +0000 (18:27 -0400)]
[AMDGPU] Add rm line to lit test to cleanup bots
River Riddle [Tue, 4 May 2021 21:50:08 +0000 (14:50 -0700)]
[mlir] Fix region successor bug in forward dataflow analysis
We weren't properly visiting region successors when the terminator wasn't return like, which could create incorrect results in the analysis. This revision ensures that we properly visit region successors, to avoid optimistically assuming a value is constant when it isn't.
Differential Revision: https://reviews.llvm.org/D101783
Florian Hahn [Tue, 4 May 2021 21:15:00 +0000 (22:15 +0100)]
[VPlan] Properly handle sinking of replicate regions.
This patch updates the code that sinks recipes required for first-order
recurrences to properly handle replicate-regions. At the moment, the
code would just move the replicate recipe out of its replicate-region,
producing an invalid VPlan.
When sinking a recipe in a replicate-region, we have to sink the whole
region. To do that, we first need to split the block at the target
recipe and move the region in between.
This patch also adds a splitAt helper to VPBasicBlock to split a
VPBasicBlock at a given iterator.
Fixes PR50009.
Reviewed By: Ayal
Differential Revision: https://reviews.llvm.org/D100751
Rob Suderman [Tue, 4 May 2021 21:21:51 +0000 (14:21 -0700)]
[mlir][tosa] Fix tosa.concat by inserting linalg.fill after linalg.init
All linalg.init operations must be fed into a linalg operation before
subtensor. The inserted linalg.fill guarantees it executes correctly.
Reviewed By: mravishankar
Differential Revision: https://reviews.llvm.org/D101848
Baptiste Saleil [Tue, 4 May 2021 21:24:39 +0000 (17:24 -0400)]
Fangrui Song [Tue, 4 May 2021 21:13:19 +0000 (14:13 -0700)]
[MC] Add MCAsmParser::parseComma to improve diagnostics
llvm-mc will error "expected comma" instead of "unexpected token".
Dávid Bolvanský [Tue, 4 May 2021 21:04:05 +0000 (23:04 +0200)]
Revert "[InstSimplify] Added tests for PR50173, NFC"
This reverts commit
4e7a4c73dab6605f4fcc7bf09c2ee85e7925f6d7. Not needed, pattern is handled by instcombine already.
Arthur O'Dwyer [Tue, 4 May 2021 19:50:28 +0000 (15:50 -0400)]
[libc++] Make sure std::to_address doesn't depend on P::element_type.
Differential Revision: https://reviews.llvm.org/D101638
Baptiste Saleil [Tue, 4 May 2021 20:30:56 +0000 (16:30 -0400)]
[AMDGPU] Disable the scalar IR, SDWA and load store vectorizer passes at -O1
This patch disables some of the passes at -O1. These passes have a significant
impact on compilation time, so we only want them to be enabled starting from -O2.
Differential Revision: https://reviews.llvm.org/D101414
Louis Dionne [Mon, 3 May 2021 16:21:13 +0000 (12:21 -0400)]
[libc++] Fix QoI bug with construction of std::tuple involving std::any
In std::tuple, we should try to avoid calling std::is_copy_constructible
whenever we can to avoid surprising interactions with (I believe) compiler
builtins. This bug was reported in https://reviews.llvm.org/D96523#2730953.
The issue was that when tuple<_Up...> was the same as tuple<_Tp...>, we
would short-circuit the _Or (because sizeof...(_Tp) != 1) and go evaluate
the following `is_constructible<_Tp, const _Up&>...`. That shouldn't
actually be a problem, but see the analysis in https://reviews.llvm.org/D101770#2736470
for why it is with Clang and GCC.
Instead, after this patch, we check whether the constructed-from tuple
is the same as the current tuple regardless of the number of elements,
since we should always prefer the normal copy constructor in that case
anyway.
Differential Revision: https://reviews.llvm.org/D101770
Fangrui Song [Tue, 4 May 2021 20:40:26 +0000 (13:40 -0700)]
[MC] Don't capitalize a floating point diagnostic
Matt Arsenault [Sat, 24 Apr 2021 15:42:12 +0000 (11:42 -0400)]
GlobalISel: Fix missing newline in debug printing
Matt Arsenault [Sat, 17 Apr 2021 13:30:59 +0000 (09:30 -0400)]
X86/GlobalISel: Rely on default assignValueToReg
The resulting output is semantically closer to what the DAG emits and
is more compatible with the existing CCAssignFns.
The returns of f32 in f80 are clearly broken, but they were broken
before when using G_ANYEXT to go from f32 to f80.
Fangrui Song [Tue, 4 May 2021 20:30:29 +0000 (13:30 -0700)]
[MC] Remove unneeded "in '.xxx' directive" from diagnostics
The directive name is not useful because the next line replicates the error line
which includes the directive.
Thomas Lively [Tue, 4 May 2021 20:25:31 +0000 (13:25 -0700)]
[WebAssembly] Mark abs of v2i64 as legal
We previously had an ISel pattern for i64x2.abs, but because the ISDNode was not
marked legal for v2i64, the instruction was not being selected.
Differential Revision: https://reviews.llvm.org/D101803
Alina Sbirlea [Tue, 4 May 2021 19:40:49 +0000 (12:40 -0700)]
Add cal entry for MemorySSA syncs.
Xun Li [Tue, 4 May 2021 18:11:43 +0000 (11:11 -0700)]
[Coroutines] Do not add alloca to the frame if the size is 0
This patch is to address https://bugs.llvm.org/show_bug.cgi?id=49916.
When the size of an alloca is 0, it will trigger an assertion in OptimizedStructLayout when being added to the frame.
Fix it by not adding it at all. We return index 0 (beginning of the frame) for all 0-sized allocas.
Differential Revision: https://reviews.llvm.org/D101841
Adrian Prantl [Tue, 4 May 2021 19:52:52 +0000 (12:52 -0700)]
Mark Basic/TargetCXXABI.def as textual in the module map.
Martin Storsjö [Mon, 12 Apr 2021 11:13:32 +0000 (14:13 +0300)]
[llvm-readobj] [ARMWinEH] Try to resolve label symbols into regular ones
Unwind info generated by MSVC tends to have relocations pointing at
static "label" symbols like "$LN4" instead of regular ones based on
the actual function's name. Try to resolve such symbols to a non-label
symbol if possible (ideally to an external symbol), to improve
the readability.
Differential Revision: https://reviews.llvm.org/D101567
Martin Storsjö [Fri, 30 Apr 2021 12:15:13 +0000 (15:15 +0300)]
[LLD] [COFF] Actually include the exported comdat symbols
This is a followup to
2b01a417d7ccb001ccc1185ef5fdc967c9fac8d7;
previously the RVAs of the exported symbols from comdats were left
zero.
Thanks to Kleis Auke Wolthuizen for the fix suggestion and pointing
out the omission.
Differential Revision: https://reviews.llvm.org/D101615
Martin Storsjö [Mon, 3 May 2021 19:14:00 +0000 (22:14 +0300)]
[libcxx] Update docs regarding the need for bash/posix tools for tests on Windows. NFC.
After
39bbfb77264a4a7a216921c2b70a30ba0f27eb56, bash is no longer
a hard requirement.
Differential Revision: https://reviews.llvm.org/D101779
Giorgis Georgakoudis [Sat, 1 May 2021 04:48:32 +0000 (21:48 -0700)]
[Utils] Run non-filecheck runlines in-order in update_cc_test_checks
The script update_cc_test_checks runs all non-filechecked runlines before the filechecked ones. This creates problems since outputs of those non-filechecked runlines may conflict and that will fail the execution of update_cc_test_checks. This patch executes non-filechecked in the order specified in the test file to avoid this issue.
Reviewed By: jdoerfert
Differential Revision: https://reviews.llvm.org/D101683
Giorgis Georgakoudis [Mon, 3 May 2021 23:30:59 +0000 (16:30 -0700)]
[OpenMP] Fix non-determinism in clang task codegen (lastprivates)
Reviewed By: jdoerfert
Differential Revision: https://reviews.llvm.org/D101800
Leonard Chan [Tue, 4 May 2021 18:43:26 +0000 (11:43 -0700)]
Fix for test failure caused by
84c475437267e7fffedc40029ce274b099d8f8f3.
Reduces the number of targets/triples for this test since not all cmake
invocations will build for those targets.
Dan Liew [Sat, 1 May 2021 02:10:18 +0000 (19:10 -0700)]
[Driver] Fix `ToolChain::getCompilerRTPath()` to return the correct path on Apple platforms.
When the target triple was an Apple platform `ToolChain::getOSLibName()`
(called by `getCompilerRTPath()`) would return the full OS name
including the version number (e.g. `darwin20.3.0`). This is not correct
because the library directory for all Apple platforms is `darwin`.
This in turn caused
* `-print-runtime-dir` to return a non-existant path.
* `-print-file-name=<any compiler-rt library>` to return the filename
instead of the full path to the library.
Two regression tests are included.
rdar://
77417317
Differential Revision: https://reviews.llvm.org/D101682
Alina Sbirlea [Tue, 4 May 2021 18:23:12 +0000 (11:23 -0700)]
Add monthly MemorySSA sync.
Fangrui Song [Tue, 4 May 2021 18:05:11 +0000 (11:05 -0700)]
[llvm-objdump] Delete temporary Hexagon workaround options
Nathan James [Tue, 4 May 2021 18:04:11 +0000 (19:04 +0100)]
[Format] Don't sort includes if DisableFormat is true
Fixes https://llvm.org/PR35099.
I'm not sure if this decision was intentional but its definitely confusing for users.
Reviewed By: MyDeveloperDay, HazardyKnusperkeks, curdeius
Differential Revision: https://reviews.llvm.org/D101628
Fangrui Song [Tue, 4 May 2021 18:00:01 +0000 (11:00 -0700)]
[Hexagon][test] Migrate llvm-objdump --mv6[0567]t?/--mhvx to --mcpu=hexagonv*/--mattr=+hvx