sdk/emulator/qemu.git
13 years agotarget-ppc: fix wrong NaN tests
Aurelien Jarno [Mon, 17 Jan 2011 18:29:33 +0000 (19:29 +0100)]
target-ppc: fix wrong NaN tests

Some tests in FPU emulation code were wrongly using float64_is_nan()
before commit 185698715dfb18c82ad2a5dbc169908602d43e81, and wrongly
using float64_is_quiet_nan() after. Fix them by using float64_is_any_nan()
instead.

Reviewed-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
13 years agotarget-ppc: fix sNaN propagation
Aurelien Jarno [Mon, 17 Jan 2011 18:29:33 +0000 (19:29 +0100)]
target-ppc: fix sNaN propagation

The current FPU code returns 0.0 if one of the operand is a
signaling NaN and the VXSNAN exception is disabled.

fload_invalid_op_excp() doesn't return a qNaN in case of a VXSNAN
exception as the operand should be propagated instead of a new
qNaN to be generated. Fix that by calling fload_invalid_op_excp()
only for the exception generation (if enabled), and use the softfloat
code to correctly compute the result.

Reviewed-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
13 years agopxa2xx_lcd: restore updating of display
Dmitry Eremin-Solenikov [Tue, 18 Jan 2011 16:11:33 +0000 (19:11 +0300)]
pxa2xx_lcd: restore updating of display

Recently PXA2xx lcd have stopped to be updated incrementally (picture
frozen). This patch fixes that by passing non min/max x/y, but rather
(correctly) x/y and w/h.

Signed-off-by: Dmitry Eremin-Solenikov <dbaryshkov@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
13 years agopxa2xx: fix vmstate_pxa2xx_i2c
Dmitry Eremin-Solenikov [Thu, 13 Jan 2011 15:37:12 +0000 (18:37 +0300)]
pxa2xx: fix vmstate_pxa2xx_i2c

vmstate_pxa2xx_i2c incorrectly recursed to itself instead of going
to store slave device. Fix that stop stop qemu from segfaulting
during savevm for pxa2xx-based devices.

Signed-off-by: Dmitry Eremin-Solenikov <dbaryshkov@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
13 years agoscoop: fix access to registers from second instance
Dmitry Eremin-Solenikov [Thu, 13 Jan 2011 15:37:11 +0000 (18:37 +0300)]
scoop: fix access to registers from second instance

Second instance of scoop contains registers shifted to 0x40 from the start
of the page. Instead of messing with register mapping, just limit register
address to 0x00..0x3f.

Signed-off-by: Dmitry Eremin-Solenikov <dbaryshkov@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
13 years agomainstone: fix name of the allocated memory for roms
Dmitry Eremin-Solenikov [Thu, 13 Jan 2011 15:37:10 +0000 (18:37 +0300)]
mainstone: fix name of the allocated memory for roms

Mainstone board has two flash chips (emulated by two ram regions), however
currently code tries to allocate them with the same name, which fails.
Fix that to make mainstone emulation work again.

Signed-off-by: Dmitry Eremin-Solenikov <dbaryshkov@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
13 years agoadd bepo (french dvorak) keyboard layout
Fred Boiteux [Sun, 9 Jan 2011 13:24:59 +0000 (14:24 +0100)]
add bepo (french dvorak) keyboard layout

I'm using the Qemu program with VNC I/O, and I had some problems with
my keyboard layout, so I've prepared a definition to be included in
Qemu, built from Xorg description.

Signed-off-by: Frédéric Boiteux <fboiteux@free.fr>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
13 years agostc91c111: Implement save/restore
Peter Maydell [Thu, 23 Dec 2010 17:19:58 +0000 (17:19 +0000)]
stc91c111: Implement save/restore

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
13 years agopl080: Implement save/restore
Peter Maydell [Thu, 23 Dec 2010 17:19:57 +0000 (17:19 +0000)]
pl080: Implement save/restore

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
13 years agopl110: Implement save/restore
Peter Maydell [Thu, 23 Dec 2010 17:19:56 +0000 (17:19 +0000)]
pl110: Implement save/restore

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
13 years agopl031: Implement save/restore
Peter Maydell [Thu, 23 Dec 2010 17:19:55 +0000 (17:19 +0000)]
pl031: Implement save/restore

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
13 years agopl050: Implement save/restore
Peter Maydell [Thu, 23 Dec 2010 17:19:54 +0000 (17:19 +0000)]
pl050: Implement save/restore

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
13 years agoarm_sysctl: Implement save/restore
Peter Maydell [Thu, 23 Dec 2010 17:19:53 +0000 (17:19 +0000)]
arm_sysctl: Implement save/restore

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
13 years agovpb_sic: Implement save/restore
Peter Maydell [Thu, 23 Dec 2010 17:19:52 +0000 (17:19 +0000)]
vpb_sic: Implement save/restore

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
13 years agopl190: Implement save/restore
Peter Maydell [Thu, 23 Dec 2010 17:19:51 +0000 (17:19 +0000)]
pl190: Implement save/restore

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
13 years agogt64xxx: qdev conversion
Aurelien Jarno [Wed, 19 Jan 2011 22:10:40 +0000 (23:10 +0100)]
gt64xxx: qdev conversion

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
13 years agosh_pci: qdev conversion
Aurelien Jarno [Wed, 19 Jan 2011 17:23:59 +0000 (18:23 +0100)]
sh_pci: qdev conversion

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
13 years agosh_serial: process all received characters
Aurelien Jarno [Wed, 19 Jan 2011 10:38:36 +0000 (11:38 +0100)]
sh_serial: process all received characters

When operating on the SCIF, process all the received characters, as long
as the FIFO can handle them.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
13 years agosh_serial: remove one level of indirection
Aurelien Jarno [Wed, 19 Jan 2011 10:35:02 +0000 (11:35 +0100)]
sh_serial: remove one level of indirection

The indirection functions are empty since commit
8da3ff180974732fc4272cb4433fef85c1822961.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
13 years agousb-hid: modifiers should generate an event
Aurelien Jarno [Mon, 17 Jan 2011 18:29:34 +0000 (19:29 +0100)]
usb-hid: modifiers should generate an event

When a modifier key is pressed or released, the USB HID keyboard still
answers NAK, unless another key is also pressed or released.

The patch fixes that by calling usb_hid_changed() when a modifier key
is pressed or released.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
13 years agosoftfloat: fix floatx80_is_{quiet,signaling}_nan()
Aurelien Jarno [Mon, 17 Jan 2011 18:29:33 +0000 (19:29 +0100)]
softfloat: fix floatx80_is_{quiet,signaling}_nan()

floatx80_is_{quiet,signaling}_nan() functions are incorrectly detecting
the type of NaN, depending on SNAN_BIT_IS_ONE, one of the two is
returning the correct value, and the other true for any kind of NaN.

This patch fixes that by applying the same kind of comparison as for
other float formats, but taking into account the explicit bit.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
13 years agotcg: README, name deposit second argument len/LEN
Edgar E. Iglesias [Thu, 20 Jan 2011 11:16:57 +0000 (12:16 +0100)]
tcg: README, name deposit second argument len/LEN

Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
13 years agotarget-i386: Use deposit operation.
Richard Henderson [Tue, 11 Jan 2011 03:23:47 +0000 (19:23 -0800)]
target-i386: Use deposit operation.

Use this for assignment to the low byte or low word of a register.

Acked-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
13 years agotcg: Define "deposit" as an optional operation.
Richard Henderson [Tue, 11 Jan 2011 03:23:42 +0000 (19:23 -0800)]
tcg: Define "deposit" as an optional operation.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
13 years agomicroblaze: Add support for load/store reversed
Edgar E. Iglesias [Wed, 19 Jan 2011 22:18:00 +0000 (23:18 +0100)]
microblaze: Add support for load/store reversed

Load/store reversed (lwr/swr) are insns that endian translate
the sub-word part of the address and byteswap the data lanes.

Signed-off-by: Edgar E. Iglesias <edgar.iglesias@petalogix.com>
13 years agomicroblaze: Tweak comment, fast cases -> common cases
Edgar E. Iglesias [Wed, 19 Jan 2011 21:48:07 +0000 (22:48 +0100)]
microblaze: Tweak comment, fast cases -> common cases

Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
13 years agosparc: fix NaN handling
Blue Swirl [Tue, 18 Jan 2011 21:34:51 +0000 (21:34 +0000)]
sparc: fix NaN handling

Fix several bugs in NaN handling:
 * e in fcmpe* only changes qNaN handling
 * FCC is unchanged if an exception is raised
 * clear previous FTT before setting it

Reported-by: Mateusz Loskot <mateusz@loskot.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
13 years agotarget-arm: Log instruction start in TCG code
Peter Maydell [Tue, 18 Jan 2011 13:08:40 +0000 (13:08 +0000)]
target-arm: Log instruction start in TCG code

Add support for logging the start of instructions in TCG
code debug dumps for ARM targets.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
13 years agomips: Break TBs after mfc0_count
Edgar E. Iglesias [Mon, 17 Jan 2011 22:00:08 +0000 (23:00 +0100)]
mips: Break TBs after mfc0_count

Break the TB after reading the count register. This makes it
possible to take timer interrupts immediately after a read of
a possibly expired timer.

Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
13 years agomips: Expire late timers when reading cp0_count
Edgar E. Iglesias [Mon, 17 Jan 2011 23:12:22 +0000 (00:12 +0100)]
mips: Expire late timers when reading cp0_count

When reading cp0_count from a timer with a late trigger that should
already have expired, expire it and raise the timer irq.

This makes it possible for guest code (e.g, Linux) that first read
cp0_count, then compare it with cp0_compare and check for raised
timer interrupt lines to run reliably.

Acked-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
13 years agomips: Break out cpu_mips_timer_expire
Edgar E. Iglesias [Mon, 17 Jan 2011 23:07:49 +0000 (00:07 +0100)]
mips: Break out cpu_mips_timer_expire

Reorganize for future patches, no functional change.

Acked-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
13 years agoReplace 'extern inline' with 'static inline'
Blue Swirl [Mon, 17 Jan 2011 20:26:30 +0000 (20:26 +0000)]
Replace 'extern inline' with 'static inline'

Acked-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
13 years agobsd-user: Fix possible memory leaks and wrong realloc call
Stefan Weil [Sun, 16 Jan 2011 15:28:20 +0000 (16:28 +0100)]
bsd-user: Fix possible memory leaks and wrong realloc call

These errors were reported by cppcheck:

[bsd-user/elfload.c:1108]: (error) Common realloc mistake: "syms" nulled but not freed upon failure
[bsd-user/elfload.c:1076]: (error) Memory leak: s
[bsd-user/elfload.c:1079]: (error) Memory leak: syms

v2:
* The previous fix for memory leaks was incomplete (thanks to Peter Maydell for te hint).
* Fix wrong realloc usage, too.

Cc: Blue Swirl <blauwirbel@gmail.com>
Signed-off-by: Stefan Weil <weil@mail.berlios.de>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
13 years agosm501: add 2D engine copyrect support
Aurelien Jarno [Mon, 17 Jan 2011 18:29:33 +0000 (19:29 +0100)]
sm501: add 2D engine copyrect support

Linux kernel started to use the SM501 2D engine for the console, and
especially the copyrect operation.

Implement this operation so that recent kernels can be used with QEMU.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
13 years agoMerge remote branch 'mst/for_anthony' into staging
Anthony Liguori [Mon, 17 Jan 2011 15:49:38 +0000 (09:49 -0600)]
Merge remote branch 'mst/for_anthony' into staging

13 years agom48t59: Fix a wrong opaque passed to nvram read and write routines
Hervé Poussineau [Sun, 2 Jan 2011 18:44:49 +0000 (19:44 +0100)]
m48t59: Fix a wrong opaque passed to nvram read and write routines

This fixes boot on PPC prep.

Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
13 years agogdbstub: Close connection in gdb_exit
Fabien Chouteau [Thu, 13 Jan 2011 11:46:57 +0000 (12:46 +0100)]
gdbstub: Close connection in gdb_exit

On Windows, this is required to flush the remaining data in the IO stream,
otherwise Gdb do not receive the last packet.

Version 2:
   Fix linux-user build error.

Signed-off-by: Fabien Chouteau <chouteau@adacore.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@petalogix.com>
13 years agoUSB keyboard emulation key mapping error
Michael Tokarev [Mon, 18 Oct 2010 12:55:25 +0000 (16:55 +0400)]
USB keyboard emulation key mapping error

The USB keyboard emulation's translation table in hw/usb-hid.c doesn't
match the codes actually sent for the Logo (a.k.a. "Windows") or Menu
keys. This results in the guest OS not being able to receive these keys
at all when the USB keyboard emulation is being used.

In particular, both the keymap in /usr/share/kvm/keymaps/modifiers and
the evdev table in x_keymap.c map these keys to 0xdb, 0xdc, and 0xdd,
while usb_hid_usage_keys[] seems to be expecting them to be mapped to
0x7d, 0x7e, and 0x7f.

The attached patch seems to fix the problem, at least in my (limited)
testing.

http://bugs.debian.org/578846
http://bugs.debian.org/600593 (cloned from the above against different pkg)
https://bugs.launchpad.net/qemu/+bug/584139

Signed-Off-By: Brad Jorsch <anomie@users.sourceforge.net>
Signed-Off-By: Michael Tokarev <mjt@tls.msk.ru>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
13 years agotarget-sh4: implement negc using TCG
Aurelien Jarno [Thu, 13 Jan 2011 07:20:39 +0000 (08:20 +0100)]
target-sh4: implement negc using TCG

Using setcond it's now possible to generate a relatively short negc
instruction in TCG.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
13 years agotarget-sh4: use rotl/rotr when possible
Aurelien Jarno [Thu, 13 Jan 2011 07:20:39 +0000 (08:20 +0100)]
target-sh4: use rotl/rotr when possible

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
13 years agotcg/sparc64: fix segfault
Blue Swirl [Sun, 16 Jan 2011 08:32:27 +0000 (08:32 +0000)]
tcg/sparc64: fix segfault

With current OpenBSD, code_gen_buffer was mapped 8GB away from
text segment. Then any helpers were beyond the 2GB range of call
instruction genereated by TCG and so the calls would go nowhere,
leading to a segfault.

Fix by specifying an address for the code_gen_buffer,
hopefully free and nearby the helpers.

Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
13 years agotarget-sh4: correct use of ! and &
Aurelien Jarno [Sat, 15 Jan 2011 12:50:38 +0000 (13:50 +0100)]
target-sh4: correct use of ! and &

Fix wrong usage of ! and & in MMU related functions. Thanks to Blue
Swirl for reporting the issue.

Reported-by: Blue Swirl <blauwirbel@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
13 years agomonitor: fix a typo
Blue Swirl [Sat, 15 Jan 2011 08:31:00 +0000 (08:31 +0000)]
monitor: fix a typo

Fix usage of wrong variable, spotted by clang:
/src/qemu/monitor.c:2278:36: warning: The left operand of '&' is a garbage value
                        prot = pde & (PG_USER_MASK | PG_RW_MASK |

Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
13 years agomake_device_config: Fix non-fatal error message with dash and other shells
Stefan Weil [Thu, 30 Dec 2010 12:04:57 +0000 (12:04 +0000)]
make_device_config: Fix non-fatal error message with dash and other shells

ORS=" " adds a blank to the name of the include file.
Some shells (e.g. dash) don't accept input redirection
(tr -d '\r' < $f) when $f ends with a blank, so they
print an error message instead of reading pci.mak.
This is a non-fatal error because pci.mak does not
contain an include line. It was introduced by commit
5d6b423c5cd6f9dfac30959ff1d5c088996719c3.

Using printf avoids adding a blank and is also supported
by older awk versions (this solution was suggested by
Paolo Bonzini, thank you).

Cc: Blue Swirl <blauwirbel@gmail.com>
Signed-off-by: Stefan Weil <weil@mail.berlios.de>
Tested-by: Andreas Färber <andreas.faerber@web.de>
13 years agoMAINTAINERS: add entries for TCG
Aurelien Jarno [Fri, 14 Jan 2011 19:39:19 +0000 (20:39 +0100)]
MAINTAINERS: add entries for TCG

The MAINTAINERS file was lacking entries concerning the TCG code, add
them based on the git history.

For the common TCG code, is probably better to keep qemu-devel@non-gnu.org
as this code can break easily, so it's better to get it reviewed by a few
persons.

Acked-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
13 years agoMAINTAINERS: Change MIPS and SH4 maintainers
Aurelien Jarno [Fri, 14 Jan 2011 19:39:19 +0000 (20:39 +0100)]
MAINTAINERS: Change MIPS and SH4 maintainers

Since nobody else seems interested in maintaining MIPS and SH4 targets,
and as I have done most of the recent code changes, let officialize
that.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
13 years agoMAINTAINERS: fix typos
Aurelien Jarno [Fri, 14 Jan 2011 19:39:19 +0000 (20:39 +0100)]
MAINTAINERS: fix typos

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
13 years agotarget-arm: Restore IT bits when resuming after an exception
Peter Maydell [Fri, 14 Jan 2011 19:39:19 +0000 (20:39 +0100)]
target-arm: Restore IT bits when resuming after an exception

We were not correctly restoring the IT bits when resuming execution
after taking an unexpected exception in the middle of an IT block.
Fix this by tracking them along with PC changes and restoring in
gen_pc_load().

This fixes bug https://bugs.launchpad.net/qemu/+bug/581335

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
13 years agolinux-user: ARM: clear the IT bits when invoking a signal handler
Peter Maydell [Fri, 14 Jan 2011 19:39:19 +0000 (20:39 +0100)]
linux-user: ARM: clear the IT bits when invoking a signal handler

When invoking a signal handler for an ARM target, make sure the IT
bits in the CPSR are cleared. (This would otherwise cause incorrect
execution if the IT state was non-zero when an exception occured.
This bug has been masked previously because we weren't getting the
IT state bits at exception entry right anyway.)

Also use the proper cpsr_read()/cpsr_write() interface to update
the CPSR rather than manipulating CPUState fields directly.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
13 years agotarget-arm: Refactor translation of exception generating instructions
Peter Maydell [Fri, 14 Jan 2011 19:39:19 +0000 (20:39 +0100)]
target-arm: Refactor translation of exception generating instructions

Create a new function which does the common sequence of gen_set_condexec,
gen_set_pc_im, gen_exception, set is_jmp to DISAS_JUMP.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
13 years agotarget-arm: Remove redundant setting of IT bits before Thumb SWI
Peter Maydell [Fri, 14 Jan 2011 19:39:19 +0000 (20:39 +0100)]
target-arm: Remove redundant setting of IT bits before Thumb SWI

Remove a redundant call to gen_set_condexec() in the translation of Thumb
mode SWI. (SWI and WFI generate "exceptions" which happen after the
execution of the instruction, ie when PC and IT bits have updated.
So the condexec bits at this point are not correct. However, the code
that handles finishing the translation of the TB will write the correct
value of the condexec bits later, so the only effect was that a conditional
Thumb SWI would generate slightly worse code than necessary.)

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
13 years agotarget-arm: Translate with user-state from TB flags, not CPUState
Peter Maydell [Fri, 14 Jan 2011 19:39:19 +0000 (20:39 +0100)]
target-arm: Translate with user-state from TB flags, not CPUState

When translating, get the user/priv state from the TB flags, not
the CPUState.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
13 years agotarget-arm: Set privileged bit in TB flags correctly for M profile
Peter Maydell [Fri, 14 Jan 2011 19:39:19 +0000 (20:39 +0100)]
target-arm: Set privileged bit in TB flags correctly for M profile

M profile ARM cores don't have a CPSR mode field. Set the bit in the
TB flags that indicates non-user mode correctly for these cores.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
13 years agotarget-arm: Translate with condexec bits from TB flags, not CPUState
Peter Maydell [Fri, 14 Jan 2011 19:39:19 +0000 (20:39 +0100)]
target-arm: Translate with condexec bits from TB flags, not CPUState

When translating, the condexec bits for the TB are in the TB flags;
the CPUState condexec bits may be different.

This patch fixes https://bugs.launchpad.net/bugs/604872 where we might
segfault if we took an exception in the middle of a TB with an IT
block, because when we came to retranslate in cpu_restore_state()
the CPUState condexec bits would have advanced compared to the start
of the TB and we would generate different (wrong) code.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
13 years agotarget-arm: Translate with Thumb state from TB flags, not CPUState
Peter Maydell [Fri, 14 Jan 2011 19:39:19 +0000 (20:39 +0100)]
target-arm: Translate with Thumb state from TB flags, not CPUState

The Thumb/ARM state for the TB being translated should come from
the TB flags, not the CPUState.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
13 years agotarget-arm: Translate with VFP len/stride from TB flags, not CPUState
Peter Maydell [Fri, 14 Jan 2011 19:39:19 +0000 (20:39 +0100)]
target-arm: Translate with VFP len/stride from TB flags, not CPUState

When translating, the VFP vector length and stride for this TB are encoded
in the TB flags; the CPUState copies may be different and must not be used.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
13 years agotarget-arm: Translate with VFP-enabled from TB flags, not CPUState
Peter Maydell [Fri, 14 Jan 2011 19:39:19 +0000 (20:39 +0100)]
target-arm: Translate with VFP-enabled from TB flags, not CPUState

When translating code, whether the VFP unit is enabled for this TB
is stored in a bit in the TB flags. Use this rather than incorrectly
reading the FPEXC from the CPUState passed to translation.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
13 years agotarget-arm: Add symbolic constants for bitfields in TB flags
Peter Maydell [Fri, 14 Jan 2011 19:39:18 +0000 (20:39 +0100)]
target-arm: Add symbolic constants for bitfields in TB flags

Add symbolic constants for the bitfields we use in the TB flags.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
13 years agotarget-arm: Don't generate code specific to current CPU mode for SRS
Peter Maydell [Fri, 14 Jan 2011 19:39:18 +0000 (20:39 +0100)]
target-arm: Don't generate code specific to current CPU mode for SRS

When translating the SRS instruction, handle the "store registers
to stack of current mode" case in the helper function rather than
inline. This means the generated code does not make assumptions
about the current CPU mode which might not be valid when the TB
is executed later.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
13 years agotarget-arm: Use the standard FPSCR value for VRSQRTS
Peter Maydell [Fri, 14 Jan 2011 19:39:18 +0000 (20:39 +0100)]
target-arm: Use the standard FPSCR value for VRSQRTS

VSQRTS always uses the standard FPSCR value as it is a Neon instruction.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
13 years agotarget-arm: Add support for 'Standard FPSCR Value' as used by Neon
Peter Maydell [Fri, 14 Jan 2011 19:39:18 +0000 (20:39 +0100)]
target-arm: Add support for 'Standard FPSCR Value' as used by Neon

Add support to the ARM helper routines for a second fp_status value
which should be used for operations which the ARM ARM indicates use
"ARM standard floating-point arithmetic" rather than being controlled
by the rounding/flush/NaN settings in the FPSCR.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
13 years agotarget-arm: Fix implementation of VRSQRTS
Peter Maydell [Fri, 14 Jan 2011 19:39:18 +0000 (20:39 +0100)]
target-arm: Fix implementation of VRSQRTS

The implementation of the ARM VRSQRTS instruction (which calculates
(3 - op1 * op2) / 2) was missing the division operation. It also
did not handle the special cases of (0,inf) and (inf,0).

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
13 years agosoftfloat: Add float32_is_zero_or_denormal() function
Peter Maydell [Fri, 14 Jan 2011 19:39:18 +0000 (20:39 +0100)]
softfloat: Add float32_is_zero_or_denormal() function

Add a utility function to softfloat to test whether a float32
is zero or denormal.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
13 years agolsi53c895a: fix endianness issues
Aurelien Jarno [Fri, 14 Jan 2011 19:39:18 +0000 (20:39 +0100)]
lsi53c895a: fix endianness issues

lsi_ram_read*() and lsi_ram_write*() are not consistent, one uses
leXX_to_cpu() the other uses nothing. As the comment above the RAM
declaration says: "Script ram is stored as 32-bit words in host
byteorder.", remove the leXX_to_cpu() calls.

This fixes the boot of an ARM versatile machine on MIPS and PowerPC
hosts.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
13 years agomips/malta: fix board id
Aurelien Jarno [Fri, 14 Jan 2011 19:39:18 +0000 (20:39 +0100)]
mips/malta: fix board id

Board id can't be written with stl_phys() as it's read-only part of
memory. Use stl_p() on the memory buffer instead.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
13 years agotarget-sh4: use setcond when possible
Aurelien Jarno [Fri, 14 Jan 2011 19:39:18 +0000 (20:39 +0100)]
target-sh4: use setcond when possible

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
13 years agotarget-sh4: log instructions start in TCG code
Aurelien Jarno [Fri, 14 Jan 2011 19:39:18 +0000 (20:39 +0100)]
target-sh4: log instructions start in TCG code

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
13 years agotarget-sh4: simplify comparisons after a 'and' op
Aurelien Jarno [Fri, 14 Jan 2011 19:39:18 +0000 (20:39 +0100)]
target-sh4: simplify comparisons after a 'and' op

When a TCG variable is anded with a value and the compared with the same
value, we can simply invert the comparison and compare it with 0. The
generated code is smaller.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
13 years agotarget-sh4: fix reset on r2d
Aurelien Jarno [Fri, 14 Jan 2011 19:39:18 +0000 (20:39 +0100)]
target-sh4: fix reset on r2d

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
13 years agotarget-sh4: optimize exceptions
Aurelien Jarno [Fri, 14 Jan 2011 19:39:18 +0000 (20:39 +0100)]
target-sh4: optimize exceptions

As exception is not the normal path, don't bother saving PC, before
raising one, instead rely on code retranslation to get the CPU state.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
13 years agotarget-sh4: add ftrv instruction
Aurelien Jarno [Fri, 14 Jan 2011 19:39:18 +0000 (20:39 +0100)]
target-sh4: add ftrv instruction

Add the ftrv XMTRX,FVn instruction, which computes the 4-row x 4-column
matrix XMTRX by the 4-dimensional vector FVn.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
13 years agotarget-sh4: add fipr instruction
Aurelien Jarno [Fri, 14 Jan 2011 19:39:18 +0000 (20:39 +0100)]
target-sh4: add fipr instruction

Add the fipr FVm,FVn instruction, which computes the inner products of
a 4-dimensional single precision floating-point vector.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
13 years agotarget-sh4: implement FPU exceptions
Aurelien Jarno [Fri, 14 Jan 2011 19:39:18 +0000 (20:39 +0100)]
target-sh4: implement FPU exceptions

FPU exception support where not implemented on SH4. Implement them by
clearing the softfloat exceptions flags before an FP instruction (the
SH4 FPU also clear them before an instruction), and calling a function
to update the FPSCR register after an FP instruction. This function
update the corresponding FPSCR bits (both flags and cumulative flags)
and trigger exception if enabled.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
13 years agotarget-sh4: implement flush-to-zero
Aurelien Jarno [Fri, 14 Jan 2011 19:39:18 +0000 (20:39 +0100)]
target-sh4: implement flush-to-zero

When the FPSCR.DN bit is set, the SH4 FPU treat denormalized numbers as
zero. Enable the corresponding softfloat option when this bit is set.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
13 years agotarget-sh4: define FPSCR constants
Aurelien Jarno [Fri, 14 Jan 2011 19:39:18 +0000 (20:39 +0100)]
target-sh4: define FPSCR constants

Define FPSCR constants for all field and use them instead of hardcoded
values.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
13 years agotarget-sh4: use default-NaN mode
Aurelien Jarno [Fri, 14 Jan 2011 19:39:17 +0000 (20:39 +0100)]
target-sh4: use default-NaN mode

SH4 FPU doesn't propagate NaN, and instead always regenerate new ones.
Enable the default-NaN mode by default.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
13 years agosoftfloat: fix default-NaN mode
Aurelien Jarno [Fri, 14 Jan 2011 19:39:17 +0000 (20:39 +0100)]
softfloat: fix default-NaN mode

When the default-NaN mode is enabled, it should return the default NaN
value, but it should anyway raise the invalid operation flag if one of
the operand is an sNaN.

I have checked that this behavior matches the ARM and SH4 manuals, as
well as real SH4 hardware.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
13 years agosoftfloat: SH4 has the sNaN bit set
Aurelien Jarno [Fri, 14 Jan 2011 19:39:17 +0000 (20:39 +0100)]
softfloat: SH4 has the sNaN bit set

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
13 years agotarget-sh4: switch sh4 to softfloat
Aurelien Jarno [Fri, 14 Jan 2011 19:39:17 +0000 (20:39 +0100)]
target-sh4: switch sh4 to softfloat

We need to be able to catch exceptions correctly and thus enable softfloat
on SH4.

As all machines except i386 and x86_64 are using softfloat, make it the
default and change the case to detect i386 and x86_64. Note that CRIS
doesn't have an FPU, so it can be configured with both softfloat-native
and softfloat.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
13 years agoconfigure: fix broken test
Aurelien Jarno [Fri, 14 Jan 2011 19:21:22 +0000 (20:21 +0100)]
configure: fix broken test

Since commit d1807a4f836c27f6dc7061e53a834dd27f78e46a ./configure tries
to test files and directories with "test -f", which only test for regular
files. Test with "test -e", which looks for any kind of files.

This unbreak the configure script when not using a separate object
directory.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
13 years agomake trace options use autoconfy names
Paolo Bonzini [Thu, 23 Dec 2010 10:44:02 +0000 (11:44 +0100)]
make trace options use autoconfy names

These are not in any release, so I am just renaming them.

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
13 years agomove --srcdir detection earlier
Paolo Bonzini [Thu, 23 Dec 2010 10:44:00 +0000 (11:44 +0100)]
move --srcdir detection earlier

This will help getting config.guess and config.sub from the srcdir.

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
13 years ago [PATCH v3 14/15] remove HOST_CC mention from roms/{sea, vga}bios/config.mak
Paolo Bonzini [Thu, 23 Dec 2010 10:44:01 +0000 (11:44 +0100)]
 [PATCH v3 14/15] remove HOST_CC mention from roms/{sea, vga}bios/config.mak

Not used in the submodules.

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
13 years agoremove source_path_used
Paolo Bonzini [Thu, 23 Dec 2010 10:43:59 +0000 (11:43 +0100)]
remove source_path_used

Not necessary since we use mkdir -p and from this patch test -f.

Also, dirname returns "." if a path has no directory component,
as is the case for "sh configure".

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
13 years agomove "ln -sf" emulation to a function
Paolo Bonzini [Thu, 23 Dec 2010 10:43:58 +0000 (11:43 +0100)]
move "ln -sf" emulation to a function

"ln -sf" does not really do anything more than "ln -s" on Solaris.

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
13 years agoreorganize sdl-config tests
Paolo Bonzini [Thu, 23 Dec 2010 10:43:57 +0000 (11:43 +0100)]
reorganize sdl-config tests

This also allows overriding it with SDL_CONFIG, and warning in suspicious
cross-compilation scenarios.

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
13 years agodo not default to non-prefixed pkg-config when cross compiling
Paolo Bonzini [Thu, 23 Dec 2010 10:43:56 +0000 (11:43 +0100)]
do not default to non-prefixed pkg-config when cross compiling

This can still be requested with PKG_CONFIG=/path/to/pkg-config.
Just do not use it as a default, and print a warning.

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
13 years agofix spelling of $pkg_config, move default together with other cross tools
Paolo Bonzini [Thu, 23 Dec 2010 10:43:55 +0000 (11:43 +0100)]
fix spelling of $pkg_config, move default together with other cross tools

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
13 years agoprovide portable HOST_LONG_BITS test
Paolo Bonzini [Thu, 23 Dec 2010 10:43:54 +0000 (11:43 +0100)]
provide portable HOST_LONG_BITS test

Do not hardcode the list of 64-bit CPUs.  Use sizeof(void *) to
compute it.  Renaming it to HOST_LONG_BITS to HOST_POINTER_BITS
is left for later.

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
13 years agodo not pass bogus $(SRC_PATH) include paths to cc during configure
Paolo Bonzini [Thu, 23 Dec 2010 10:43:53 +0000 (11:43 +0100)]
do not pass bogus $(SRC_PATH) include paths to cc during configure

Non-existent -I paths are dropped silently by the compiler, but still
it is not polite to pass bogus options.  Configure-time tests do not
need any include files from the source path, so only include -I flags
at make time (when they're properly expanded).

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
13 years agotest cc with the complete set of chosen flags
Paolo Bonzini [Thu, 23 Dec 2010 10:43:52 +0000 (11:43 +0100)]
test cc with the complete set of chosen flags

The "test the C compiler works ok" comes before a bunch of flags
are added for --cpu or just depending on the host.  It helps
debugging if the test is done after these flags are (unconditionally)
added.

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
13 years agofix sparse support (?)
Paolo Bonzini [Thu, 23 Dec 2010 10:43:51 +0000 (11:43 +0100)]
fix sparse support (?)

I didn't test with sparse, but the old code using += before a variable
was set was wrong.  Sparse support should probably be ripped out or
redone, but this at least keeps some sanity.

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
13 years agomove feature variables to the top
Paolo Bonzini [Thu, 23 Dec 2010 10:43:50 +0000 (11:43 +0100)]
move feature variables to the top

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
13 years agodefault make and install to environment variables
Paolo Bonzini [Thu, 23 Dec 2010 10:43:49 +0000 (11:43 +0100)]
default make and install to environment variables

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
13 years agodefault compilation tools to environment variables
Paolo Bonzini [Thu, 23 Dec 2010 10:43:48 +0000 (11:43 +0100)]
default compilation tools to environment variables

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
13 years agomicroblaze: Improve unconditional direct branching
Edgar E. Iglesias [Fri, 14 Jan 2011 11:30:26 +0000 (12:30 +0100)]
microblaze: Improve unconditional direct branching

Avoid emitting conditional tcg operations for uncoditional
direct branches.

Signed-off-by: Edgar E. Iglesias <edgar.iglesias@petalogix.com>
13 years agocris: Set btaken when storing direct jumps
Edgar E. Iglesias [Thu, 13 Jan 2011 14:14:04 +0000 (15:14 +0100)]
cris: Set btaken when storing direct jumps

When storing a direct jmp from translation state into
runtime state we should set the btaken flag.

Signed-off-by: Edgar E. Iglesias <edgar@axis.com>
13 years agoslirp: Use strcasecmp() to check tftp mode, tsize
Sergei Gavrikov [Wed, 12 Jan 2011 13:57:18 +0000 (15:57 +0200)]
slirp: Use strcasecmp() to check tftp mode, tsize

According to RFC 1350 (TFTP Revision 2) the mode field can contain any
combination of upper and lower case; also RFC 2349 propagates that the
transfer size option ("tsize") is case in-sensitive too.

Current implementation of embedded TFTP server missed that what does
mess some TFTP clients. Fixed by using STRCASECMP(3) in the required
places.

Signed-off-by: Sergei Gavrikov <sergei.gavrikov@gmail.com>
Reviewed-by: Stefan Hajnoczi <stefanha@linux.vnet.ibm.com>
Signed-off-by: Edgar E. Iglesias <edgar@axis.com>
13 years agoppc405_uc: fix a buffer overflow
Blue Swirl [Wed, 12 Jan 2011 21:12:31 +0000 (21:12 +0000)]
ppc405_uc: fix a buffer overflow

Fix a buffer overflow, reported by cppcheck:
[/src/qemu/hw/ppc405_uc.c:72]: (error) Buffer access out-of-bounds: bd.bi_s_version

The use of field bi_s_version seems to be a typo, it should be
bi_r_version.

Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
13 years agolan9118: fix a buffer overflow
Blue Swirl [Wed, 12 Jan 2011 21:00:01 +0000 (21:00 +0000)]
lan9118: fix a buffer overflow

Fix a buffer overflow, reported by cppcheck:
[/src/qemu/hw/lan9118.c:849]: (error) Buffer access out-of-bounds: s.eeprom

All eeprom handling code assumes that the size of eeprom is 128,
except lan9118_eeprom_cmd. Fix this by restricting the address passed.

Signed-off-by: Blue Swirl <blauwirbel@gmail.com>