Alyssa Rosenzweig [Fri, 4 Jun 2021 23:18:23 +0000 (19:18 -0400)]
panfrost: Emulate indirect draws on Midgard
I can't really justify spending time on this right now, even to myself.
So take the perf hit and get out checkbox.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Fri, 4 Jun 2021 23:06:36 +0000 (19:06 -0400)]
panfrost: Fix dirty state emission
If we have per-draw state (vertex ID stuff), there's an ordering
mismatch. Fixes
dEQP-GLES31.functional.draw_base_vertex.draw_elements_instanced_base_vertex.builtin_variable.vertex_id
on Midgard, and I'm not sure why it was passing on Bifrost before. Also
should fix (on both architectures) DRAWID issues.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Wed, 9 Jun 2021 17:19:41 +0000 (13:19 -0400)]
pan/mdg: Insert moves to load/store registers
Ensures a valid schedule/regalloc is possible when vectors are used in
funny ways, as occurs in dEQP-GLES31 resulting in a scheduler hang (or
with prior patches, an RA failure).
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Wed, 9 Jun 2021 17:18:13 +0000 (13:18 -0400)]
pan/mdg: Assert scheduled instructions are reasonable
Would've got a scheduler hang.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Wed, 9 Jun 2021 17:17:39 +0000 (13:17 -0400)]
pan/mdg: Don't skip unit-based checks in choose_instruction
If an explicit unit isn't specified, we still should check.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Wed, 9 Jun 2021 17:17:04 +0000 (13:17 -0400)]
pan/mdg: Use more accurate ld/st reg estimates
And assert that we got them right.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Fri, 4 Jun 2021 23:07:41 +0000 (19:07 -0400)]
pan/mdg: Lower away gl_VertexID offset
Technically we can stick the offset in the vertex ID attribute record,
but this is a faster way to get the test passing and Midgard perf?
what's that?
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Fri, 4 Jun 2021 22:57:28 +0000 (18:57 -0400)]
pan/mdg: Wire in PAN_SYSVAL_VERTEX_INSTANCE_OFFSETS
If we're going to advertise the CAP, better not crash..
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Fri, 4 Jun 2021 22:36:43 +0000 (18:36 -0400)]
panfrost: Don't allocate WLS when not needed
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Fri, 4 Jun 2021 21:36:26 +0000 (17:36 -0400)]
panfrost: Mark 16/32_UNORM as non-renderable (v5)
You'd just get a blend shader anyway, and since they're not spec
requirements, let's not worry about backporting the Midgard lowerings.
Takes dEQP-GLES31.functional.fbo.color.tex2d.* on Midgard from crashing
to not supported.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Fri, 4 Jun 2021 21:17:28 +0000 (17:17 -0400)]
pan/mdg: Fix incorrect rewrite in Midgard scheduler
Fixes on Midgard
dEQP-GLES31.functional.shaders.builtin_functions.uniform.findLSBMinusOne.highp_fragment
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Fri, 4 Jun 2021 21:04:43 +0000 (17:04 -0400)]
pan/mdg: Update r1.w comment
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Fri, 4 Jun 2021 19:26:30 +0000 (15:26 -0400)]
pan/mdg: Handle {i,u}{add,sub}_sat
As SATADD with different modifiers.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Fri, 4 Jun 2021 19:24:44 +0000 (15:24 -0400)]
pan/mdg: Fix units for SUBSAT
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Fri, 4 Jun 2021 18:55:14 +0000 (14:55 -0400)]
panfrost: Respect early-Z force on Midgard
Fixes dEQP-GLES31.functional.image_load_store.early_fragment_tests.* on
Midgard.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Fri, 4 Jun 2021 18:50:53 +0000 (14:50 -0400)]
panfrost: Don't force early-z with occlusion query
..even if there is no z/s enabled. Fixes
dEQP-GLES31.functional.fbo.no_attachments.* on Midgard.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Fri, 4 Jun 2021 18:43:10 +0000 (14:43 -0400)]
panfrost: Simplify Midgard blend disable
Probably a bit faster too.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Fri, 4 Jun 2021 18:42:56 +0000 (14:42 -0400)]
panfrost: Clarify how fs_sidefx works with oq
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Fri, 4 Jun 2021 17:38:02 +0000 (13:38 -0400)]
pan/mdg: Stub memory_barrier{_image}
Same as we do for Bifrost.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Fri, 4 Jun 2021 16:50:46 +0000 (12:50 -0400)]
pan/mdg: Make -Wswitch happy
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Fri, 4 Jun 2021 16:04:50 +0000 (12:04 -0400)]
pan/mdg: Use consistent casing in midgard_print
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Thu, 3 Jun 2021 19:15:01 +0000 (15:15 -0400)]
panfrost: Assert alignment of indirect records
Continuation records need alignment, this shows they already have it.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Thu, 3 Jun 2021 19:14:00 +0000 (15:14 -0400)]
panfrost: Make instancing code more obvious
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Thu, 3 Jun 2021 19:09:06 +0000 (15:09 -0400)]
panfrost: Fix src_offset data type
We treat it as signed but had it marked as unsigned. It can be negative
in obscure cases.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Thu, 3 Jun 2021 19:06:05 +0000 (15:06 -0400)]
panfrost: Align NPOT divisor records
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Thu, 3 Jun 2021 18:09:18 +0000 (14:09 -0400)]
panfrost: Add util_draw_indirect() debug path
Useful for finding problems with the GPU indirect path.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Thu, 3 Jun 2021 15:07:45 +0000 (11:07 -0400)]
panfrost: Zero r_dimension for buffer textures
Instead of reading wrong side of the union (undefined behaviour). Fixes
a GenXML assertion failure in
KHR-GLES31.core.texture_buffer.texture_buffer_texture_buffer_range
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Wed, 2 Jun 2021 21:08:53 +0000 (17:08 -0400)]
panfrost: Fix crc_valid condition
Fixes fails in dEQP-GLES31.functional.texture.border_clamp.* when run in
parallel with certain other tests.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Wed, 2 Jun 2021 21:07:10 +0000 (17:07 -0400)]
panfrost: Simplify compute_checksum_size formula
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Wed, 2 Jun 2021 19:45:51 +0000 (15:45 -0400)]
panfrost: Fix vertex image attribute overrun
Images take a continuation record, don't scribble zeroes over.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Fixes:
dc85f65e059 ("panfrost: emit shader image attribute descriptors")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Wed, 2 Jun 2021 18:52:56 +0000 (14:52 -0400)]
pan/bi: Force u32 for flat varyings
Since the GLSL compilers will pack together flat varyings with no regard
to type, under the assumption the backend can deal with it. I guess we
can deal with it then... Fixes fails in
dEQP-GLES31.functional.separate_shader.random.*
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Wed, 2 Jun 2021 20:15:17 +0000 (16:15 -0400)]
panfrost: Use varying format from frag shader
Needed to fix up flat varyings to u32 due to TGSI brokenness. If we wack
TGSI, we can drop this.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Wed, 2 Jun 2021 18:52:36 +0000 (14:52 -0400)]
panfrost: Correctly size varyings
The same slot could be specified multiple times with different
location_frac out of order, so we use two passes.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Tue, 1 Jun 2021 23:47:03 +0000 (19:47 -0400)]
pan/indirect_draw: Fix 1 instance, nonzero divisor
Instead of doing a complicated hack with the POT divisor, just zero the
stride of the linear attribute buffer like we do on the CPU.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Tue, 1 Jun 2021 23:35:46 +0000 (19:35 -0400)]
pan/indirect_draw: Use unsigned comparisons
Instead of signed -- get the types right.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Tue, 1 Jun 2021 23:32:43 +0000 (19:32 -0400)]
pan/indirect: Factor out is_power_of_two_or_zero
The function is complicated enough as it is -- hide the bit twiddling
behind a helper function.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Tue, 1 Jun 2021 23:42:54 +0000 (19:42 -0400)]
panfrost: Default indirect attributes to 1D type
Avoids some complexity in the indirect draw happy path.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Tue, 1 Jun 2021 23:14:06 +0000 (19:14 -0400)]
panfrost: Use util_last_bit for images
Probbaly more correct for hols in image_mask.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Tue, 1 Jun 2021 23:09:00 +0000 (19:09 -0400)]
panfrost: Be explicit in image modifier handling
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Thu, 20 May 2021 13:40:43 +0000 (09:40 -0400)]
panfrost: Separate image attribute and buffer emit
Trying to disentangle attributes and attribute buffers, so here's
a leaf node for that change.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Wed, 19 May 2021 22:34:25 +0000 (18:34 -0400)]
panfrost: Don't duplicate attribute buffers
If the (vbi, divisor) tuple matches, we can save an attribute buffer
descriptor. We do the linking at CSO create time. This should be a bit
more cache friendly.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Thu, 3 Jun 2021 21:38:35 +0000 (17:38 -0400)]
panfrost: Disable AFBC on v7
Broken in several ways. Hide it until we can get this sorted, and have a
test plan to keep it sorted.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Cc: mesa-stable
Acked-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Tue, 1 Jun 2021 21:51:05 +0000 (17:51 -0400)]
panfrost: Add missing 'Reverse issue order flag'
Should fix an issue I'm seeing. Spoiler alert, it does not.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Acked-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Tue, 1 Jun 2021 19:47:20 +0000 (15:47 -0400)]
panfrost: Remove AFBC format fixups
It's too complicated and probably for no actual benefit. The main reason
we have BGR formats is for display, but that's export and doesn't get
hit by this path. Internal BGRA textures are possible with a Mesa
extension but sufficiently rare that I regret suggesting this as a
possible optimization. My apologies, and thanks for the fish.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Acked-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Tue, 8 Jun 2021 20:04:05 +0000 (16:04 -0400)]
pan/bi: Don't allocate past the end of the reg file
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Tue, 8 Jun 2021 18:49:04 +0000 (14:49 -0400)]
pan/bi: Track words instead of bytes in RA
Reduces RA memory footprint by 4x, fixing an OOM in the following dEQP
test that otherwise would allocate 8GB of memory...
dEQP-GLES31.functional.ssbo.layout.random.all_shared_buffer.36
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Tue, 8 Jun 2021 18:35:52 +0000 (14:35 -0400)]
pan/bi: Simplify spill code
Now allow spilling all nodes. Fixes failed spilling in
dEQP-GLES31.functional.ssbo.layout.random.all_shared_buffer.21
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Wed, 2 Jun 2021 22:30:30 +0000 (18:30 -0400)]
pan/bi: Emit a dummy ATEST if needed
Match what the blob does, since Bifrost has so many random errata we'd
be fools not to.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Wed, 2 Jun 2021 22:08:41 +0000 (18:08 -0400)]
pan/bi: Lower 64-bit ints again
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Wed, 2 Jun 2021 14:46:57 +0000 (10:46 -0400)]
pan/bi: Lower stores with component != 0
If the shader packs multiple varyings into the same location with
different location_frac, we'll need to lower to a single varying store
that collects all of the channels together. This is not trivial during
code gen, but it is trivial to do in NIR right before codegen by relying
on nir_lower_io_to_temporaries. Since we're guaranteed all varyings will
be written exactly once, in the exit block, we can scan the shader
linearly and collect stores together in a single pass.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Wed, 2 Jun 2021 00:24:31 +0000 (20:24 -0400)]
pan/bi: Lower loads with component > 0
We have no native way to swizzle out a nonzero component in a load, but
we can simply load extra components and do the swizzle in shader
instructions. This is inefficient, since it loads data to discard
immediately, but it's required for conformance in some edge cases.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Tue, 1 Jun 2021 22:50:30 +0000 (18:50 -0400)]
pan/bi: Handle images in vertex shaders
We need to offset by the number of attributes, since the primary
attribute table is shared for images and vertex attributes.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Tue, 25 May 2021 19:49:27 +0000 (15:49 -0400)]
pan/bi: Model +BLEND clobbering of r48
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Tue, 25 May 2021 17:56:41 +0000 (13:56 -0400)]
pan/bi: Don't restrict the register file in non-blend shaders
Now that preloading is handled correctly, there's nothing 'special'
about R59 and up, so this gets us a few more registers to work with.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Tue, 25 May 2021 17:52:56 +0000 (13:52 -0400)]
pan/bi: Allow move/sink in blend shaders
Now that we handle precolouring we don't need to workaround anything.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Tue, 25 May 2021 17:50:54 +0000 (13:50 -0400)]
pan/bi: Model interference with preloaded regs
Now that we have affinity masks in RA, we can handle this as an easy
case of register liveness analysis, rather than creating pseudo-nodes
and trying hard to coalesce the resulting moves.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Tue, 25 May 2021 17:50:13 +0000 (13:50 -0400)]
pan/bi: Explicit zero reg_live_{in, out} when needed
I want to use these fields for a similar purpose in the register
allocator, so they won't be zero anymore for scheduling.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Tue, 25 May 2021 16:22:55 +0000 (12:22 -0400)]
pan/bi: Inline spilling in RA
Should be faster for both spill and not spill cases.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Tue, 25 May 2021 17:52:48 +0000 (13:52 -0400)]
pan/bi: Use explicit affinities in RA
Inline LCRA to allow us to make the change without disrupting Midgard,
and get some nice cleanup from doing so.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Thu, 6 May 2021 17:10:00 +0000 (13:10 -0400)]
pan/bi: Allow IADD.u32 on FMA as *IADDC
There's a common special case, slight boost in scheduler freedom.
total nops in shared programs: 101130 -> 101048 (-0.08%)
nops in affected programs: 1677 -> 1595 (-4.89%)
helped: 13
HURT: 0
helped stats (abs) min: 6 max: 8 x̄: 6.31 x̃: 6
helped stats (rel) min: 3.24% max: 25.00% x̄: 7.42% x̃: 4.48%
95% mean confidence interval for nops value: -6.76 -5.85
95% mean confidence interval for nops %-change: -12.02% -2.81%
Nops are helped.
total clauses in shared programs: 27076 -> 27075 (<.01%)
clauses in affected programs: 8 -> 7 (-12.50%)
helped: 1
HURT: 0
total quadwords in shared programs: 113142 -> 113113 (-0.03%)
quadwords in affected programs: 1935 -> 1906 (-1.50%)
helped: 13
HURT: 0
helped stats (abs) min: 2 max: 4 x̄: 2.23 x̃: 2
helped stats (rel) min: 0.95% max: 7.50% x̄: 2.16% x̃: 1.26%
95% mean confidence interval for quadwords value: -2.59 -1.87
95% mean confidence interval for quadwords %-change: -3.45% -0.88%
Quadwords are helped.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Thu, 6 May 2021 15:11:09 +0000 (11:11 -0400)]
pan/bi: Track liveness while scheduling
If we know that a value is killed in the next tuple, there is no need to
write it out to the register file. We already handled this as a packing
fixup. However, avoiding this write also frees up an extra slot in the
register block, which offers additional scheduling freedom. To take
advantage of this, we extend liveness analysis to work while scheduling,
and modify the schedulable predicate accordingly.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Tue, 4 May 2021 21:49:24 +0000 (17:49 -0400)]
pan/bi: Add post-RA optimizer
Delete coalesced moves. Now this is trivial! See e.g shaders/tesseract/118.shader_test
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Tue, 4 May 2021 21:27:07 +0000 (17:27 -0400)]
pan/bi: Bundle after RA
Flag day change to swap the order of the "scheduler" with the register
allocator. This gives RA much more freedom without significantly
hndering bundling.
It also opens up the door to Adult-level Scheduling which would occur
prior to bundling.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Wed, 5 May 2021 18:06:26 +0000 (14:06 -0400)]
pan/bi: Fix bi_rewrite_passthrough ordering
The ordering is irrelevant for SSA form input, but is very relevant for
register input.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Wed, 5 May 2021 19:48:35 +0000 (15:48 -0400)]
pan/bi: Simplify TEXC codegen for sr_count=0
Obscure case.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Tue, 4 May 2021 21:42:13 +0000 (17:42 -0400)]
pan/bi: Use TEXS_2D for rect textures
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Tue, 4 May 2021 21:20:45 +0000 (17:20 -0400)]
pan/bi: Pull out bi_count_write_registers
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Yiwei Zhang [Thu, 10 Jun 2021 16:26:01 +0000 (16:26 +0000)]
vulkan: fix back compat with Android Oreo and below
buffer_handle_t definition was previously inside the deprecated
system/core/include/system/window.h.
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Acked-by: Chia-I Wu <olvaffe@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11301>
Neha Bhende [Wed, 9 Jun 2021 18:08:28 +0000 (11:08 -0700)]
svga: Initialize pipe_shader_state for transform shaders
This fixes crashes for opengl apps. Issue is found in vmware
internal testing
Fixes:
f01c0565bb9 ("draw: free the NIR IR.")
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11274>
Mike Blumenkrantz [Thu, 10 Jun 2021 09:49:05 +0000 (05:49 -0400)]
util/blitter: remove duplicated set_sample_mask calls
it doesn't make sense to have both, so just keep the simpler one
no functional changes because this was redundant
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11294>
Adam Jackson [Fri, 4 Jun 2021 17:40:52 +0000 (13:40 -0400)]
swrast: Fix a warning from gcc 11
gcc 11 dixit:
In function ‘sample_2d_ewa’,
inlined from ‘sample_lambda_2d_aniso’ at ../src/mesa/swrast/s_texfilter.c:1995:10:
../src/mesa/swrast/s_texfilter.c:1729:13: warning: ‘sample_2d_nearest’ reading 16 bytes from a region of size 8 [-Wstringop-overread]
1729 | sample_2d_nearest(ctx, samp, img, newCoord, rgba);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../src/mesa/swrast/s_texfilter.c: In function ‘sample_lambda_2d_aniso’:
../src/mesa/swrast/s_texfilter.c:1729:13: note: referencing argument 4 of type ‘const GLfloat *’ {aka ‘const float *’}
Indeed, newCoord is GLfloat[2] but the argument is typed GLfloat[4],
even though only the first two (s and t) are ever read. Fix the array
size in the function signature to reflect the maximum element actually
addressed.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11273>
Roman Stratiienko [Fri, 28 May 2021 16:00:50 +0000 (19:00 +0300)]
nouveau: Don't require RTTI and use it only when enabled
The only case RTTI is used in nouveau is type assertion at:
File src/gallium/drivers/nouveau/codegen/nv50_ir.cpp:
assert(typeid(*i) == typeid(*this));
This assertion is used 'to be on the safe side' only and not mandatory.
In Android we do not have rtti for libLLVM therefore this assertion
has to be skipped.
Signed-off-by: Roman Stratiienko <r.stratiienko@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11069>
Charlie [Wed, 9 Jun 2021 19:20:34 +0000 (20:20 +0100)]
v3dv: enable KHR_uniform_buffer_standard_layout
We already support this memory layout. All relevant CTS tests seem to
pass
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11276>
Charlie [Wed, 9 Jun 2021 19:16:30 +0000 (20:16 +0100)]
v3dv: enable KHR_incremental_present
All bits should already be provided by wsi/common.
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11276>
Charlie [Wed, 9 Jun 2021 19:08:40 +0000 (20:08 +0100)]
v3dv: enable KHR_sampler_mirror_clamp_to_edge
This is already implemented
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11276>
Charlie [Wed, 9 Jun 2021 19:04:40 +0000 (20:04 +0100)]
v3dv: enable KHR_image_format_list
There's nothing checking for mutable formats, so this needs no changes
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11276>
Rhys Perry [Fri, 15 Jan 2021 12:54:45 +0000 (12:54 +0000)]
nir: document that ACCESS_RESTRICT is not set at intrinsics
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7295>
Rhys Perry [Fri, 15 Jan 2021 13:01:14 +0000 (13:01 +0000)]
nir/opt_load_store_vectorize: only require one variable to be restrict
No fossil-db changes.
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7295>
Rhys Perry [Fri, 23 Oct 2020 14:31:28 +0000 (15:31 +0100)]
nir/opt_load_store_vectorize: check for restrict at the variable
SPIR-V -> NIR doesn't set ACCESS_RESTRICT at the intrinsic.
fossil-db (GFX10.3):
Totals from 3 (0.00% of 139391) affected shaders:
CodeSize: 12364 -> 12356 (-0.06%)
Instrs: 2493 -> 2494 (+0.04%); split: -0.04%, +0.08%
Cycles:
15279372 ->
15295756 (+0.11%); split: -0.11%, +0.21%
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7295>
Rhys Perry [Fri, 6 Nov 2020 19:27:09 +0000 (19:27 +0000)]
nir/load_store_vectorizer: fix check_for_robustness() with indirect loads
fossil-db (GFX10.3, robustness2 enabled):
Totals from 13958 (9.54% of 146267) affected shaders:
VGPRs: 609168 -> 624304 (+2.48%); split: -0.05%, +2.53%
CodeSize:
48229504 ->
48488392 (+0.54%); split: -0.02%, +0.56%
MaxWaves: 354426 -> 349448 (-1.40%); split: +0.00%, -1.41%
Instrs: 9332093 -> 9375053 (+0.46%); split: -0.03%, +0.49%
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7295>
Charlie Birks [Wed, 9 Jun 2021 14:57:51 +0000 (14:57 +0000)]
v3dv: document two supported extensions
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11268>
Rhys Perry [Wed, 9 Jun 2021 11:47:39 +0000 (12:47 +0100)]
radv: increase maxComputeSharedMemorySize
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11262>
Rhys Perry [Thu, 10 Jun 2021 10:07:31 +0000 (11:07 +0100)]
aco: fix emit_mbcnt() with a VGPR mask
Found by inspection. Should be possible with nir_intrinsic_mbcnt_amd.
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11295>
Iago Toral Quiroga [Wed, 9 Jun 2021 10:00:18 +0000 (12:00 +0200)]
v3dv: implement VK_KHR_get_display_properties2
This is entirely implemented in the common WSI code, we just need to
implement the API entry points.
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11287>
Michel Zou [Sat, 5 Jun 2021 07:27:02 +0000 (09:27 +0200)]
glapi: fix Warray-parameter
Fixes these new gcc11 warnings:
In file included from ../src/mapi/glapi/glapi_dispatch.c:174:
src/mapi/glapi/gen/glapitemp.h:3191:68: warning: argument 1 of type 'const GLdouble *' {aka 'const double *'} declared as a pointer [-Warray-parameter=]
3191 | KEYWORD1 void KEYWORD2 NAME(LoadTransposeMatrixd)(const GLdouble * m)
| ~~~~~~~~~~~~~~~~~^
In file included from ../src/mapi/glapi/glapi_priv.h:31,
from ../src/mapi/glapi/glapi_dispatch.c:40:
../include/GL/gl.h:1901:62: note: previously declared as an array 'const GLdouble[16]' {aka 'const double[16]'}
1901 | GLAPI void GLAPIENTRY glLoadTransposeMatrixd( const GLdouble m[16] );
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11198>
Timur Kristóf [Thu, 10 Jun 2021 09:40:16 +0000 (11:40 +0200)]
aco: Use as_vgpr for the second source of mbcnt_amd.
Fixes:
1e49018cedf700fd21fe1498d24742cecf4b5ff4
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11292>
Samuel Pitoiset [Tue, 8 Jun 2021 07:00:07 +0000 (09:00 +0200)]
ci: add expected list of failures for Bonaire (RADV)
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11239>
Mike Blumenkrantz [Tue, 25 May 2021 18:17:56 +0000 (14:17 -0400)]
zink: fix caching of shader variants with inlined uniforms
attempting to read the inlined uniforms directly after the variant key
using the size of the variant is not going to work since the variant union
is (sometimes) much larger than the size of the actual struct being used,
meaning that this would just copy a bunch of zeroes instead of the actual
inlined uniforms
Fixes:
7f28775edcc ("zink: implement uniform inlining")
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11003>
Samuel Pitoiset [Tue, 8 Jun 2021 12:46:58 +0000 (14:46 +0200)]
radv/winsys: add a small comment explaining the CHAIN bit
Without it the hardware launches an IB2 which might hang in some
rare situations.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11214>
Samuel Pitoiset [Mon, 7 Jun 2021 08:14:01 +0000 (10:14 +0200)]
radv: do not launch an IB2 for secondary cmdbuf with INDIRECT_MULTI on GFX7
It's illegal to emit DRAW_{INDEX}_INDIRECT_MULTI from an IB2 on GFX7.
PAL applies this workaround for indirect dispatches and also on
GFX8-9 but it doesn't seem needed.
This fixes various GPU hangs on Bonaire (GFX7).
Cc: 21.1 mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11214>
Tomeu Vizoso [Wed, 9 Jun 2021 16:46:49 +0000 (13:46 -0300)]
panfrost/ci: Add some failures that crept in
For a few days the CI wasn't reporting failures, and these crept in.
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11218>
Tomeu Vizoso [Wed, 9 Jun 2021 16:45:03 +0000 (13:45 -0300)]
iris/ci: Update the checksums for the pixmark-piano trace
The rendering changed while the CI was down. The rendering still looks
good, only some pixels in the edges have changed, probably due to
blending?
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11218>
Daniel Stone [Wed, 9 Jun 2021 14:00:50 +0000 (15:00 +0100)]
ci/lava: Handle proxy download failures
LAVA doesn't consider failure to download a kernel/initramfs as an
infrastructure error, rather just a user error for supplying a broken
URL. We know our URLs aren't broken (because we're perfect), so assume
that failures in download validation are network issues and retry when
we hit them.
LAVA itself has been fixed to retry internally, so we'll get that when
upgrade in a couple of weeks, but gloss over it for now.
Signed-off-by: Daniel Stone <daniels@collabora.com>
Reviewed-by: Gustavo Padovan <gustavo.padovan@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11218>
Daniel Stone [Wed, 9 Jun 2021 13:53:23 +0000 (14:53 +0100)]
ci/lava: Iterate all job results, not just the first
Each step in a LAVA job returns separate results; a successfully-retired
job can have about 12 entries. Make sure we iterate through all of them
when we're looking for infrastructure errors.
Signed-off-by: Daniel Stone <daniels@collabora.com>
Reviewed-by: Gustavo Padovan <gustavo.padovan@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11218>
Gustavo Padovan [Tue, 8 Jun 2021 17:47:33 +0000 (14:47 -0300)]
ci/lava: do not save lava.yaml in the artifacts
We want to avoid leaking private data used in merge process.
Signed-off-by: Gustavo Padovan <gustavo.padovan@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11218>
Gustavo Padovan [Mon, 7 Jun 2021 11:03:24 +0000 (08:03 -0300)]
ci/lava: propely report test failure through sys.exit()
We added lava_job_submitter.py to improve our robusteness, but
the final result reporting was not handled correctly by the script.
This change fix it by properly calling sys.exit() on failures.
Signed-off-by: Gustavo Padovan <gustavo.padovan@collabora.com>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11218>
Iago Toral Quiroga [Wed, 9 Jun 2021 06:44:07 +0000 (08:44 +0200)]
v3dv: don't lower vulkan resource index result to scalar
The intrinsic produces a vec2, so let's honor that and avoid the weird
lowering to scalar and later reconstruction to vec2 when we find
load vulkan descriptor intrinsics.
It fixes tests like this (which require that we expose KHR_spirv_1_4):
dEQP-VK.spirv_assembly.instruction.spirv1p4.opptrequal.null_comparisons_ssbo_equal
that otherwise produce bad code that tries to access a vec2 from the result of
that intrinsic, leading to NIR validation errors.
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11257>
Iago Toral Quiroga [Tue, 8 Jun 2021 09:05:36 +0000 (11:05 +0200)]
v3dv: expose KHR_variable_pointers
We only support the VariablePointersStorageBuffer feature for now,
which is the only one that is mandatory, and for which we seem to
be passing all the relevant tests already.
Exposing the optional VariablePointers feature would require that
we support non-constant indexing on UBO/SSBO first.
Relevant CTS tests:
dEQP-VK.*pointer*
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11257>
Dave Airlie [Wed, 9 Jun 2021 22:30:44 +0000 (08:30 +1000)]
u_blitter: fix stencil blit fallback for crocus.
crocus needs the sampler view decl to know it's a uint return value.
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11280>
Dave Airlie [Thu, 24 Dec 2020 02:58:48 +0000 (12:58 +1000)]
u_blitter: fix fs used when no color emitted
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11280>
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