iris: Add and use fill_surface_states

This helper simplifies some repeated logic.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14806>

iris: Add and use use_surface_state

This helper simplifies some repeated logic.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14806>

iris: Add and use iris_surface_state::aux_usages

An iris_surface_state can have a different set of possible aux usages
than its iris_resource.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14806>

iris: Drop res param from surf_state_offset_for_aux

This has been unused since commit 117a0368b0cc.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14806>

iris: Drop format param from fast_clear_color

It's unused.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14806>

iris: Don't fast clear with the view format

Fast clear with the resource format instead. This is safe to do because
can_fast_clear_color ensures that the clear color generates the same
pixel with either the view format or the resource format.

On SKL, this prevents us from using an invalid surface state. This platform
doesn't support CCS_E with sRGB formats, but prior to this patch we allowed
fast-clearing with this combination. Piglit's fcc-write-after-clear test
can trigger this.

Fixes: 230952c2101 ("iris: Don't support sRGB + Y_TILED_CCS on gen9")
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14806>

aux/draw: fix llvm tcs lane vec generation

the idx param for LLVMBuildInsertElement is zero-indexed based on the
value of 'vector_length' (always 4), and the vector length is (obviously)
sized to 'vector_length', so this should be the member of the vec that is being
inserted, not the invocation index

cc: mesa-stable

fixes (zink, but only on my one machine):
KHR-GL46.tessellation_shader.single.max_patch_vertices
KHR-GL46.tessellation_shader.tessellation_shader_tc_barriers.barrier_guarded_read_write_calls
dEQP-GLES31.functional.tessellation.shader_input_output.barrier
dEQP-GLES31.functional.tessellation.shader_input_output.patch_vertices_5_in_10_out
dEQP-GLES31.functional.tessellation_geometry_interaction.feedback.tessellation_output_isolines_geometry_output_points
dEQP-GLES31.functional.tessellation_geometry_interaction.feedback.tessellation_output_isolines_point_mode_geometry_output_triangles
dEQP-GLES31.functional.tessellation_geometry_interaction.feedback.tessellation_output_quads_geometry_output_points
dEQP-GLES31.functional.tessellation_geometry_interaction.feedback.tessellation_output_quads_point_mode_geometry_output_lines
dEQP-GLES31.functional.tessellation_geometry_interaction.feedback.tessellation_output_triangles_geometry_output_points
dEQP-GLES31.functional.tessellation_geometry_interaction.feedback.tessellation_output_triangles_point_mode_geometry_output_lines

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14949>

radv: Add submit locking with trace bo.

Otherwise cmdbuffers from different queues can override the trace id
from each other, making for a very confusing hang report.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14868>

gallivm/nir: Call nir_lower_bool_to_int32 after nir_opt_algebraic_late

All of the opcodes in nir_opt_algebraic_late are the unsized (1-bit)
versions.  If the lowering to int32 happens first, many of the
optimizations and lowerings won't happen.

Of particular importance is the lowering of fisfinite.  If a shader
happens to contain fisfinite of an fp16 value, it will assert later
during compliation.

Reviewed-by: Dave Airlie <airlied@redhat.com>
Fixes: 78b4e417d44 ("gallivm: handle fisfinite/fisnormal")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14942>

ci/freedreno: Try to detect a wedged MMU that's happened recently.

Possibly since the VK-GL-CTS 1.3.1.0 uprev.  It doesn't seem to recover,
like it says.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14945>

ci/lvp: Add a flake that's shown up a couple of times since VKCTS 1.3.1.

Acked-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14945>

ci/r300: Drop xfails that were fixed with the VK-GL-CTS 1.3.1.0 uprev.

Acked-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14404>

nir: Delete the per-instr SSA liveness impl.

It was introduced for nir-to-tgsi, and I found that it was the wrong
approach.  There's a reason nobody else does RA this way.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14404>

nir_to_tgsi: Replace the NIR SSA liveness with TGSI reg-level liveness.

Allocating NIR registers ends up being required for drivers like r600 and
nv30, which don't do their own allocation (except in some cases on r600
where sb is used).

Rather than add a NIR register liveness impl
(https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14158), switch
from NIR-based liveness to just doing the same channel-based liveness
logic that the NIR registers needed at the TGSI level.  The actual
liveness code here basically comes straight out of
brw_vec4_live_variables.cpp.

Since we do the liveness in TGSI now, it also means we don't need to be
careful about not reading SSA values from later TGSI instructions (which
may be useful for doing some greedy instruction selection in generating
TGSI instructions).

i915g:
total instructions in shared programs: 400719 -> 380730 (-4.99%)
instructions in affected programs: 284760 -> 264771 (-7.02%)
total tex_indirect in shared programs: 12289 -> 12290 (<.01%)
tex_indirect in affected programs: 4 -> 5 (25.00%)
total temps in shared programs: 32172 -> 22086 (-31.35%)
temps in affected programs: 30647 -> 20561 (-32.91%)
LOST:   0
GAINED: 148

r300:
total instructions in shared programs: 1472463 -> 1459286 (-0.89%)
instructions in affected programs: 507009 -> 493832 (-2.60%)
total temps in shared programs: 212143 -> 201678 (-4.93%)
temps in affected programs: 78007 -> 67542 (-13.42%)

softpipe:
total temps in shared programs: 517071 -> 294387 (-43.07%)
temps in affected programs: 509324 -> 286640 (-43.72%)

Acked-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14404>

nir_to_tgsi: Track our TGSI insns in blocks before emitting tokens.

To do register allocation well, we want to have a point before
ureg_insn_emit() to look at the liveness of the values and allocate them
to TGSI temporaries.  In order to do that, we have to switch from
ureg_OPCODE() emitting TGSI tokens directly to a new ntt_OPCODE() that
stores the ureg args in a block structure.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14404>

tgsi: Refactor out a tgsi_util_get_src_usage_mask().

The function operated on a tgsi_full_instruction, but for code generation
in NIR-to-TGSI I want to reuse this logic using pieces of tgsi_ureg
structs.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14404>

i915g: Report the temps usage

This is another important metric for this driver, and we don't do our own
RA so ours is just what TGSI uses.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14404>

docs: update calendar and link releases notes for 21.3.6

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14956>

docs: add release notes for 21.3.6

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14956>

docs: update calendar for 22.0.0-rc2

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14953>

turnip: Depth/stencil formats should not expose any bufferFeatures

From the Vulkan 1.3.205 spec, section 19.3 "43.3. Required Format Support":

   Mandatory format support: depth/stencil with VkImageType
   VK_IMAGE_TYPE_2D
   [...]
   bufferFeatures must not support any features for these formats

See https://gitlab.khronos.org/vulkan/vulkan/-/merge_requests/4849

Fixes CTS tests: dEQP-VK.api.buffer.invalid_buffer_features.*

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14927>

radv: only emit the per-vertex VRS state if the pipeline forced it

If the primitive shading rate is not written by the last VGT stage
(like if no FS), it's useless to emit the VRS state.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14907>

radv: do not force per-vertex VRS if there is no pixel shader

This has no effect.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14907>

radv: rewrite RADV_FORCE_VRS directly in NIR

This introduces a small NIR pass that exports
VARYING_SLOT_PRIMITIVE_SHADING_RATE if RADV_FORCE_VRS is used,
instead of doing this in both backend compilers.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14907>

v3dv/ci: Update failure list

Add more failing tests to the expected failures.

These are obtained after executing the full Vulkan CTS.

v2:
 - Add comments in the tests (Alejandro)

Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14948>

zink: ci updates

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14852>

zink: add Sample decorations to fragment shader inputs with sample shading

PIPE_CAP_FORCE_PERSAMPLE_INTERP is broken for the no-attachment case, so
this is the only option

fixes (lavapipe):
KHR-GL46.sample_shading.render*
dEQP-GLES31.functional.sample_shading.min_sample_shading*

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14852>

iris/ci: Enable Whiskey Lake boards by default

The boards should be stable now.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Acked-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
Acked-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14822>

radeonsi: workaround Specviewperf13 Catia hang on GFX9

The root cause is unknown but PAL always update IA_MULTI_VGT_PARAM
whenever primitive type change.

cc: mesa-stable

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Singed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14944>

intel/fs: Assert that old pull-const code is not used if devinfo->has_lsc

Jason changed this to use LSC in:

f5876dfdb9b ("intel/fs: Lower uniform pull constant load message to LSC dataport")

Cc: 22.0 <mesa-stable>
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14384>

iris: invalidate L3 read only cache when VF cache is invalidated

When enabling the caching of index,vertex data in the L3 RO Cache
(L3BypassDisable), we need to use L3ReadOnlyCacheInvalidationEnable
to invalidate cache when buffer is modified by CPU/GPU.

Ref: bspec 46314
Fixes: ed8f2c4cbee ("iris: Cache VB/IB in L3$ for Gen12")
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14815>

anv: invalidate L3 read only cache when VF cache is invalidated

When enabling the caching of index,vertex data in the L3 RO Cache
(L3BypassDisable), we need to use L3ReadOnlyCacheInvalidationEnable
to invalidate cache when buffer is modified by CPU/GPU.

Ref: bspec 46314
Fixes: 6c345ddbe40 ("anv: Cache VB/IB in L3$ for Gfx12")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5941
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14815>

intel/genxml: add PIPE_CONTROL field for L3 read only cache invalidation

Cc: mesa-stable
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14815>

anv: Refactor descriptor copy

Refactor descriptor copies to use the existing helper functions instead
of rolling our own. In order to facilitate this, we need to store the
appropriate buffer views for the relevant descriptors internally and
reuse them in the helpers.

Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14909>

radv: allow RADV_FORCE_VRS with pipeline VRS declared as dynamic

This is for vkd3d which needs to always declare the VRS dynamic state
because it's fully dynamic in DX12. Ignoring the VRS dynamic state
when it's a no-op seems the best way to handle this, although it's
definitely not perfect.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14910>

iris: Disable PIPE_CAP_PREFER_BACK_BUFFER_REUSE

This cap bit only affects DRI_PRIME setups.  Since iris now uses the
blitter to perform dGPU -> iGPU copies asynchronously, it's better to
always use at least two backbuffers so the 3D engine can start rendering
the next frame during the copy.

See commit d17e75285732878bc3ee8307541c1b4f09cbee7c where this change
was made for radeonsi.

Acked-by: Caio Oliveira <caio.oliveira@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13877>

iris: Use the hardware blitter for DRI PRIME blits

In a hybrid graphics setup, Mesa allocates two buffers for the window
surface.  The first is what the discrete card renders to; it lives in
VRAM and is usually tiled and possibly compressed.  The second is a
shadow copy that lives in system memory (readable by the integrated
card with the displays); it's usually linear and uncompressed.

Mesa's window system code schedules blits to update the shadow copy
when needed, typically at the end of a frame.  These can be fairly
costly when running a full-screen application at high resolutions.

We'd like to use the blitter for these copies, as it lets us perform
the copy asynchronously, letting the 3D engine race ahead and start
rendering the next frame.  If we used the 3D engine, the next frame
could not start rendering until the PRIME blit finishes, giving us
less time to draw the frame.  Fortunately, Tigerlake introduced new
blitter commands which can operate at full memory bandwidth.

DRI PRIME blits happen via the Gallium blit() hook.  We can detect that
case by looking for the PIPE_BIND_PRIME_BLIT_DST flag on the destination
resource.  This patch detects that case and calls iris_copy_region() on
IRIS_BATCH_BLITTER to handle it.  We know a priori that the blitter can
handle this operation (it's not a scaled blit, the formats match and
should not be 96bpp, there's no combined depth stencil, or other weird
edge cases).  blorp_copy() will also assert that edge cases don't occur.

Together with the next patch, this improves performance on DG1 Hybrid
scenarios by about 5-6%.

Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13877>

iris: Allow IRIS_BATCH_BLITTER in iris_copy_region()

This updates iris_copy_region() to support using the blitter batch.
(Future patches will actually do so; for now, we keep using render.)

Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13877>

broadcom/simulator: enable multisync in the simulator

Use drmSyncobjSignal to signal out_syncobjs when a GPU job submission
ends in the simulator. With this, we can enable multisync support in the
simulator and keep the multisync approach to process fence by submitting
a serialized no-op job that adds the fence to the array of out syncobjs,
i.e.  syncobjs to be signaled in the kernel when a job completes (job
post deps).

Signed-off-by: Melissa Wen <mwen@igalia.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14768>

translate: improve sse2 32-bit unsigned -> float conversion

The existing logic would drop the low bit. Instead, let's drop the high
bit, do the conversion, and then add the fixed constant back in if the
value had the high bit set originally.

Fixes KHR-GL45.direct_state_access.vertex_arrays_attribute_format on
drivers that use this module to handle the format conversion.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Acked-by: Emma Anholt <emma@anholt.net>
Tested-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14922>

rtasm: add pcmpgtd operation

This will be used shortly by the translate code. Available in SSE2.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Acked-by: Emma Anholt <emma@anholt.net>
Tested-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14922>

rtasm: fix printf specifier for ptrdiff_t

In practice it's a small number, but new gcc versions complain.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Acked-by: Emma Anholt <emma@anholt.net>
Tested-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14922>

zink: ci updates

hooray

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14932>

zink: do not copy colors through floats

Copying per compoents might flush NaN values, leading to changes in the
values, so it'd be safer to copy as unsigned integers here. But in one
of the cases here we can do even better, and just copy the whole damn
union instead.

Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14932>

zink: Re-interpret formats when using vkCmdClearColorImage()

vkCmdClearColorImage() doesn't take a view format so it always uses the
underlying format of the image.  If there's texture views going on, we
need to manually mangle the colors into the image format.

Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14932>

st/mesa: only enable ARB_enhanced_layouts if there are xfb buffers

It really doesn't make sense without any xfb support. One could limp
along, but our validation does not work as-is. Doesn't seem important to
support this use-case.

This disables GL_ARB_enhanced_layouts on crocus with gen4/5.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14869>

glsl: only validate xfb_buffer values when we have enhanced layouts

XFB might not be supported, and the shader wouldn't be setting this
flag. But validation would still fail, since the number of xfb buffers
would be 0. So only validate if an xfb_buffer is set in the qualifiers.

See: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5415
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14869>

glsl: simplify conditions for setting various allowed flags

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14869>

nir_to_tgsi: Add a flag for lowering fabs, and use it in r300/i915.

Saves instructions if the same fabs value is used multiple times.

i915g:
total instructions in shared programs: 397005 -> 396525 (-0.12%)
instructions in affected programs: 11061 -> 10581 (-4.34%)
LOST:   0
GAINED: 22

r300 (not r500):
total instructions in shared programs: 180286 -> 179767 (-0.29%)
instructions in affected programs: 27102 -> 26583 (-1.91%)
total temps in shared programs: 29692 -> 29638 (-0.18%)
temps in affected programs: 356 -> 302 (-15.17%)

Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14938>

nir: Split the flag for lowering of fabs and fneg to source modifiers.

i915 and r300 have fneg source modifier but not fabs, and doing it in NIR
can save us some backend pain.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14938>

r300: Throw a compile error instead of an assert in r300 swizzle rewrites.

I hit this on shader-db, but I really just want to get stats for unrelated
changes.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14938>

r300: Demote a compiler assert(0) to a compile failure.

This triggers in shader-db and doesn't have an obvious fix.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14938>

d3d12: Fix take_ownership semantic for constant buffers

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14941>

r300: Request that nir-to-tgsi avoid generating TGSI_OPCODE_CMP.

Given that our fcsels are on float-bools, we can emit the LRP directly and
save the backend having to emit a SLT to turn the CMP src[0] into a bool.

This required passing a codegen flags struct for nir-to-tgsi.  I think
this is a good way forward for it, as the alternative I think has mostly
been adding flags to nir_shader_compiler_options (since adding
PIPE_SHADER_CAPs is an unreasonable amount of pain).

r300 shader-db:
total instructions in shared programs: 1484320 -> 1472463 (-0.80%)
instructions in affected programs: 243588 -> 231731 (-4.87%)
total temps in shared programs: 212485 -> 212143 (-0.16%)
temps in affected programs: 3845 -> 3503 (-8.89%)

Acked-by: Pavel Ondračka <pavel.ondracka@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14886>

ci/lavapipe: update lvp asan results after leak fixes.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14939>

lavapipe: fix sampler + sampler view leaks.

The compute sampler views are using a different method
of generation so have to be deleted explicitly.

Fixes: e94fd4cc6589 ("lavapipe: rename vallium to lavapipe")

Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14939>

r300: fix transformation of abs modifiers with negate

It is being overwritten by the memset. Just set the only remaining
member RelAddr explicitly.

Signed-off-by: Pavel Ondračka <pavel.ondracka@gmail.com>
Reviewed-by: Filip Gawin <filip.gawin@zoho.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14915>

ci: Bump VK-GL-CTS to 1.3.1.0.

The main thing is VK 1.3 testing, but also includes test bugfixes.  The
1.3 CTS required an uprev of deqp-runner to handle a new style of test
output, and that deqp-runner brings in some neat new features, too (piglit
in your deqp-runner suite, and extension list checking).

A bunch of VK tests got renamed, so I replaced panvk's custom test list
with simple include filters on the main test list.

Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com> (panvk)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14920>

ci/broadcom: Remove unused v3dv xfails file.

It's actually in broadcom-rpi4-fails.txt.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14920>

ci/panfrost: Add a flake a few of us have run into in the last couple days.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14920>

d3d12: Allow 8bit index buffer conversions by vbuf

Reviewed-by: Sil Vilerino <sivileri@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14933>

d3d12: Use CPU storage in TC for buffers

Reviewed-by: Sil Vilerino <sivileri@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14933>

d3d12: Add a buffer busy callback to the bufmgr

Not all cached buffers can be mapped, so using map with do-not-wait
is a terrible heuristic. Use an explicit buffer busy callback which
is always false, since buffers are only put into the cache once they're
free.

Reviewed-by: Sil Vilerino <sivileri@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14933>

d3d12: Actually suballocate and cache buffers

Reviewed-by: Sil Vilerino <sivileri@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14933>

d3d12: Fix offset for buf/image copies with suballocated buffers

Reviewed-by: Sil Vilerino <sivileri@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14933>

d3d12: Don't suballocate TBO buffers

Reviewed-by: Sil Vilerino <sivileri@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14933>

d3d12: Fix TBOs from suballocated buffers

Reviewed-by: Sil Vilerino <sivileri@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14933>

d3d12: Delete make_resource_writeable

This never did anything useful AFAICT since we didn't actually
suballocate buffers, and when this ended up being invoked it breaks
the ability to read back XFB data.

Reviewed-by: Sil Vilerino <sivileri@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14933>

d3d12: Always respect offsets when mapping a bo, not just when there's a range

Reviewed-by: Sil Vilerino <sivileri@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14933>

d3d12: Fix range calculation for suballocated buffers in d3d12_bo_unmap

Reviewed-by: Sil Vilerino <sivileri@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14933>

d3d12: Fix set constant buffers

Reviewed-by: Sil Vilerino <sivileri@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14933>

tc: CPU storage needs to be freed with align_free

Cc: mesa-stable
Acked-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Sil Vilerino <sivileri@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14933>

panfrost: Fix Depth Source enum

As I suspected... sigh.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14935>

panfrost: Remove unused layout enums

Folded into Valhall-specific plane descriptor enums.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14935>

panfrost: Remove some indexed formats on Valhall

Block compressed formats like ETC2 are now indicated in the plane descriptor,
rather than the pixel format descriptor. Various other minor formats were
removed in Valhall; remove them from the XML so we don't accidentally try to use
them.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14935>

panfrost: Update supported job types

Remove a few that no longer exist, and rename IDVS helper to Malloc Vertex. The
distinction between Malloc Vertex jobs and regular Indexed Vertex jobs is that
the hardware allocates varying buffers dynamically for Malloc Vertex jobs.
Regular IDVS and even legacy tiler jobs are also supported where desired.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14935>

panfrost: Flesh out tiler heap descriptor

Merged with the Buffer descriptor, hence why it shares a type nibble. However,
Bifrost uses a dedicated tiler heap descriptor, and I see no benefit to merging.
So pretending it's a dedicated descriptor on Valhall too allows us to reuse the
Bifrost code with no modifications.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14935>

panfrost: Strip % in GenXML names

A new Valhall enum will represent percentages, so allow that.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14935>

panfrost: Flesh out Buffer descriptor

Add fields required for structured buffers.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14935>

vulkan,lavapipe: Simplify command recording code-gen

The Entrypoint class already has utilities for gettingt he parameter
list as either declarations or as comma-separated argument names for a
call.  Use that instead of hand-rolling it.  The only modification we
need to make is to add the ability to start the list somewhere other
than at the beginning.

Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Acked-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14919>

lavapipe: ci updates

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14911>

zink: ci updates

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14911>

lavapipe: use util_pack_color_union() for generating clear colors

this enables clamping for packed formats (e.g., RGB10_A2UI) where color
values may exceed the width of the component

cc: mesa-stable

fixes (zink):
KHR-GL45.direct_state_access.renderbuffers_storage*

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14911>

ci/freedreno: Add another unsizedArrayLength flake.

Started appearing on Feb 1, but given that the rest of this test group
flakes, I assume it's similar.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14934>

venus: Allow usage of virtio-mmio based device

Libdrm reports bustype as DRM_BUS_PLATFORM for virtio-mmio
based device. DRM_BUS_PCI is reported only for virtio-pci based
devices. Add possibility to use devices with DRM_BUS_PLATFORM.

Signed-off-by: Andrii Pauk <Andrii.Pauk@opensynergy.com>
Reviewed-by: Chia-I Wu <olvaffe@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14531>

aco: optimize discard_if when WQM is not needed afterwards

Totals from 11560 (8.57% of 134913) affected shaders: (GFX10.3)
CodeSize: 12092560 -> 11997652 (-0.78%)
Instrs: 2205325 -> 2181598 (-1.08%)
Latency: 15376048 -> 15356958 (-0.12%); split: -0.12%, +0.00%
InvThroughput: 3526105 -> 3525120 (-0.03%); split: -0.03%, +0.00%
Copies: 98543 -> 87601 (-11.10%)
Branches: 16919 -> 16873 (-0.27%)
PreSGPRs: 291584 -> 291532 (-0.02%)

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14805>

aco: merge block_kind_uses_[demote|discard_if]

These serve the same purpose. The new name is
block_kind_uses_discard.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14805>

aco: make Preserve_WQM independent from block_kind_uses_discard_if

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14805>

aco: remove block_kind_discard

This case doesn't seem to happen in practice.
No need to micro-optimize it.

This patch merges instruction selection for discard/discard_if.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14805>

aco: emit nir_intrinsic_discard() as p_discard_if()

This simplifies the code and emits a slightly better
sequence in some cases.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14805>

mesa: align constant/uniform uploads to driver expected alignment

This fixed a problem for Zink where uniform buffer alignment varies by
GPU, e.g. 64 bytes for an RTX 2070 SUPER but 256 bytes for a GTX 1070
Ti.

Tested running Superposition on Windows 10 with Nvidia 1070 Ti with
496.13 driver.  Without the fix Superposition soft locks on its splash
screen.  With the fix Superposition runs through its benchmark.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14674>

zink: Fix MSVC RTC in zink_get_framebuffer_imageless()

The bit fields in zink_framebuffer_state cause a false positive with
MSVC's run-time checks enabled.  setting state.num_attachments in
zink_get_framebuffer_imageless().  Writing some bits of num_attachments
involves reading bits from layers and samples that haven't been
initialized.

Fixed by assigning to num_attachments earlier in the function.  Not
quite sure why that makes a difference but at a guess there's a
heuristic that considers assignment close to declaration as
initialization.

Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14566>

zink: export PIPE_CAP_CULL_DISTANCE_NOCOMBINE

fixes:
KHR-GL46.cull_distance.functional

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14878>

gallium: add PIPE_CAP_CULL_DISTANCE_NOCOMBINE

for drivers where separate cull distance variables are required, this
lets them avoid having to write yet another pass to undo gallium's mangling
of shader info

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14878>

anv: fix conditional render for vkCmdDrawIndirectByteCountEXT

We just forgot about conditional render for this entry point.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 2be89cbd826f9a ("anv: Implement vkCmdDrawIndirectByteCountEXT")
Tested-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14891>

anv: enable ray queries

Only on platforms that support it.

v3: Split out code setting up ray query shadow buffer (Caio)
    Don't forget to setup ray query globals even when no shadow buffer
    is used (Lionel)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13719>

intel/fs: lower ray query intrinsics

v2: Add helper for acceleration->root_node computation (Caio)

v3: Update comment on "done" bit (Caio)
    Remove progress bool value for impl function (Caio)
    Don't use nir_shader_instructions_pass to search the shader (Caio)

v4: Rename variable for if/else block (Caio)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13719>

intel/nir: document RT builder

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13719>

nir/lower_shader_calls: consider relocated constants as rematerializable

After all they're constants.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13719>

intel/nir/rt: add more helpers for ray queries

v2: Split stack_id helper in sync/async version (Caio)
    Fixup a few bit field mistake (Caio)
    Simplify some bitfield manipulations (Caio)

v3: Remove duplicated helper (Caio)
    Simplify brw_nir_rt_set_dword_bit_at (Caio)
    Comment brw_nir_rt_query_mark_init (Lionel)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13719>