Saleem Abdulrasool [Mon, 2 Aug 2021 16:34:56 +0000 (16:34 +0000)]
unwind: repair register restoration for OR1K
Currently, OR1K architecture put the program counter at offset 0x128 of
the current `or1k_thread_state_t`. However, the PC is restored after
updating the thread pointer in `r3`, which causes the PC to be fetched
incorrectly.
This patch swaps the order of restoration of `r9` and `r3`, such that
the PC is restored to `r9` using the current thread state.
Patch by Oi Chee Cheung!
Reviewed By: whitequark, compnerd
Differential Revision: https://reviews.llvm.org/D107042
Valeriy Savchenko [Wed, 9 Dec 2020 11:08:43 +0000 (14:08 +0300)]
[analyzer] Highlight arrows for currently selected event
In some cases, when the execution path of the diagnostic
goes back and forth, arrows can overlap and create a mess.
Dimming arrows that are not relevant at the moment, solves this issue.
They are still visible, but don't draw too much attention.
Differential Revision: https://reviews.llvm.org/D92928
Valeriy Savchenko [Tue, 1 Dec 2020 08:53:53 +0000 (11:53 +0300)]
[analyzer] Add control flow arrows to the analyzer's HTML reports
This commit adds a very first version of this feature.
It is off by default and has to be turned on by checking the
corresponding box. For this reason, HTML reports still keep
control notes (aka grey bubbles).
Further on, we plan on attaching arrows to events and having all arrows
not related to a currently selected event barely visible. This will
help with reports where control flow goes back and forth (eg in loops).
Right now, it can get pretty crammed with all the arrows.
Differential Revision: https://reviews.llvm.org/D92639
Sjoerd Meijer [Mon, 2 Aug 2021 15:13:19 +0000 (16:13 +0100)]
[AArch64] Add shufflevector concat codegen tests. NFC.
Kazu Hirata [Mon, 2 Aug 2021 15:07:25 +0000 (08:07 -0700)]
[ADT] Remove PointerUnionTypeSelector (NFC)
The last use was removed on May 17, 2019 in commit
9b92875bbdde7c1e01b9e739da66aa876022eadd.
Benjamin Kramer [Mon, 2 Aug 2021 14:52:29 +0000 (16:52 +0200)]
[tsan] Complete renaming kMaxSid to kThreadSlotCount
This was missing from
5c2b48fdb0a6
Pushpinder Singh [Mon, 2 Aug 2021 07:13:09 +0000 (07:13 +0000)]
[OpenMP][AMDGCN] Initial math headers support
With this patch, OpenMP on AMDGCN will use the math functions
provided by ROCm ocml library. Linking device code to the ocml will be
done in the next patch.
Reviewed By: JonChesterfield, jdoerfert, scchan
Differential Revision: https://reviews.llvm.org/D104904
Marshall Clow [Mon, 2 Aug 2021 13:57:43 +0000 (06:57 -0700)]
Change code owner of libc++ from Marshall to Louis
Simon Pilgrim [Mon, 2 Aug 2021 12:54:17 +0000 (13:54 +0100)]
[VectorCombine] Fix PR30986 poison test case
Thanks @xbolva00!
Hans Wennborg [Mon, 26 Jul 2021 13:09:36 +0000 (15:09 +0200)]
prfchwintrin.h: Make _m_prefetchw take a pointer to volatile (PR49124)
For some reason, Microsoft declares _m_prefetch to take a const void*,
but _m_prefetchw to take a /volatile/ const void*.
Do the same for compatibility.
Differential revision: https://reviews.llvm.org/D106790
David Green [Mon, 2 Aug 2021 13:15:45 +0000 (14:15 +0100)]
[ARM] Remove setPreservesCFG from ARMBlockPlacement
As of
28293918409dd3a5a it no longer preserves the CFG, needing to
split blocks in order to add DLS instructions.
Justas Janickas [Tue, 27 Jul 2021 11:21:35 +0000 (12:21 +0100)]
[OpenCL] __cpp_threadsafe_static_init is by default undefined in OpenCL mode.
Definition of `__cpp_threadsafe_static_init` macro is controlled by
language option Opts.ThreadsafeStatics. This patch sets language
option to false by default in OpenCL mode, resulting in macro
`__cpp_threadsafe_static_init` being undefined. Default value can be
overridden using command line option -fthreadsafe-statics.
Change is supposed to address portability because not all OpenCL
vendors support thread safe implementation of static initialization.
Fixes llvm.org/PR48012
Differential Revision: https://reviews.llvm.org/D107163
Florian Mayer [Mon, 2 Aug 2021 12:56:02 +0000 (13:56 +0100)]
[hwasan] Commit missed REQUIRES: stable-runtime.
Differential Revision: https://reviews.llvm.org/D107268
Irina Dobrescu [Thu, 22 Jul 2021 15:21:48 +0000 (16:21 +0100)]
[AArch64] Optimise min/max lowering in ISel
Differential Revision: https://reviews.llvm.org/D106561
Justas Janickas [Mon, 2 Aug 2021 12:12:41 +0000 (13:12 +0100)]
[clang][NFC] Typo fixes. Test commit.
Fixed spelling of word "whether"
Kunwar Shaanjeet Singh Grover [Mon, 2 Aug 2021 12:17:46 +0000 (17:47 +0530)]
[MLIR] FlatAffineConstraints: Fixed bug where some divisions were not being detected
This patch fixes a bug in the existing implementation of detectAsFloorDiv,
where floordivs with numerator with non-zero constant term and floordivs with
numerator only consisting of a constant term were not being detected.
Reviewed By: vinayaka-polymage
Differential Revision: https://reviews.llvm.org/D107214
Dmitry Vyukov [Mon, 2 Aug 2021 12:15:07 +0000 (14:15 +0200)]
tsan: remove unbalanced mutex unlock
The mutex is now unlocked by the scoped Lock object.
Differential Revision: https://reviews.llvm.org/D107266
Guillaume Chatelet [Mon, 2 Aug 2021 12:14:11 +0000 (12:14 +0000)]
[libc] Add a Google Benchmark target to support continuous monitoring of memory operation performance
The next step is to be able to benchmark several implementations at once and compare which one performs best on a particular machine.
Differential Revision: https://reviews.llvm.org/D107265
Simon Pilgrim [Mon, 2 Aug 2021 12:05:47 +0000 (13:05 +0100)]
[VectorCombine] Add PR30986 test case
Dmitry Vyukov [Fri, 30 Jul 2021 14:00:54 +0000 (16:00 +0200)]
tsan: add new vector clock
Add new fixed-size vector clock for the new tsan runtime.
For now it's unused.
Reviewed By: melver
Differential Revision: https://reviews.llvm.org/D107167
Dmitry Vyukov [Mon, 2 Aug 2021 09:06:58 +0000 (11:06 +0200)]
tsan: don't save creation stack for some sync objects
Currently we save the creation stack for sync objects always.
But it's not needed to some sync objects, most notably atomics.
We simply don't use atomic creation stack anywhere.
Allow callers to control saving of the creation stack
and don't save it for atomics.
Depends on D107257.
Reviewed By: melver
Differential Revision: https://reviews.llvm.org/D107258
Dmitry Vyukov [Mon, 2 Aug 2021 09:06:54 +0000 (11:06 +0200)]
tsan: add LIKELY/UNLIKELY to MetaMap::GetSync
MetaMap::GetSync shows up in profiles,
so add LIKELY/UNLIKELY annotations.
Depends on D107256.
Reviewed By: melver
Differential Revision: https://reviews.llvm.org/D107257
Dmitry Vyukov [Mon, 2 Aug 2021 09:06:47 +0000 (11:06 +0200)]
tsan: refactor MetaMap::GetAndLock interface
Don't lock the sync object inside of MetaMap methods.
This has several advantages:
- the new interface does not confuse thread-safety analysis
so we can remove a bunch of NO_THREAD_SAFETY_ANALYSIS attributes
- this allows use of scoped lock objects
- this allows more flexibility, e.g. locking some other mutex
between searching and locking the sync object
Also prefix the methods with GetSync to be consistent with GetBlock method.
Also make interface wrappers inlinable, otherwise we either end up with
2 copies of the method, or with an additional call.
Reviewed By: melver
Differential Revision: https://reviews.llvm.org/D107256
Sjoerd Meijer [Mon, 2 Aug 2021 11:07:21 +0000 (12:07 +0100)]
[CostModel][AArch64] Add some shuffle concat tests. NFC.
Test ported over from test/Analysis/CostModel/ARM/shuffle.ll.
Carl Ritson [Mon, 2 Aug 2021 10:27:40 +0000 (19:27 +0900)]
[AMDGPU] Disable NSA for BVH instructions when appropriate
Check maximum NSA size when selecting NSA or non-NSA BVH instructions.
Differential Revision: https://reviews.llvm.org/D103230
Petar Avramovic [Mon, 2 Aug 2021 10:16:52 +0000 (12:16 +0200)]
GlobalISel: Fix infinite loop in legalization artifact combiner
ArtifactValueFinder keeps trying to combine g_unmerge_values in some cases.
Fix is to skip combine attempt for dead defs.
Differential Revision: https://reviews.llvm.org/D106879
Simon Pilgrim [Mon, 2 Aug 2021 10:42:10 +0000 (11:42 +0100)]
[CostModel] Treat 'widen subvector' patterns as zero cost
As discussed on D107228, widening a subvector by inserting the whole subvector into the bottom a larger undef vector should always be cheap enough that we can treat it as zero cost.
NOTE: If this proves to cause issues we have the option of introducing a "SK_WidenSubvector" shuffle kind enum that targets could override the zero cost, but that doesn't seem necessary atm.
Differential Revision: https://reviews.llvm.org/D107228
Florian Mayer [Mon, 2 Aug 2021 07:58:49 +0000 (08:58 +0100)]
[hwasan] Detect use after scope within function.
Reviewed By: vitalybuka
Differential Revision: https://reviews.llvm.org/D105201
Simon Pilgrim [Mon, 2 Aug 2021 10:21:42 +0000 (11:21 +0100)]
[TTI] Add basic SK_InsertSubvector shuffle mask recognition
This patch adds an initial ShuffleVectorInst::isInsertSubvectorMask helper to recognize 2-op shuffles where the lowest elements of one of the sources are being inserted into the "in-place" other operand, this includes "concat_vectors" patterns as can be seen in the Arm shuffle cost changes. This also helped fix a x86 issue with irregular/length-changing SK_InsertSubvector costs - I'm hoping this will help with D107188
This doesn't currently attempt to work with 1-op shuffles that could either be a "widening" shuffle or a self-insertion.
The self-insertion case is tricky, but we currently always match this with the existing SK_PermuteSingleSrc logic.
The widening case will be addressed in a follow up patch that treats the cost as 0.
Masks with a high number of undef elts will still struggle to match optimal subvector widths - its currently bounded by minimum-width possible insertion, whilst some cases would benefit from wider (pow2?) subvectors.
Differential Revision: https://reviews.llvm.org/D107228
Simon Pilgrim [Sat, 31 Jul 2021 17:47:53 +0000 (18:47 +0100)]
Fix MSVC signed/unsigned comparison warning. NFCI.
Rosie Sumpter [Fri, 30 Jul 2021 09:51:09 +0000 (10:51 +0100)]
[LoopFlatten] Fix missed LoopFlatten opportunity
When the limit of the inner loop is a known integer, the InstCombine
pass now causes the transformation e.g. imcp ult i32 %inc, tripcount ->
icmp ult %j, tripcount-step (where %j is the inner loop induction
variable and %inc is add %j, step), which is now accounted for when
identifying the trip count of the loop. This is also an acceptable use
of %j (provided the step is 1) so is ignored as long as the compare
that it's used in is also the condition of the inner branch.
Differential Revision: https://reviews.llvm.org/D105802
Andrzej Warzynski [Thu, 29 Jul 2021 12:39:10 +0000 (12:39 +0000)]
[flang][nfc] Fix variable names in `FrontendOptions` & `PreprocessorOptions`
As all member variables in `FrontendOptions` and `PreprocessorOptions`
are public, we should be naming them as `variable` rather than
`variable_` [1]. This patch fixes that.
Also, `FrontendOptions` & `PreprocessorOptions` are re-defined as a
structs rather than classes (all fields are meant to be public).
[1]
https://github.com/llvm/llvm-project/blob/main/flang/docs/C%2B%2Bstyle.md#naming
Differential Revision: https://reviews.llvm.org/D107062
David Green [Mon, 2 Aug 2021 09:59:52 +0000 (10:59 +0100)]
[ARM] Revert WLSTP to DLSTP if the target block is out of range
If the block target for a WLSTP instruction is known to be out of range,
and cannot be fixed by the ARMBlockPlacementPass, we can relax it to a
DLSTP (and cmp/branch) to still allow the creation of tail predicated
loops. That is what this patch does, adding extra revert code to the
fallback path of ARMBlockPlacementPass.
Due to the code produced when reverting, this creates a DLSTP between a
Bcc and a Br. As a DLS isn't necessarily a terminator we need to split
the block to move the DLS/Br into.
Differential Revision: https://reviews.llvm.org/D104709
Alex Zinenko [Mon, 2 Aug 2021 09:47:29 +0000 (11:47 +0200)]
[OpenMPIRBuilder] Add a constructor to ReductionInfo to appease gcc5
Otherwise, it produces wrong code for brace initializers.
Cullen Rhodes [Mon, 2 Aug 2021 08:30:55 +0000 (08:30 +0000)]
[AArch64][AsmParser] NFC: Parser.Lex() -> Lex()
Reviewed By: tmatheson
Differential Revision: https://reviews.llvm.org/D107146
Andy Yankovsky [Mon, 26 Jul 2021 14:36:51 +0000 (16:36 +0200)]
[clang-tidy] Always open files using UTF-8 encoding
The encoding used for opening files depends on the OS and might be different
from UTF-8 (e.g. on Windows it can be CP-1252). The documentation files use
UTF-8 and might be incompatible with other encodings. For example, right now
`clang-tools-extra/docs/clang-tidy/checks/abseil-no-internal-dependencies.rst`
has non-ASCII quotes and running `add_new_check.py` fails on Windows, because
it tries to read the file with incompatible encoding.
Use `io.open` for compatibility with both Python 2 and Python 3.
Reviewed By: kbobyrev
Differential Revision: https://reviews.llvm.org/D106792
Dmitry Vyukov [Sat, 31 Jul 2021 07:51:57 +0000 (09:51 +0200)]
tsan: minor IgnoreSet refactoring
1. Move kMaxSize declaration to private section.
2. Inline Reset, it's trivial and called semi-frequently.
Reviewed By: melver
Differential Revision: https://reviews.llvm.org/D107215
Dmitry Vyukov [Sat, 31 Jul 2021 09:43:32 +0000 (11:43 +0200)]
tsan: inline ProcessPendingSignals check
ProcessPendingSignals is called in all interceptors
and user atomic operations. Make the fast-path check
(no pending signals) inlinable.
Reviewed By: melver
Differential Revision: https://reviews.llvm.org/D107217
Matthias Springer [Mon, 2 Aug 2021 08:52:48 +0000 (17:52 +0900)]
[mlir][linalg] Fix comments around ConstraintsSet
Differential Revision: https://reviews.llvm.org/D107018
David Spickett [Fri, 30 Jul 2021 15:36:33 +0000 (16:36 +0100)]
Revert "[libcxx][CI] Work around Arm buildkite failures"
This reverts commit
f8bef4734845226c079900de3c273c8ab1915b49.
Buildkite agent 3.32.0 includes a fix for the PATH issue.
https://github.com/buildkite/agent/releases/tag/v3.32.0
Differential Revision: https://reviews.llvm.org/D107172
Butygin [Wed, 28 Jul 2021 19:31:26 +0000 (22:31 +0300)]
[mlir] Remove invalid DeallocOpLowering pattern insertion
It is inserted later under then condition.
Differential Revision: https://reviews.llvm.org/D107238
David Green [Mon, 2 Aug 2021 08:03:22 +0000 (09:03 +0100)]
[ARM] Add trackLiveness to block-placement.mir. NFC
Also move the test to mve-wls-block-placement.mir, to better fit what it
tests.
Max Kazantsev [Mon, 2 Aug 2021 05:00:56 +0000 (12:00 +0700)]
[GC][NFC] Make getGCStrategy by name available in IR
We might want to use info from GC strategy in middle end analysis.
The motivation for this is provided in D99135: we may want to ask
a GC if it's going to work with a given pointer (currently this code
makes naive check by the method name).
Differetial Revision: https://reviews.llvm.org/D100559
Reviewed By: reames
Kirill Bobyrev [Mon, 2 Aug 2021 07:08:09 +0000 (09:08 +0200)]
[clangd] Fix the crash in getQualification
Happens when DestContext is LinkageSpecDecl and hense CurContext happens to be
both not TagDecl and NamespaceDecl.
Minimal reproducer: trigger define outline in
```
namespace ns {
extern "C" {
typedef int foo;
}
foo Fo^o(int id) { return id; }
}
```
Reviewed By: kadircet
Differential Revision: https://reviews.llvm.org/D107047
Alina Sbirlea [Mon, 2 Aug 2021 06:48:25 +0000 (23:48 -0700)]
[docs]Update meeeting frequency to match new cal entry
Lang Hames [Mon, 2 Aug 2021 05:15:15 +0000 (15:15 +1000)]
[examples] Fix incomplete_type on ZLinux when compiling RemoteJITUtils.
When compiling on ZLinux, we got this error:
/llvm-project/llvm/examples/OrcV2Examples/LLJITWithRemoteDebugging/ \
RemoteJITUtils.h:80:65: required from here...
/usr/include/c++/7/bits/unique_ptr.h:76:22: error: invalid application of
'sizeof' to incomplete type 'llvm::orc::RemoteExecutorProcessControl'
static_assert(sizeof(_Tp)>0,
This patch just removes nullptr from the initialization of
std::unique_ptr<RemoteExecutorProcessControl> to avoid the issue.
Patch by Tung D. Le (tung@jp.ibm.com). Thanks Tung!
Reviewed By: lhames
Differential Revision: https://reviews.llvm.org/D107247
Carl Ritson [Mon, 2 Aug 2021 02:46:09 +0000 (11:46 +0900)]
[AMDGPU][GlobalISel] Add missing default mapping for BVH intrinsics
Application of default mapping to BVH intrinsics was missing.
Copy parts of SelectionDAG test to GlobalISel test as these would
have indicated this error.
Reviewed By: arsenm
Differential Revision: https://reviews.llvm.org/D107211
Freddy Ye [Mon, 2 Aug 2021 00:56:36 +0000 (08:56 +0800)]
[X86] Support auto-detect for tigerlake and alderlake
Differential Revision: https://reviews.llvm.org/D107245
Muhammad Omair Javaid [Mon, 2 Aug 2021 01:31:52 +0000 (06:31 +0500)]
[LLDB] Change pexpect timeout to 30 to 60
Test dependent on pexpect fail randomly with timeouts on Arm/AArch64 Linux
buildbots. I am setting pexpect timeout from 30 to 60.
I will revert this back if this doesnt improve random failures.
Muhammad Omair Javaid [Mon, 2 Aug 2021 00:15:59 +0000 (05:15 +0500)]
Revert "Revert "[LLDB][GUI] Expand selected thread tree item by default""
This reverts commit
fd18f0e84cca023df6cb19e88c07c0e2059f659b.
I reverted this change to see its effect on failing GUI tests on LLDB
Arm/AArch64 Linux buildbots. I could not find any evidence against this
particular change so reverting it back.
Differential Revision: https://reviews.llvm.org/D100243
Muhammad Omair Javaid [Mon, 2 Aug 2021 00:20:19 +0000 (05:20 +0500)]
[LLDB] Skip random failing tests on Arm/AArch64 Linux bots
Following tests have been failing randomly on LLDB Arm and AArch64 Linux
builtbots:
TestMultilineNavigation.py
TestMultilineCompletion.py
TestIOHandlerCompletion.py
TestGuiBasic.py
I have increased allocated CPU resources to these bots but it has not
improved situation to an acceptable level. This patch marks them as
skipped on Arm/AArch64 for now.
Michael Kruse [Sun, 1 Aug 2021 23:50:40 +0000 (18:50 -0500)]
[Preprocessor] Ensure newline after #pragma introduced by -fms-extensions.
The -fms-extensions converts __pragma (and _Pragma) into a #pragma that
has to occur at the beginning of a line and end with a newline. This
patch ensures that the newline after the #pragma is added even if
Token::isAtStartOfLine() indicated that we should not start a newline.
Committing relying post-commit review since the change is small, some
downstream uses might be blocked without this fix, and to make clear the
decision of the new -fminimize-whitespace feature (fix on main, revert
on clang-13.x branch) suggested by @aaron.ballman in D104601.
Differential Revision: https://reviews.llvm.org/D107183
Douglas Chen [Sun, 1 Aug 2021 22:20:12 +0000 (15:20 -0700)]
[clang-tidy] Add new case type to check variables with Hungarian notation
Add IdentifierNamingCheck::CaseType, CT_HungarianNotation, supporting
naming check with Hungarian notation.
Differential Revision: https://reviews.llvm.org/D86671
Mateusz Mikuła [Sun, 1 Aug 2021 20:26:25 +0000 (23:26 +0300)]
[LLD][MinGW] Accept joined format for --stack
Postgresql uses `--stack=` in its Makefile.
Downstream issue: https://github.com/msys2/MINGW-packages/pull/9167
Reviewed By: mstorsjo
Differential Revision: https://reviews.llvm.org/D107237
Martin Storsjö [Sat, 31 Jul 2021 19:58:29 +0000 (22:58 +0300)]
[clang-repl] Fix building with win32 dylibs
Use `clang_target_link_libraries` to avoid duplicate libraries when
the same symbol is provided both by a static library and a larger
dylib, fixing linking with win32 dylibs. This fixes errors like
these:
ld.lld: error: duplicate symbol: llvm::createStringError(std::__1::error_code, char const*)
>>> defined at libLLVMSupport.a(Error.cpp.obj)
>>> defined at libLLVM-14git.dll
This matches how other clang tools declare their dependencies.
Differential Revision: https://reviews.llvm.org/D107231
Dave Lee [Fri, 16 Jul 2021 18:04:27 +0000 (11:04 -0700)]
[lldb] Avoid moving ThreadPlanSP from plans vector
Change `ThreadPlanStack::PopPlan` and `::DiscardPlan` to not do the following:
1. Move the last plan, leaving a moved `ThreadPlanSP` in the plans vector
2. Operate on the last plan
3. Pop the last plan off the plans vector
This leaves a period of time where the last element in the plans vector has been moved. I am not sure what, if any, guarantees there are when doing this, but it seems like it would/could leave a null `ThreadPlanSP` in the container. There are asserts in place to prevent empty/null `ThreadPlanSP` instances from being pushed on to the stack, and so this could break that invariant during multithreaded access to the thread plan stack.
An open question is whether this use of `std::move` was the result of a measure performance problem.
Differential Revision: https://reviews.llvm.org/D106171
Krishna [Sun, 1 Aug 2021 13:22:37 +0000 (18:52 +0530)]
[InstCombine] Precommit tests for D106872 (NFC)
Kazu Hirata [Sun, 1 Aug 2021 14:53:16 +0000 (07:53 -0700)]
[Analysis] Remove unused declaration isGEPBaseAtNegativeOffset (NFC)
The corresponding function definition was removed on Mar 3, 2021 in
commit
ea7d208b780657c236986d7dfd7ba577583fd99a.
Markus Böck [Sun, 1 Aug 2021 12:01:20 +0000 (14:01 +0200)]
[mlir] Change ABI breaking use of NDEBUG to LLVM_ENABLE_ABI_BREAKING_CHECKS
The `DataLayout` class currently contains the member `layoutStack` which is hidden behind a preprocessor region dependant on the NDEBUG macro. Code wise this makes a lot of sense, as the `layoutStack` is used for extra assertions that users will want when compiling a debug build.
It however has the uncomfortable consequence of leading to a different ABI in Debug and Release builds. This I think is a bit annoying for downstream projects and others as they may want to build against a stable Release of MLIR in Release mode, but be able to debug their own project depending on MLIR.
This patch changes the related uses of NDEBUG to LLVM_ENABLE_ABI_BREAKING_CHECKS. As the macro is computed at configure time of LLVM, it may not change based on compiler settings of a downstream projects like NDEBUG would.
Differential Revision: https://reviews.llvm.org/D107227
Butygin [Wed, 28 Jul 2021 19:31:26 +0000 (22:31 +0300)]
[mlir] Add populateGpuToLLVMConversionPatterns function
Differential Revision: https://reviews.llvm.org/D107218
Tommy Chiang [Sun, 1 Aug 2021 08:50:00 +0000 (16:50 +0800)]
[docs] Update outdated doxygen download link
Fangrui Song [Sun, 1 Aug 2021 01:57:19 +0000 (18:57 -0700)]
[ELF][test] Improve .symver & --version-script tests
And delete redundant tests.
Craig Topper [Sat, 31 Jul 2021 22:44:39 +0000 (15:44 -0700)]
[RISCV] Add some tests for SimplifyCFG's switch to lookup table transform
These are some of the basic cases taken from X86.
We currently fail to use lookup tables on many of these cases
because SimplifyCFG requires a legal type to do the transform and
RISCV only has one legal integer type.
Shimin Cui [Sat, 31 Jul 2021 22:42:02 +0000 (18:42 -0400)]
[GlobalOpt] support ConstantExpr use of global address for OptimizeGlobalAddressOfMalloc
I'm working on extending the OptimizeGlobalAddressOfMalloc to handle some more general cases. This is to add support of the ConstantExpr use of the global variables. The function allUsesOfLoadedValueWillTrapIfNull is now iterative with the added CE use of GV. Also, the recursive function valueIsOnlyUsedLocallyOrStoredToOneGlobal is changed to iterative using a worklist with the GEP case added.
Reviewed By: efriedma
Differential Revision: https://reviews.llvm.org/D106589
Jan Kratochvil [Sat, 31 Jul 2021 22:37:10 +0000 (00:37 +0200)]
[nfc] [lldb] Removed unused DWARFDebugInfo::GetDIEForDIEOffset
Its last use was removed by D63428.
Hsiangkai Wang [Fri, 23 Jul 2021 03:26:58 +0000 (11:26 +0800)]
[RISCV][Docs] Add description about inline asm constraint for V.
Add inline asm constraint 'vr' for vector registers and 'vm' for vector
mask registers.
Differential Revision: https://reviews.llvm.org/D106633
Hsiangkai Wang [Fri, 30 Jul 2021 09:10:30 +0000 (17:10 +0800)]
[RISCV] Rename vector inline constraint from 'v' to 'vr' and 'vm' in IR.
Differential Revision: https://reviews.llvm.org/D107139
Eli Friedman [Sat, 31 Jul 2021 21:09:59 +0000 (14:09 -0700)]
Fix the default alignment of i1 vectors.
Currently, the default alignment is much larger than the actual size of
the vector in memory. Fix this to use a sane default.
For SVE, temporarily remove lowering of load/store operations for
predicates with less than 16 elements. The layout the backend was
assuming for SVE predicates with less than 16 elements doesn't agree
with the frontend. More work probably needs to be done here.
This change is, strictly speaking, not backwards-compatible at the
bitcode level. But probably nobody is actually depending on that; i1
vectors in memory are rare, and the code that does use them probably
ends up forcing the alignment to something sane anyway. If we think
this is a concern, I can restrict this to scalable vectors for now
(where it's actually causing issues for me at the moment).
Differential Revision: https://reviews.llvm.org/D88994
Eli Friedman [Sat, 31 Jul 2021 20:41:15 +0000 (13:41 -0700)]
Fix a couple regression tests I missed updating in
2a284782
Eli Friedman [Sat, 31 Jul 2021 20:20:47 +0000 (13:20 -0700)]
[ConstantFold] Get rid of special cases for sizeof etc.
Target-dependent constant folding will fold these down to simple
constants (or at least, expressions that don't involve a GEP). We don't
need heroics to try to optimize the form of the expression before that
happens.
Fixes https://bugs.llvm.org/show_bug.cgi?id=51232 .
Differential Revision: https://reviews.llvm.org/D107116
Aart Bik [Sat, 31 Jul 2021 00:52:39 +0000 (17:52 -0700)]
[mlir][sparse] add sparse tensor type conversion operation
Introduces a conversion from one (sparse) tensor type to another
(sparse) tensor type. See the operation doc for details. Actual
codegen for all cases is still TBD.
Reviewed By: ThomasRaoux
Differential Revision: https://reviews.llvm.org/D107205
Sanjay Patel [Sat, 31 Jul 2021 19:13:42 +0000 (15:13 -0400)]
[Analysis] improve function signature checking for snprintf
The check for size_t parameter 1 was already here for snprintf_chk,
but it wasn't applied to regular snprintf. This could lead to
mismatching and eventually crashing as shown in:
https://llvm.org/PR50885
Craig Topper [Sat, 31 Jul 2021 18:05:55 +0000 (11:05 -0700)]
[RISCV] Rename RISCVISD::FCVT_W_RV64 to FCVT_W_RTZ_RV64. NFC
fcvt.w(u) supports multiple rounding modes, but the ISD node
doesn't encode that. So name it to match the rounding mode it uses.
Sanjay Patel [Sat, 31 Jul 2021 18:07:30 +0000 (14:07 -0400)]
[SROA] prevent crash on large memset length (PR50910)
I don't know much about this pass, but we need a stronger
check on the memset length arg to avoid an assert. The
current code was added with D59000.
The test is reduced from:
https://llvm.org/PR50910
Differential Revision: https://reviews.llvm.org/D106462
Sanjay Patel [Sat, 31 Jul 2021 17:16:25 +0000 (13:16 -0400)]
[InstCombine] canonicalize cmp-of-bitcast-of-vector-cmp to use zero constant
We can invert a compare constant and preserve the logic
as shown in this sampling:
https://alive2.llvm.org/ce/z/YAXbfs
(In theory, we could deal with non-all-ones/zero as well,
but it doesn't seem worthwhile.)
I noticed this as a part of the x86 codegen difference in
https://llvm.org/PR51259 - it ends up using "test"
instead of "not + cmp" in that example.
This pattern also shows up in https://llvm.org/PR41312
and https://llvm.org/PR50798 .
Differential Revision: https://reviews.llvm.org/D107170
Simon Pilgrim [Sat, 31 Jul 2021 17:05:13 +0000 (18:05 +0100)]
[TTI] Make SK_ExtractSubvector matching length-changing only and simplify nested shuffle mask detection chain.
Match style and don't use an else after a return.
Minor cleanup for an upcoming SK_InsertSubvector patch.
pooja2299 [Sat, 31 Jul 2021 07:50:43 +0000 (13:20 +0530)]
Fixed syntax error that occured in the patch D104974
David Green [Sat, 31 Jul 2021 15:28:52 +0000 (16:28 +0100)]
[ARM] Switch order of creating VADDV and VMLAV.
It can be beneficial to attempt to try the larger VMLAV patterns before
VADDV, in case both may match the same code.
David Green [Sat, 31 Jul 2021 10:02:52 +0000 (11:02 +0100)]
[ARM] Regenerate Thumb PR35481.ll test. NFC
Florian Hahn [Sat, 31 Jul 2021 14:59:49 +0000 (15:59 +0100)]
[VPlan] Add interleave group printing test.
Matt Arsenault [Tue, 27 Jul 2021 15:08:06 +0000 (11:08 -0400)]
GlobalISel: Scalarize unaligned vector stores
This has the same problems and limitations as the load path.
Matt Arsenault [Tue, 27 Jul 2021 21:47:31 +0000 (17:47 -0400)]
AMDGPU/GlobalISel: Check some remarks for failed legalizations
The load/store tests are giant and have some cases that fail in them,
but it's hard to tell which ones are really failing. Check the remarks
to make it easier to track.
Kazu Hirata [Sat, 31 Jul 2021 14:24:53 +0000 (07:24 -0700)]
[ADT] Remove set_is_strict_subset (NFC)
The last use was removed on Mar 13, 2020 in commit
6b57d7f57d2cec7ec717757a6a52f2203d6e9db7.
Simon Pilgrim [Sat, 31 Jul 2021 14:08:13 +0000 (15:08 +0100)]
[DAG] isGuaranteedNotToBeUndefOrPoison - handle ISD::BUILD_VECTOR nodes
If all demanded elements of the BUILD_VECTOR pass a isGuaranteedNotToBeUndefOrPoison check, then we can treat this specific demanded use of the BUILD_VECTOR as guaranteed not to be undef or poison either.
Differential Revision: https://reviews.llvm.org/D107174
Matt Arsenault [Mon, 26 Jul 2021 23:41:48 +0000 (19:41 -0400)]
GlobalISel: Have lowerStore handle some unaligned stores
This is NFC until some of the AMDGPU legalization rules are ripped
out.
Uday Bondhugula [Fri, 30 Jul 2021 09:47:43 +0000 (15:17 +0530)]
[MLIR] NFC Clean up doc comments on memref replacement utility
NFC. Clean up stale doc comments on memref replacement utility and some
variable renaming in it to avoid confusion.
Differential Revision: https://reviews.llvm.org/D107144
Alexandros Lamprineas [Sat, 31 Jul 2021 07:59:19 +0000 (08:59 +0100)]
[AArch64] Legalize MVT::i64x8 in DAG isel lowering
This patch legalizes the Machine Value Type introduced in D94096 for loads
and stores. A new target hook named getAsmOperandValueType() is added which
maps i512 to MVT::i64x8. GlobalISel falls back to DAG for legalization.
Differential Revision: https://reviews.llvm.org/D94097
Alexandros Lamprineas [Sat, 31 Jul 2021 07:46:20 +0000 (08:46 +0100)]
[AArch64] Add a Machine Value Type for 8 consecutive registers
Adds MVT::i64x8, a Machine Value Type needed for lowering inline assembly
operands which materialize a sequence of eight general purpose registers.
Differential Revision: https://reviews.llvm.org/D94096
Alexandros Lamprineas [Wed, 28 Jul 2021 15:40:59 +0000 (16:40 +0100)]
[Clang][AArch64] Inline assembly support for the ACLE type 'data512_t'
In LLVM IR terms the ACLE type 'data512_t' is essentially an aggregate
type { [8 x i64] }. When emitting code for inline assembly operands,
clang tries to scalarize aggregate types to an integer of the equivalent
length, otherwise it passes them by-reference. This patch adds a target
hook to tell whether a given inline assembly operand is scalarizable
so that clang can emit code to pass/return it by-value.
Differential Revision: https://reviews.llvm.org/D94098
Eric Leese [Fri, 30 Jul 2021 11:08:00 +0000 (13:08 +0200)]
[lldb] [DWARF-5] Be lazier about loading .dwo files
This change makes sure that DwarfUnit does not load a .dwo file until
necessary. I also take advantage of DWARF 5's guarantee that the first
support file is also the primary file to make it possible to create
a compile unit without loading the .dwo file.
Testcases now require Linux as it is needed for -gsplit-dwarf.
Review By: jankratochvil, dblaikie
Differential Revision: https://reviews.llvm.org/D100299
Fangrui Song [Sat, 31 Jul 2021 07:36:16 +0000 (00:36 -0700)]
[profile][test] Delete --path-equivalence=/tmp,%S
This causes the test to fail if %S is under /tmp
Dmitry Vyukov [Sat, 31 Jul 2021 07:09:01 +0000 (09:09 +0200)]
tsan: prevent insertion of memset into BenignRaceImpl
Some bots started failing with the following error
after changing Alloc to New. Change it back.
ThreadSanitizer: CHECK failed: ((locked[i].recursion)) == ((0))
4 __sanitizer::CheckedMutex::CheckNoLocks()
5 __tsan::ScopedInterceptor::~ScopedInterceptor()
6 memset
7 __tsan::New<__tsan::ExpectRace>()
8 __tsan::AddExpectRace()
9 BenignRaceImpl()
Differential Revision: https://reviews.llvm.org/D107212
Dmitry Vyukov [Fri, 30 Jul 2021 11:50:15 +0000 (13:50 +0200)]
tsan: introduce Tid and StackID typedefs
Currently we inconsistently use u32 and int for thread ids,
there are also "unique tid" and "os tid" and just lots of other
things identified by integers.
Additionally new tsan runtime will introduce yet another
thread identifier that is very different from current tids.
Similarly for stack IDs, it's easy to confuse u32 with other
integer identifiers. And when a function accepts u32 or a struct
contains u32 field, it's not always clear what it is.
Add Tid and StackID typedefs to make it clear what is what.
Reviewed By: melver
Differential Revision: https://reviews.llvm.org/D107152
Dmitry Vyukov [Fri, 30 Jul 2021 14:56:36 +0000 (16:56 +0200)]
sanitizers: build tests with -g
We currently build tests without -g, which is quite inconvenient.
Crash stacks don't have line numbers, gdb don't how line numbers either.
Always build tests with -g.
Reviewed By: vitalybuka
Differential Revision: https://reviews.llvm.org/D107168
Dmitry Vyukov [Fri, 30 Jul 2021 16:05:47 +0000 (18:05 +0200)]
tsan: remove "expected" races
"Expected" races is a very ancient facility used in tsanv1 tests.
It's not used/needed anymore. Remove it.
Reviewed By: vitalybuka
Differential Revision: https://reviews.llvm.org/D107175
Dmitry Vyukov [Fri, 30 Jul 2021 17:52:48 +0000 (19:52 +0200)]
tsan: always setup sigaction signal handler
Currently we setup either sigaction signal handler with 3 arguments
or old style signal handler with 1 argument depending on user handler type.
This unnecessarily complicates code. Always setup sigaction handler.
Reviewed By: vitalybuka
Differential Revision: https://reviews.llvm.org/D107186
Vitaly Buka [Sat, 31 Jul 2021 02:24:45 +0000 (19:24 -0700)]
[NFC][sanitizer] clang-format few files
Petr Hosek [Sat, 31 Jul 2021 01:56:51 +0000 (18:56 -0700)]
Revert "[clang][cache] Update Fuchsia-stage2.cmake to create hwasan multilibs"
This reverts commit
bb438f6cbfc08eaa2cd9124a0ad581dd29f819b4 since
it broke our Windows builders and we need more time to investigate
the issue.
Petr Hosek [Fri, 30 Jul 2021 09:40:27 +0000 (02:40 -0700)]
[profile] Fix profile merging with binary IDs
This fixes support for merging profiles which broke as a consequence
of
e50a38840dc3db5813f74b1cd2e10e6d984d0e67. The issue was missing
adjustment in merge logic to account for the binary IDs which are
now included in the raw profile just after header.
In addition, this change also:
* Includes the version in module signature that's used for merging
to avoid accidental attempts to merge incompatible profiles.
* Moves the binary IDs size field after version field in the header
as was suggested in the review.
Differential Revision: https://reviews.llvm.org/D107143
Petr Hosek [Sat, 31 Jul 2021 01:53:48 +0000 (18:53 -0700)]
Revert "[profile] Fix profile merging with binary IDs"
This reverts commit
dcadd64986b8a84dc244d4e7faa848fb4c18cea6.