Simon Glass [Tue, 4 Aug 2015 18:33:48 +0000 (12:33 -0600)]
x86: dts: Add a device tree file for EFI
This contains just enough to bring up the serial UART.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Ben Stoltz [Tue, 4 Aug 2015 18:33:47 +0000 (12:33 -0600)]
x86: Add EFI board code
Add support for the efi-x86 board, which supports running U-Boot as an
EFI 32-bit application.
Signed-off-by: Ben Stoltz <stoltz@google.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Ben Stoltz [Tue, 4 Aug 2015 18:33:46 +0000 (12:33 -0600)]
x86: Add support for U-Boot as an EFI application
Add the required x86 glue code. This includes the initial start-up,
relocation and jumping to efi_main(). We also need to avoid fiddling with
interrupts.
Signed-off-by: Ben Stoltz <stoltz@google.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Tue, 4 Aug 2015 18:33:45 +0000 (12:33 -0600)]
x86: Add asm/elf.h for x86-specific ELF definitions
Bring in this file from Linux 4.1. It supports relocation features specific
to x86.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Tue, 4 Aug 2015 18:33:44 +0000 (12:33 -0600)]
x86: Support skipping relocation for EFI
When running as an EFI application we must skip relocation. Add support for
this in the x86 relocation code.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Tue, 4 Aug 2015 18:33:43 +0000 (12:33 -0600)]
efi: Support building a u-boot-app.efi executable
Add support for building U-Boot as an EFI application with a .efi suffix.
This can be loaded by EFI provided that EFI has the same bit width (32-
or 64-bit) as U-Boot. This unfortunate limitation is imposed by EFI.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Ben Stoltz [Tue, 4 Aug 2015 18:33:42 +0000 (12:33 -0600)]
x86: Set up toolchain flags for running as EFI application
Adjust the toolchain flags to build U-Boot as a relocatable shared library,
as required by EFI.
Signed-off-by: Ben Stoltz <stoltz@google.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Ben Stoltz [Tue, 4 Aug 2015 18:33:41 +0000 (12:33 -0600)]
efi: Drop CONFIG_SYS_TEXT_BASE for EFI
When U-Boot runs as an EFI application is does not have a definition of
CONFIG_SYS_TEXT_BASE. U-Boot is a relocatable application and the relocation
is done by EFI. U-Boot can be loaded at any address.
Ensure that this CONFIG option is not set in this case.
Signed-off-by: Ben Stoltz <stoltz@google.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Tue, 4 Aug 2015 18:33:40 +0000 (12:33 -0600)]
efi: Add a serial driver
Add a serial driver which makes use of EFI's console in/out service.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested on Intel Crown Bay and QEMU
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Tue, 4 Aug 2015 18:33:39 +0000 (12:33 -0600)]
Add a way to skip relocation
When running U-Boot as an EFI application we cannot relocate since we do not
have relocation information. U-Boot has already been relocated to a suitable
address.
Add a global_data flag to control skipping relocation.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Mon, 27 Jul 2015 21:47:31 +0000 (15:47 -0600)]
x86: Update README to explain booting Ubuntu on Minnowmax
The steps required to boot a Linux distribution from U-Boot on x86 are not
very complicated, but it is a good idea to have these written down in an
accessible place.
Document how to examine the boot media from U-Boot, how to load a kernel,
load a ramdisk, set the kernel boot arguments and start the kernel. With
these instructions Ubuntu boots mostly normally on Minnowmax.
Note that the TSC timer does not operate correctly and gives warnings in
the boot log. I expect that ACPI support will solve this.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Mon, 27 Jul 2015 21:47:29 +0000 (15:47 -0600)]
x86: minnowmax: Drop the old PCI settings
These are now in the device tree so we don't need to use the CONFIG options.
Drop them.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Mon, 27 Jul 2015 21:47:26 +0000 (15:47 -0600)]
x86: dts: Fix typo in intel,irq-router.txt
Fix a small typo in this binding file.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Mon, 27 Jul 2015 21:47:25 +0000 (15:47 -0600)]
x86: Drop CONFIG_DCACHE_RAM_MRC_VAR_SIZE from header file
This is provided in Kconfig so we don't need it here.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Mon, 27 Jul 2015 21:47:23 +0000 (15:47 -0600)]
x86: Move CONFIG_X86_SERIAL to Kconfig
Move this config option to Kconfig and tidy up.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Mon, 27 Jul 2015 21:47:22 +0000 (15:47 -0600)]
x86: Move Chrome OS options to defconfig
Drop these from the header file and use Kconfig instead.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Mon, 27 Jul 2015 21:47:19 +0000 (15:47 -0600)]
dm: Add a return value comment to device_get_child()
At present this function does not specify its return value. Fix it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Mon, 27 Jul 2015 21:47:18 +0000 (15:47 -0600)]
pci: Indicate prefetchable memory allocate when debugging
At present the PCI output displays 'Mem' when it allocates memory for a PCI
device, whether it is prefetchable or not. There is a distinction since the
memory comes from separate pools. Use 'Prf' instead of 'Mem' when allocating
prefetchable memory.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Mon, 27 Jul 2015 21:47:17 +0000 (15:47 -0600)]
pci: Add a constant for an invalid interrupt
Rather than using 0xff in the code, add a constant.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Fri, 31 Jul 2015 15:31:38 +0000 (09:31 -0600)]
efi: Display the correct initcall pre-relocation values
With EFI the start address of U-Boot is specified differently. We could
consider just setting GD_FLG_RELOC and then setting up reloc_off. But that
flag has other implementations and we are not able to use U-Boot relocation
which this flag implies.
Instead, just add a special case for EFI.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Ben Stoltz [Fri, 31 Jul 2015 15:31:37 +0000 (09:31 -0600)]
efi: Avoid using non-existent text base
When U-Boot runs as an EFI application is does not have a definition of
CONFIG_SYS_TEXT_BASE. U-Boot is a relocatable application and the relocation
is done by EFI. U-Boot can be loaded at any address.
This is similar to how sandbox works. Adjust the early board init to deal
with this.
Signed-off-by: Ben Stoltz <stoltz@google.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Fri, 31 Jul 2015 15:31:36 +0000 (09:31 -0600)]
efi: Add start-up library code
When running as an EFI application, U-Boot must request memory from EFI,
and provide access to the boot services U-Boot needs.
Add library code to perform these tasks. This includes efi_main() which is
the entry point from EFI. U-Boot is built as a shared library.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Fri, 31 Jul 2015 15:31:35 +0000 (09:31 -0600)]
x86: Allow use of global_data with EFI
On x86 the global_data pointer is provided through a somewhat-bizarre and
x86-specific mechanism: the F segment register is set to a pointer to the
start of global_data, so that accesses can use this build-in register.
When running as an EFI application we don't want to mess with the Global
Descriptor Table (GDT) and there is little advantage (in terms of code size)
to doing so.
Allow global_data to be a simple variable in this case.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Fri, 31 Jul 2015 15:31:34 +0000 (09:31 -0600)]
pci: Fix up code for CONFIG_PCI_ENUM_ONLY
This option is not used by any board but appears to still be useful, at least
for testing. With recent commits it does not build, so fix it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Fri, 31 Jul 2015 15:31:33 +0000 (09:31 -0600)]
pci: Use debug() instead of DEBUGF() in pci_auto.c
This file does not need its own way of doing debug(). Clean it up to use the
new way.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Pavel Machek <pavel@denx.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Fri, 31 Jul 2015 15:31:32 +0000 (09:31 -0600)]
x86: Tidy up a few minor issues with interrupts
Fix a typo, remove an unused field and make sure to use existing #define
constants instead of open-coded values.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Fri, 31 Jul 2015 15:31:31 +0000 (09:31 -0600)]
x86: Add some missing global_data declarations in files that use gd
Some files use global_data but don't declare it. Fix this.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Fri, 31 Jul 2015 15:31:30 +0000 (09:31 -0600)]
x86: Tidy up the 64-bit calling code
The GDT works but technically the length is incorrect. Fix this and add a
comment.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Fri, 31 Jul 2015 15:31:29 +0000 (09:31 -0600)]
x86: Drop unused copy_fdt_to_ram()
This is now handled by generic U-Boot code so we do not need an x86 version.
It is no-longer called, so remove it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Fri, 31 Jul 2015 15:31:28 +0000 (09:31 -0600)]
x86: Tidy up global_data flags
These flags now overlap some global ones. Adjust the x86-specific flags to
avoid this. Since this requires a change to the start.S code, add a way for
tools to find the 32-bit cold reset entry point. Previously this was at a
fixed offset.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Fri, 31 Jul 2015 15:31:27 +0000 (09:31 -0600)]
Reserve the top 16 flag bits for architecture-specific use
Add a convention that the generic global_data only occupy the bottom 16 bits
of the flags word, so that there is less chance of a conflict. At present the
x86 flags conflict.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Fri, 31 Jul 2015 15:31:26 +0000 (09:31 -0600)]
x86: Use CR0 constants in CPU init
We should use these constants where possible.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Fri, 31 Jul 2015 15:31:25 +0000 (09:31 -0600)]
x86: Add various minor tidy-ups to the 32-bit startup code
Fix a typo, improve some comments and add a little more detail in some
cases.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Fri, 31 Jul 2015 15:31:24 +0000 (09:31 -0600)]
Bring in __aligned_u64 and friends to linux/types.h
These will be used for efi.h both for U-Boot running as an EFI application
and as a payload. They come from Linux 4.1.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Fri, 31 Jul 2015 15:31:23 +0000 (09:31 -0600)]
Allow objcopy to work without filling gaps with 0xff
This is currently done for all targets, since 0xff is the default erased
value for most flash devices. In some cases this is not what we want (e.g.
for EFI images) so provide a command to do a vanilla objcopy.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Fri, 31 Jul 2015 15:31:21 +0000 (09:31 -0600)]
elf: Add a few definitions for 64-bit relocation
Provide the types necessary to relocate 64-bit images.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Fri, 31 Jul 2015 15:31:20 +0000 (09:31 -0600)]
dm: serial: Correct logic in serial_find_console_or_panic()
In a final attempt to find a console UART this function uses the first
first available serial device. However the check for a valid device is
inverted.
This code is only executed when there is in fact no serial UART, but at
present it can fail to reach the panic_str() call in this case, and start
trying to use a non-existent UART.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Fri, 31 Jul 2015 15:31:19 +0000 (09:31 -0600)]
dm: core: Check for empty list in uclass_find_device()
This function needs to check the list has entries before traversing it.
Fix this bug.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Fri, 31 Jul 2015 15:31:18 +0000 (09:31 -0600)]
Support removing default assembler flags
The CFLAGS_REMOVE_<file> feature allows default C compiler flags to be
removed for particular files. Add the same feature for assembler, using
AFLAGS_REMOVE_<file>.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Peng Fan [Tue, 28 Jul 2015 14:45:37 +0000 (22:45 +0800)]
common: command add '\n' for debug msg
Add '\n' for debug msg.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Tom Rini <trini@konsulko.com>
Cc: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Simon Glass <sjg@chromium.org>
Acked-by: Simon Glass <sjg@chromium.org>
Masahiro Yamada [Sat, 1 Aug 2015 07:03:25 +0000 (16:03 +0900)]
lib: fdt: fix indent of #ifdef..#endif conditional
Match the depth of indentation between #ifdef and #endif
for better readability.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Fri, 31 Jul 2015 07:24:40 +0000 (00:24 -0700)]
common: Print nothing in the __weak checkboard()
Do not print confusing "Board: Unknown" during boot.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Fri, 31 Jul 2015 07:24:39 +0000 (00:24 -0700)]
gitignore: Add defconfig and fdtgrep
Ignore defconfig and tools/fdtgrep.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Thu, 30 Jul 2015 10:49:18 +0000 (03:49 -0700)]
x86: bayleybay: Configure PCI IRQ
Add PCI IRQ routing information in the board device tree and enable
writing PIRQ routing table and MP table.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Thu, 30 Jul 2015 10:49:17 +0000 (03:49 -0700)]
x86: Add Intel Bayley Bay board support
Intel Bayley Bay board is a BayTrail based board. Add this board
with existing baytrail fsp support.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Thu, 30 Jul 2015 10:49:16 +0000 (03:49 -0700)]
x86: Add microcode for BayTrail-I B0 stepping
This commit adds the microcode blob for BayTrail-I B0 stepping,
CPUID signature 30671h.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Thu, 30 Jul 2015 10:49:15 +0000 (03:49 -0700)]
x86: baytrail: Update UPD setting for FSP Gold4 release
BayTrail FSP Gold4 release adds one UPD parameter to control IGD
enable/disable.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Thu, 30 Jul 2015 10:49:14 +0000 (03:49 -0700)]
x86: minnowmax: Remove smsc47x superio codes
On Intel BayTrail SoC, there is a legacy UART (I/O 0x3f8) integrated
into the SoC which is enabled by the FSP. Remove the smsc47x superio
initialization codes.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Thu, 30 Jul 2015 10:49:13 +0000 (03:49 -0700)]
x86: Sanity test on vesa parameters before setting up kernel screen_info
We should not set up kernel screen_info when the vesa parameters are
insane, otherwise kernel will panic.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Mon, 27 Jul 2015 11:16:08 +0000 (19:16 +0800)]
x86: qemu: Add MP initialization
Add a cpu1 node to the device tree and enable the MP initialization
on QEMU targets (i440fx and q35).
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Miao Yan [Mon, 27 Jul 2015 11:16:07 +0000 (19:16 +0800)]
x86: Add a 'pause' instruction in __udelay() for QEMU target
When running SMP configuration on QEMU (tcg mode, no kvm), there is
a busy loop in start_aps(), calling udelay(), that waits for APs to
show up online. However, there is a chance that VCPU1 will be timeout
waiting, IOW the secondary VCPUs haven't started their execution yet.
This patch adds a 'pause' instruction in __udelay() only for QEMU
target, to give other VCPUs a chance to run. When QEMU sees the
'pause' instruction, it will yeild the execution to other CPUs.
Signed-off-by: Miao Yan <yanmiaobest@gmail.com>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Bin Meng [Mon, 27 Jul 2015 07:33:43 +0000 (00:33 -0700)]
doc: dm: Update pci-info.txt for pci support
Correct two typos and mention how pci bus will be probed.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Mon, 27 Jul 2015 07:33:39 +0000 (00:33 -0700)]
dm: pci: Allow scan bridge child devices before relocation
On some platforms pci devices behind bridge need to be probed (eg:
a pci uart on recent x86 chipset) before relocation. Remove such
limitation so that dm pci can be used before relocation.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tom Rini [Tue, 4 Aug 2015 16:21:45 +0000 (12:21 -0400)]
Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq
Vitaly Andrianov [Mon, 3 Aug 2015 19:54:32 +0000 (15:54 -0400)]
configs: ti_armv7_keystone2: replace addr_uboot with loadaddr
This patch replaces not existing addr_uboot environment variable by
loadaddr at get_uboot_net and burn_uboot_xxx commands. Otherwise these
commands are broken.
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
Acked-by: Nishanth Menon <nm@ti.com>
Nikhil Badola [Fri, 26 Jun 2015 11:32:18 +0000 (17:02 +0530)]
armv8/ls2085ardb: Add USB support for ls2085ardb
Add USB XHCI support for ls2085rdb platform
Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Nikhil Badola [Fri, 26 Jun 2015 11:32:00 +0000 (17:02 +0530)]
armv8/ls2085aqds: Add USB support for ls2085aqds
Add USB XHCI support for ls2085qds platform
Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Nikhil Badola [Fri, 26 Jun 2015 11:31:50 +0000 (17:01 +0530)]
armv8/lsch3/config: Define USB XHCI controller base address for LS2085A
Define base address of both usb xhci controllers in lsch3 config
in the format (IMMR + offset) for LS2085A
Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Nikhil Badola [Fri, 26 Jun 2015 11:29:21 +0000 (16:59 +0530)]
armv8/lsch3/config: Define CONFIG_SYS_CACHELINE_SIZE for LS2085A
Define CONFIG_SYS_CACHELINE_SIZE for LS2085A which is required by
USB XHCI stack for alignment
Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
York Sun [Thu, 23 Jul 2015 21:04:48 +0000 (14:04 -0700)]
drivers/ddr/fsl: Adjust bstopre value
By default the bstopre value has been set to 0x100, used to be 1/4
value of refint. Modern DDR has increased the refresh time. Adjust
to 1/4 of refresh interval dynamically. Individual board can still
override this value in board ddr file, or to use auto-precharge.
Signed-off-by: York Sun <yorksun@freescale.com>
horia.geanta@freescale.com [Wed, 8 Jul 2015 14:24:58 +0000 (17:24 +0300)]
drivers/crypto/fsl: clean-up - use fdt_setprop_u32 helper
Signed-off-by: Horia Geantă <horia.geanta@freescale.com>
Acked-by: Ruchika Gupta<ruchika.gupta@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
horia.geanta@freescale.com [Wed, 8 Jul 2015 14:24:57 +0000 (17:24 +0300)]
drivers/crypto/fsl: fix snooping for write transactions
HW coherency won't work properly for CAAM write transactions
if AWCACHE is left to default (POR) value - 4'b0001.
It has to be programmed to 4'b0010.
For platforms that have HW coherency support:
-PPC-based: the update has no effect; CAAM coherency already works
due to the IOMMU (PAMU) driver setting the correct memory coherency
attributes
-ARM-based: the update fixes cache coherency issues,
since IOMMU (SMMU) driver is not programmed to behave similar to PAMU
Fixes:
b9eebfade974c ("fsl_sec: Add hardware accelerated SHA256 and SHA1")
Signed-off-by: Horia Geantă <horia.geanta@freescale.com>
Reviewed-by: Aneesh Bansal <aneesh.bansal@freescale.com>
Reviewed-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Acked-by: Ruchika Gupta<ruchika.gupta@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
horia.geanta@freescale.com [Wed, 8 Jul 2015 14:24:56 +0000 (17:24 +0300)]
drivers/crypto/fsl: fix "era" property value on LE platforms
Use fdt_setprop_u32() instead of fdt_setprop().
Fixes:
0181937fa371a ("crypto/fsl: Add fixup for crypto node")
Signed-off-by: Horia Geantă <horia.geanta@freescale.com>
Reviewed-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Acked-by: Ruchika Gupta<ruchika.gupta@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Minghuan Lian [Fri, 10 Jul 2015 03:35:09 +0000 (11:35 +0800)]
drivers/pci/layerscape: Add EP mode support
The patch will initialize PCIe controller on EP mode
1. Setup bar:
bar0 32bit 4K for specific configuration
bar1 32bit 8K for MSIX
bar2 64bit 4K for descriptor of memory
bar4 64bit 1M for DMA memory test
2. Setup iATU:
iATU inbound 0-3 to map bar transaction to memory address
started at CONFIG_SYS_PCI_EP_MEMORY_BASE
iATU outbound 0 to map 4G memory space
Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Minghuan Lian [Fri, 10 Jul 2015 03:35:08 +0000 (11:35 +0800)]
drivers/pci: Add function to find an extended capability
PCIe extends device's configuration space to 4k and provides
extended capability. The patch adds function to find them.
The code is ported from Linux PCIe driver.
Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Prabhakar Kushwaha [Tue, 7 Jul 2015 10:10:06 +0000 (15:40 +0530)]
drivers/fsl-mc: flib changes for mc 8.0.0
MC firware version 8.0.0 contains new command flags. This patch
contains modifications in FLIB files to support the new command flags.
Signed-off-by: Itai Katz <itai.katz@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Alex Porosanu [Tue, 5 May 2015 13:48:35 +0000 (16:48 +0300)]
drivers/crypto/fsl: enable raw data instead of von Neumann data
The sampling of the oscillator can be done in multiple modes for
generating the entropy value. By default, this is set to von
Neumann. This patch changes the sampling to raw data, since it
has been discovered that the generated entropy has a better
'quality'.
Signed-off-by: Alex Porosanu <alexandru.porosanu@freescale.com>
Acked-by: Ruchika Gupta<ruchika.gupta@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Alex Porosanu [Tue, 5 May 2015 13:48:34 +0000 (16:48 +0300)]
drivers/crypto/fsl: change starting entropy delay value
The entropy delay (the length in system clocks of each
entropy sample) for the RNG4 block of CAAM is dependent
on the frequency of the SoC. By elaborate methods, it
has been determined that a good starting value for all
platforms integrating the CAAM IP is 3200. Using a
higher value has additional benefit of speeding up
the process of instantiating the RNG, since the entropy
delay will be increased and instantiation of the RNG
state handles will be reattempted by the driver. If the
starting value is low, for certain platforms, this can
lead to a quite lengthy process.
This patch changes the starting value of the length of
the entropy sample to 3200 system clocks.
In addition to this change, the attempted entropy delay
values are now printed on the console upon initialization
of the RNG block.
Signed-off-by: Alex Porosanu <alexandru.porosanu@freescale.com>
Acked-by: Ruchika Gupta<ruchika.gupta@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Alex Porosanu [Tue, 5 May 2015 13:48:33 +0000 (16:48 +0300)]
drivers/crypto/fsl: disable RNG oscillator maximum frequency check
The rtfrqmax & rtfrqmin set the bounds of the expected frequency of the
oscillator, when SEC runs at its maximum frequency. For certain platforms
(f.i. T2080), the oscillator is very fast and thus if the SEC runs at
a lower than normal frequency, the ring oscillator is incorrectly detected
as being out of bounds.
This patch effectively disables the maximum frequency check, by setting a
high enough maximum allowable frequency for the oscillator. The reasoning
behind this is that usually a broken oscillator will run too slow
(i.e. not run at all) rather than run too fast.
Signed-off-by: Alex Porosanu <alexandru.porosanu@freescale.com>
Acked-by: Ruchika Gupta<ruchika.gupta@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Alison Wang [Thu, 9 Jul 2015 03:09:05 +0000 (11:09 +0800)]
armv7/ls1021a/etsec: Enable Tx Data and TxBD snooping
To improve eTSEC performance on LS1021A Rev2.0,
snooping of all transmit frames from memory and
all transmit BD memory accesses in enabled.
Signed-off-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Alison Wang [Thu, 9 Jul 2015 02:50:07 +0000 (10:50 +0800)]
armv7/ls1021a: allow OCRAM access permission as R/W in SPL
On LS1021A Rev2.0, OCRAM's security level needs to be changed to
non-secure access for SD boot. This patch will allow OCRAM
access permission as R/W in SPL.
Signed-off-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Wang Dongsheng [Thu, 18 Jun 2015 10:32:58 +0000 (18:32 +0800)]
armv7/ls102xa: Fix non-boot cpus cannot correctly fall in spin table
Bootrom will put cpus into WFE state when boot cpu release cpus, so
target cpu cannot correctly go to spin state.
Add 'sev' to wakeup non-boot cpu that hold on bootrom space, let target
cpu can fall into u-boot spin table.
Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
chenhui zhao [Fri, 15 May 2015 06:42:30 +0000 (14:42 +0800)]
armv7/ls1021atwr: program the regulator for deep sleep
Program the external regulator to switch off voltage in deep sleep.
Signed-off-by: Chenhui Zhao <chenhui.zhao@freescale.com>
Acked-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Tang Yuantian [Thu, 14 May 2015 09:20:28 +0000 (17:20 +0800)]
armv7/ls1021atwr: added deep sleep support in uboot
Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
Acked-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
gaurav rana [Tue, 12 May 2015 06:55:01 +0000 (12:25 +0530)]
armv7/lS1021atwr: Enable bootscript for secure boot
Enable bootscript support in secure boot for establishing
chain of trust on LS1021atwr.
Signed-off-by: Gaurav Rana <gaurav.rana@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Zhao Qiang [Tue, 5 May 2015 07:53:33 +0000 (15:53 +0800)]
driver/qe: use strncpy instead of strcpy
strncpy is safer than strcpy, use it to instead of strcpy.
Signed-off-by: Zhao Qiang <B45475@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Zhao Qiang [Tue, 5 May 2015 07:53:32 +0000 (15:53 +0800)]
drivers/qe: transform parameter to compatible type
when using printf, the parameter type need to be compatible
type, so transform them to compatible type
Signed-off-by: Zhao Qiang <B45475@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Zhuoyu Zhang [Tue, 24 Mar 2015 09:27:37 +0000 (17:27 +0800)]
armv7/ls1021a: Reserve secure code into RAM instead of OCRAM
For ls1021a, Reserve secure code in to memory in case OCRAM
is needed by other usage.
Signed-off-by: Zhuoyu Zhang <Zhuoyu.Zhang@freescale.com>
Acked-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Tom Rini [Mon, 3 Aug 2015 14:52:14 +0000 (10:52 -0400)]
Prepare v2015.10-rc1
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Sun, 2 Aug 2015 14:27:52 +0000 (10:27 -0400)]
fsl_esdhc.c: Always make check_and_invalidate_dcache_range available
This function is called from esdhc_send_cmd so we need it available to
everyone.
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Sun, 2 Aug 2015 11:40:37 +0000 (07:40 -0400)]
Merge branch 'master' of git://denx.de/git/u-boot-imx
Stefano Babic [Sun, 26 Jul 2015 12:28:25 +0000 (14:28 +0200)]
arm: mx6: tqma6: fix build for WRU-IV baseboard
Fix:
undefined reference to `spi_flash_free'
undefined reference to `spi_flash_probe'
Signed-off-by: Stefano Babic <sbabic@denx.de>
CC: Stefan Roese <sr@denx.de>
Cc: Markus Niebel <Markus.Niebel@tq-group.com>
Acked-by: Stefan Roese <sr@denx.de>
Peng Fan [Mon, 20 Jul 2015 11:28:35 +0000 (19:28 +0800)]
imx: mx6ul_14x14_evk add basic board support
1. Add USDHC, I2C, UART, 74LV, USB, QSPI support.
2. Support SPL
3. CONFIG_MX6UL_14X14_EVK_EMMC_REWORK is introduced, this board default
supports sd for usdhc2, but can do hardware rework to make usdhc2 support
emmc.
Boot Log:
U-Boot SPL 2015.07-rc3-00124-g35d727b (Jul 20 2015 - 18:40:59)
reading u-boot.img
reading u-boot.img
U-Boot 2015.07-rc3-00124-g35d727b (Jul 20 2015 - 18:40:59 +0800)
CPU: Freescale i.MX6UL rev1.0 792 MHz (running at 396 MHz)
CPU: Commercial temperature grade (0C to 95C)CPU: Thermal invalid data, fuse: 0x0
- invalid sensor device
Reset cause: POR
Board: MX6UL 14x14 EVK
I2C: ready
DRAM: 512 MiB
MMC: FSL_SDHC: 0, FSL_SDHC: 1
*** Warning - bad CRC, using default environment
In: serial
Out: serial
Err: serial
Net: CPU Net Initialization Failed
No ethernet found.
Hit any key to stop autoboot: 0
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Peng Fan [Mon, 20 Jul 2015 11:28:34 +0000 (19:28 +0800)]
imx: imx6_spl add mx6ul support
i.MX6UL's DRAM space starts from 0x80000000, same to i.MX6SX, so use
same address with i.MX6SX.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Peng Fan [Mon, 20 Jul 2015 11:28:33 +0000 (19:28 +0800)]
imx:mx6ul add dram spl configuration and header file
1. Define two structures mx6ul_iomux_ddr_regs and mx6ul_iomux_grp_regs.
2. Add a new function mx6ul_dram_iocfg to configure dram io.
3. Refactor MMDC1 macro, discard "#ifdef CONFIG_MX6SX". Since
only mmdc0 channel exists on i.MX6SX/UL, redefine MMDC1 macro support
runtime check, but not hardcoding #ifdef macros.
4. Introduce mx6ul-ddr.h, which includes the register address for DRAM
IO configuration.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Peng Fan [Mon, 20 Jul 2015 11:28:32 +0000 (19:28 +0800)]
mx6_common: Fix LOADADDR and SYS_TEXT_BASE for i.MX6UL
DRAM space starts from 0x80000000 for i.MX6UL, so need to
fix LOADADDR, SYS_TEXT_BASE.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Peng Fan [Mon, 20 Jul 2015 11:28:31 +0000 (19:28 +0800)]
mxc: gpio add i.MX6UL support
i.MX6UL does not have GPIO6/7, so do not include them for i.MX6UL.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Peng Fan [Mon, 20 Jul 2015 11:28:30 +0000 (19:28 +0800)]
imx: mx6 add PAD_CTL_SPEED_LOW for i.MX6SX/UL
PAD_CTL_SPEED_LOW for i.MX6SX/UL is (0 << 6)
Signed-off-by: Ye.Li <B37916@freescale.com>
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Peng Fan [Mon, 20 Jul 2015 11:28:29 +0000 (19:28 +0800)]
imx: mx6ul update soc related settings
1.Update WDOG settings.
2.No need to gate/ungate all PFDs for i.MX6UL.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Signed-off-by: Ye.Li <B37916@freescale.com>
Peng Fan [Mon, 20 Jul 2015 11:28:28 +0000 (19:28 +0800)]
imx: mx6ul select SYS_L2CACHE_OFF
i.MX6UL features an Cortex-A7 core, it does not have PL310 as other i.MX6
chips. To Cortex-A7 core, If D-Cache is enabled, L2 Cache is enabled.
There is on specific switch for on/off L2 Cache, so default select
SYS_L2CACHE_OFF.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Peng Fan [Mon, 20 Jul 2015 11:28:27 +0000 (19:28 +0800)]
imx:mx6ul add clock support
1. Add enet, uart, i2c, ipg clock support for i.MX6UL.
2. Correct get_periph_clk, it should account for
MXC_CCM_CBCDR_PERIPH_CLK2_PODF_MASK.
3. Refactor get_mmdc_ch0_clk to make all i.MX6 share one function,
but not use 'ifdef'.
4. Use CONFIG_FSL_QSPI for enable_qspi_clk, but not #ifdef CONFIG_MX6SX.
5. Use CONFIG_PCIE_IMX for pcie clock settings, use CONFIG_CMD_SATA for
sata clock settings. In this way, we not need "#if defined(CONFIG_MX6Q)
|| defined....", only need one CONFIG_PCIE_IMX in header file.
Signed-off-by: Ye.Li <B37916@freescale.com>
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Peng Fan [Mon, 20 Jul 2015 11:28:26 +0000 (19:28 +0800)]
imx: mx6ul remove errata for i.MX6UL
Since i.MX6UL use A7 core, but not A9 core, we do not need
the erratas for i.MX6UL.
Signed-off-by: Ye.Li <B37916@freescale.com>
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Peng Fan [Mon, 20 Jul 2015 11:28:25 +0000 (19:28 +0800)]
imx-common: timer: add i.MX6UL support
Add i.MX6UL GPT timer support.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Peng Fan [Mon, 20 Jul 2015 11:28:24 +0000 (19:28 +0800)]
imx: mx6ul Add CONFIG_SYS_CACHELINE_SIZE for i.MX6UL
Since i.MX6UL's cache line size is 64bytes, need to
define the macro CONFIG_SYS_CACHELINE_SIZE to 64 for i.MX6UL.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Peng Fan [Mon, 20 Jul 2015 11:28:23 +0000 (19:28 +0800)]
imx: mx6ul: Update imx registers head file
1. Update imx register base address for i.MX6UL.
2. Remove duplicated MXS_APBH/GPMI/BCH_BASE.
3. Remove #ifdef for register addresses that equal to
"AIPS2_OFF_BASE_ADDR + 0x34000" for different chips.
4. According fuse map, complete fuse_bank4_regs.
5. Move AIPS3_ARB_BASE_ADDR and AIPS3_ARB_END_ADDR out of #ifdef CONFIG_MX6SX,
because we can use runtime check
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Peng Fan [Mon, 20 Jul 2015 11:28:22 +0000 (19:28 +0800)]
imx: mx6ul: Add pins IOMUX head file
Add i.MX6UL pins IOMUX file which defines the IOMUX settings for choose.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Signed-off-by: Ye.Li <B37916@freescale.com>
Peng Fan [Mon, 20 Jul 2015 11:28:21 +0000 (19:28 +0800)]
imx: mx6ul: Add i.MX6UL CPU type
Add MXC_CPU_MX6UL for i.MX6UL CPU type which is got at runtime from
DIGPROG register. But the value has been occupied by MXC_CPU_MX6D which
is not real id from DIGPROG register, so change i.MX6D to value 0x67 which
was not occupied.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Signed-off-by: Ye.Li <B37916@freescale.com>
Nikita Kiryanov [Thu, 23 Jul 2015 14:19:38 +0000 (17:19 +0300)]
sf: kconfig: add kconfig options for spi flashes
Add kconfig options for various SPI flashes and use them in cm-fx6 defconfig.
Cc: Jagan Teki <jteki@openedev.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Igor Grinberg <grinberg@compulab.co.il>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Acked-by: Igor Grinberg <grinberg@compulab.co.il>
Nikita Kiryanov [Thu, 23 Jul 2015 14:19:37 +0000 (17:19 +0300)]
usb: kconfig: create a menu for usb
With recent additions to USB Kconfig the number of USB options had grown
large enough to warrant a separate menu for USB.
Add a Kconfig menu for USB.
Cc: Marek Vasut <marex@denx.de>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Nikita Kiryanov [Thu, 23 Jul 2015 14:19:36 +0000 (17:19 +0300)]
usb: kconfig: usb keyboard kconfig
Add Kconfig options for USB keyboard and use them for cm-fx6.
Cc: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Igor Grinberg <grinberg@compulab.co.il>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Acked-by: Igor Grinberg <grinberg@compulab.co.il>