platform/kernel/u-boot.git
3 years agotpm: Switch TPMv1 over to use the new API
Simon Glass [Sat, 6 Feb 2021 21:23:36 +0000 (14:23 -0700)]
tpm: Switch TPMv1 over to use the new API

Take over the plain 'tpm_...' functions for use by the new TPM API. Rename
all the TPMv1 functions so they are called from the API.

Update the TPMv1 functions so that they are called from the API. Change
existing users to use the tpm1_ prefix so they don't need to go through
the API, which might introduce uncertainty.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
3 years agotpm: Add an API that can support v1.2 and v2
Simon Glass [Sat, 6 Feb 2021 21:23:35 +0000 (14:23 -0700)]
tpm: Add an API that can support v1.2 and v2

There are two different TPM standards. U-Boot supports both but each has
its own set of functions. We really need a single TPM API that can call
one or the other. This is not always possible as there are some
differences between the two standards, but it is mostly possible.

Add an API to handle this. So far it is not plumbed into the build and
only supports TPMv1.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
3 years agotpm: Add debugging of request in tpm_sendrecv_command()
Simon Glass [Sat, 6 Feb 2021 21:23:34 +0000 (14:23 -0700)]
tpm: Add debugging of request in tpm_sendrecv_command()

The response is shown but not the request. Update the code to show both
if debugging is enabled.

Use a 'uint' type for size so it matches the register-word size on both
32- and 64-bit machines.

Signed-off-by: Simon Glass <sjg@chromium.org>
3 years agotpm: Use logging in the uclass
Simon Glass [Sat, 6 Feb 2021 21:23:33 +0000 (14:23 -0700)]
tpm: Use logging in the uclass

Update this to use log_debug() instead of the old debug().

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
3 years agotpm: Don't include cr50 in TPL/SPL
Simon Glass [Sat, 6 Feb 2021 21:23:32 +0000 (14:23 -0700)]
tpm: Don't include cr50 in TPL/SPL

At present the security chip is not used in these U-Boot phases. Update
the Makefile to exclude it.

Fix a few logging statements while we are here.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
3 years agobootm: Fix duplicate debugging in bootm_process_cmdline()
Simon Glass [Sat, 6 Feb 2021 16:57:35 +0000 (09:57 -0700)]
bootm: Fix duplicate debugging in bootm_process_cmdline()

These two returns use the same string so are not distinguishable with
LOG_ERROR_RETURN. Fix it.

Signed-off-by: Simon Glass <sjg@chromium.org>
3 years agosandbox: Write out bloblist when exiting
Simon Glass [Sat, 6 Feb 2021 16:57:34 +0000 (09:57 -0700)]
sandbox: Write out bloblist when exiting

Sandbox provides a way to write out its emulated memory on exit. This
makes it possible to pass a bloblist from one phase (e.g. SPL) to the
next.

However the bloblist is not closed off, so the checksum is generally
invalid. Fix this by finishing up the bloblist before writing the memory
file.

Signed-off-by: Simon Glass <sjg@chromium.org>
3 years agosandbox: Avoid using malloc() for system state
Simon Glass [Sat, 6 Feb 2021 16:57:33 +0000 (09:57 -0700)]
sandbox: Avoid using malloc() for system state

This state is not accessible to the running U-Boot but at present it is
allocated in the emulated SDRAM. This doesn't seem very useful. Adjust
it to allocate from the OS instead.

The RAM buffer is currently not freed, but should be, so add that into
state_uninit(). Update the comment for os_free() to indicate that NULL is
a valid parameter value.

Note that the strdup() in spl_board_load_image() is changed as well, since
strdup() allocates memory in the RAM buffer.

Signed-off-by: Simon Glass <sjg@chromium.org>
3 years agosandbox: Add os_realloc()
Simon Glass [Sat, 6 Feb 2021 16:57:32 +0000 (09:57 -0700)]
sandbox: Add os_realloc()

We provide os_malloc() and os_free() but not os_realloc(). Add this,
following the usual semantics. Also update os_malloc() to behave correctly
when passed a zero size.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
3 years agos5p4418_nanopi2: Drop dead code
Simon Glass [Sat, 6 Feb 2021 16:57:31 +0000 (09:57 -0700)]
s5p4418_nanopi2: Drop dead code

This code is still using the old command typedef. It was not noticed since
this file is not currently built. It is using a non-existent option in the
Makefile.

Drop this file since it is not needed for correct operation.

Signed-off-by: Simon Glass <sjg@chromium.org>
3 years agodoc: Add a note about producing 'md.b' output using hexdump
Simon Glass [Sat, 6 Feb 2021 16:57:30 +0000 (09:57 -0700)]
doc: Add a note about producing 'md.b' output using hexdump

Comparing a hex dump on the U-Boot command line with the contents of a
file on the host system is fairly easy and convenient to do manually if
it is small. But the format used hexdump by default differs from that
shown by U-Boot. Add a note about how to make them the same.

(For large dumps, writing the data to the network with tftpput, or to a
USB stick with ext4save is easiest.)

Signed-off-by: Simon Glass <sjg@chromium.org>
3 years agodoc: describe the md command
Simon Glass [Sat, 6 Feb 2021 16:57:29 +0000 (09:57 -0700)]
doc: describe the md command

Provide a man-page for the md command.

Signed-off-by: Simon Glass <sjg@chromium.org>
3 years agobinman: Indicate how to make binman verbose
Simon Glass [Sat, 6 Feb 2021 16:57:28 +0000 (09:57 -0700)]
binman: Indicate how to make binman verbose

Add notes about how to make binman produce verbose logging when building.

Add a comment on how to do this.

Signed-off-by: Simon Glass <sjg@chromium.org>
3 years agospl: Drop duplicate 'Jumping to U-Boot' message
Simon Glass [Sat, 6 Feb 2021 16:57:27 +0000 (09:57 -0700)]
spl: Drop duplicate 'Jumping to U-Boot' message

This is printed twice but we only need one message, since there is very
little processing in between them. Drop the second one, since all branches
of the switch() already have output. Update the U-Boot message to include
the phase being jumped to.

Signed-off-by: Simon Glass <sjg@chromium.org>
3 years agoarm: remove set_dacr/get_dacr functions
Patrick Delaunay [Fri, 5 Feb 2021 12:53:39 +0000 (13:53 +0100)]
arm: remove set_dacr/get_dacr functions

Remove the unused function set_dacr/get_dacr

Serie-cc: Ard Biesheuvel <ardb@kernel.org>
Serie-cc: R Sricharan <r.sricharan@ti.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
3 years agoarm: cp15: remove weak function arm_init_domains
Patrick Delaunay [Fri, 5 Feb 2021 12:53:38 +0000 (13:53 +0100)]
arm: cp15: remove weak function arm_init_domains

Remove the unused weak function arm_init_domains used to change the
DACR value.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
3 years agoarm: omap2: remove arm_init_domains
Patrick Delaunay [Fri, 5 Feb 2021 12:53:37 +0000 (13:53 +0100)]
arm: omap2: remove arm_init_domains

Remove the arm_init_domains and the DACR update, as it is now done
in ARMv7 CP15 level.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
3 years agoarm: cp15: update DACR value to activate access control
Patrick Delaunay [Fri, 5 Feb 2021 12:53:36 +0000 (13:53 +0100)]
arm: cp15: update DACR value to activate access control

Update the initial value of Domain Access Control Register (DACR)
and set by default the access permission to client (DACR_Dn_CLIENT = 1U)
for each of the 16 domains and no more to all-supervisor
(DACR_Dn_MANAGER = 3U).

This patch allows to activate the domain checking in MMU against the
permission bits in the translation tables and avoids prefetching issue
on ARMv7 [1].

Today it was already done for OMAP2 architecture
./arch/arm/mach-omap2/omap-cache.c::arm_init_domains
introduced by commit de63ac278cba ("ARM: mmu: Set domain permissions
to client access") which fixes lot of speculative prefetch aborts seen
on OMAP5 secure devices.

[1] https://developer.arm.com/documentation/ddi0406/b/System-Level-Architecture/Virtual-Memory-System-Architecture--VMSA-/Memory-access-control/The-Execute-Never--XN--attribute-and-instruction-prefetching

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reported-by: Ard Biesheuvel <ardb@kernel.org>
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
3 years agoarm: cosmetic: align TTB_SECT define value
Patrick Delaunay [Fri, 5 Feb 2021 12:53:35 +0000 (13:53 +0100)]
arm: cosmetic: align TTB_SECT define value

Align TTB_SECT define value with previous value.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
3 years agoarm: remove TTB_SECT_XN_MASK in DCACHE_WRITETHROUGH
Patrick Delaunay [Fri, 5 Feb 2021 12:53:34 +0000 (13:53 +0100)]
arm: remove TTB_SECT_XN_MASK in DCACHE_WRITETHROUGH

The normal memory (other that DCACHE_OFF) should be executable by default,
only the device memory (DCACHE_OFF) used for peripheral access should have
the bit execute never (TTB_SECT_XN_MASK).

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
3 years agostm32mp: update the mmu configuration for SPL and prereloc
Patrick Delaunay [Fri, 5 Feb 2021 12:53:33 +0000 (13:53 +0100)]
stm32mp: update the mmu configuration for SPL and prereloc

Overidde the weak function dram_bank_mmu_setup() to set the DDR
(preloc case) or the SYSRAM (in SPL case) executable before to enable
the MMU and configure DACR.

This weak function is called in dcache_enable/mmu_setup.

This patchs avoids a permission access issue when the DDR is marked
executable (by calling mmu_set_region_dcache_behaviour with
DCACHE_DEFAULT_OPTION) after MMU setup and domain access permission
activation with DACR in dcache_enable.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
3 years agostm32mp: update MMU config before the relocation
Patrick Delaunay [Fri, 5 Feb 2021 12:53:32 +0000 (13:53 +0100)]
stm32mp: update MMU config before the relocation

Mark the top of ram, used for relocated U-Boot as a normal memory
(cacheable and executable) to avoid permission access issue when
U-Boot jumps to this relocated code.

When MMU is activated in pre-reloc stage; only the beginning of
DDR is marked executable.

This patch avoids access issue when DACR is correctly managed.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
3 years agoreset: Remove addr parameter from reset_cpu()
Harald Seiler [Tue, 15 Dec 2020 15:47:52 +0000 (16:47 +0100)]
reset: Remove addr parameter from reset_cpu()

Historically, the reset_cpu() function had an `addr` parameter which was
meant to pass in an address of the reset vector location, where the CPU
should reset to.  This feature is no longer used anywhere in U-Boot as
all reset_cpu() implementations now ignore the passed value.  Generic
code has been added which always calls reset_cpu() with `0` which means
this feature can no longer be used easily anyway.

Over time, many implementations seem to have "misunderstood" the
existence of this parameter as a way to customize/parameterize the reset
(e.g.  COLD vs WARM resets).  As this is not properly supported, the
code will almost always not do what it is intended to (because all
call-sites just call reset_cpu() with 0).

To avoid confusion and to clean up the codebase from unused left-overs
of the past, remove the `addr` parameter entirely.  Code which intends
to support different kinds of resets should be rewritten as a sysreset
driver instead.

This transformation was done with the following coccinelle patch:

    @@
    expression argvalue;
    @@
    - reset_cpu(argvalue)
    + reset_cpu()

    @@
    identifier argname;
    type argtype;
    @@
    - reset_cpu(argtype argname)
    + reset_cpu(void)
    { ... }

Signed-off-by: Harald Seiler <hws@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
3 years agoRevert "lpc32xx: cpu: add support for soft reset"
Harald Seiler [Tue, 15 Dec 2020 15:47:51 +0000 (16:47 +0100)]
Revert "lpc32xx: cpu: add support for soft reset"

This reverts commit 576007aec9a4a5f4f3dd1f690fb26a8c05ceb75f.

The parameter passed to reset_cpu() no longer holds a meaning as all
call-sites now pass the value 0.  Thus, branching on it is essentially
dead code and will just confuse future readers.

Revert soft-reset support and just always perform a hard-reset for now.
This is a preparation for removal of the reset_cpu() parameter across
the entire tree in a later patch.

Fixes: 576007aec9a4 ("lpc32xx: cpu: add support for soft reset")
Cc: Sylvain Lemieux <slemieux@tycoint.com>
Signed-off-by: Harald Seiler <hws@denx.de>
3 years agoboard: ns3: Remove superfluous reset logic
Harald Seiler [Tue, 15 Dec 2020 15:47:50 +0000 (16:47 +0100)]
board: ns3: Remove superfluous reset logic

The current implementation of reset_cpu() in the ns3 board code does not
archieve what it is supposed to (according to the comments), due to
a number of reasons:

 1. The argument to reset_cpu() is _not_ actually passed from the
    `reset` command, but is set to 0 in all call-sites (in this
    specific case, see arch/arm/lib/reset.c).  Thus, performing
    different kinds of resets based on its value will not work as
    expected.

 2. Contrary to its documentation, the passed argument is not
    interpreted, but a static `L3_RESET` define is used.  The other
    comment properly notes that this will always perform a L3 reset,
    though.

 3. The "parsing" of the static `L3_RESET` value is not even using the
    upper and lower nibble as stated in the comment, but uses the last
    two decimal digits of the value.

This is currently one of the only implementations left in U-Boot, which
make "use" of the value passed to reset_cpu().  As this is done under
false assumption (the value does not have any meaning anymore), it makes
sense to bring it into line with the rest and start ignoring the
parameter.

This is a preparation for removal of the reset_cpu() parameter across
the entire tree in a later patch.

Fixes: b5a152e7ca0b ("board: ns3: default reset type to L3")
Cc: Bharat Gooty <bharat.gooty@broadcom.com>
Cc: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
Signed-off-by: Harald Seiler <hws@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
3 years agonds32: Remove dead reset_cpu() implementation
Harald Seiler [Tue, 15 Dec 2020 15:47:49 +0000 (16:47 +0100)]
nds32: Remove dead reset_cpu() implementation

nds32 is one of the only architectures which still have a reset_cpu()
implementation that makes use of the `addr` parameter.  The rest of
U-Boot now ignores it and passes 0 everywhere.  It turns out that even
here, reset_cpu() is no longer referenced anywhere; reset is either not
implemented (e.g. ae3xx) or realized using a WDT (e.g. ag101).

Remove this left-over implementation in preparation for the removal of
the `addr` parameter in the entire tree.

Cc: Rick Chen <rick@andestech.com>
Signed-off-by: Harald Seiler <hws@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Rick Chen <rick@andestech.com>
3 years agoPrepare v2021.04-rc3
Tom Rini [Tue, 2 Mar 2021 03:46:41 +0000 (22:46 -0500)]
Prepare v2021.04-rc3

Signed-off-by: Tom Rini <trini@konsulko.com>
3 years agolog: convert pr_*() to logging
Heinrich Schuchardt [Mon, 4 Jan 2021 07:02:55 +0000 (08:02 +0100)]
log: convert pr_*() to logging

In drivers we use a family of printing functions including pr_err() and
pr_cont(). CONFIG_LOGLEVEL is used to control which of these lead to output
via printf().

Our logging functions allow finer grained control of output. So replace
printf() by the matching logging functions. The usage of CONFIG_LOGLEVEL
remains unchanged.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
3 years agofs: btrfs: do not fail when offset of a ROOT_ITEM is not -1
Marek Behún [Tue, 9 Feb 2021 17:33:37 +0000 (18:33 +0100)]
fs: btrfs: do not fail when offset of a ROOT_ITEM is not -1

When the btrfs_read_fs_root() function is searching a ROOT_ITEM with
location key offset other than -1, it currently fails via BUG_ON.

The offset can have other value than -1, though. This can happen for
example if a subvolume is renamed:

  $ btrfs subvolume create X && sync
  Create subvolume './X'
  $ btrfs inspect-internal dump-tree /dev/root | grep -B 2 'name: X$
        location key (270 ROOT_ITEM 18446744073709551615) type DIR
        transid 283 data_len 0 name_len 1
        name: X
  $ mv X Y && sync
  $ btrfs inspect-internal dump-tree /dev/root | grep -B 2 'name: Y$
        location key (270 ROOT_ITEM 0) type DIR
        transid 285 data_len 0 name_len 1
        name: Y

As can be seen the offset changed from -1ULL to 0.

Do not fail in this case.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Cc: David Sterba <dsterba@suse.com>
Cc: Qu Wenruo <wqu@suse.com>
Cc: Tom Rini <trini@konsulko.com>
3 years agouboot-test-hooks: Switch to our GitLab instance
Tom Rini [Wed, 24 Feb 2021 22:05:04 +0000 (17:05 -0500)]
uboot-test-hooks: Switch to our GitLab instance

As Stephen is no longer actively maintaining the uboot-test-hooks
repository, switch to using the instance on our GitLab.

Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
3 years agoCorrect U-Boot upstream repository
Heinrich Schuchardt [Wed, 24 Feb 2021 12:19:04 +0000 (13:19 +0100)]
Correct U-Boot upstream repository

The U-Boot source moves to https://source.denx.de/u-boot/u-boot.git
effective 2021-02-28.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
3 years agoMerge tag 'efi-2021-04-rc3-2' of https://gitlab.denx.de/u-boot/custodians/u-boot-efi
Tom Rini [Sat, 27 Feb 2021 13:06:10 +0000 (08:06 -0500)]
Merge tag 'efi-2021-04-rc3-2' of https://gitlab.denx.de/u-boot/custodians/u-boot-efi

Pull request for efi-2021-04-rc3-2

Bug fixes:
* debug build for mkeficapsule
* limit output length for VenHw, VenMedia
* ACPI tables must be in EfiACPIReclaimMemory

3 years agoMerge https://gitlab.denx.de/u-boot/custodians/u-boot-usb
Tom Rini [Fri, 26 Feb 2021 20:11:08 +0000 (15:11 -0500)]
Merge https://gitlab.denx.de/u-boot/custodians/u-boot-usb

- fastboot updates / fixes

3 years agoMerge https://gitlab.denx.de/u-boot/custodians/u-boot-spi
Tom Rini [Fri, 26 Feb 2021 17:41:19 +0000 (12:41 -0500)]
Merge https://gitlab.denx.de/u-boot/custodians/u-boot-spi

- new GigaDevice flash ids
- fixes for imx, nxp_spi drivers

3 years agoMerge tag 'u-boot-stm32-20210226' of https://gitlab.denx.de/u-boot/custodians/u-boot-stm
Tom Rini [Fri, 26 Feb 2021 17:41:06 +0000 (12:41 -0500)]
Merge tag 'u-boot-stm32-20210226' of https://gitlab.denx.de/u-boot/custodians/u-boot-stm

- Add USB host boot support in stm32mp1 config
- Enable uefi related commands for STMicroelectronics STM32MP15 boards
- Remove duplicate uart nodes in stm32mp15 device tree

3 years agocmd/efidebug: add firmware management protocol GUID
Heinrich Schuchardt [Fri, 26 Feb 2021 16:57:47 +0000 (17:57 +0100)]
cmd/efidebug: add firmware management protocol GUID

Add missing GUID short text used in the efidebug tables and efidebug dh
sub-commands.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
3 years agoefi_loader: fix documentation in efi_loader.h
Heinrich Schuchardt [Thu, 25 Feb 2021 07:02:37 +0000 (08:02 +0100)]
efi_loader: fix documentation in efi_loader.h

Correct missing descriptions and typos in efi_loader.h.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
3 years agoefi_loader: limit output length for VenHw, VenMedia
Heinrich Schuchardt [Tue, 23 Feb 2021 20:15:35 +0000 (21:15 +0100)]
efi_loader: limit output length for VenHw, VenMedia

VenHw and VenMedia device path nodes may carry vendor defined data of
arbitrary length. When converting a device path node to text ensure that we
do not overrun our internal buffer.

In our implementation of
EFI_DEVICE_PATH_TO_TEXT_PROTOCOL.ConvertDevicePathToText() we could first
determine the output length and then allocate buffers but that would nearly
double the code size. Therefore keep the preallocated buffers and truncate
excessive device paths instead.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
3 years agotools/mkeficapsule.c: fix DEBUG build
Klaus Heinrich Kiwi [Sat, 20 Feb 2021 20:40:45 +0000 (17:40 -0300)]
tools/mkeficapsule.c: fix DEBUG build

Fix a missing comma sign (,) from a printf(), that is only
reachable if DEBUG is defined, in which case the build fails with:

    tools/mkeficapsule.c:266:36: error: expected ‘)’ before ‘bin’
      266 |  printf("\tbin: %s\n\ttype: %pUl\n" bin, guid);
          |                                    ^~~~
          |                                    )

Signed-off-by: Klaus Heinrich Kiwi <klaus@linux.vnet.ibm.com>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
3 years agoMAINTAINERS: assign tools/mkeficapsule.c to EFI PAYLOAD
Heinrich Schuchardt [Mon, 22 Feb 2021 19:26:34 +0000 (20:26 +0100)]
MAINTAINERS: assign tools/mkeficapsule.c to EFI PAYLOAD

tools/mkeficapsule.c is used to prepare test files for testing the UEFI
sub-system.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
3 years agoefi_loader: ACPI tables must be in EfiACPIReclaimMemory
Heinrich Schuchardt [Sun, 21 Feb 2021 09:16:58 +0000 (10:16 +0100)]
efi_loader: ACPI tables must be in EfiACPIReclaimMemory

The UEFI spec does not allow ACPI tables to be in runtime services memory.
It recommends EfiACPIReclaimMemory.

Remove a superfluous check that the allocated pages are 16 byte aligned.
EFI pages are 4 KiB aligned.

Fixes: 86df34d42b05 ("efi_loader: Install ACPI configuration tables")
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
3 years agoconfigs: stm32mp1: enable uefi related commands
Ilias Apalodimas [Fri, 26 Feb 2021 12:52:51 +0000 (14:52 +0200)]
configs: stm32mp1: enable uefi related commands

The board can boot with UEFI. With the latest changes in U-Boot's
EFI subsystem we also have support for EFI runtime variables, without
SetVariable support.  We can also store the EFI variables in a file on the
ESP partition and preserve them across reboots.
The env and efidebug commands are missing in order to configure
EFI variables and the efibootmgr though.  Since U-Boot's default config
enables other EFI related commands (e.g bootefi), let's add the env related
and efidebug commands and allow users to do that

Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
3 years agoarm: dts: stm32mp15: remove duplicate uart nodes
Patrick Delaunay [Wed, 24 Feb 2021 10:00:56 +0000 (11:00 +0100)]
arm: dts: stm32mp15: remove duplicate uart nodes

Remove duplicated uart nodes introduced with commit 62f95af92a3f
("ARM: dts: stm32mp1: DT alignment with Linux kernel v5.9-rc4"),
because the uart nodes wasn't correctly ordered in alphabetic order.

Only cosmetic: the generated device tree don't change.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
3 years agoARM: stm32: Add USB host boot support
Marek Vasut [Fri, 12 Feb 2021 12:50:52 +0000 (13:50 +0100)]
ARM: stm32: Add USB host boot support

Add support for booting from USB pen drive, since USB host port is
available on the STM32MP1.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrice Chotard <patrice.chotard@foss.st.com>
Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
3 years agousb: gadget: dwc2_udc_otg: Fix dwc2_gadget_start() and usb_gadget_register_driver()
Patrice Chotard [Wed, 17 Feb 2021 09:17:27 +0000 (10:17 +0100)]
usb: gadget: dwc2_udc_otg: Fix dwc2_gadget_start() and usb_gadget_register_driver()

Since commit 8745b9ebccae ("usb: gadget: add super speed support")
ums was no more functional on platform which use dwc2_udc_otg driver.

This was due to a too restrictive test which checked that the gadget
driver speed was either FS or HS.

So all gadget driver with max speed set to speed higher than
HS (SS in case of composite gadget driver in our case) are not
allowed, which is wrong.

Update the speed test in usb_gadget_register_driver() and in
dwc2_gadget_start() to allow all gadget driver speed equal or higher
than FS.

Tested on stm32mp157c-ev1 board.

Fixes: c791c8431c34 ("usb: dwc2: convert driver to DM_USB_GADGET")

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
3 years agousb: kbd: Also accept keyboards with Interrupt OUT endpoint
Stefan Brüns [Sat, 20 Feb 2021 16:26:06 +0000 (17:26 +0100)]
usb: kbd: Also accept keyboards with Interrupt OUT endpoint

The OUT endpoint can just be ignored as it is not used, just as the
corresponding Set_Report request for IN-only interfaces. E.g. the
Linux gadget hid keyboard also provides an interrupt endpoint.

Also cleanup confusing debug messages like "found set protocol", which
is printed when a keyboard device is found, while the Set_Protocol request
is issued quite some time later.

Signed-off-by: Stefan Brüns <stefan.bruens@rwth-aachen.de>
3 years agofastboot: add UUU command UCmd and ACmd support
Heiko Schocher [Wed, 10 Feb 2021 08:29:03 +0000 (09:29 +0100)]
fastboot: add UUU command UCmd and ACmd support

add support for the UUU commands ACmd and UCmd.

Enable them through the Kconfig option
CONFIG_FASTBOOT_UUU_SUPPORT

base was commit in NXP kernel
9b149c2a2882: ("MLK-18591-3 android: Add FSL android fastboot support")

and ported it to current mainline. Tested this patch
on imx6ul based board.

Signed-off-by: Heiko Schocher <hs@denx.de>
Acked-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
3 years agodoc: Document partition specifications
Sean Anderson [Fri, 5 Feb 2021 14:39:02 +0000 (09:39 -0500)]
doc: Document partition specifications

This documents the way U-Boot understands partitions specifications.
This also updates the fastboot documentation for the changes in the
previous commit.

Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
3 years agodoc: Rename k210 partitions anchor
Sean Anderson [Fri, 5 Feb 2021 14:39:01 +0000 (09:39 -0500)]
doc: Rename k210 partitions anchor

This anchor is only for the k210 partition layout, so rename it
appropriately. This keeps it from conflicting with the (to be added)
anchor for U-Boot partitions in general.

Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
3 years agofastboot: Allow u-boot-style partitions
Sean Anderson [Fri, 5 Feb 2021 14:39:00 +0000 (09:39 -0500)]
fastboot: Allow u-boot-style partitions

This adds support for partitions of the form "dev.hwpart:part" and
"dev#partname". This allows one to flash to eMMC boot partitions without
having to use CONFIG_FASTBOOT_MMC_BOOT1_SUPPORT. It also allows one to
flash to an entire device without needing CONFIG_FASTBOOT_MMC_USER_NAME.
Lastly, one can also flash MMC devices other than
CONFIG_FASTBOOT_FLASH_MMC_DEV.

Because devices can be specified explicitly, CONFIG_FASTBOOT_FLASH_MMC_DEV
is used only when necessary for existing functionality. For those cases,
fastboot_mmc_get_dev has been added as a helper function. This allows

There should be no conflicts with the existing system, but just in case, I
have ordered detection of these names after all existing names.

The fastboot_mmc_part test has been updated for these new names.

Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
3 years agofastboot: Move part_get_info_by_name_or_alias after raw_part_get_info_by_name
Sean Anderson [Fri, 5 Feb 2021 14:38:59 +0000 (09:38 -0500)]
fastboot: Move part_get_info_by_name_or_alias after raw_part_get_info_by_name

This makes the next commit more readable by doing the move now.

Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
3 years agofastboot: Remove mmcpart argument from raw_part_get_info_by_name
Sean Anderson [Fri, 5 Feb 2021 14:38:58 +0000 (09:38 -0500)]
fastboot: Remove mmcpart argument from raw_part_get_info_by_name

The only thing mmcpart was used for was to pass to blk_dselect_hwpart.
This calls blk_dselect_hwpart directly from raw_part_get_info_by_name. The
error handling is dropped, but it is reintroduced in the next commit
(albeit less specificly).

Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
3 years agopart: Support string block devices in part_get_info_by_dev_and_name
Sean Anderson [Fri, 5 Feb 2021 14:38:57 +0000 (09:38 -0500)]
part: Support string block devices in part_get_info_by_dev_and_name

This adds support for things like "#partname" and "0.1#partname". The block
device parsing is done like in blk_get_device_part_str.

Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
3 years agopart: Support getting whole disk from part_get_info_by_dev_and_name_or_num
Sean Anderson [Fri, 5 Feb 2021 14:38:56 +0000 (09:38 -0500)]
part: Support getting whole disk from part_get_info_by_dev_and_name_or_num

This adds an option to part_get_info_by_dev_and_name_or_num to allow
callers to specify whether whole-disk partitions are fine.

Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
3 years agopart: Give several functions more useful return values
Sean Anderson [Fri, 5 Feb 2021 14:38:55 +0000 (09:38 -0500)]
part: Give several functions more useful return values

Several functions in disk/part.c just return -1 on error. This makes them
return different errnos for different failures. This helps callers
differentiate between failures, even if they cannot read stdout.

Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
3 years agotest: dm: Add test for fastboot mmc partition naming
Sean Anderson [Fri, 5 Feb 2021 14:38:54 +0000 (09:38 -0500)]
test: dm: Add test for fastboot mmc partition naming

This test verifies the mapping between fastboot partitions and partitions
as understood by U-Boot. It also tests the creation of GPT partitions,
though that is not the primary goal.

Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
3 years agommc: sandbox: Add support for writing
Sean Anderson [Fri, 5 Feb 2021 14:38:53 +0000 (09:38 -0500)]
mmc: sandbox: Add support for writing

This adds support writing to the sandbox mmc backed by an in-memory
buffer. The unit test has been updated to test reading, writing, and
erasing. I'm not sure what MMCs erase to; I picked 0, but if it's 0xFF
then that can be easily changed.

Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
3 years agoMerge https://gitlab.denx.de/u-boot/custodians/u-boot-marvell
Tom Rini [Fri, 26 Feb 2021 12:55:16 +0000 (07:55 -0500)]
Merge https://gitlab.denx.de/u-boot/custodians/u-boot-marvell

- turris_mox: Enhancements, mostlly defconfig changes (Pali)
- pci-aardvark: Set Max Payload Size and Max Read Request Size
                to 512 bytes (Pali)
- pci_mvebu: Minor cleanup and refactoring (Marek)
- Upgrade A38x DDR3 training to version 14.0.0 (Marek)

3 years agoMerge https://gitlab.denx.de/u-boot/custodians/u-boot-samsung
Tom Rini [Fri, 26 Feb 2021 12:54:27 +0000 (07:54 -0500)]
Merge https://gitlab.denx.de/u-boot/custodians/u-boot-samsung

3 years agoMerge https://gitlab.denx.de/u-boot/custodians/u-boot-riscv
Tom Rini [Fri, 26 Feb 2021 12:53:04 +0000 (07:53 -0500)]
Merge https://gitlab.denx.de/u-boot/custodians/u-boot-riscv

3 years agomtd: nand: spi: Support GigaDevice GD5F1GQ5UExxG
Reto Schneider [Thu, 11 Feb 2021 12:05:48 +0000 (13:05 +0100)]
mtd: nand: spi: Support GigaDevice GD5F1GQ5UExxG

The relevant changes to the already existing GD5F1GQ4UExxG support has
been determined by consulting the GigaDevice product change notice
AN-0392-10, version 1.0 from November 30, 2020.

As the overlaps are huge, variable names have been generalized
accordingly.

Apart form the lowered ECC strength (4 instead of 8 bits per 512 bytes),
the new device ID, and the extra quad IO dummy byte, no changes had to
be taken into account.

New hardware features are not supported, namely:
 - Power on reset
 - Unique ID
 - Double transfer rate (DTR)
 - Parameter page
 - Random data quad IO

The inverted semantic of the "driver strength" register bits, defaulting
to 100% instead of 50% for the Q5 devices, got ignored as the driver has
never touched them anyway.

The no longer supported "read from cache during block erase"
functionality is not reflected as the current SPI NAND core does not
support it anyway.

Implementation has been tested on MediaTek MT7688 based GARDENA smart
Gateways using both, GigaDevice GD5F1GQ5UEYIG and GD5F1GQ4UBYIG.

Signed-off-by: Reto Schneider <reto.schneider@husqvarnagroup.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Acked-by: Jagan Teki <jagan@amarulasolutions.com>
3 years agomtd: nand: spi: Only one dummy byte in QUADIO
Hauke Mehrtens [Thu, 11 Feb 2021 12:05:47 +0000 (13:05 +0100)]
mtd: nand: spi: Only one dummy byte in QUADIO

The datasheet only lists one dummy byte in the 0xEB operation for the
following chips:
* GD5F1GQ4xExxG
* GD5F1GQ4xFxxG
* GD5F1GQ4UAYIG
* GD5F4GQ4UAYIG

Reto Schneider:
- Linux patch ported to U-Boot
- Checked for compatibility with GD5F1GQ4xBxxG
- Fixed operation code in original commit message (0xEH -> 0xEB)

Signed-off-by: Reto Schneider <reto.schneider@husqvarnagroup.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Acked-by: Jagan Teki <jagan@amarulasolutions.com>
3 years agomtd: spi-nor-core: Fix typo in documentation
Sean Anderson [Fri, 5 Feb 2021 04:11:08 +0000 (23:11 -0500)]
mtd: spi-nor-core: Fix typo in documentation

This line should come before the docs for the next function.

Fixes: 7aeedac0153 ("mtd: spi: Port SPI NOR framework from Linux")

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Pratyush Yadav <p.yadav@ti.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
3 years agocmd: sf: Print error on test failure
Sean Anderson [Fri, 5 Feb 2021 04:11:07 +0000 (23:11 -0500)]
cmd: sf: Print error on test failure

The sf test command is used to test spi flashes (and spi masters). Printing
the exact error code is very helpful to those debugging the spi stack.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Pratyush Yadav <p.yadav@ti.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
3 years agocmd: sf: Display errno on erase failure
Sean Anderson [Fri, 5 Feb 2021 04:11:06 +0000 (23:11 -0500)]
cmd: sf: Display errno on erase failure

If there is an error while erasing SPI flash, no errno is displayed. This
makes it difficult to determine the cause of the error. This change mirrors
the logic for write errors above.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Pratyush Yadav <p.yadav@ti.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
3 years agospi: nxp_fspi: Fix error reporting
Adam Ford [Mon, 18 Jan 2021 21:32:49 +0000 (15:32 -0600)]
spi: nxp_fspi: Fix error reporting

On the i.MX8M Mini, ret = clk_set_rate() sets ret to the value of the
rate the clock was able to set.  When checking for errors, it only
checks that it is not NULL.  Since positive numbers are not errors,
only check for negative numbers when handling errors.

Fixes: 383fded70c4f ("spi: nxp_fspi: new driver for the FlexSPI controller")
Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Pratyush Yadav <p.yadav@ti.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
3 years agoddr: marvell: a38x: fix comment in conditional macro
Marek Behún [Fri, 19 Feb 2021 16:11:26 +0000 (17:11 +0100)]
ddr: marvell: a38x: fix comment in conditional macro

The code was processed with unifdef utility to omit portions not
relevant to A38x and DDR3. This removes usage of many macros, including
A70X0, A80X0 and A3900. It seems that the unifdef utility did not remove
the macros from #else comment.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Tested-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
3 years agoddr: marvell: a38x: bump version to 14.0.0
Marek Behún [Fri, 19 Feb 2021 16:11:25 +0000 (17:11 +0100)]
ddr: marvell: a38x: bump version to 14.0.0

Bump version of a38x DDR3 trianing to version 14.0.0 to reflect the
version in the mv-ddr-devel branch of upstream repository
https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell.git.

There is a new version numbering system, where after 18.12.0 came
1.0.0, 2.0.0, and so on until 14.0.0. So 14.0.0 is newer than 18.12.0.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Tested-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
3 years agoddr: marvell: a38x: enum mv_ddr_twin_die: change order
heaterC [Fri, 19 Feb 2021 16:11:24 +0000 (17:11 +0100)]
ddr: marvell: a38x: enum mv_ddr_twin_die: change order

commit 56db5d1464b44df10a02b99e615ebd6f6a35c428 upstream.

@pali suggested this change
In commit 6285efb ("mv_ddr: add support for twin-die combined memory
device") was added support for twin-die combined memory device and
default value for explicitly uninitialized structure members is zero, s
also twin_die_combined is initialized to zero. Which means COMBINED
value.
As prior this commit there was no support for twin-die combined memory
device, default value for twin_die_combined should be NOT_COMBINED. This
change change order of enum mv_ddr_twin_die to ensure that NOT_COMBINED
has value zero.

Signed-off-by: heaterC <airyguy@gmx.de>
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Tested-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
3 years agoddr: marvell: a38x: import code change from upstream
Marek Behún [Fri, 19 Feb 2021 16:11:23 +0000 (17:11 +0100)]
ddr: marvell: a38x: import code change from upstream

commit 2bdd12dd68b1f8e27a03a3443ae49a09a14c18e4 upstream.

The commit mentioned above changes non-DDR3 stuff in upstream, but it
also changes code in ddr3_training.c.

Import this change to remain consistent with upstream.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Tested-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
3 years agoddr: marvell: a38x: fix memory cs size function
Moti Buskila [Fri, 19 Feb 2021 16:11:22 +0000 (17:11 +0100)]
ddr: marvell: a38x: fix memory cs size function

commit c8b301463d508c807a33f7b7eaea98bbda4aa35e upstream.

The funtion returnd cs size in byte instead of MB, that cause
calculation error since the caller was expected to get u32 and when he
got above 4G it refers it as 0.
The fix was to get the cs memory size from function as in MB and then
multiply it by 1MB.

Signed-off-by: Moti Buskila <motib@marvell.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Tested-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
3 years agoddr: marvell: a38x: import header change from upstream
Marek Behún [Fri, 19 Feb 2021 16:11:21 +0000 (17:11 +0100)]
ddr: marvell: a38x: import header change from upstream

commit d653b305d0b3da9727c49124683f1a6d95d5c9a5 upstream.

The commit mentioned above changes non-DDR3 stuff in upstream, but it
also changes header ddr_topology_def.h.

Import this header change to remain consistent with upstream.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Tested-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
3 years agoddr: marvell: a38x: disable WL phase correction stage in case of bus_width=16bit
Moti Buskila [Fri, 19 Feb 2021 16:11:20 +0000 (17:11 +0100)]
ddr: marvell: a38x: disable WL phase correction stage in case of bus_width=16bit

commit 20c89a28548cdab11f88d2ec8936344af0686a1e upstream.

WL phase correcion stage is failing while using bus_width of 16bit, not
to be fix this stage is un-necessary when working with bus_width of 16
bit.

Signed-off-by: Moti Buskila <motib@marvell.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Tested-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
3 years agoddr: marvell: a38x: add support for twin-die combined memory device
Moti Buskila [Fri, 19 Feb 2021 16:11:19 +0000 (17:11 +0100)]
ddr: marvell: a38x: add support for twin-die combined memory device

commit 6285efb8a118940877522c4c07bd7c64569b4f5f upstream.

the twin-die combined memory device should be treatened as X8
device and not as X16 one

Signed-off-by: Moti Buskila <motib@marvell.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
[ - the default value for twin_die_combined is set to NOT_COMBINED for
    all boards, as this was default behaviour prior this change ]
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Tested-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
3 years agoddr: marvell: a38x: add 16Gbit memory devices support
Moti Buskila [Fri, 19 Feb 2021 16:11:18 +0000 (17:11 +0100)]
ddr: marvell: a38x: add 16Gbit memory devices support

commit 994509eb4fe6771d92cd06314c37895098ac48fa upstream.

Signed-off-by: Moti Buskila <motib@marvell.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Tested-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
3 years agoddr: marvell: a38x: allow board specific ODT configuration
Baruch Siach [Fri, 19 Feb 2021 16:11:17 +0000 (17:11 +0100)]
ddr: marvell: a38x: allow board specific ODT configuration

commit 2d3b9437cf38c06c4330e0de07f29476197f5e04 upstream.

The ODT enable heuristic based on active chip-selects is not always
correct. Some board might use two chip-selects, but have only one ODT
line connected. Allow board specific mv_ddr_topology_map to directly set
the ODT configuration register value.

Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Reviewed-by: Moti Buskila <motib@marvell.com>
Reviewed-by: Nadav Haklai <Nadav.Haklai@cavium.com>
Reviewed-by: Kostya Porotchkin <Kostya.Porotchkin@cavium.com>
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Tested-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
3 years agoddr: marvell: a38x: import header change from upstream
Marek Behún [Fri, 19 Feb 2021 16:11:16 +0000 (17:11 +0100)]
ddr: marvell: a38x: import header change from upstream

commit 3908e20c6c520339e9bddb566823ae5e065d5218 upstream.

The commit mentioned above changes non-DDR3 stuff in upstream, but it
also changes header ddr_topology_def.h.

Import this header change to remain consistent with upstream.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Tested-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
3 years agoddr: marvell: a38x: fix memory size calculation using 32bit bus width
Moti Buskila [Fri, 19 Feb 2021 16:11:15 +0000 (17:11 +0100)]
ddr: marvell: a38x: fix memory size calculation using 32bit bus width

commit ab9240402a70cc02496683971779e75eff410ab4 upstream.

- function mv_ddr_spd_die_capacity_user_get() has a bug,
  since it insert a user memory enum to it,
  instead of SPD memory enum (which are different)
- fix: remove mv_ddr_spd_die_capacity_user_get() function.
- memory size with 64 and 32 bit already calculated correctly
  at mv_ddr_mem_sz_per_cs_get() function

Signed-off-by: Moti Buskila <motib@marvell.com>
Reviewed-by: Stefan Chulski <Stefan.Chulski@cavium.com>
Reviewed-by: Alex Leibovich <alexl@marvell.com>
Reviewed-by: Kostya Porotchkin <Kostya.Porotchkin@cavium.com>
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Tested-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
3 years agoddr: marvell: a38x: fix 32bit
Moti Buskila [Fri, 19 Feb 2021 16:11:14 +0000 (17:11 +0100)]
ddr: marvell: a38x: fix 32bit

commit 0b5adedd4ced9b8f528faad1957d4d69e95759ef upstream.

Signed-off-by: Moti Buskila <motib@marvell.com>
Reviewed-by: Alex Leibovich <alexl@marvell.com>
Reviewed-by: Kostya Porotchkin <Kostya.Porotchkin@cavium.com>
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Tested-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
3 years agoddr: marvell: a38x: import header change from upstream
Marek Behún [Fri, 19 Feb 2021 16:11:13 +0000 (17:11 +0100)]
ddr: marvell: a38x: import header change from upstream

commit 6c705ebc0d70f67ed7cae83ad1978c3305ef25be upstream.

The commit mentioned above changes non-DDR3 stuff in upstream, but it
also changes header mv_ddr_topology.h.

Import this header change to remain consistent with upstream.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Tested-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
3 years agoddr: marvell: a38x: add ddr 32bit ECC support
Alex Leibovich [Fri, 19 Feb 2021 16:11:12 +0000 (17:11 +0100)]
ddr: marvell: a38x: add ddr 32bit ECC support

commit 61a8910998d7b553e80f600ebe8147a8b98f0945 upstream.

Required changes made for 32bit ddr support.
An update is made to the topology map, according to
bus_act_mask, set in the dram_port.c

Signed-off-by: Alex Leibovich <alexl@marvell.com>
Reviewed-by: Kostya Porotchkin <Kostya.Porotchkin@cavium.com>
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Tested-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
3 years agoddr: marvell: a38x: add ddr32 support
Alex Leibovich [Fri, 19 Feb 2021 16:11:11 +0000 (17:11 +0100)]
ddr: marvell: a38x: add ddr32 support

commit 32800667b375ebd1f82120da0f3479b1cf52d96d upstream.

Required changes made for 32bit ddr support.
An update is made to the topology map, according to
bus_act_mask, set in the dram_port.c

Signed-off-by: Alex Leibovich <alexl@marvell.com>
Reviewed-by: Nadav Haklai <Nadav.Haklai@cavium.com>
Reviewed-by: Kostya Porotchkin <Kostya.Porotchkin@cavium.com>
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Tested-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
3 years agoddr: marvell: a38x: import header change from upstream
Marek Behún [Fri, 19 Feb 2021 16:11:10 +0000 (17:11 +0100)]
ddr: marvell: a38x: import header change from upstream

commit a165037ec26f301be75e1fabc263643683e85255 upstream.

The commit mentioned above changes non-DDR3 stuff in upstream, but it
also changes header ddr_topology_def.h.

Import this header change to remain consistent with upstream.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Tested-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
3 years agoddr: marvell: a38x: fix write leveling suplementary algo
Moti Buskila [Fri, 19 Feb 2021 16:11:09 +0000 (17:11 +0100)]
ddr: marvell: a38x: fix write leveling suplementary algo

commit ce62bef8fac559e27245259882e45f19cdc293ad upstream.

- fix JIRA A7K8K-5056
- remove TEST_PATTERN write at the load patern stage earlier to WL SUP stage
- the WL SUP stage already writes this pattern to the memory, if the pattern exist at the memory
  then the algorithm will fail, since it think that there are no phase to correct

Signed-off-by: Moti Buskila <motib@marvell.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Tested-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
3 years agoARM: dts: armada-385-turris-omnia: rename node in -u-boot.dtsi file
Marek Behún [Tue, 9 Feb 2021 02:43:03 +0000 (03:43 +0100)]
ARM: dts: armada-385-turris-omnia: rename node in -u-boot.dtsi file

The SPI NOR flash node name in main device tree for Turris Omnia is
called `spi-nor@0`.

Rename node spi-flash@0 in Turris Omnia's -u-boot.dtsi file to spi-nor@0
so that U-Boot does not try to probe the same SPI NOR device multiple
times.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Cc: Stefan Roese <sr@denx.de>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Pali Rohár <pali@kernel.org>
3 years agopci: pci_mvebu: set local dev to number 1
Marek Behún [Mon, 8 Feb 2021 22:01:41 +0000 (23:01 +0100)]
pci: pci_mvebu: set local dev to number 1

Linux displays the real PCIe card connected to a mvebu PCIe slot as
device 0, not 1. This is done by setting local dev number to 1, so that
the local "Marvell Memory controller" device is on address 1.

Let's do it also in U-Boot.

With this commit the pci command in U-Boot prints something like:
  => pci
  Scanning PCI devices on bus 0
  BusDevFun  VendorId   DeviceId   Device Class       Sub-Class
  _____________________________________________________________
  00.00.00   0x168c     0x003c     Network controller      0x80

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Cc: Stefan Roese <sr@denx.de>
Cc: Phil Sutter <phil@nwl.cc>
Cc: Mario Six <mario.six@gdsys.cc>
Cc: Baruch Siach <baruch@tkos.co.il>
Reviewed-by: Stefan Roese <sr@denx.de>
3 years agopci: pci_mvebu: refactor validation of addresses for config access
Marek Behún [Mon, 8 Feb 2021 22:01:40 +0000 (23:01 +0100)]
pci: pci_mvebu: refactor validation of addresses for config access

Refactor validation of bdf parameter in mvebu_pcie_read/write_config
functions.

We can simplify the code by putting the validation into separate
function.

Also there are always only two devices visible on local bus:
* on slot configured by function mvebu_pcie_set_local_dev_nr()
  (by default this register is set to 0) there is a
  "Marvell Memory controller", which isn't useful in root complex
  mode,
* on all other slots the real PCIe card connected to the PCIe slot.

We can simplify the code even more by simply allowing access only to
the real PCIe card.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Cc: Stefan Roese <sr@denx.de>
Cc: Phil Sutter <phil@nwl.cc>
Cc: Mario Six <mario.six@gdsys.cc>
Cc: Baruch Siach <baruch@tkos.co.il>
Reviewed-by: Stefan Roese <sr@denx.de>
3 years agopci: pci_mvebu: debug rd/wr config as other drivers do
Marek Behún [Mon, 8 Feb 2021 22:01:39 +0000 (23:01 +0100)]
pci: pci_mvebu: debug rd/wr config as other drivers do

Other drivers (aardvark, intel_fpga) print "(addr,size,val)" when
debugging is enabled. Print size for pci_mvebu as well.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Cc: Stefan Roese <sr@denx.de>
Cc: Phil Sutter <phil@nwl.cc>
Cc: Mario Six <mario.six@gdsys.cc>
Cc: Baruch Siach <baruch@tkos.co.il>
Reviewed-by: Stefan Roese <sr@denx.de>
3 years agopci: pci_mvebu: cosmetic fix
Marek Behún [Mon, 8 Feb 2021 22:01:38 +0000 (23:01 +0100)]
pci: pci_mvebu: cosmetic fix

Write bdf address in a same way in mvebu_pcie_read/write_config.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Cc: Stefan Roese <sr@denx.de>
Cc: Phil Sutter <phil@nwl.cc>
Cc: Mario Six <mario.six@gdsys.cc>
Cc: Baruch Siach <baruch@tkos.co.il>
Reviewed-by: Stefan Roese <sr@denx.de>
3 years agopci: pci_mvebu: use dev_seq instead of static variable
Marek Behún [Mon, 8 Feb 2021 22:01:37 +0000 (23:01 +0100)]
pci: pci_mvebu: use dev_seq instead of static variable

PCI uclass maps PCI bus numbers to the seq member of struct udevice.
Use dev_seq(dev) as the bus number in mvebu_pcie_probe instead of an
incrementing a static variable.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Cc: Stefan Roese <sr@denx.de>
Cc: Phil Sutter <phil@nwl.cc>
Cc: Mario Six <mario.six@gdsys.cc>
Cc: Baruch Siach <baruch@tkos.co.il>
Reviewed-by: Stefan Roese <sr@denx.de>
3 years agoarm: mvebu: turris_mox: Enable NVMe support
Marek Behún [Fri, 5 Feb 2021 14:32:31 +0000 (15:32 +0100)]
arm: mvebu: turris_mox: Enable NVMe support

NVMe drives can be connected to Turris MOX via MOX B and MOX G
extensions.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
3 years agoarm: mvebu: turris_mox: Enable CONFIG_USB_XHCI_PCI
Pali Rohár [Fri, 5 Feb 2021 14:32:30 +0000 (15:32 +0100)]
arm: mvebu: turris_mox: Enable CONFIG_USB_XHCI_PCI

USB devices can be connected to Turris MOX also via MOX F extension which
contains VL805 PCIe based USB 3.0 controller.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
3 years agoarm: mvebu: turris_mox: Enable CONFIG_PCI_PNP
Pali Rohár [Fri, 5 Feb 2021 14:32:29 +0000 (15:32 +0100)]
arm: mvebu: turris_mox: Enable CONFIG_PCI_PNP

PCIe devices do not work in U-Boot without proper initialization and
configuration of PCI config space like the PCI_BASE_ADDRESS_0 register.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
3 years agoarm: a37xx: pci: Set Max Payload Size and Max Read Request Size to 512 bytes
Pali Rohár [Fri, 5 Feb 2021 14:32:28 +0000 (15:32 +0100)]
arm: a37xx: pci: Set Max Payload Size and Max Read Request Size to 512 bytes

Fix usage of VL805 XHCI PCIe controller when it is connected via PCIe to
Armada 3720 SOC. Without this U-Boot crashes when trying to access
enumerated USB devices connected to this XHCI PCIe controller.

This should be done according to the PCIe Link Initialization sequence, as
defined in Marvell Armada 3720 Functional Specification.

Linux has this code too.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
3 years agomtd: spi-nor-ids: Add support of flash protection to w25q128
Su Baocheng [Mon, 25 Jan 2021 02:59:05 +0000 (10:59 +0800)]
mtd: spi-nor-ids: Add support of flash protection to w25q128

The NOR flash w25q128 denoted by JEDEC ID 0xef4018 actually represents
various models. From Winbond's website, I could only find 3 types of
them:

    W25Q128JV-IQ/JQ
    datasheet:https://www.winbond.com/resource-files/
w25q128jv%20revg%2004082019%20plus.pdf

    W25Q128FV (SPI Mode)
    datasheet: https://www.winbond.com/resource-files/
w25q128fv%20rev.m%2005132016%20kms.pdf

    W25Q128BV
    datesheet: https://www.winbond.com/resource-files/
w25q128bv_revh_100313_wo_automotive.pdf

According to the datasheets, all of these 3 types support BP(0,1,2) and
TB bits in the status register (SR), so it could reuse the flash
protection logic for ST Micro.

So it should be safe to add the SPI_NOR_HAS_LOCK and SPI_NOR_HAS_TB
flags to the w25q128 entry of spi_nor_ids table.

Signed-off-by: Su Baocheng <baocheng.su@siemens.com>
[jagan: remove comments in spi-nor-ids.c]
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
3 years agomtd: spi-nor.h: Change spaces to tabs
Bin Meng [Wed, 6 Jan 2021 12:58:54 +0000 (20:58 +0800)]
mtd: spi-nor.h: Change spaces to tabs

U-Boot coding convention prefers tabs over spaces.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
3 years agomtd: spi-nor-ids: Add Gigadevice GD25LQ64C
Alper Nebi Yasak [Sat, 31 Oct 2020 16:20:12 +0000 (19:20 +0300)]
mtd: spi-nor-ids: Add Gigadevice GD25LQ64C

Add GD25LQ24C 64Mbit chip to spi-nor id table. This chip is used on
rk3399-gru-kevin:

    => sf probe
    SF: Detected gd25lq64c with page size 256 Bytes, erase size 4 KiB, total 8 MiB
    => sf erase 0x600000 0x200000
    SF: 2097152 bytes @ 0x600000 Erased: OK
    => sf test 0x700000 0x1000
    SPI flash test:
    0 erase: 52 ticks, 76 KiB/s 0.608 Mbps
    1 check: 5 ticks, 800 KiB/s 6.400 Mbps
    2 write: 14 ticks, 285 KiB/s 2.280 Mbps
    3 read: 3 ticks, 1333 KiB/s 10.664 Mbps
    Test passed
    0 erase: 52 ticks, 76 KiB/s 0.608 Mbps
    1 check: 5 ticks, 800 KiB/s 6.400 Mbps
    2 write: 14 ticks, 285 KiB/s 2.280 Mbps
    3 read: 3 ticks, 1333 KiB/s 10.664 Mbps

The values are the same as in Linux, except adjusted for the U-Boot
definition of INFO().

Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
3 years agospi: imx: Implement set_speed
Marek Vasut [Wed, 3 Feb 2021 16:53:57 +0000 (17:53 +0100)]
spi: imx: Implement set_speed

The set_speed() callback should configure the bus speed, make it so.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
3 years agoMerge branch '2021-02-25-remove-platforms'
Tom Rini [Thu, 25 Feb 2021 18:18:27 +0000 (13:18 -0500)]
Merge branch '2021-02-25-remove-platforms'

- Remove various older platforms that are missing DM migrations and have
  had their removal ack'd.

3 years agoppc: Remove MPC8569MDS board
Tom Rini [Sun, 21 Feb 2021 01:06:29 +0000 (20:06 -0500)]
ppc: Remove MPC8569MDS board

This board has not been converted to CONFIG_DM_MMC by the deadline.
Remove it.  As this is the last ARCH_MPC8569 board, remove that support
as well.

Cc: Priyanka Jain <priyanka.jain@nxp.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>