Scott Wood [Wed, 8 Aug 2012 15:06:18 +0000 (15:06 +0000)]
powerpc/mpc85xx/p1_p2_rdb: add all LAWs during SPL
LAW init is skipped in the SPL payload because it's assumed that the SPL
has taken care of it -- so make sure the SPL loads all the LAWs as is
done on other boards.
This bug was introduced by:
commit
4589728e214958a4e6e011a081a68d360c49d7a5
Author: Kumar Gala <galak@kernel.crashing.org>
Date: Fri Nov 11 08:14:53 2011 -0600
powerpc/85xx: Fix builds of P1020/P2020RDB-PC_36BIT_NAND
Size grew a bit so nand-spl didn't fit in 4k, reduce done by removing
LAW entries not needed during SPL phase.
Signed-off-by: Scott Wood <scottwood@freescale.com>
Andy Fleming [Thu, 23 Aug 2012 17:00:31 +0000 (12:00 -0500)]
Revert "powerpc: Fix declaration type for I/O functions"
This reverts commit
20959471b5d07fdeb8603b918d80385aa2954711.
Scott Wood [Mon, 20 Aug 2012 13:16:30 +0000 (13:16 +0000)]
powerpc/p1_p2_rdb_pc: print -PC suffix in board name
Currently the -PC variants of the P1/P2 RDB boards do not print it on boot --
e.g. a P2020RDB-PC will claim to be a plain P2020RDB. Besides being incorrect,
this can confuse a user into building U-Boot for P2020RDB rather than P2020RDB-PC,
resulting in a board that does not boot.
P1024RDB and P1025RDB are not included, as these boards apparently do not
have -PC as part of their name, even though they are supported by p1_p2_rdb_pc.
The P2020RDB variant covered by this is apparently P2020RDB-PCA rather
than P2020RDB-PC.
Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Scott Wood [Mon, 20 Aug 2012 13:10:08 +0000 (13:10 +0000)]
powerpc/85xx: clear out TLB on boot
Instead of just shooting down the entry that covers CCSR, clear out
every TLB entry that isn't the one that we're executing out of.
Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
York Sun [Fri, 17 Aug 2012 09:00:54 +0000 (09:00 +0000)]
powerpc/mpc8xxx: Move HWCONFIG_BUFFER_SIZE into config.h
Before proper environment is setup, we extract hwconfig and put it into a
buffer with size HWCONFIG_BUFFER_SIZE. We need to enlarge the buffer to
accommodate longer string. Since this macro is used in multiple files, we
move it into arch/powerpc/include/asm/config.h.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
York Sun [Fri, 17 Aug 2012 08:22:43 +0000 (08:22 +0000)]
powerpc/mpc8xxx DDR: Fix interactive DDR debugging
Add one more argument to call function readline_into_buffer().
Fix print SPD format for negative values.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
York Sun [Fri, 17 Aug 2012 08:22:42 +0000 (08:22 +0000)]
powerpc/mpc8xxx DDR: Fall back to raw timing for first controller only
Only the first DIMM of first controller should fall back to raw timing
parameters if SPD is missing or corrupted.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
York Sun [Fri, 17 Aug 2012 08:22:41 +0000 (08:22 +0000)]
powerpc/mpc8xxx DDR: Fix CAS latency calculation
Empty slot should be skipped when calculating CAS latency.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
York Sun [Fri, 17 Aug 2012 08:22:40 +0000 (08:22 +0000)]
powerpc/mpc8xxx: Fix bug for extended DDR timing
Faster DDR3 timing requires parameters exceeding previously defined
range. Extended parameters are fixed. Added some debug messages.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
York Sun [Fri, 17 Aug 2012 08:22:39 +0000 (08:22 +0000)]
powerpc/mpc8xxx: Enable 3-way and 4-way DDR interleaving
Restructure DDR interleaving option to support 3 and 4 DDR controllers
for 2-, 3- and 4-way interleaving.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
York Sun [Fri, 17 Aug 2012 08:22:38 +0000 (08:22 +0000)]
powerpc/mpc8xxx: Add support for cas latency 12 and above
Required by JEDEC 79-3E for high speed DDR3.
Also change "CSn disabled" message to debug.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
York Sun [Fri, 17 Aug 2012 08:22:37 +0000 (08:22 +0000)]
powerpc/mpc8xxx: Add fine timing support for DDR3
When the DDR3 speed goes higher, we need to utilize fine offset
from SPD.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
York Sun [Fri, 17 Aug 2012 08:22:36 +0000 (08:22 +0000)]
powerpc/mpc85xx: Skip zero values for DDR debug registers
Some debug registers have non-zero default out of reset. If software is
not setting debug registers, skip writing to them to avoid unnecessary
overriding.
Also add debug messages for workarounds and debug registers.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
York Sun [Fri, 17 Aug 2012 08:20:26 +0000 (08:20 +0000)]
powerpc/mpc8xxx: fix core id for multicore booting
For the cores with multiple threads, we need to figure out which physical
core a thread belongs. To match the core ids, update PIR registers and
spin tables.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Kumar Gala [Fri, 17 Aug 2012 08:20:25 +0000 (08:20 +0000)]
Added new ext fields to IFC
In case more than 32 bit address is used, the EXT bit should be set.
Need to fix up address map for IFC #CS for 4, also need to move # of IFC
banks into config_mpc85xx.h
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Kumar Gala [Fri, 17 Aug 2012 08:20:24 +0000 (08:20 +0000)]
Add IFC offset for DPAA/Corenet platforms
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Kumar Gala [Fri, 17 Aug 2012 08:20:23 +0000 (08:20 +0000)]
Add e6500 processor detection
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
York Sun [Fri, 17 Aug 2012 08:20:22 +0000 (08:20 +0000)]
powerpc/mpc8xxx: use topology registers to calculate number of cores
We have actual topology infomation to find out exactly which core is present.
Calculate the number of cores if not specified.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
York Sun [Fri, 17 Aug 2012 08:20:21 +0000 (08:20 +0000)]
powerpc/mpc8xxx: Add immap for topology and rcpm registers
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Prabhakar Kushwaha [Wed, 15 Aug 2012 06:24:15 +0000 (06:24 +0000)]
powerpc/mpc85xx: Add IFC LAW target ID for FSL High-End SoC
Freescale's High-End SoC are going to have Integrated Flash controller
(IFC)'s support.
So add IFC LAW target ID support for High-End SoC or corenet SoC.
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Prabhakar Kushwaha [Wed, 15 Aug 2012 04:12:43 +0000 (04:12 +0000)]
powerpc/mpc85xx:Enable debugger support to missed e500v2 SoC
Freescale's e500v1 and e500v2 cores (used in mpc85xx chips) have some
restrictions on external debugging (JTAG). Need to define define
CONFIG_SYS_PPC_E500_DEBUG_TLB to enable a temporary TLB entry to be
used during boot to work around the limitations.
Enable missed e500v2 SoC i.e. MPC8536, MPC8544, MPC8548 and MPC8572 for
debug support.
Signed-off-by: Radu Lazarescu <radu.lazarescu@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Cc: Tang Yuantian <Yuantian.Tang@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Scott Wood [Tue, 14 Aug 2012 10:14:53 +0000 (10:14 +0000)]
powerpc/fsl-corenet: work around erratum A004510
Erratum A004510 says that under certain load conditions, modified
cache lines can be discarded, causing data corruption.
To work around this, several CCSR and DCSR register updates need to be
made in a careful manner, so that there is no other transaction in
corenet when the update is made.
The update is made from a locked cacheline, with a delay before to flush
any previous activity, and a delay after to flush the CCSR/DCSR update.
We can't use a readback because that would be another corenet
transaction, which is not allowed.
We lock the subsequent cacheline to prevent it from being fetched while
we're executing the previous cacheline. It is filled with nops so that a
branch doesn't cause us to fetch another cacheline.
Ordinarily we are running in a cache-inhibited mapping at this point, so
we temporarily change that. We make it guarded so that we should never
see a speculative load, and we never do an explicit load. Thus, only the
I-cache should ever fill from this mapping, and we flush/unlock it
afterward. Thus we should avoid problems from any potential cache
aliasing between inhibited and non-inhibited mappings.
NOTE that if PAMU is used with this patch, it will need to use a
dedicated LAW as described in the erratum. This is the responsibility
of the OS that sets up PAMU.
Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Scott Wood [Tue, 14 Aug 2012 10:14:51 +0000 (10:14 +0000)]
powerpc/fsl-corenet: remove dead variant symbols
These are not supported as individual build targets, but instead
are supported by another target.
The dead p4040 defines in particular had bitrotted significantly.
Signed-off-by: Scott Wood <scottwood@freescale.com>
Acked-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Timur Tabi [Tue, 14 Aug 2012 06:47:27 +0000 (06:47 +0000)]
powerpc/85xx: remove support for the Freescale P3060
The P3060 was cancelled before it went into production, so there's no point
in supporting it.
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Timur Tabi [Tue, 14 Aug 2012 06:47:25 +0000 (06:47 +0000)]
powerpc/85xx: get rid of enum board_slots in P4080 MDIO driver
enum board_slots contained six values, where SLOT1 == 1, SLOT2 == 2, and
so on. This is pointless, so remove it. Also move the lane_to_slot[]
array to the top of the file so that it can be used by other functions.
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Timur Tabi [Tue, 14 Aug 2012 06:47:24 +0000 (06:47 +0000)]
fm-eth: use fdt_status_disabled() function in ft_fixup_port()
We have a dedicated function for setting the node status now, so use it.
Also improve a comment and fix the type of the phandle variable.
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Timur Tabi [Tue, 14 Aug 2012 06:47:23 +0000 (06:47 +0000)]
powerpc/85xx: introduce function serdes_device_from_fm_port()
In order to figure out which SerDes lane a given Fman port is connected
to, we need a function that maps the fm_port namespace to the srds_prtcl
namespace.
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Timur Tabi [Tue, 14 Aug 2012 06:47:22 +0000 (06:47 +0000)]
fm-eth: add function fm_info_get_phy_address()
Function fm_info_get_phy_address() returns the PHY address for a given
Fman port. This is handy when the MDIO code needs to fixup the Ethernet
nodes in the device tree to point to PHY nodes for a specific PHY address.
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Timur Tabi [Tue, 14 Aug 2012 06:47:21 +0000 (06:47 +0000)]
powerpc/85xx: add support for FM2 DTSEC5
Unlike previous SOCs, the Freescale P5040 has a fifth DTSEC on the second
Fman, so add the Fman and SerDes macros for that DTSEC.
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Paul Gortmaker [Mon, 13 Aug 2012 13:48:57 +0000 (13:48 +0000)]
mpc85xx: use LCRR_DBYP define instead of raw constant
Using the raw value of 0x80000000 directly in the code can
lead to "count the zeros" bugs like that fixed in commit
718e9d13b98 ("MPC85xxCDS: Fix missing LCRR_DBYP bits for
66-133MHz LBC")
Change all existing raw values to use the symbolic value of
LCRR_DBYP instead.
Cc: Kumar Gala <galak@kernel.crashing.org>
Cc: Scott Wood <scottwood@freescale.com>
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Matthew McClintock [Mon, 13 Aug 2012 08:10:42 +0000 (08:10 +0000)]
nand_spl: change out_be32 to raw_writel and depend on subsequent sync
This change reduces the SPL size by removing the redundant syncs produced
by out_be32 and just replies on one final sync
Done with:
sed -r '/in_be32/b; s/(out_be32)\(([^,]*),\s+(.*)\)/__raw_writel(\3, \2)/g' -i `git grep --name-only sdram_init nand_spl/`
Signed-off-by: Matthew McClintock <msm@freescale.com>
Acked-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Matthew McClintock [Mon, 13 Aug 2012 10:00:40 +0000 (10:00 +0000)]
nand_spl: p1023rds: wait before enabling DDR controller
We have a requirement to wait a period of time before enabling the
DDR controller
Signed-off-by: Matthew McClintock <msm@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Matthew McClintock [Mon, 13 Aug 2012 13:21:19 +0000 (13:21 +0000)]
nand_spl: update udelay for Freescale boards
Let's use the more appropriate udelay for the nand_spl. While we
can't make use of u-boot's full udelay we can atl east use a for
loop that won't get optimized away .Since we have the bus clock
we can use the timebase to calculate wall time.
Looked at reusing the u-boot udelay functions but it pulls in a lot
of code and would require quite a bit of work to keep us within the
very small space constrains we currently have
Signed-off-by: Matthew McClintock <msm@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Matthew McClintock [Mon, 13 Aug 2012 08:10:39 +0000 (08:10 +0000)]
powerpc/p1010rdb: nandboot: compare SVR properly
We were not comparing the SVRs properly previously. This comparison
will properly shift the SVR and mask off the E bit
This fixes the boot output to show the correct DDR bus width:
512 MiB (DDR3, 16-bit, CL=5, ECC off)
instead of
512 MiB (DDR3, 32-bit, CL=5, ECC off)
Signed-off-by: Matthew McClintock <msm@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Matthew McClintock [Mon, 13 Aug 2012 08:10:38 +0000 (08:10 +0000)]
p1010rdb: fix ddr values for p1014rdb (setting bus width to 16bit)
There was an extra 0 in front of the value we were using to mask,
remove it to improve the code.
Also fix the value written to ddr_sdram_cfg to set the bus width
properly to 16 bits
Signed-off-by: Matthew McClintock <msm@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Matthew McClintock [Mon, 13 Aug 2012 08:10:37 +0000 (08:10 +0000)]
p1014rdb: set ddr bus width properly depending on SVR
Currently, for NAND boot for the P1010/4RDB we hard code the DDR
configuration. We can still dynamically set the DDR bus width in
the nand spl so the P1010/4RDB boards can boot from the same
u-boot image
Signed-off-by: Matthew McClintock <msm@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
York Sun [Fri, 10 Aug 2012 11:07:26 +0000 (11:07 +0000)]
powerpc/mpc8xxx: Remove P1015 and P1016 from CPU list
P1015 is the same as P1011 and P1016 is the same as P1012 from software
point of view. They have different packages but share SVRs.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Shaohui Xie [Fri, 10 Aug 2012 02:49:35 +0000 (02:49 +0000)]
powerpc/CoreNet: add tool to support pbl image build.
Provides a tool to build boot Image for PBL(Pre boot loader) which is
used on Freescale CoreNet SoCs, PBL can be used to load some instructions
and/or data for pre-initialization. The default output image is u-boot.pbl,
for more details please refer to doc/README.pblimage.
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Liu Gang [Thu, 9 Aug 2012 05:10:03 +0000 (05:10 +0000)]
powerpc/corenet_ds: Slave module for boot from PCIE
When boot from PCIE, slave's core should be in holdoff after powered on for
some specific requirements. Master will release the slave's core at the
right time by PCIE interface.
Slave's ucode and ENV can be stored in master's memory space, then slave
can fetch them through PCIE interface. For the corenet platform, ucode is
for Fman.
NOTE: Because the slave can not erase, write master's NOR flash by
PCIE interface, so it can not modify the ENV parameters stored
in master's NOR flash using "saveenv" or other commands.
environment and requirement:
master:
1. NOR flash for its own u-boot image, ucode and ENV space.
2. Slave's u-boot image is in master NOR flash.
3. Put the slave's ucode and ENV into it's own memory space.
4. Normally boot from local NOR flash.
5. Configure PCIE system if needed.
slave:
1. Just has EEPROM for RCW. No flash for u-boot image, ucode and ENV.
2. Boot location should be set to one PCIE interface by RCW.
3. RCW should configure the SerDes, PCIE interfaces correctly.
4. Must set all the cores in holdoff by RCW.
5. Must be powered on before master's boot.
For the slave module, need to finish these processes:
1. Set the boot location to one PCIE interface by RCW.
2. Set a specific TLB entry for the boot process.
3. Set a LAW entry with the TargetID of one PCIE for the boot.
4. Set a specific TLB entry in order to fetch ucode and ENV from
master.
5. Set a LAW entry with the TargetID one of the PCIE ports for
ucode and ENV.
6. Slave's u-boot image should be generated specifically by
make xxxx_SRIO_PCIE_BOOT_config.
This will set SYS_TEXT_BASE=0xFFF80000 and other configurations.
In addition, the processes are very similar between boot from SRIO and
boot from PCIE. Some configurations like the address spaces can be set to
the same. So the module of boot from PCIE was added based on the existing
module of boot from SRIO, and the following changes were needed:
1. Updated the README.srio-boot-corenet to add descriptions about
boot from PCIE, and change the name to
README.srio-pcie-boot-corenet.
2. Changed the compile config "xxxx_SRIOBOOT_SLAVE" to
"xxxx_SRIO_PCIE_BOOT", and the image builded with
"xxxx_SRIO_PCIE_BOOT" can support both the boot from SRIO and
from PCIE.
3. Updated other macros and documents if needed to add information
about boot from PCIE.
Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Liu Gang [Thu, 9 Aug 2012 05:10:02 +0000 (05:10 +0000)]
powerpc/corenet_ds: Master module for boot from PCIE
For the powerpc processors with PCIE interface, boot location can be
configured from one PCIE interface by RCW. The processor booting from PCIE
can do without flash for u-boot image. The image can be fetched from another
processor's memory space by PCIE link connected between them.
The processor booting from PCIE is slave, the processor booting from normal
flash memory space is master, and it can help slave to boot from master's
memory space.
When boot from PCIE, slave's core should be in holdoff after powered on for
some specific requirements. Master will release the slave's core at the
right time by PCIE interface.
Environment and requirement:
master:
1. NOR flash for its own u-boot image, ucode and ENV space.
2. Slave's u-boot image is in master NOR flash.
3. Normally boot from local NOR flash.
4. Configure PCIE system if needed.
slave:
1. Just has EEPROM for RCW. No flash for u-boot image, ucode and ENV.
2. Boot location should be set to one PCIE interface by RCW.
3. RCW should configure the SerDes, PCIE interfaces correctly.
4. Must set all the cores in holdoff by RCW.
5. Must be powered on before master's boot.
For the master module, need to finish these processes:
1. Initialize the PCIE port and address space.
2. Set inbound PCIE windows covered slave's u-boot image stored in
master's NOR flash.
3. Set outbound windows in order to configure slave's registers
for the core's releasing.
4. Should set the environment variable "bootmaster" to "PCIE1", "PCIE2"
or "PCIE3" using the following command:
setenv bootmaster PCIE1
saveenv
Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Liu Gang [Thu, 9 Aug 2012 05:10:01 +0000 (05:10 +0000)]
powerpc/corenet_ds: Update README and README.srio-pcie-boot-corenet
Added descriptions about boot from PCIE in the files README and
doc/README.srio-pcie-boot-corenet, and changed the name of the
doc/README.srio-boot-corenet to doc/README.srio-pcie-boot-corenet.
Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Liu Gang [Thu, 9 Aug 2012 05:10:00 +0000 (05:10 +0000)]
powerpc/corenet_ds: Get rid of the CONFIG_SRIOBOOT_SLAVE_PORTx macro
When compile the slave image for boot from SRIO, no longer need to
specify which SRIO port it will boot from. The code will get this
information from RCW and then finishes corresponding configurations.
This has the following advantages:
1. No longer need to rebuild an image when change the SRIO port for
boot from SRIO, just rewrite the new RCW with selected port,
then the code will get the port information by reading new RCW.
2. It will be easier to support other boot location options, for
example, boot from PCIE.
Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Liu Gang [Thu, 9 Aug 2012 05:09:59 +0000 (05:09 +0000)]
powerpc/corenet_ds: Get rid of the SRIOBOOT_MASTER build target
Get rid of the SRIOBOOT_MASTER build target, and to support for serving as
a SRIO boot master via environment variable. Set the environment variable
"bootmaster" to "SRIO1" or "SRIO2" using the following command:
setenv bootmaster SRIO1
saveenv
The "bootmaster" will enable the function of the SRIO boot master, and
this has the following advantages compared with SRIOBOOT_MASTER build
configuration:
1. Reduce a build configuration item in boards.cfg file.
No longer need to build a special image for master, just use a
normal target image and set the "bootmaster" variable.
2. No longer need to rebuild an image when change the SRIO port for
boot from SRIO, just set the corresponding value to "bootmaster"
based on the using SRIO port.
Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Liu Gang [Thu, 9 Aug 2012 05:09:58 +0000 (05:09 +0000)]
powerpc/corenet_ds: Update README.srio-boot-corenet
Update some descriptions due to the implementation changes:
For master:
Get rid of the SRIOBOOT_MASTER build target, and to support
for serving as a SRIO boot master via environment variable.
For slave:
1. When compile the slave image for boot from SRIO, no longer
need to specify which SRIO port it will boot from.
2. All slave's cores should be in hold off.
Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
York Sun [Wed, 8 Aug 2012 18:04:53 +0000 (18:04 +0000)]
powerpc/mpc85xx: Make NMG_CPU_A011 workaround conditional
This erratum applies to the following SoCs:
P4080 rev 1.0, 2.0, fixed in rev 3.0
P2041 rev 1.0, 1.1, fixed in rev 2.0
P3041 rev 1.0, 1.1, fixed in rev 2.0.
Workaround for erratum NMG_CPU_A011 is enabled by default. This workaround
may degrade performance. P4080 erratum CPU22 shares the same workaround.
So it is always enabled for P4080. For other SoCs, it can be disabled by
hwconfig with syntax:
fsl_cpu_a011:disable
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Scott Wood [Wed, 8 Aug 2012 15:03:33 +0000 (15:03 +0000)]
nand/fsl_elbc: shrink SPL a bit by converting out_be32() to __raw_writel()
This is needed to make room for a bugfix on p1_p2_rdb_pc. A sync is used
before the final write to LSOR that initiates the transaction, to ensure
all the other set up has been completed.
Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Joakim Tjernlund [Mon, 23 Jul 2012 10:58:03 +0000 (10:58 +0000)]
powerpc: Stack Pointer not properly aligned
The code first aligns the SP to 16 then subtract 8, making it
8 bytes aligned. Furthermore the initial stack frame not
quite correct either.
Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Joakim Tjernlund [Mon, 23 Jul 2012 10:58:02 +0000 (10:58 +0000)]
mpc85xx: Initial SP alignment is wrong.
PowerPC mandates SP to be 16 bytes aligned.
Furthermore, a stack frame is added, pointing to the reset vector
which may in the way when gdb is walking the stack because
the reset vector may not accessible depending on emulator settings.
Also use a temp register so gdb doesn't pick up intermediate values.
Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
Acked-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Scott Wood [Tue, 14 Aug 2012 01:44:29 +0000 (01:44 +0000)]
Makefile: fix HAVE_VENDOR_COMMON_LIB
Commit
8b5a02640adf77301f943e8754992c50df004e8a ("Makefile: cosmetic:
optimize usage of LIBS-y") broke the build of boards that have a board
vendor "common" directory, by introducing a space between "LIBS-" and
"y".
Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Acked-by: Kim Phillips <kim.phillips@freescale.com>
Holger Brunck [Thu, 9 Aug 2012 08:22:41 +0000 (10:22 +0200)]
mtd/cfi_flash: fix write problems for Numonyx P33/30 32 MBit flashs
commit
54652991
Work around bug in Numonyx P33/P30 256-Mbit 65nm flash chips
fixes a problem for Numonyx P33/P30 flashes for 256-Mbit, but this leads
to problems for smaller versions of this chip e.g. the 32Mbit version
with deviceid 0x16 on mgcoge. So move the code for this work around to
an own function and check previously manufacturer id and device id to
not break other flashes which don't need this work around.
Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
Signed-off-by: Heiko Schocher <hs@denx.de>
cc: Stefan Roese <sr@denx.de>
cc: Philippe De Muyter <phdm@macqel.be>
cc: Gerlando Falauto <gerlando.falauto@keymile.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Anatolij Gustschin [Thu, 9 Aug 2012 06:18:12 +0000 (08:18 +0200)]
cfi_flash: add support for Spansion flash PPB sector protection
Erasing flash sectors protected with persistent protection bit (PPB)
mechanism on Spansion flash chips doesn't work. Add sector protection
status checking and sector lock and unlock commands to fix this.
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Cc: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
Horst Kronstorfer [Fri, 13 Jul 2012 03:03:40 +0000 (03:03 +0000)]
dts/Makefile: Turn off some predefined macros
Add '-ansi' to DTS_CPPFLAGS to avoid unwanted expansion of dts content
that matches some predefined macros.
Example: A number of PowerPC related *.dts files in the kernel define a
property named 'linux,network-index' which (w/o '-ansi') is expanded to
'1,network-index' by the preprocessor because of '#define linux 1.'
Signed-off-by: Horst Kronstorfer <hkronsto@frequentis.com>
Kenth Eriksson [Thu, 12 Jul 2012 19:59:44 +0000 (19:59 +0000)]
Add support for DS1388.
Support for DS1388 is added by extending the DS1337 driver. DS1388 is
similar to DS1337. The time registers are offset by 1 (due to support
for hundreds of seconds), and there is no century bit.
The configuration and trickle charge registers are also different.
Tested on hardware with Freescale P2010 and DS1388.
Signed-off-by: Kenth Eriksson <kenth.eriksson@transmode.com>
Horst Kronstorfer [Thu, 12 Jul 2012 02:58:32 +0000 (02:58 +0000)]
dts/Makefile: Check for empty $(LDSCRIPT)
Make sure that $(LDSCRIPT) is not empty before calling process_lds
with 'cat $(LDSCRIPT)' else cat will block waiting for input from
stdin.
Signed-off-by: Horst Kronstorfer <hkronsto@frequentis.com>
Daniel Schwierzeck [Thu, 19 Jul 2012 13:39:58 +0000 (13:39 +0000)]
Makefile: cosmetic: optimize usage of LIBS-y
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Daniel Schwierzeck [Thu, 28 Jun 2012 06:45:20 +0000 (06:45 +0000)]
Makefile: replace LIBS by LIBS-y
Synchronize with ALL-y handling and code in spl/Makefile.
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Acked-by: Mike Frysinger <vapier@gentoo.org>
Daniel Schwierzeck [Thu, 28 Jun 2012 06:45:19 +0000 (06:45 +0000)]
Makefile: allow appending to LIB in sub-makefiles
The top Makefile and the SPL Makefile have lines like those:
ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP34XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX),)
LIBS += $(CPUDIR)/omap-common/libomap-common.o
endif
ifeq ($(SOC),mx5)
LIBS += $(CPUDIR)/imx-common/libimx-common.o
endif
This should be done in the arch/CPU/SoC specific sub-makefiles to
keep the top Makefiles clean. This patch also allows adding of new
arch/CPU/SoC specific libraries in the future without touching
the top Makefiles.
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Acked-by: Mike Frysinger <vapier@gentoo.org>
Mike Frysinger [Mon, 6 Aug 2012 13:46:37 +0000 (13:46 +0000)]
nds32: fix unused pmu_init warning
Fixes the build-time warning:
board.c: At top level:
board.c:106: warning: 'pmu_init' defined but not used
This makes the ifdef logic at the call site match the logic at the
function definition.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Mike Frysinger [Mon, 6 Aug 2012 13:46:36 +0000 (13:46 +0000)]
nds32: delete unused local variable
Fixes the build-time warning:
board.c: In function 'board_init_r':
board.c:304: warning: unused variable 's'
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Mike Frysinger [Mon, 6 Aug 2012 13:46:35 +0000 (13:46 +0000)]
nds32: drop bi_enetaddr from global data
Nothing is using this, so punt it from the gd. Seems to just be a copy
& paste wart from the initial port.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Jorgen Lundman [Thu, 19 Jul 2012 20:48:25 +0000 (20:48 +0000)]
zfs: Add ZFS filesystem support
U-Boot port is based on sources forked from GRUB-0.97 by Sun in 2004,
which can be found here:
http://src.opensolaris.org/source/xref/onnv/onnv-gate/usr/src/grub/grub-0.97/stage2/zfs-include/zfs.h
Released by Sun for GRUB under the license:
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
GRUB official releases include ZFS in version:
ftp://alpha.gnu.org/gnu/grub/grub-1.99~rc1.tar.gz
And patched against GRUB Bazaar repository for ashift fixes (4KB HDDs)
more conveniently found at github:
https://github.com/pendor/grub-zfs/commit/
e7b6ef3ac3b9685ac4c394c897b1d4221b7381f1
Signed-off-by: Jorgen Lundman <lundman@lundman.net>
Charles Manning [Wed, 9 May 2012 16:55:17 +0000 (16:55 +0000)]
u-boot: Update yaffs2 file system
This patch updates the yaffs2 in u-boot to correspond to
git://www.aleph1.co.uk/yaffs2
commit id
9ee5d0643e559568dbe62215f76e0a7bd5a63d93
Signed-off-by: Charles Manning <cdhmanning@gmail.com>
Julius Baxter [Sat, 5 May 2012 12:32:11 +0000 (12:32 +0000)]
openrisc: Work around potential relocation issues
When reset code is in flash, the jump instructions emitted by the
compiler are relative instead of absolute jumps.
A fix to the reset code to make correct jumps to the beginning of
code relocated to RAM have also been added.
Signed-off-by: Julius Baxter <juliusbaxter@gmail.com>
Jens Scharsig [Wed, 2 May 2012 00:57:08 +0000 (00:57 +0000)]
rename EB+MCF-EV123 to its current marketing name EB+CPU5282
* rename board directory to eb_cpu5282
* rename EB+MCF-EV123_.*config to eb_cpu5282_.*config
* add Maintainer for EB+CPU5282 board
* rename prompt
Signed-off-by: Jens Scharsig (BuS Elektronik) <esw@bus-elektronik.de>
Dirk Eibach [Thu, 26 Apr 2012 01:49:33 +0000 (01:49 +0000)]
Consider CONFIG_ZERO_BOOTDELAY_CHECK when CONFIG_AUTOBOOT_KEYED is set
When CONFIG_ZERO_BOOTDELAY_CHECK is not defined, bootdelay==0
prevents the check for console input (as stated in README.autoboot).
This must also work in CONFIG_AUTOBOOT_KEYED mode.
Signed-off-by: Dirk Eibach <eibach@gdsys.de>
Allen Martin [Thu, 19 Apr 2012 07:58:57 +0000 (07:58 +0000)]
mkconfig: add support for SPL CPU
Add support for specifying a differnt CPU for main u-boot and SPL
u-boot builds. This is done by adding an optional SPL CPU after the
main CPU in boards.cfg as follows:
normal_cpu:spl_cpu
This this case CPU will be set to "normal_cpu" during the main u-boot
build and "spl_cpu" during the SPL build.
Signed-off-by: Allen Martin <amartin@nvidia.com>
Fabio Estevam [Fri, 13 Apr 2012 05:51:36 +0000 (05:51 +0000)]
configs: Remove unused symbol CONFIG_DISCOVER_PHY
CONFIG_DISCOVER_PHY is not used anywhere, so remove it from config files.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Timo Ketola [Wed, 11 Apr 2012 23:33:49 +0000 (23:33 +0000)]
Build: Ignore build tree and IDE control file
Signed-off-by: Timo Ketola <timo@exertus.fi>
Prabhakar Kushwaha [Tue, 10 Apr 2012 22:49:12 +0000 (22:49 +0000)]
powerpc: Fix declaration type for I/O functions
Prototype declaration of I/O operation functions are not correct. as both
'extern' and function definition are at same place.
Chage protoype declaration as static.
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Prabhakar Kushwaha [Tue, 10 Apr 2012 22:48:59 +0000 (22:48 +0000)]
powerpc:Fix return type & parameter passed for I/O functions
Return type of in_8, in_be16 and in_le16 should not be'int'. Update it to type
u8/u16/u32.
Although 'unsigned' for in_be32 and in_le32 is correct. But to make return type
uniform across the file changed to u32
Similarly, parameter passed to out_8, out_be16, out_le16 ,out_be32 & out_le32
should not be 'int'.Change it to type u8/u16/u32.
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Bernhard Walle [Mon, 2 Apr 2012 01:58:34 +0000 (01:58 +0000)]
UBIFS: Improve error message when reading superblock failed
In addition to the error message also display the error code. I had the
problem that my malloc memory was not enough (ENOMEM), and if u-boot
had displayed the error code immediately that would have saved me some
debugging.
Signed-off-by: Bernhard Walle <walle@corscience.de>
Use ubifs_err instead of printf.
Add "errno=%d" in output as suggested by Albert Aribaud.
Signed-off-by: Thomas Weber <weber@corscience.de>
Simon Glass [Fri, 30 Mar 2012 21:30:58 +0000 (21:30 +0000)]
sandbox: Add basic test for command execution
Since run_command() and run_command_list() are important and a little
confusing, add some basic tests to check that the behaviour is correct.
Note: I am not sure that this should be committed, nor where it should go
in the source tree. Comments welcome.
To run the unit tests use the ut_cmd command available in sandbox:
make sandbox_config
make
./u-boot -c ut_cmd
(To test both hush and built-in parsers, you need to manually change
CONFIG_SYS_HUSH_PARSER in include/configs/sandbox.h and build/run again)
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Fri, 30 Mar 2012 21:30:56 +0000 (21:30 +0000)]
Allow newlines within command environment vars
Any environment variable can hold commands to be executed by the 'run'
command. The environment variables preboot, bootcmd and menucmd have
special code for triggering execution in certain circumstances.
We adjust these calls to use run_command_list() instead of run_command().
This change permits these variables to have embedded newlines so that
they work the same as the 'source' command.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Fri, 30 Mar 2012 21:30:55 +0000 (21:30 +0000)]
Add run_command_list() to run a list of commands
This new function runs a list of commands separated by semicolon or newline.
We move this out of cmd_source so that it can be used by other code. The
PXE code also uses the new function.
Suggested-by: Michael Walle <michael@walle.cc>
Signed-off-by: Simon Glass <sjg@chromium.org>
Marek Vasut [Thu, 29 Mar 2012 09:28:15 +0000 (09:28 +0000)]
Malloc: Fix -Wundef warnings
In file included from arch/arm/lib/board.c:43:0:
include/malloc.h:490:5: warning: "HAVE_MMAP" is not defined [-Wundef]
include/malloc.h:590:5: warning: "HAVE_USR_INCLUDE_MALLOC_H" is not defined [-Wundef]
include/malloc.h:757:5: warning: "HAVE_MMAP" is not defined [-Wundef]
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Wolfgang Denk <wd@denx.de>
Mike Frysinger [Sun, 18 Mar 2012 14:31:24 +0000 (14:31 +0000)]
global_data: unify global flag defines
All the global flag defines are the same across all arches. So unify them
in one place, and add a simple way for arches to extend for their needs.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Andy Fleming [Wed, 8 Aug 2012 14:12:30 +0000 (14:12 +0000)]
MAKEALL: Allow empty ERR directory
If we build everything correctly with multiple builds, and an
ERR directory had been previously created, we failed to report
that everything was fine because grep failed to find anything
in the ERR directory. Use grep -r, which doesn't complain if
there are no input files.
Signed-off-by: Andy Fleming <afleming@freescale.com>
Tested-by: Tom Rini <trini@ti.com>
Wolfgang Denk [Thu, 9 Aug 2012 19:04:05 +0000 (21:04 +0200)]
Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx
* 'master' of git://git.denx.de/u-boot-mpc85xx:
powerpc/85xx: use CONFIG_SYS_FSL_PCIE_COMPAT macro when setting the PCI LIODNs
powerpc/mpc85xx: Ignore E bit for BSC9130/1
powerpc/sgmii: To support PHY link state auto detect in SGMII mode
powerpc/85xx: improve definition of BR_PHYS_ADDR macro
powerpc/p2041: configure the CPLD lane_mux according to RCW
powerpc/ddr: fix fsl_ddr_get_dimm_params compile error
powerpc/corenet: fix compile error when CONFIG_SYS_NO_FLASH is defined
powerpc/mpc8xxx: fix workaround for errata DDR111 and DDR134 for DDR over 4GB
powerpc/p1022ds: fix DIU/LBC switching with NAND enabled
powerpc/p1022ds: add support for SPI and SD boot
Signed-off-by: Wolfgang Denk <wd@denx.de>
Timur Tabi [Wed, 25 Jul 2012 11:03:34 +0000 (11:03 +0000)]
powerpc/85xx: use CONFIG_SYS_FSL_PCIE_COMPAT macro when setting the PCI LIODNs
The SET_PCI_LIODN() macro takes a compatible property string as a parameter, so that it knows
which PCI device tree node to look for. The calls to these macros are using a hard-coded string,
but we already have the CONFIG_SYS_FSL_PCIE_COMPAT macro which contains the same string, so we
should use that.
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
York Sun [Fri, 20 Jul 2012 10:59:38 +0000 (10:59 +0000)]
powerpc/mpc85xx: Ignore E bit for BSC9130/1
Commit
48f6a5c34 removed E bit. BSC9130/1 were left out due to patch apply
timing. Remove them now.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Hongtao Jia [Wed, 11 Jul 2012 23:39:53 +0000 (23:39 +0000)]
powerpc/sgmii: To support PHY link state auto detect in SGMII mode
PHYs on SGMII riser card are used in SGMII mode with different external
IRQs from eTSEC. This means in SGMII mode phy-handle and phy-connection-type
under ethernet node should be updated. Otherwise the PHY interrupt can not
be handled therefor PHY link state change can not be auto detected.
For we have seperate SGMII PHY nodes, ethernet PHY reg fixup is not needed
but it's still be kept to guarantee the sgmii mode could work with old
device tree.
Signed-off-by: Li Yang <leoli@freescale.com>
Signed-off-by: Jia Hongtao <B38951@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Timur Tabi [Fri, 6 Jul 2012 07:39:26 +0000 (07:39 +0000)]
powerpc/85xx: improve definition of BR_PHYS_ADDR macro
The BR_PHYS_ADDR(x) macro was missing parentheses around "x" in the macro
definition, so callers had to supply their own parenthesis.
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Shaohui Xie [Thu, 28 Jun 2012 23:37:25 +0000 (23:37 +0000)]
powerpc/p2041: configure the CPLD lane_mux according to RCW
Lane muxing on p2041 is controlled by a reg in CPLD, offset of this reg
is 0xc, CPLD supports SATA by default, we should re-configure the lane
muxing according to RCW, which indicates what SerDes protocol it is running.
Default lane muxing map is as below:
Lane G on bank1 routes to SGMII, controlled by bit 1 of the reg;
Lane A on bank2 routes to AURORA, controlled by bit 0 of the reg;
Lane C/D on bank2 routes to SATA0 and SATA1, controlled by bit 2
and bit 3 respectively.
Default value of these bits for lane muxing is '1', we should set or clear
these bits accoring to RCW.
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Acked-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Shaohui Xie [Thu, 28 Jun 2012 23:36:38 +0000 (23:36 +0000)]
powerpc/ddr: fix fsl_ddr_get_dimm_params compile error
fsl_ddr_get_dimm_params() should be wrapped by
CONFIG_SYS_DDR_RAW_TIMING, otherwise, when using fixed_sdram() instead of
using SPD, it will cause compile error.
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Acked-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Shaohui Xie [Thu, 28 Jun 2012 23:35:34 +0000 (23:35 +0000)]
powerpc/corenet: fix compile error when CONFIG_SYS_NO_FLASH is defined
ENV location compile logic is wrong, and when CONFIG_SYS_NO_FLASH is defined
and non-NOR u-boot is building, it will cause compile error. Also, add
CONFIG_SYS_FLASH_USE_BUFFER_WRITE for p2041, which will improve NOR flash
write performance.
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
York Sun [Mon, 21 May 2012 08:43:11 +0000 (08:43 +0000)]
powerpc/mpc8xxx: fix workaround for errata DDR111 and DDR134 for DDR over 4GB
The fix for errata workaround is to avoid covering physical address
0xff000000 to 0xffffffff during the implementation. Early commit
eb672e92
works until DDR size exceeds 4GB. This fix works for DDR size up to 64GB.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Timur Tabi [Fri, 18 May 2012 09:09:09 +0000 (09:09 +0000)]
powerpc/p1022ds: fix DIU/LBC switching with NAND enabled
In order for indirect mode on the PIXIS to work properly, both chip selects
need to be set to GPCM mode, otherwise writes to the chip select base
addresses will not actually post to the local bus -- they'll go to the
NAND controller instead. Therefore, we need to set BR0 and BR1 to GPCM
mode before switching to indirect mode.
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Matthew McClintock [Fri, 18 May 2012 06:04:17 +0000 (06:04 +0000)]
powerpc/p1022ds: add support for SPI and SD boot
Add TLB mappings, board target options, and configuration items
need for SPI/SD boot.
Since P1022DS RevB board, the NOR flash have been changed to 16 bit/28bit
address flash, therefore, when SDHC/ESPI booting and access to eLBC,
the PMUXCR[0~1] must be set to 10b, and PMUXCR[9~10] must be set to
00b for them.
Configure the PX_BRDCFG0[0~1] to 10b which is connected to
SPI devices as SPI_CS(0:3)_B.
Signed-off-by: Matthew McClintock <msm@freescale.com>
Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com>
Signed-off-by: Jiang Yutang <b14898@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Nobuhiro Iwamatsu [Thu, 21 Jun 2012 02:26:38 +0000 (11:26 +0900)]
sh: Add support pin function control using GPIO
Renesas SH and R-Mobile set up device using PFC.
This provide the framework. Most codes were brought from linux kernel.
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Hideyuki Sano [Mon, 25 Jun 2012 01:29:56 +0000 (10:29 +0900)]
serial: sh: Add support Renesas R8A7740
The serial device of R8A7740 has the same structure as SH7372 of SH, etc.
Signed-off-by: Hideyuki Sano <hideyuki.sano.dn@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Nobuhiro Iwamatsu [Thu, 21 Jun 2012 04:21:32 +0000 (13:21 +0900)]
serial: sh: Add support Renesas SH73A0
The serial device of SH73A0 has the same structure as SH7372 of SH, etc.
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Yoshihiro Shimoda [Mon, 23 Jul 2012 14:53:42 +0000 (14:53 +0000)]
sh: modify checkcpu() for SH-4A
Even if using CPU is SH-4A, the previous code always put "SH4".
This patch fixes it.
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Wolfgang Denk [Tue, 7 Aug 2012 21:42:55 +0000 (23:42 +0200)]
Merge branch 'master' of git://git.denx.de/u-boot-onenand
* 'master' of git://git.denx.de/u-boot-onenand:
env_onenand: set ONENAND_MAX_ENV_SIZE to CONFIG_ENV_SIZE
Signed-off-by: Wolfgang Denk <wd@denx.de>
Holger Brunck [Mon, 6 Aug 2012 02:16:33 +0000 (02:16 +0000)]
MAINTAINERS: cleanup for km ppc boards
Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
cc: Heiko Schocher <hs@denx.de>
cc: Valentin Longchamp <valentin.longchamp@keymile.com>
cc: Gerlando Falauto <gerlando.falauto@keymile.com>
Acked-by: Heiko Schocher <hs@denx.de>
Michal Simek [Fri, 3 Aug 2012 03:37:44 +0000 (03:37 +0000)]
spi: Fix merge conflicts - Makefile
The patch "spi: tegra2: rename tegra2_spi.* to tegra_spi.*"
(sha1:
edffa63d3d6e76991998789f9fcbaa483731ca65)
renamed tegra2_spi.c to tegra_spi.c
and the patch "Merge branch 'master' of git://git.denx.de/u-boot-microblaze"
(sha1:
d978780b2e676c005460cd561f4f15b5220bdf49)
has wrongly resolved confict.
This patch fix it.
Signed-off-by: Michal Simek <monstr@monstr.eu>
Tom Rini [Tue, 7 Aug 2012 16:58:34 +0000 (09:58 -0700)]
ext2fs: fix warning: 'blocknxt' may be used uninitialized with gcc 4.2
The above warning was introduced originally in 436da3c "ext2load:
increase read speed" and fixed for newer toolchains in b803273 "ext2fs:
fix warning: 'blocknxt' may be used uninitialized". This change did not
fix the warning with gcc 4.2, as found in ELDK 4.2.
If we rework the while loop to initalize blocknxt before entering the
warning really goes away. Tested on am335x with an approx 7mb file and
crc32 in U-Boot befor and after this change.
Cc: Wolfgang Denk <wd@denx.de>
Cc: Eric Nelson <eric.nelson@boundarydevices.com>
Cc: Thierry Reding <thierry.reding@avionic-design.de>
Cc: Jason Cooper <u-boot@lakedaemon.net>
Cc: Andreas Bießmann <andreas.devel@googlemail.com>
Cc: Reinhard Arlt <reinhard.arlt@esd-electronics.com>
Cc: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: Tom Rini <trini@ti.com>
David du Colombier [Wed, 13 Jun 2012 21:24:35 +0000 (23:24 +0200)]
env_onenand: set ONENAND_MAX_ENV_SIZE to CONFIG_ENV_SIZE
This fix prevents env_import() CRC to fail when CONFIG_ENV_SIZE
is not equal to 4096 bytes
It also prevents mtd->read and mtd->write to be incomplete when
the environment is larger than 4096 bytes.
Signed-off-by: David du Colombier <0intro@gmail.com>
Gerlando Falauto [Fri, 27 Jul 2012 05:16:40 +0000 (05:16 +0000)]
powerpc/82xx: adapt SDRAM settings for mgcoge3ne
The HW guys suggested to change these two values. And these values are
now identical to the values we use on mgcoge.
PSDMR_WRC was set to 1C as it should lead to better performance.
Signed-off-by: Gerlando Falauto <gerlando.falauto@keymile.com>
Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
Gerlando Falauto [Fri, 27 Jul 2012 05:16:39 +0000 (05:16 +0000)]
powerpc/82xx: use SDRAM detection for mgcoge2ne
mgcoge2ne was an intermediate step towards mgcoge3ne. One difference is the
smaller SDRAM on mgcoge2ne (128MB). To support both boards with the same
u-boot we use here the SDRAM detection.
This patch enables SDRAM detection between 256MB and 128MB.
So in addition to the existing 256MB geometry:
4 chips x 8M (13 rows, 10 cols) x 16 bit x 4 banks
we can now also have 128MB geometry:
4 chips x 4M (13 rows, 9 cols) x 16 bit x 4 banks
Signed-off-by: Gerlando Falauto <gerlando.falauto@keymile.com>
Gerlando Falauto [Fri, 27 Jul 2012 05:16:38 +0000 (05:16 +0000)]
powerpc/82xx: add SDRAM detection for km82xx
This patch adds SDRAM detection feature to km82xx boards.
To enable this feature, define CONFIG_SYS_SDRAM_LIST as the initializer
for an array of struct sdram_conf_s.
These structs will expose the bitfields within registers PSDMR and OR1 which
have to be different between configurations; common bitfields will be
defined, as usual, within CONFIG_SYS_PSDMR and CONFIG_SYS_OR1.
If CONFIG_SYS_SDRAM_LIST is not defined, then the usual behavior is retained.
Signed-off-by: Gerlando Falauto <gerlando.falauto@keymile.com>