Daniel Schürmann [Fri, 14 May 2021 09:29:33 +0000 (11:29 +0200)]
aco/ra: prevent underflow register for p_create_vector operands
It could happen that we tested negative out-of-range
registers for p_create_vector operands resulting in a crash.
Fixes:
8962510e38fbaff792f60bc17d46507bb77401ac ('aco/ra: Conservatively refactor get_reg_specified to use PhysRegInterval')
Closes: #4697
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Tony Wasserka <tony.wasserka@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10799>
Emma Anholt [Thu, 13 May 2021 21:31:20 +0000 (14:31 -0700)]
ci/freedreno: Skip refract on a306 now that it hangchecks sometimes.
Not every MR, but several per day since I landed the apitrace switch which
increased trace replay resolution to 1080p. Hopefully some day we can
tune the hangcheck to be less aggressive.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10793>
Caio Marcelo de Oliveira Filho [Tue, 27 Apr 2021 21:49:40 +0000 (14:49 -0700)]
nir: Rename nir_is_per_vertex_io to nir_is_arrayed_io
VS outputs are "per vertex" but not the kind of I/O we want to match
with this helper. Change to a name that covers the "arrayness"
required by the type.
Name inspired by the GLSL spec definition of arrayed I/O.
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10493>
Gert Wollny [Sun, 2 May 2021 12:41:21 +0000 (14:41 +0200)]
compiler/nir: check whether var is an input in lower_fragcoord_wtrans
Otherwise the lowering pass might try to lower any other load from
a deref if its data.location value happens to be zero.
Fixes:
418c4c0d7d48a42f475df1ffb93b3a33763e7a4a
compiler/nir: extend lower_fragcoord_wtrans to support VARYING_SLOT_POS
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10577>
Mike Blumenkrantz [Fri, 15 Jan 2021 18:21:09 +0000 (13:21 -0500)]
zink: emit some barriers out of renderpass where possible
when emitting barriers, we don't need to end the renderpass in some cases
this handles the case of emitting barriers for new resources which have
never before been accessed and thus do not require synchronization at a
specific point in the batch
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10700>
Mike Blumenkrantz [Wed, 3 Mar 2021 20:56:14 +0000 (15:56 -0500)]
zink: add flags for determining whether to update framebuffer and renderpass
we can optimize restarting renderpasses here a little by only performing
lookups if states have actually changed
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10761>
Mike Blumenkrantz [Thu, 4 Mar 2021 14:26:13 +0000 (09:26 -0500)]
zink: add a flag for tracking/validating renderpass clears
we've been tracking which attachments are deferring clears but not
specifically the ones that are going to be cleared in a renderpass
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10761>
Mike Blumenkrantz [Wed, 3 Mar 2021 20:43:02 +0000 (15:43 -0500)]
zink: split out base renderpass begin into separate function
let fb setup and barriers and whatever be separate
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10761>
Tony Wasserka [Thu, 13 May 2021 10:04:11 +0000 (12:04 +0200)]
util: tune signatures of generated enum operators
This allows use of these operators in a constexpr context and silences
a clang -Wunused-function warning.
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10784>
Tony Wasserka [Thu, 13 May 2021 09:21:16 +0000 (11:21 +0200)]
util: add support for defining bitwise operators on strongly typed enums
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10784>
Jordan Justen [Thu, 13 May 2021 00:01:52 +0000 (17:01 -0700)]
intel: Add 2 ADL-S pci-ids
Cc: mesa-stable
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10781>
Daniel Schürmann [Tue, 4 May 2021 13:30:50 +0000 (15:30 +0200)]
driconf: set vk_x11_strict_image_count for Metro: Exodus
Otherwise, the game crashes on startup under xwayland.
Closes: #4650
Cc: mesa-stable
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10750>
Mike Blumenkrantz [Sun, 9 May 2021 14:25:00 +0000 (10:25 -0400)]
util/queue: don't require a fence when adding a job
sometimes we just want to fire jobs off into the void and don't care
if or when they finish
Reviewed-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10719>
Icecream95 [Thu, 13 May 2021 21:11:00 +0000 (09:11 +1200)]
panfrost: Skip blit shader labelling if the buffer has no space
Fixes stack corruption in dEQP-GLES31.functional.draw_buffers_indexed.
random.max_implementation_draw_buffers.10
Fixes:
8ba2f9f6985 ("panfrost: Create a blitter library to replace the existing preload helpers")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10792>
Lionel Landwerlin [Thu, 13 May 2021 19:48:15 +0000 (22:48 +0300)]
anv: handle spirv parsing failure
v2: don't leak spec_entries
v3: Also switch to VK_ERROR_UNKNOWN when parsing fails
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10790>
Jordan Justen [Thu, 9 Jul 2020 09:51:07 +0000 (02:51 -0700)]
intel/dev: Add device info for ADL GT2
Cc: mesa-stable
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9465>
Jordan Justen [Thu, 10 Dec 2020 09:42:12 +0000 (01:42 -0800)]
intel/isl: Add Wa_22011186057 to disable CCS on ADL GT2 A0
Cc: mesa-stable
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9465>
Daniel Stone [Thu, 13 May 2021 22:19:35 +0000 (23:19 +0100)]
CI: Disable all Panfrost/AMD/Iris automatic jobs
The power in Cambridge is unstable; disable these jobs until it's back
clear.
Signed-off-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10797>
Mike Blumenkrantz [Thu, 13 May 2021 22:16:47 +0000 (18:16 -0400)]
zink: immediately return false when getting query result if it's not gonna happen
this is a small optimization for the no-wait case when unflushed usage
exists since it's impossible for a qbo update to happen instantly
no functionality will be fixed by this, it's just a very minor optimization
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10796>
Mike Blumenkrantz [Thu, 13 May 2021 22:14:51 +0000 (18:14 -0400)]
lavapipe: fix fencing when submitting multiple cmdbufs
a fence applies to all the submitted cmdbufs, so it's necessary to do
the flush which creates the user fence after all the cmdbufs have been
processed in order to avoid creating a fence that only applies to the
first cmdbuf
Fixes:
b38879f8c5f ("vallium: initial import of the vulkan frontend")
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10795>
Mike Blumenkrantz [Thu, 13 May 2021 18:36:19 +0000 (14:36 -0400)]
zink: fix DrawParameters shader cap usage
this is for vertex shaders and covers more than just baseinstance
Fixes:
dcb9e4ddb4b ("zink: emit cap early")
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10788>
Mike Blumenkrantz [Thu, 13 May 2021 16:38:46 +0000 (12:38 -0400)]
zink: stop overwriting buffer map pointers for stream uploader
this breaks the driver!
the uploader always maps its own pointer, so modifying that at any
point just explodes things later
Fixes:
d179c5d28e6 ("zink: implement threaded context")
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10787>
Caio Marcelo de Oliveira Filho [Fri, 30 Apr 2021 08:00:51 +0000 (01:00 -0700)]
intel/compiler: Clarify why VUE is recomputed by FS
FS will get the last geometry VUE, but it still needs to recompute in
case the number of position slots assigned by geometry is larger than
one -- this happens when Primitive Replication is used.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10653>
Danylo Piliaiev [Thu, 13 May 2021 09:15:56 +0000 (12:15 +0300)]
ci/turnip: drop fail annotation for image.extend_operands_spirv1p4.*
They were fixed in
ed20e69b "vtn: Handle ZeroExtend/SignExtend image operands"
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10783>
Danylo Piliaiev [Thu, 13 May 2021 09:00:57 +0000 (12:00 +0300)]
ci/turnip: drop fail annotation for float_control tests
These tests are NotSupported and therefore cannot fail.
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10783>
Lionel Landwerlin [Sat, 17 Apr 2021 16:59:22 +0000 (19:59 +0300)]
anv: fix perf query pass with command buffer batching
We've only considered the perf query pool change previously. But we
also need to pay attention to the pass index.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes:
0a7224f3ff7542 ("anv: group as many command buffers into a single execbuf")
Reviewed-by: Felix DeGrood <felix.j.degrood@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10301>
Lionel Landwerlin [Sat, 17 Apr 2021 15:21:26 +0000 (18:21 +0300)]
intel/mi_builder: fix resolve call
Giving NULL for anv_combine_address() triggers an assert in that
function.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes:
8525ebe6e375 ("intel/mi_builder: Return an address from __gen_get_batch_address")
Reviewed-by: Felix DeGrood <felix.j.degrood@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10301>
Abel García Dorta [Wed, 12 May 2021 17:34:19 +0000 (18:34 +0100)]
i915g: add HW atomic counters as unsupported
Closes: #4772
Fixes:
2a06423c009 ("gallium: add CAPs to support HW atomic counters. (v3)")
Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10776>
Tony Wasserka [Fri, 7 May 2021 10:10:52 +0000 (12:10 +0200)]
aco/scheduler: Verify register demand invariants in debug mode
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10644>
Tony Wasserka [Fri, 7 May 2021 14:22:45 +0000 (16:22 +0200)]
aco/scheduler: Fix register demand computation for upwards moves
The initial value needs to be taken from the instruction that is being
moved over, not the one to be moved.
Additionally the parameter of this function was removed because it was
misleading. Setting it to any value other than source_idx would cause
register_demand to be initialized incorrectly. (Instead, the maximum
demand among the covered instructions would need to be determined.)
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10644>
Tony Wasserka [Wed, 5 May 2021 10:53:13 +0000 (12:53 +0200)]
aco/scheduler: Fix register demand computation for downwards moves
Previously, changes in total_demand_clause were not always propagated to
total_demand. For instance, clause moves do not change the local register
demand at the end of a clause, yet they may still affect the total maximum.
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Fixes:
8235bc64112 ("aco: try to group together VMEM loads of the same resource")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4533
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10644>
Daniel Schürmann [Wed, 12 May 2021 10:52:52 +0000 (12:52 +0200)]
aco: relax validation rules for p_reduce dst RegType
By exposing a subgroupSize of 64, reductions with
cluster_size 32 in wave32 might be considered divergent,
and thus, result in a VGPR.
Fixes: dEQP-VK.subgroups.clustered.graphics.subgroupclustered* with wave32
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10769>
Tapani Pälli [Wed, 12 May 2021 12:19:43 +0000 (15:19 +0300)]
isl: require hiz for depth surface in isl_surf_get_ccs_surf
Fixes:
752eefdb ("intel/isl: Refactor isl_surf_get_ccs_surf")
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10768>
Jose Fonseca [Wed, 12 May 2021 12:29:45 +0000 (13:29 +0100)]
wgl: Remove opengl32.mingw.def.
MinGW DEF parsing is even more broken than before, and 32-bits import
libs are broken regardless one uses opengl32.mingw.def or opengl32.def.
This change removes opengl32.mingw.def and addresses the issue differently:
- link opengl32.dll with --enable-stdcall-fixup
- use the systems opengl32 import lib (libopengl32.a/opengl32.lib)
instead of our own
This change also gets test_wgl built with MinGW (even if it's never tested),
which I used to verify this; and to not link against internal libraries.
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
v2: Revert back to shared_library.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10767>
Mike Blumenkrantz [Fri, 2 Apr 2021 16:13:53 +0000 (12:13 -0400)]
zink: always do maybe_flush after draw/compute
this is a bit more sensible since a forced flush is going to require
refs and layouts be reapplied
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10760>
Mike Blumenkrantz [Fri, 2 Apr 2021 16:13:13 +0000 (12:13 -0400)]
zink: check for a work_count-based stall in zink_maybe_flush_or_stall()
put all the maybes in one place
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10760>
Mike Blumenkrantz [Wed, 20 Jan 2021 20:11:49 +0000 (15:11 -0500)]
zink: flush every 100k draws/computes
this ensures more consistent throughput in e.g., drawoverhead
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10760>
Timothy Arceri [Wed, 12 May 2021 05:44:02 +0000 (15:44 +1000)]
glsl: add missing support for explicit components in interface blocks
From the ARB_enhanced_layouts spec:
"As with input layout qualifiers, all shaders except compute shaders
allow *location* layout qualifiers on output variable declarations,
output block declarations, and output block member declarations. Of
these, variables and block members (but not blocks) additionally
allow the *component* layout qualifier."
We previously had compile tests in piglit to make sure this was not a
compile error but no execution tests.
Fixes:
d99a040bbf2c ("i965: enable ARB_enhanced_layouts for gen8+")
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10763>
Timothy Arceri [Wed, 12 May 2021 05:42:44 +0000 (15:42 +1000)]
glsl: create validate_component_layout_for_type() helper
This will be used in the following patch.
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10763>
Ryan Houdek [Thu, 6 May 2021 19:17:42 +0000 (12:17 -0700)]
Update release notes with mention that x87 is no longer used on x86
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9868>
Ryan Houdek [Thu, 6 May 2021 08:45:47 +0000 (01:45 -0700)]
Switch u_format_test to passed on i386
Switching from x87 to SSE resolves the rounding behaviour in this test.
It was some of the dxt formats failing and now they are not.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9868>
Ryan Houdek [Fri, 26 Mar 2021 23:25:01 +0000 (16:25 -0700)]
Default enable SSE2 on mesa builds.
With the idea of branching classic device support in to its own tree now would be a good time to also raise the minimum
requirements to something that is more "modern" on x86.
SSE2 was introduced in 2000(!) by default let's make it the minimum spec now
All the old hardware that is moving to the maintenance branch will finally be out of the way.
For the 64-bit side of the discussion there isn't much changed.
* GCC already enables -msse and -msse2 by default
* Same with clang
* fpmath=sse might remove some extraneous x87 usage
** Clang implies fpmath=sse ALWAYS
For the 32-bit side of things is where the exciting details change
* GCC by default doesn't enable sse1 or sse2
** Does all `float`, `double`, and `long double` math with x87
** -msse2 enables sse2 and sse1, gcc still uses x87 even with those enabled
** -mfpmath=sse moves away from using x87 and instead uses sse1 and sse2
* Clang already default enables sse1/sse2 which then turns on their implied fpmath=sse
What does this mean for users?
On Linux raises the default minimum processor spec to SSE2 supporting CPUs
* Intel requirements raise from P5 (1993) to Netburst (2000)
* AMD requirements raise from Athlon(1999/2000) to Athlon 64 (2003)
* Via requirements raise from C3(2001) to C7 (2005)
What does it mean for package maintainers?
For x86-64 distributions that have i386/i686 multilib, then nothing changes. You're already on a platform guaranteed to support SSE2.
For i386/i686 distributions they will need to weigh their min spec against this. Not sure how many still support classic processors.
Who is left out in the cold?
* Intel Quark (2013)
** Embedded board, doesn't have a GPU, Technically has 1x PCIe 2.0 lane that someone could plug a GPU in to
* Some older transmeta CPUs, but they had a followup that also had SSE2.
** Anyone hacking on these with a modern GPU? I'm guessing they know how to turn this option off
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9868>
Vinson Lee [Sat, 8 May 2021 23:42:52 +0000 (16:42 -0700)]
nv50/ir: Add ConstantFolding constructor.
Fix defect reported by Coverity Scan.
Uninitialized scalar field (UNINIT_CTOR)
member_not_init_in_gen_ctor: The compiler-generated constructor for this
class does not initialize foldCount.
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10713>
Vinson Lee [Sun, 9 May 2021 00:23:52 +0000 (17:23 -0700)]
nvc0/ir: Initialize CodeEmitterGK110 member progType in constructor.
Fix defect reported by Coverity Scan.
Uninitialized scalar field (UNINIT_CTOR)
uninit_member: Non-static class member progType is not initialized in
this constructor nor in any functions that it calls.
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10715>
Chia-I Wu [Wed, 12 May 2021 20:50:56 +0000 (13:50 -0700)]
venus: get rid of #ifdef's in vn_CreateImage
No real change after compiler optimizations.
Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10779>
Lionel Landwerlin [Wed, 12 May 2021 08:24:12 +0000 (11:24 +0300)]
intel/fs: use the final destination type for regioning restrictions
This is most likely a rebase mistake :(
Fixes:
f3e5cd813ae6a8 ("intel/fs: Handle regioning restrictions of split FP/DP pipelines.")
Ref:
aa53665fda6348 ("intel/fs/copy_prop: check stride constraints with actual final type")
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10764>
Ezequiel Garcia [Tue, 11 May 2021 19:57:25 +0000 (16:57 -0300)]
panfrost: Add GPU IDs for G52 1-Core-2EE (RK3568/RK3566)
Rockchip SoCs RK3566 and RK3568 have a Gondul with
one shader core and two execution engines, with product ID 0x7402.
Quoting the datasheet:
Mali-G52 1-Core-2EE
* Support 1600Mpix/s fill rate when 800MHz clock frequency
* Support 38.4GLOPs when 800MHz clock frequency
To distinguish it from other variants of G52, we agreed
to call this "G52L", L is for Little.
Signed-off-by: Ezequiel Garcia <ezequiel@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10771>
Alyssa Rosenzweig [Wed, 12 May 2021 17:22:24 +0000 (13:22 -0400)]
pan/mdg: Use smaller LD_UNIFORM instructions
If we only read 8 bytes from a UBO, we need to use LD_UNIFORM.64 as
opposed to LD_UNIFORM.128. In addition to probably being faster, this
fixes a buffer overrun manifesting as MMU faults with source ID
0x500/0x600/0x700, visible in WebGL Aquarium.
This is essentially the same patch as
616394cf31c ("pan/mdg: Use
appropriate sizes for global loads/stores"), only this is for UBOs where
that was for SSBOs.
Before enabling PACKED_UNIFORMS, this bug was not visible since we could
guarantee the UBO size was a multiple of 16. We no longer have that
invariant, and in rare cases the last 8 bytes of the last 16-byte slot
of a mapped uniform buffer would overrun the BO and trigger a fault,
even if the result is unused.
Fixes:
24d7c413fe7 ("panfrost: Enable packed uniforms.")
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10772>
Alyssa Rosenzweig [Wed, 12 May 2021 17:21:40 +0000 (13:21 -0400)]
panfrost: Don't upload empty push uniform table
Instead zero out the pointer in this case.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10772>
Alyssa Rosenzweig [Wed, 12 May 2021 16:17:28 +0000 (12:17 -0400)]
panfrost: Clean up cases for emit_fbd
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10774>
Alyssa Rosenzweig [Wed, 12 May 2021 16:13:37 +0000 (12:13 -0400)]
panfrost: Remove spurious assignment
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10774>
Alyssa Rosenzweig [Wed, 12 May 2021 14:41:09 +0000 (10:41 -0400)]
panfrost: Don't translate compare funcs
Matches Gallium.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10774>
Alyssa Rosenzweig [Wed, 12 May 2021 19:08:19 +0000 (15:08 -0400)]
panfrost: Hide CAP_INT16 behind is_deqp
The GLSL precision lowering is still buggy (see !10729), no other driver
enables all the CAPs yet. I don't know enough GLSL IR to be the one to
fix this. In the mean time, this is a hotfix to expose the same set of
CAPs that radeonsi does.
By keeping it with is_deqp, we still get CI coverage of int16.
Closes: #4759
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10777>
Rob Clark [Wed, 12 May 2021 17:15:03 +0000 (10:15 -0700)]
freedreno/ir3: Don't force RTNE if rounding mode is undefined
Forcing round-to-nearest-even results in loss of opportunities for
conversion folding, causing a regression in gfxbench gl_alu2.
Fixes:
de195671bdb ("ir3: nir_op_f2f16 should round to even")
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10773>
Leo Liu [Sun, 9 May 2021 15:58:55 +0000 (11:58 -0400)]
frontends/va: fix multi planes for external memeory type
For the multi planes case, only the first plane is required with the
template buffer formats, and shouldn't fail for other planes.
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: James Zhu <James.Zhu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10751>
Rob Clark [Tue, 11 May 2021 15:44:42 +0000 (08:44 -0700)]
gallium/u_threaded: Add call logging
Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10753>
Rob Clark [Tue, 11 May 2021 15:24:47 +0000 (08:24 -0700)]
gallium/u_threaded: Add to_call() helper
Add helper for casting the call, which when asserts are enabled will
sanity check the call size to detect corruption.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10753>
Erik Faye-Lund [Tue, 11 May 2021 08:58:58 +0000 (10:58 +0200)]
ci: Uprev piglit to
3351e8952 ("max-texture-size: report merged results")
This pulls in a fix for the max-texture-size test using piglit-runner,
among other things.
Acked-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10749>
Marek Olšák [Tue, 11 May 2021 10:46:26 +0000 (06:46 -0400)]
gallium/u_threaded: fix 32-bit breakage due to incorrect pointer arithmetic
Fixes:
1233c90ab4a - gallium/u_threaded: rewrite slot layout to reduce wasted space
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4755
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4758
Acked-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10746>
Daniel Schürmann [Tue, 11 May 2021 20:58:27 +0000 (22:58 +0200)]
aco: fix additional register requirements for spilling
It could happen that VGPR spilling without SGPR spilling
calculated a negative spills_to_vgpr number and then
increasing the VGPR target demand above the limit.
Cc: mesa-stable
Reviewed-by: Tony Wasserka <tony.wasserka@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10756>
Timur Kristóf [Thu, 22 Apr 2021 12:44:28 +0000 (14:44 +0200)]
radv: Use new NIR lowering of NGG GS when ACO is used.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10740>
Timur Kristóf [Thu, 22 Apr 2021 12:43:54 +0000 (14:43 +0200)]
ac: Add NIR lowering for NGG GS.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10740>
Timur Kristóf [Thu, 15 Apr 2021 15:21:57 +0000 (17:21 +0200)]
radv: Use new NGG NIR lowering for VS/TES when ACO is used.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10740>
Timur Kristóf [Fri, 9 Apr 2021 14:56:57 +0000 (16:56 +0200)]
ac: Add new NIR pass to lower NGG VS/TES.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10740>
Timur Kristóf [Fri, 9 Apr 2021 14:59:30 +0000 (16:59 +0200)]
aco: Implement new NGG specific NIR intrinsics.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10740>
Timur Kristóf [Thu, 22 Apr 2021 12:24:48 +0000 (14:24 +0200)]
radv: Gather NGG info sooner.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10740>
Timur Kristóf [Thu, 15 Apr 2021 15:02:57 +0000 (17:02 +0200)]
radv: Fill shader info earlier.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10740>
Timur Kristóf [Thu, 15 Apr 2021 14:51:45 +0000 (16:51 +0200)]
aco: Split ngg_emit_sendmsg_gs_alloc_req from the wave0 check.
This allows us to emit the gs_alloc_req independently of the
wave ID check, which is what the NIR lowering will need.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10740>
Timur Kristóf [Thu, 22 Apr 2021 12:11:39 +0000 (14:11 +0200)]
aco: Fixup the NIR metadata after sanitize_cf_list.
sanitize_cf_list can in fact invalidate the dominance metadata,
which we need to use eg. nir_unsigned_upper_bound.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10740>
Timur Kristóf [Wed, 21 Apr 2021 12:20:45 +0000 (14:20 +0200)]
aco: Allow workgroup barrier and shared scope for NGG shaders.
NGG already needs to use workgroup barriers, but this commit allows
them to come from NIR as opposed to just emitting it in ACO
instruction selection.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10740>
Timur Kristóf [Tue, 4 May 2021 11:40:28 +0000 (13:40 +0200)]
nir: Add AMD specific intrinsics for merged shaders and NGG.
These intrinsics represent what the hardware can actually do.
Lowering our shaders to use these intrinsics will allow us to
deal with mapping the classic VS, TES, GS (and the future MS)
stages to the hardware capabilities using NIR, which makes our
backend compilers simpler.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10740>
Timur Kristóf [Mon, 10 May 2021 20:37:46 +0000 (22:37 +0200)]
nir: Allow load_primitive_id in VS in nir_divergence_analysis.
The lowered NIR code of NGG VS shaders uses this intrinsic
when the VS has to export the primitive ID.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10740>
Timur Kristóf [Fri, 23 Apr 2021 06:48:46 +0000 (08:48 +0200)]
nir: Support upper bound of unsigned bit size conversions.
These allow us to generate slightly better code in some cases,
eg. multiplications in ACO.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10740>
Timur Kristóf [Fri, 23 Apr 2021 06:46:18 +0000 (08:46 +0200)]
nir: Support upper bound of subgroup_id/num_subgroups for non-compute.
These intrinsics will be used when lowering NGG shaders, including
currently supported stages like VS, TES, GS and also by mesh shaders
in the future.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10740>
Alyssa Rosenzweig [Tue, 11 May 2021 19:39:21 +0000 (15:39 -0400)]
panfrost: Implement framebuffer invalidation
The strategy is lifted from Freedreno. The trick is to remove buffers
from the resolve set, rather than add buffers to a discard set (as you
would naively try). The latter is wrong -- draws after the
glInvalidateFramebuffer() still need to be respected.
glmark2 -btexture on-screen with sway on Mali T860 from 1393fps to
1998fps
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Closes: #2407
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6295>
Alyssa Rosenzweig [Tue, 11 May 2021 19:38:52 +0000 (15:38 -0400)]
panfrost: Set discard based on the resolve set
This is a bit simpler and will allow resolve to be disabled
independently.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6295>
Alyssa Rosenzweig [Tue, 11 May 2021 19:38:23 +0000 (15:38 -0400)]
panfrost: Track buffers needing resolve
This is a subset of the buffers cleared or drawed.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6295>
Marcin Ślusarz [Thu, 12 Nov 2020 19:13:26 +0000 (20:13 +0100)]
nir: handle float atomics in nir_lower_memory_model
Signed-off-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Fixes:
2adb337256f ("nir,radv/aco: add and use pass to lower make available/visible barriers")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10766>
Marcin Ślusarz [Thu, 12 Nov 2020 19:13:18 +0000 (20:13 +0100)]
nir: handle float atomics in nir_gather_info
Signed-off-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10766>
Erik Faye-Lund [Mon, 10 May 2021 15:47:47 +0000 (17:47 +0200)]
translate: assert that nr_elements is in range
This just ensures that we don't end up reading/writing outside of the
space reserved in the key. This would have made it easier to to track
down the issue in the previous commit faster.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10730>
Erik Faye-Lund [Mon, 10 May 2021 15:46:28 +0000 (17:46 +0200)]
translate: reserve more vertex-shader outputs
It's not just position that's special here, we also need space for
other special vertex-shader outputs.
This fixes a crash with Zink on Lavapipe, because Zink always emits
psize to avoid some shader-keys. While this might not be ideal, it's not
illegal. So we need to handle it.
But it seems we're missing more, and this list is taken from
compute_vertex_info() in lp_state_derived.c.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10730>
Erik Faye-Lund [Mon, 10 May 2021 16:15:57 +0000 (18:15 +0200)]
lavapipe: correct reported number of UBOs
When emitting the state we add one to the UBO index, so we have to
subtract one from the number of UBOs that we support. This is still
fine, because Vulkan only requires 14 UBOs to be supported, and LLVMpipe
supports 16.
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10731>
Boris Brezillon [Tue, 11 May 2021 10:40:33 +0000 (12:40 +0200)]
panfrost: Flag indirect draw/dispatch shaders as internal
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10417>
Boris Brezillon [Tue, 11 May 2021 10:24:45 +0000 (12:24 +0200)]
panfrost: Expose the DRAW_PARAMETERS cap on Bifrost
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10417>
Boris Brezillon [Tue, 11 May 2021 10:21:52 +0000 (12:21 +0200)]
pan/bi: Add support for gl_DrawID
We simply pass the drawid as a sysval.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Acked-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10417>
Boris Brezillon [Tue, 11 May 2021 09:16:46 +0000 (11:16 +0200)]
pan/bi: Add support for gl_{BaseVertex,BaseInstance}
Extend the VERTEX_INSTANCE_OFFSETS sysval to pass
BaseVertex/BaseInstance information to the shader.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Acked-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10417>
Alyssa Rosenzweig [Thu, 22 Apr 2021 23:35:56 +0000 (19:35 -0400)]
pan/bi: Add first_vertex to vertex ID
Apparently r61 is zero based.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Tested-by: Boris Brezillon <boris.brezillon@collabora.com>
Acked-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10417>
Boris Brezillon [Tue, 11 May 2021 09:01:20 +0000 (11:01 +0200)]
panfrost: Split the indexed and !indexed indirect draw info structs
Some fields are overlapping, so let's just split those structs to
avoid confusion.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Acked-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10417>
Gustavo Padovan [Fri, 30 Apr 2021 15:02:39 +0000 (12:02 -0300)]
iris/ci: enable intel devices automatically in MR pipelines
After a period of stabilization it is now time to move them
to be part of the MR pipelines. We will still watch the
behavior and look for any issue that arises.
Signed-off-by: Gustavo Padovan <gustavo.padovan@collabora.com>
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10550>
Gustavo Padovan [Fri, 30 Apr 2021 10:07:16 +0000 (07:07 -0300)]
iris/ci: disable failing gimark test for now
In order to enable the intel devices to automatically be part of
Marge pipelines we need it to be fully passing all tests. We will
remove the gimark tests temporaly to achieve that.
Signed-off-by: Gustavo Padovan <gustavo.padovan@collabora.com>
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10550>
Vinson Lee [Sat, 8 May 2021 23:59:15 +0000 (16:59 -0700)]
nv50/ir: Initialize GCRA::RIG_Node members.
Fix defects reported by Coverity Scan.
uninit_member: Non-static class member degree is not initialized in this constructor nor in any functions that it calls.
uninit_member: Non-static class member degreeLimit is not initialized in this constructor nor in any functions that it calls.
uninit_member: Non-static class member maxReg is not initialized in this constructor nor in any functions that it calls.
uninit_member: Non-static class member f is not initialized in this constructor nor in any functions that it calls.
uninit_member: Non-static class member reg is not initialized in this constructor nor in any functions that it calls.
uninit_member: Non-static class member weight is not initialized in this constructor nor in any functions that it calls.
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10714>
Hyunjun Ko [Thu, 6 May 2021 05:05:39 +0000 (05:05 +0000)]
turnip: Implement VK_KHR_timeline_semaphore.
Implements non-shareable timelines using legacy syncobjs,
inspired by anv/radv implementation.
v1. Avoid memcpy in/out_syncobjs and fix some mistakes.
v2.
- Handle vkQueueWaitIdle.
- Add enum tu_semaphore_type.
- Fix to handle VK_SEMAPHORE_WAIT_ANY_BIT_KHR correctly.
- Fix a crash of dEQP-VK.synchronization.timeline_semaphore.device_host.misc.max_difference_value.
v3. Avoid indefinite waiting in vkQueueWaitIdle by calling
tu_device_submit_deferred_locked itself.
Signed-off-by: Hyunjun Ko <zzoon@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10126>
Hyunjun Ko [Thu, 8 Apr 2021 05:05:32 +0000 (05:05 +0000)]
turnip: prep work for timeline semaphore support
Small refactor to classify semphore types, currently only binary
syncobj is being used though.
v1. Fix a crash of dEQP-VK.api.null_handle.destroy_semaphore
Signed-off-by: Hyunjun Ko <zzoon@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10126>
Mike Blumenkrantz [Thu, 1 Apr 2021 18:52:21 +0000 (14:52 -0400)]
zink: pop descriptor refs when invalidating sets
this avoids memory ballooning, mainly for samplers, when a descriptorset
component has refs for a very, very large number of sets
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10699>
Mike Blumenkrantz [Thu, 1 Apr 2021 19:16:35 +0000 (15:16 -0400)]
zink: remove screen param from zink_descriptors_update()
this was redundant
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10699>
Mike Blumenkrantz [Thu, 1 Apr 2021 19:13:18 +0000 (15:13 -0400)]
zink: make zink_context_update_descriptor_states() static
this is no longer used externally
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10699>
Mike Blumenkrantz [Thu, 1 Apr 2021 18:51:53 +0000 (14:51 -0400)]
zink: call invalidate on invalid descriptor sets during recycle
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10699>
Mike Blumenkrantz [Thu, 1 Apr 2021 18:48:58 +0000 (14:48 -0400)]
zink: use better iterating for buffer rebinds
now that the number of descriptors for a given type is known, we can iterate
over all bound descriptors for the type instead of relying on shader usage
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10699>
Mike Blumenkrantz [Thu, 1 Apr 2021 18:45:51 +0000 (14:45 -0400)]
zink: add slot params to zink_context_invalidate_descriptor_state
allow more precision with invalidation
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10699>
Mike Blumenkrantz [Thu, 1 Apr 2021 18:21:34 +0000 (14:21 -0400)]
zink: track number of tbos in shader data
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10699>