Jesse Barnes [Fri, 8 Mar 2013 18:45:53 +0000 (10:45 -0800)]
drm/i915: allow force wake at init time on VLV v2
We need to set the 'allow force wake' bit to enable forcewake handling
later on.
v2: split from clock gating patch (Jani)
check for allowwakeack (Ville)
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Ben Widawsky [Thu, 14 Mar 2013 00:21:06 +0000 (17:21 -0700)]
drm/i915: Remove unneeded dev argument
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Acked-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Ben Widawsky [Thu, 14 Mar 2013 00:21:05 +0000 (17:21 -0700)]
drm/i915: Remove unused file arg from execbuf
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Acked-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Chris Wilson [Thu, 14 Mar 2013 15:52:05 +0000 (17:52 +0200)]
drm/i915: Resurrect ring kicking for semaphores, selectively
Once we thought we got semaphores working, we disabled kicking the ring
if hangcheck fired whilst waiting upon a ring as it was doing more harm
than good:
commit
4e0e90dcb8a7df1229c69e30abebb59b0b3c2a1f
Author: Daniel Vetter <daniel.vetter@ffwll.ch>
Date: Wed Dec 14 13:56:58 2011 +0100
drm/i915: kicking rings stuck on semaphores considered harmful
However, life is never that easy and semaphores are still causing
problems whereby the value written by one ring (bcs) is not being
propagated to the waiter (rcs). Thus the waiter never wakes up and we
declare the GPU hung, which often has unfortunate consequences, even if
we successfully reset the GPU.
But the GPU is idle as it has completed the work, just didn't notify its
clients. So we can detect the incomplete wait during hang check and
probe the target ring to see if has indeed emitted the breadcrumb seqno
following the work and then and only then kick the waiter.
Based on a suggestion by Ben Widawsky.
v2: cross-check wait with iphdr. fix signaller calculation.
References: https://bugs.freedesktop.org/show_bug.cgi?id=54226
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: Ben Widawsky <ben@bwidawsk.net>
Acked-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Paulo Zanoni [Wed, 6 Mar 2013 23:03:22 +0000 (20:03 -0300)]
drm/i915: add missing space in error message
To avoid this:
[ 256.798060] [drm] capturing error event; look for more information
in/sys/kernel/debug/dri/0/i915_error_state
Ben Widawsky identified that this regression has been introduced in
commit
2f86f1916504525a6fdd6b412374b4ebf1102cbe
Author: Ben Widawsky <ben@bwidawsk.net>
Date: Mon Jan 28 15:32:15 2013 -0800
drm/i915: Error state should print /sys/kernel/debug
...
[danvet: split up long line.] <----- he did it
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
[danvet: Pimp commit message with the regression note. Also, order
more brown paper bags, I've run out.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Paulo Zanoni [Wed, 6 Mar 2013 23:03:20 +0000 (20:03 -0300)]
drm/i915: don't save/restore PCH_LVDS on LPT
Because the register does not exist on LPT. The interesting fact is
that reading/writing PCH_LVDS on LPT does *not* give us "unclaimed
register" messages, but the register value is always 0.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Paulo Zanoni [Wed, 6 Mar 2013 23:03:19 +0000 (20:03 -0300)]
drm/i915: reorganize intel_lvds_supported
Now it returns false for all platforms unless they're explicitly
listed on the function. There should be no real difference, except for
the fact that it now returns false on Haswell.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Paulo Zanoni [Wed, 6 Mar 2013 23:03:18 +0000 (20:03 -0300)]
drm/i915: add HAS_POWER_WELL
We're starting to add many IS_HASWELL checks for the power well code,
so add a HAS_POWER_WELL macro to properly document that we're checking
for hardware that has the power down well.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
[danvet: Resolve conflicts since some converted code was added by
not-yet merged patches.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Paulo Zanoni [Wed, 6 Mar 2013 23:03:14 +0000 (20:03 -0300)]
drm/i915: there's no DSPADDR register on Haswell
So don't read it when we hang the GPU. This solves "unclaimed
register" messages.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
[danvet: Future-proof by adding a gen >= 7 check in addition to the
!IS_HSW check from Paulo's original patch, suggested by Ben.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Paulo Zanoni [Wed, 6 Mar 2013 23:03:13 +0000 (20:03 -0300)]
drm/i915: there's no DSPSIZE register on gen4+
So don't read it when capturing the error state. This solves some
"unclaimed register" messages on Haswell when we hang the GPU.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Paulo Zanoni [Wed, 6 Mar 2013 23:03:12 +0000 (20:03 -0300)]
drm/i915: capture the correct cursor registers on IVB
This solves some "unclaimed register" messages when there's a GPU hang
on Haswell.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
[danvet: Add missing IS_VLV check as spotted by Ville Syrjälä.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Paulo Zanoni [Wed, 6 Mar 2013 23:03:09 +0000 (20:03 -0300)]
drm/i915: disable sound first on intel_disable_ddi
Our mode set sequence documentation says audio must be disabled first.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
[danvet: Resolve conflict since the first patch in this series isn't
applied yet. Also bikeshed commit message as suggested by Ben.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Jani Nikula [Tue, 12 Mar 2013 08:49:19 +0000 (10:49 +0200)]
drm/i915: reduce power in the ilk rc6 enable error message
Even if "power power" is good for grepping.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Kees Cook [Mon, 11 Mar 2013 21:37:35 +0000 (14:37 -0700)]
drm/i915: clarify reasoning for the access_ok call
This clarifies the comment above the access_ok check so a missing
VERIFY_READ doesn't alarm anyone.
v2:
- rewrote comment, thanks to Chris Wilson
Signed-off-by: Kees Cook <keescook@chromium.org>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
[danvet: add patch history log to commit message.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Kees Cook [Sun, 10 Mar 2013 21:10:06 +0000 (14:10 -0700)]
drm/i915: use simple attribute in debugfs routines
This replaces the manual read/write routines in debugfs with the common
simple attribute helpers. Doing this gets rid of repeated copy/pasting
of copy_from_user and value formatting code.
Signed-off-by: Kees Cook <keescook@chromium.org>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
[danvet: Squash in follow-up fix from Kees Cook to fix u64 divides on
32bit platforms.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Mihnea Dobrescu-Balaur [Sun, 10 Mar 2013 12:22:48 +0000 (14:22 +0200)]
gpu: don't cast kzalloc() return value
Signed-off-by: Mihnea Dobrescu-Balaur <mihneadb@gmail.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Jesse Barnes [Fri, 1 Mar 2013 21:14:31 +0000 (13:14 -0800)]
drm/i915/dp: add pre-PCH eDP checking to DP detect for VLV
Allows us to detect eDP panels that may not have the hotplug pin wired up.
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Jesse Barnes [Fri, 1 Mar 2013 22:08:29 +0000 (14:08 -0800)]
drm/i915: use gen6 stolen check on VLV
It uses the same bit definitions.
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Jesse Barnes [Fri, 1 Mar 2013 21:14:30 +0000 (13:14 -0800)]
drm/i915/dp: don't use ILK paths on VLV
Fix up a couple of places where we messed with PCH bits on VLV.
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Jesse Barnes [Fri, 1 Mar 2013 21:14:13 +0000 (13:14 -0800)]
drm/i915: VLV has force wake
This was omitted from
commit
b7884eb45ec98c0d34c7f49005ae9d4b4b4e38f6
Author: Daniel Vetter <daniel.vetter@ffwll.ch>
Date: Mon Jun 4 11:18:15 2012 +0200
drm/i915: hold forcewake around ring hw init
which introduced the ->has_force_wake flag.
Note that this only enables the above w/a hack.
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
[danvet: Put some interesting stuff into the empty commit message.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Jesse Barnes [Sat, 2 Feb 2013 12:56:14 +0000 (13:56 +0100)]
drm/i915: don't init LVDS on VLV
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Ben Widawsky [Tue, 5 Mar 2013 01:00:29 +0000 (17:00 -0800)]
drm/i915: Capture current context on error
On error, this represents the state of the currently running context at
the time it was loaded.
Unfortunately, since we're hung and can't switch out the context this
may not tell us too much about the most current state of the context,
but does give clues about what has happened since loading.
Thanks to recent doc updates, we have a little more confidence regarding
what is actually in this memory, and perhaps it will help us gain more
insight into certain bugs. AFAICT, the most interesting info is in the
first page. To save space, we only capture the first page. In the
future, we might want to dump more.
Sample of the relevant part of error state:
render ring --- HW Context = 0x01b20000
[0000]
00000000 1100105f 00002028 ffff0880
[0010]
0000209c feff4040 000020c0 efdf0080
[0020]
00002178 00000001 0000217c 00145855
[0030]
00002310 00000000 00002314 00000000
v2: Move error collection to the ring error code
Change format of dump to not confuse intel_error_decode (Chris)
Put the context error object with the others (Chris)
Don't search bound_list instead of active_list (chris)
v3: extract and flatten context recording (daniel)
checkpatch related fixes for the copypasta in debugfs
v4: bug in v3 (Daniel)
- if ((ring->id == RCS) && error->ccid)
+ if ((ring->id != RCS) || !error->ccid)
References: https://bugs.freedesktop.org/show_bug.cgi?id=55845
Reviewed-by (v2): Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
[danvet: Bikeshed away the redudant parenthese around ring->id != RCS]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Paulo Zanoni [Tue, 19 Feb 2013 19:21:47 +0000 (16:21 -0300)]
drm/i915: rename some HDMI bit definitions
Bits used only on HDMI mode now have HDMI_ prefix instead of SDVO_.
The COLOR_FORMAT bits now have prefixes (and the 12bpc bit is for HDMI
only).
Notice that this patch uncovers a bug on the SDVO code: the
COLOR_RANGE_16_235 bit can only be used if the port is in TMDS mode,
not SDVO mode. This will have to be fixed in a later patch.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Paulo Zanoni [Tue, 19 Feb 2013 19:21:46 +0000 (16:21 -0300)]
drm/i915: remove duplicated SDVO/HDMI bit definitions
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Paulo Zanoni [Tue, 19 Feb 2013 19:21:45 +0000 (16:21 -0300)]
drm/i915: unify the definitions of the HDMI/SDVO register
Since they're all the same register, leave all the #defines at the
same place, organized by Gen and also specify which bits are used by
only a specific port or encoding.
Also remove a few unused duplicates and adjust indentation.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Paulo Zanoni [Mon, 18 Feb 2013 22:00:27 +0000 (19:00 -0300)]
drm/i915: clarify confusion between SDVO and HDMI registers
Some HDMI registers can be used for SDVO, so saying "HDMIB" should be
the same as saying "SDVOB" for a given HW generation. This was not
true and led to confusions and even a regression.
Previously we had:
- SDVO{B,C} defined as the Gen3+ registers
- HDMI{B,C,D} and PCH_SDVOB defined as the PCH registers
But now:
- SDVO{B,C} became GEN3_SDVO{B,C} on SDVO code
- SDVO{B,C} became GEN4_HDMI{B,C} on HDMI code
- HDMI{B,C,D} became PCH_HDMI{B,C,D}
- PCH_SDVOB is still the same thing
v2: Rebase (v1 was sent in May 2012).
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Jesse Barnes [Tue, 19 Feb 2013 20:11:43 +0000 (12:11 -0800)]
drm/i915: remove disabled memset of framebuffer from intel_fb
Commented out and unneeded.
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Ben Widawsky [Mon, 25 Feb 2013 02:10:01 +0000 (18:10 -0800)]
drm/i915: exclude CCID for platforms without it
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Ben Widawsky [Mon, 25 Feb 2013 02:10:00 +0000 (18:10 -0800)]
drm/i915: Created a sized object error dump
v2: Actually use num_pages (Chris)
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Ville Syrjälä [Fri, 1 Mar 2013 12:35:39 +0000 (14:35 +0200)]
drm/i915: Single thread force wake isn't used on HSW anymore
Kill the HSW check from the single thread force wake code. HSW
uses MT force wake exclusively these days.
The commit that removed HSW single thread forcewake support:
commit
36ec8f877481449bdfa072e6adf2060869e2b970
Author: Daniel Vetter <daniel.vetter@ffwll.ch>
Date: Thu Oct 18 14:44:35 2012 +0200
drm/i915: unconditionally use mt forcewake on hsw/ivb
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Ville Syrjälä [Fri, 1 Mar 2013 12:35:38 +0000 (14:35 +0200)]
drm/i915: Use '1' instead of FORCEWAKE_KERNEL for ST force wake
Use the number '1' instead of FORCEWAKE_KERNEL when requesting single
thread force wake since there is only one bit in the register. Using
the FORCEWAKE_KERNEL name might give someone the wrong impression.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Ville Syrjälä [Fri, 1 Mar 2013 12:35:37 +0000 (14:35 +0200)]
drm/i915: Use FORCEWAKE_KERNEL instead of hardcoded number in MT forcewake ACK
The MT forcewake ACK register also has a corresponding bit to each of
the bits in the MT forcewake register. Use the define we have for the
bit we care about instead of a hardcoded number.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Ville Syrjälä [Thu, 28 Feb 2013 17:19:46 +0000 (19:19 +0200)]
drm/i915: Kill a few pointless comments
The code is totally obvious so these comments serve no purpose. What's
worse, one of them was wrong. Just remove them.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Ville Syrjälä [Thu, 28 Feb 2013 17:19:45 +0000 (19:19 +0200)]
drm/i915: Remove a stale and misplaced comment
The load detection code has moved around at some point, but it left
a comment behind. The code now looks to be different enough to make
the comment stale as well. Just remove it.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Ville Syrjälä [Thu, 28 Feb 2013 17:19:44 +0000 (19:19 +0200)]
drm/i915: Document the find_pll() function
The proper use of find_pll() isn't always so easy to determine from the
code itself. Some documentation should help.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Ville Syrjälä [Fri, 22 Feb 2013 14:12:51 +0000 (16:12 +0200)]
drm/i915: Add to_user_ptr()
to_user_ptr() simply casts a pointer passed as u64 from user space
to void __user * correctly. Using this lets us get rid of all the
tiresome casts.
The idea came from Chris Wilson <chris@chris-wilson.co.uk>.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Daniel Vetter [Thu, 21 Feb 2013 23:53:05 +0000 (00:53 +0100)]
drm/i915: gen2 has no tv out support
So ditch that if clause from the i8xx pll update code.
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Rodrigo Vivi [Mon, 25 Feb 2013 22:55:16 +0000 (19:55 -0300)]
drm/i915: Use cpu_transcoder for HSW_TVIDEO_DIP_* instead of pipe
While old platforms had 3 transcoders and 3 pipes (1:1), HSW has
4 transcoders and 3 pipes.
These regs were being used only by HDMI code where pipe is always the same
thing as cpu_transcoder.
This patch allow us to use them for DP, specially for TRANSCODER_EDP.
v2: Adding HSW_TVIDEO_DIP_VSC_DATA to transmit vsc to eDP.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Ville Syrjälä [Wed, 20 Feb 2013 19:16:18 +0000 (21:16 +0200)]
drm/i915: Kill pipestat[] cache
Caching the PIPESTAT enable bits has been deemed pointless. Just
read them from the register itself.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Ville Syrjälä [Tue, 19 Feb 2013 21:16:44 +0000 (23:16 +0200)]
drm/i915: Refactor gen2 to gen4 vblank interrupt handling
The indentation is getting way too deep. Pull the vblank interupt
handling out to separate functions.
v2: Keep flip_mask handling in the main irq handler and
flatten {i8xx,i915}_handle_vblank() even further.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Ville Syrjälä [Tue, 19 Feb 2013 13:16:39 +0000 (15:16 +0200)]
drm/i915: Fix races in gen4 page flip interrupt handling
Use the gen3 logic for handling page flip interrupts on gen4.
Unfortuantely this kills the stall_check since that looks like it can
easily trigger too early. With the current logic the stall check would
kick in on the first vblank after the flip has been submitted to the
ring. If the CS takes longer than that to process the commands in the
ring, the stall check will cause the page flip to be complete too
early. That doesn't sound like a very good idea. Something better
should be deviced if we still need the stall check. For now, mark
i915_pageflip_stall_check() as unused.
v2: Fix irq enable_mask and add __always_unused (Chris Wilson)
References: https://bugs.launchpad.net/ubuntu/+source/xserver-xorg-video-intel/+bug/1116587
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Tested-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Ville Syrjälä [Tue, 19 Feb 2013 13:16:38 +0000 (15:16 +0200)]
drm/i915: Eliminate race from gen2/3 page flip interrupt handling
If the interrupt handler were to process a previous vblank interrupt and
the following flip pending interrupt at the same time, the page flip
would be completed too soon.
To eliminate this race, check the live pending flip status from the ISR
register before finishing the page flip.
v2: Added a comment explaining the logic (by Chris Wilson)
v3: Fix a typo in the comment
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Tested-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Jesse Barnes [Tue, 19 Feb 2013 20:11:38 +0000 (12:11 -0800)]
drm/i915: don't restore LVDS enable state blindly v2
We still rely on a few LVDS bits, but restoring the enable bit can cause
trouble at this point, so don't.
v2: use the right mask to prevent restore (Daniel)
conditionalize on KMS support (Denial)
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Paulo Zanoni [Tue, 19 Feb 2013 19:13:35 +0000 (16:13 -0300)]
drm/i915: clear the FPGA_DBG_RM_NOCLAIM bit at driver init
Otherwise, if the BIOS did anything wrong, our first I915_{WRITE,READ}
will give us "unclaimed register" messages.
V2: Even earlier.
V3: Move it to intel_early_sanitize_regs.
Bugzilla: http://bugs.freedesktop.org/show_bug.cgi?id=58897
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Paulo Zanoni [Mon, 18 Feb 2013 22:00:21 +0000 (19:00 -0300)]
drm/i915: use FPGA_DBG for the "unclaimed register" checks
We plan to treat GEN7_ERR_INT as an interrupt, so use this register
for the checks inside I915_WRITE. This way we can have the best of
both worlds: the error message with a register address and the
V2: Split in 2 patches: one for the macro, one for changing the
register, as requested by Ben.
V3: Rebase.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Paulo Zanoni [Mon, 18 Feb 2013 22:00:20 +0000 (19:00 -0300)]
drm/i915: create functions for the "unclaimed register" checks
This avoids polluting i915_write##x and also allows us to reuse code
on i915_read##x.
v2: Rebase
v3: Convert the macros to static functions
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Paulo Zanoni [Mon, 18 Feb 2013 22:00:26 +0000 (19:00 -0300)]
drm/i915: rename sdvox_reg to hdmi_reg on HDMI context
Some (but not all) of the HDMI registers can be used to control sDVO,
so those registers have two names. IMHO, when we're talking about
HDMI, we really should call the HDMI control register "hdmi_reg"
instead of "sdvox_reg", otherwise we'll just confuse people reading
our code (we now have platforms with HDMI but without SDVO). So now
"struct intel_hdmi" has a member called "hdmi_reg" instead of
"sdvox_reg".
Also, don't worry: "struct intel_sdvo" still has a member called
"sdvo_reg".
v2: Rebase (v1 was sent in May 2012).
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Paulo Zanoni [Mon, 18 Feb 2013 22:00:25 +0000 (19:00 -0300)]
drm/i915: add aux_ch_ctl_reg to struct intel_dp
This way we can remove some duplicated code and avoid more mistakes
and regressions with these registers in the future.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Paulo Zanoni [Mon, 18 Feb 2013 22:00:24 +0000 (19:00 -0300)]
drm/i915: wait_event_timeout's timeout is in jiffies
So use msecs_to_jiffies(10) to make the timeout the same as in the
"!has_aux_irq" case.
This patch was initially written by Daniel Vetter and posted on
pastebin a few weeks ago. I'm just bringing it to the mailing list.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Paulo Zanoni [Mon, 18 Feb 2013 22:00:23 +0000 (19:00 -0300)]
drm/i915: use HAS_DDI on intel_hdmi.c and intel_display.c
Since basically every code called on these places comes from
intel_ddi.c
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Mika Kuoppala [Tue, 19 Feb 2013 10:50:09 +0000 (12:50 +0200)]
drm/i915: remove obsolete obj assignment in page flip
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Jani Nikula [Thu, 14 Feb 2013 08:42:11 +0000 (10:42 +0200)]
drm/i915: add \n to the end of sysfs attributes
It is customary to end sysfs attributes with a newline.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Ville Syrjälä [Mon, 18 Feb 2013 17:08:49 +0000 (19:08 +0200)]
drm/i915: Finish page flips and update primary planes after a GPU reset
GPU reset will drop all flips that are still in the ring. So after the
reset, call update_plane() for all CRTCs to make sure the primary
planes are scanning out from the correct buffer.
Also finish all pending flips. That means user space will get its
page flip events and won't get stuck waiting for them.
v2: Explicitly finish page flips instead of relying on FLIP_DONE
interrupt being generated by the base address update.
v3: Make two loops over crtcs to avoid deadlocks with the crtc mutex
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
[danvet: Fixup long line complaint from checkpatch.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Ville Syrjälä [Mon, 18 Feb 2013 17:08:48 +0000 (19:08 +0200)]
drm/i915: Really wait for pending flips when panning
Since obj->pending_flips was never set, intel_pipe_set_base() never
actually waited for pending page flips to complete.
We really do want to wait for the pending flips, because otherwise the
mmio surface base address update could overtake the flip, and you
could end up with an old frame on the screen once the flip really
completes.
Just call intel_crtc_wait_pending_flips() prior to calling
intel_pipe_set_base() instead of calling just intel_finish_fb()
from intel_pipe_set_base(). Moving the call outside of
intel_pipe_set_base() avoids calling it twice from the full
modeset path.
v2: Wait for pending flips w/o holding struct_mutex
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Damien Lespiau [Mon, 18 Feb 2013 16:47:42 +0000 (16:47 +0000)]
drm/i915: Remove platforms in the preliminary_hw_support description
We already managed to get it out of sync (Haswell has been promoted out
of this option), so let's remove all mentions to platforms.
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Jesse Barnes [Mon, 4 Feb 2013 13:37:21 +0000 (13:37 +0000)]
fb: add support for drivers not needing VT switch at suspend/resume time
Use the new PM routines to indicate whether we need to VT switch at suspend
and resume time. When a new driver is bound, set its flag accordingly,
and when unbound, remove it from the PM's console tracking list.
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Jesse Barnes [Mon, 4 Feb 2013 13:37:20 +0000 (13:37 +0000)]
PM: make VT switching to the suspend console optional v3
KMS drivers can potentially restore the display configuration without
userspace help. Such drivers can can call a new funciton,
pm_vt_switch_required(false) if they support this feature. In that
case, the PM layer won't VT switch to the suspend console at suspend
time and then back to the original VT on resume, but rather leave things
alone for a nicer looking suspend and resume sequence.
v2: make a function so we can handle multiple drivers (Alan)
v3: use a list to track device requests (Rafael)
v4: Squash in build fix from Jesse for CONFIG_VT_CONSOLE_SLEEP=n
v5: Squash in patch from Wu Fengguang to add a few missing static
qualifiers.
v6: Add missing EXPORT_SYMBOL.
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Reviewed-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> (v3)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Daniel Vetter [Mon, 21 Jan 2013 18:48:59 +0000 (19:48 +0100)]
intel/iommu: force writebuffer-flush quirk on Gen 4 Chipsets
We already have the quirk entry for the mobile platform, but also
reports on some desktop versions. So be paranoid and set it
everywhere.
References: http://www.mail-archive.com/dri-devel@lists.freedesktop.org/msg33138.html
Cc: stable@vger.kernel.org
Cc: David Woodhouse <dwmw2@infradead.org>
Cc: "Sankaran, Rajesh" <rajesh.sankaran@intel.com>
Reported-and-tested-by: Mihai Moldovan <ionic@ionic.de>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Chris Wilson [Wed, 13 Feb 2013 09:31:53 +0000 (09:31 +0000)]
drm/i915: Disable WC PTE updates to w/a buggy IOMMU on ILK
Whilst IOMMU is enabled for the Intel GPU on Ironlake, it appears that
using WC writes to update the PTE on the GPU fails miserably. The
result looks like the majority of the writes do not land leading to
lots of screen corruption and a hard system hang.
v2: s/</<=/ to preserve the current exclusion of Sandybridge
Reported-by: Nathan Myers <ncm@cantrip.org>
Bugzilla: https://bugzilla.freedesktop.org/show_bug.cgi?id=60391
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Tested-by: Nathan Myers <ncm@cantrip.org>
[danvet: Remove cc: stable and add tested-by.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Ville Syrjälä [Fri, 18 Jan 2013 17:11:38 +0000 (19:11 +0200)]
drm/i915: Implement pipe CSC based limited range RGB output
HSW no longer has the PIPECONF bit for limited range RGB output.
Instead the pipe CSC unit must be used to perform that task.
The CSC pre offset are set to 0, since the incoming data is full
[0:255] range RGB, the coefficients are programmed to compress the
data into [0:219] range, and then we use either the CSC_MODE black
screen offset bit, or the CSC post offsets to shift the data to
the correct [16:235] range.
Also have to change the confiuration of all planes so that the
data is sent through the pipe CSC unit. For simplicity send the
plane data through the pipe CSC unit always, and in case full
range output is requested, the pipe CSC unit is set up with an
identity transform to pass the plane data through unchanged.
I've been told by some hardware people that the use of the pipe
CSC unit shouldn't result in any measurable increase in power
consumption numbers.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Daniel Vetter [Fri, 15 Feb 2013 17:35:30 +0000 (18:35 +0100)]
drm/i915: inverted brightness quirk for Acer Aspire 4736Z
Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=53881
Cc: stable@vger.kernel.org
Cc: Jani Nikula <jani.nikula@intel.com>
Tested-by: Jani Monoses <jani@ubuntu.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Ben Widawsky [Thu, 14 Feb 2013 23:05:12 +0000 (15:05 -0800)]
drm/i915: Print the hw context status is debugfs
Print out the HW context object information per ring. Even though the
existing code only utilizes the render ring, it's simple enough to
support future expansion.
I had this in a patch somewhere in a rev of the original implementation,
but I must have lost it.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
[danvet: s/context/default context/ bikeshed applied.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Daniel Vetter [Thu, 14 Feb 2013 18:46:07 +0000 (19:46 +0100)]
drm/i915: Use HAS_L3_GPU_CACHE in i915_gem_l3_remap
Yet another remnant ... this might explain why l3 remapping didn't
really work on HSW.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=57441
Spotted-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: stable@vger.kernel.org
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Ville Syrjälä [Thu, 14 Feb 2013 19:53:51 +0000 (21:53 +0200)]
drm/i915: Fix PIPE_CONTROL DW/QW write through global GTT on IVB+
The bit controlling whether PIPE_CONTROL DW/QW write targets
the global GTT or PPGTT moved moved from DW 2 bit 2 to
DW 1 bit 24 on IVB.
I verified on IVB that the fix is in fact effective. Without the fix
none of the scratch writes actually landed in the pipe control page.
With the fix the writes show up correctly.
v2: move PIPE_CONTROL_GLOBAL_GTT_IVB setup to where other flags are set
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Patrik Jakobsson [Wed, 13 Feb 2013 21:20:22 +0000 (22:20 +0100)]
drm/i915: Set i9xx sdvo clock limits according to specifications
The Intel PRM says the M1 and M2 divisors must be in the range of 10-20 and 5-9.
Since we do all calculations based on them being register values (which are
subtracted by 2) we need to specify them accordingly.
Signed-off-by: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=56359
Cc: stable@vger.kernel.org
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Patrik Jakobsson [Wed, 13 Feb 2013 21:20:21 +0000 (22:20 +0100)]
drm/i915: Set i9xx lvds clock limits according to specifications
The Intel PRM says the M1 and M2 divisors must be in the range of 10-20 and 5-9.
Since we do all calculations based on them being register values (which are
subtracted by 2) we need to specify them accordingly.
Signed-off-by: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Damien Lespiau [Tue, 11 Dec 2012 18:48:30 +0000 (18:48 +0000)]
drm/i915: Preserve the DDI link reversal configuration
Similarly to:
commit
6a0d1df3d3a0d2370541164eb0595fe35dcd6de3
Author: Damien Lespiau <damien.lespiau@intel.com>
Date: Tue Dec 11 15:18:28 2012 +0000
drm/i915: Preserve the FDI line reversal override bit on CPT
DDI port support lane reversal to easy the PCB layouting work. Let's
preserve the bit configured by the BIOS (until we find how to correctly
retrieve the information from the VBT, but this does sound more fragile
then just relying on the BIOS that has, hopefully, been validated
already.
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Cc: stable@vger.kernel.org
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Damien Lespiau [Tue, 11 Dec 2012 18:48:29 +0000 (18:48 +0000)]
drm/i915: Preserve the FDI line reversal override bit on CPT
The FDI link has supported link reversal to make the PCB layout
engineer's life easier for quite a while and we have always presered
this bit as we programmed FDI_RX_CTL with a read/modify/write sequence.
We're trying to take a bit more control over what the BIOS leaves in
various register and with the introduction of DDI, started to program
FDI_RX_CTL fully.
There's a fused bit to indicate DMI link reversal and FDI defaults to
mirroring that configuration. We have a bit to override that behaviour
that we need to preserve from the BIOS.
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Cc: stable@vger.kernel.org
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Jani Nikula [Thu, 14 Feb 2013 09:23:35 +0000 (11:23 +0200)]
drm/i915: add missing \n to UTS_RELEASE in the error_state
Amending
commit
4518f611ba21ba165ea3714055938a8984a44ff9
Author: Daniel Vetter <daniel.vetter@ffwll.ch>
Date: Wed Jan 23 16:16:35 2013 +0100
drm/i915: dump UTS_RELEASE into the error_state
CC: stable@vger.kernel.org
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Ville Syrjälä [Thu, 31 Jan 2013 17:43:38 +0000 (19:43 +0200)]
drm: Use C8 instead of RGB332 when determining the format from depth/bpp
Support for real RGB332 is a rarity, most hardware only really support
C8. So use C8 instead of RGB332 when determining the format based on
depth/bpp.
This fixes 8bpp fbcon on i915, since i915 will only accept C8 and not
RGB332.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=59572
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Acked-by: Dave Airlie <airlied@gmail.com>
Tested-by: mlsemon35@gmail.com
Cc: stable@vger.kernel.org
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Ville Syrjälä [Thu, 31 Jan 2013 17:43:37 +0000 (19:43 +0200)]
drm: Fill depth/bits_per_pixel for C8 format
Set depth/bits_per_pixel to 8 for C8 format.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Acked-by: Dave Airlie <airlied@gmail.com>
Cc: stable@vger.kernel.org
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Imre Deak [Wed, 13 Feb 2013 19:56:05 +0000 (21:56 +0200)]
drm/i915: don't clflush gem objects in stolen memory
As explained by Chris Wilson gem objects in stolen memory are always
coherent with the GPU so we don't need to ever flush the CPU caches for
these.
This fixes a breakage - at least with the compact sg patches applied -
during the resume/restore gtt mappings path, when we tried to clflush an
FB object in stolen memory, but since stolen objects don't have backing
pages we passed an invalid page pointer to drm_clflush_page().
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Ville Syrjälä [Tue, 29 Jan 2013 16:13:34 +0000 (18:13 +0200)]
drm/i915: Don't wait for page flips if there was GPU reset
If a GPU reset occurs while a page flip has been submitted to the ring,
the flip will never complete once the ring has been reset.
The GPU reset can be detected by sampling the reset_counter before the
flip is submitted, and then while waiting for the flip, the sampled
counter is compared with the current reset_counter value.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
[danvet: Move the reset_counter assignment to an earlier place in
common code as discussed on the mailing list.]
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=60140
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Ville Syrjälä [Tue, 29 Jan 2013 16:13:33 +0000 (18:13 +0200)]
drm/i915: Kill obj->pending_flip
The pending flip mask no longer set anywhere, so trying to wait for
while it's non-zero is a no-op. Remove it completely.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Damien Lespiau [Wed, 13 Feb 2013 13:29:23 +0000 (13:29 +0000)]
drm/i915: Fix a typo in a intel_modeset_stage_output_state() comment
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Daniel Vetter [Tue, 12 Feb 2013 14:36:03 +0000 (15:36 +0100)]
drm/i915: remove bogus mutex_unlock from error-path
This has been lost in the locking rework for intel_alloc_context_page:
commit
2c34b850ee1e9f86b41706149d0954eee58757a3
Author: Ben Widawsky <ben@bwidawsk.net>
Date: Sat Mar 19 18:14:26 2011 -0700
drm/i915: fix ilk rc6 teardown locking
Cc: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Ville Syrjälä [Tue, 12 Feb 2013 20:01:38 +0000 (22:01 +0200)]
drm/i915: Print the pipe control page GTT address
We already print the HWS addresses during init, so do the same for the
pipe control page. Reduces guesswork when looking at hex addresses
later.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Mika Kuoppala [Fri, 8 Feb 2013 14:35:38 +0000 (16:35 +0200)]
drm/i915: clean up panel fitter handling in lvds
With the previous patch "drm/i915: disable shared panel fitter for
pipe" we now disable the panel fitter at the right spot in the modeset
sequence in the crtc functions on all platforms. Hence the disabling
in intel_disable_lvds is no longer required and potentially harmful
(since the plane is still enabled at this point).
Similarly on the enabling side we enable the panel fitter in the lvds
callback only once the plane is enabled. Which is too late. Hence move
this into a new intel_pre_enable_lvds callback.
Finally we can ditch lvds_encoder->pfit_dirty - this was required to
work around the crtc helper semantics, but with the new i915 modeset
infrastructure we should enable/disable the pfit only when enabling or
disabling the entire output pipeline. So separate state tracking for
the pfit is no longer required.
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
[danvet: Bikeshed the commit message a bit to stress that now we
enable/disable the pfit on i9xx platforms at the right point of time
compared to the old code.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Mika Kuoppala [Fri, 8 Feb 2013 14:35:37 +0000 (16:35 +0200)]
drm/i915: disable shared panel fitter for pipe
If encoder is switched off by BIOS, but the panel fitter is left on,
we never try to turn off the panel fitter and leave it still attached
to the pipe - which can cause blurry output elsewhere.
Based on work by Chris Wilson <chris@chris-wilson.co.uk>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=58867
Cc: stable@vger.kernel.org
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
Tested-by: Andreas Sturmlechner <andreas.sturmlechner@gmail.com>
[danvet: Remove the redundant HAS_PCH_SPLIT check and add a tiny
comment.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Daniel Vetter [Sat, 9 Feb 2013 20:03:42 +0000 (21:03 +0100)]
drm/i915: detect wrong MCH watermark values
Some early bios versions seem to ship with the wrong tuning values for
the MCH, possible resulting in pipe underruns under load. Especially
on DP outputs this can lead to black screen, since DP really doesn't
like an occasional whack from an underrun.
Unfortunately the registers seem to be locked after boot, so the only
thing we can do is politely point out issues and suggest a BIOS
upgrade.
Arthur Runyan pointed us at this issue while discussion DP bugs - thus
far no confirmation from a bug report yet that it helps. But at least
some of my machines here have wrong values, so this might be useful in
understanding bug reports.
v2: After a bit more discussion with Art and Ben we've decided to only
the check the watermark values, since the OREF ones could be be a
notch more aggressive on certain machines.
Cc: Ben Widawsky <ben@bwidawsk.net>
Cc: Runyan, Arthur J <arthur.j.runyan@intel.com>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Ben Widawsky [Mon, 11 Feb 2013 21:31:27 +0000 (13:31 -0800)]
drm/i915/ctx: Remove bad invariant
It's not that the assertion is incorrect, but rather that we can call
do_destroy early in loading, and we will falsely BUG().
Since contexts have been in for a while now, and in the internal APIs
are pretty stable, it should be fairly safe to remove this.
v2: Remove unused dev_priv, and dev
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Ben Widawsky [Fri, 8 Feb 2013 19:49:24 +0000 (11:49 -0800)]
drm/i915: Extract ring init from hw_init
The ring initialization will differ a bit in upcoming generations, and
this split will prepare the code for what's needed.
This patch also fixes a bug introduced in:
commit
99433931950f33039d9e1a52b4ed9af3f1b58e84
Author: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Date: Tue Jan 22 14:12:17 2013 +0200
drm/i915: use gem_set_seqno() on hardware init
After doing the extraction, the bad error handling became obvious. I
acknowledge that this should be two patches, but it's a pretty
small/trivial patch. If requested, I can certainly do the fix as a
distinct patch.
v2: Should be cleanup blt, not init blt on failure (Chris)
v3: Forgot to git add on v2
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Ben Widawsky [Fri, 8 Feb 2013 19:32:47 +0000 (11:32 -0800)]
drm/i915: Fix gen2 mappable calculations
When I refactored the code initially, I forgot that gen2 uses a
different bar for the CPU mappable aperture. The agp-less code knows
nothing of generations less than 5, so we have to expand the gtt_probe
function to include the mappable base and end.
It was originally broken by me:
commit
baa09f5fd8a6d033ec075355dda99a65b7f6a0f3
Author: Ben Widawsky <ben@bwidawsk.net>
Date: Thu Jan 24 13:49:57 2013 -0800
drm/i915: Add probe and remove to the gtt ops
Reported-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Paulo Zanoni [Fri, 8 Feb 2013 19:35:15 +0000 (17:35 -0200)]
drm/i915: add ibx_irq_postinstall
So we can remove duplicated code. Note that this function is used not
only on IBX, but also CPT and LPT.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
[danvet: Also bikeshed s/ironlake_enable_pch_hotplug/ibx_enable_hotplug
to keep consistent with our ibx for pch naming scheme.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Ville Syrjälä [Fri, 8 Feb 2013 21:13:35 +0000 (23:13 +0200)]
drm/i915: Fix sprite_scaling_enabled for multiple sprites
We have more than one sprite, so a boolean simply won't cut it.
Turn sprite_scaling_enabled into a bitmask and track the state
of sprite scaler for each sprite independently.
Also don't re-enable LP watermarks until the sprite registers
have actually been written, and thus sprite scaling has really
been disabled.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Daniel Vetter [Thu, 7 Feb 2013 11:42:32 +0000 (12:42 +0100)]
drm/i915: unify HDMI/DP hpd definitions
They're physically the same pins and also the same bits, duplicating
only confuses the reader. This also makes it a bit obvious that we
have quite some code duplication going on here. Squashing that is for
a larger rework in our hpd handling though.
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Ben Widawsky [Thu, 7 Feb 2013 21:34:19 +0000 (13:34 -0800)]
drm/i915: Clarify HW context size logic
This was a rebase error from when the patches originally landed. Since
the context size is unsigned, there is also no use in checking if it's
less than 0.
The existing code is not really wrong, but it's not simple as it should
be.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Daniel Vetter [Wed, 6 Feb 2013 10:24:41 +0000 (11:24 +0100)]
drm/i915: write backlight harder
770c12312ad617172b1a65b911d3e6564fc5aca8 is the first bad commit
commit
770c12312ad617172b1a65b911d3e6564fc5aca8
Author: Takashi Iwai <tiwai@suse.de>
Date: Sat Aug 11 08:56:42 2012 +0200
drm/i915: Fix blank panel at reopening lid
changed the register write sequence for restoring the backlight, which
helped prevent non-working backlights on some machines. Turns out that
the original sequence was the right thing to do for a different set of
machines. Worse, setting the backlight level _after_ enabling it seems
to reset it somehow. So we need to make that one conditional upon the
backlight having been reset to zero, and add the old one back.
Cargo-culting at it's best, but it seems to work.
Cc: stable@vger.kernel.org
Cc: Takashi Iwai <tiwai@suse.de>
Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=47941
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Acked-by: Takashi Iwai <tiwai@suse.de>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Zhang Rui [Tue, 5 Feb 2013 07:41:53 +0000 (15:41 +0800)]
i915: ignore lid open event when resuming
i915 driver needs to do modeset when
1. system resumes from sleep
2. lid is opened
In PM_SUSPEND_MEM state, all the GPEs are cleared when system resumes,
thus it is the i915_resume code does the modeset rather than intel_lid_notify().
But in PM_SUSPEND_FREEZE state, this will be broken because
system is still responsive to the lid events.
1. When we close the lid in Freeze state, intel_lid_notify() sets modeset_on_lid.
2. When we reopen the lid, intel_lid_notify() will do a modeset,
before the system is resumed.
here is the error log,
[92146.548074] WARNING: at drivers/gpu/drm/i915/intel_display.c:1028 intel_wait_for_pipe_off+0x184/0x190 [i915]()
[92146.548076] Hardware name: VGN-Z540N
[92146.548078] pipe_off wait timed out
[92146.548167] Modules linked in: hid_generic usbhid hid snd_hda_codec_realtek snd_hda_intel snd_hda_codec parport_pc snd_hwdep ppdev snd_pcm_oss i915 snd_mixer_oss snd_pcm arc4 iwldvm snd_seq_dummy mac80211 snd_seq_oss snd_seq_midi fbcon tileblit font bitblit softcursor drm_kms_helper snd_rawmidi snd_seq_midi_event coretemp drm snd_seq kvm btusb bluetooth snd_timer iwlwifi pcmcia tpm_infineon i2c_algo_bit joydev snd_seq_device intel_agp cfg80211 snd intel_gtt yenta_socket pcmcia_rsrc sony_laptop agpgart microcode psmouse tpm_tis serio_raw mxm_wmi soundcore snd_page_alloc tpm acpi_cpufreq lpc_ich pcmcia_core tpm_bios mperf processor lp parport firewire_ohci firewire_core crc_itu_t sdhci_pci sdhci thermal e1000e
[92146.548173] Pid: 4304, comm: kworker/0:0 Tainted: G W 3.8.0-rc3-s0i3-v3-test+ #9
[92146.548175] Call Trace:
[92146.548189] [<
c10378e2>] warn_slowpath_common+0x72/0xa0
[92146.548227] [<
f86398b4>] ? intel_wait_for_pipe_off+0x184/0x190 [i915]
[92146.548263] [<
f86398b4>] ? intel_wait_for_pipe_off+0x184/0x190 [i915]
[92146.548270] [<
c10379b3>] warn_slowpath_fmt+0x33/0x40
[92146.548307] [<
f86398b4>] intel_wait_for_pipe_off+0x184/0x190 [i915]
[92146.548344] [<
f86399c2>] intel_disable_pipe+0x102/0x190 [i915]
[92146.548380] [<
f8639ea4>] ? intel_disable_plane+0x64/0x80 [i915]
[92146.548417] [<
f8639f7c>] i9xx_crtc_disable+0xbc/0x150 [i915]
[92146.548456] [<
f863ebee>] intel_crtc_update_dpms+0x5e/0x90 [i915]
[92146.548493] [<
f86437cf>] intel_modeset_setup_hw_state+0x42f/0x8f0 [i915]
[92146.548535] [<
f8645b0b>] intel_lid_notify+0x9b/0xc0 [i915]
[92146.548543] [<
c15610d3>] notifier_call_chain+0x43/0x60
[92146.548550] [<
c105d1e1>] __blocking_notifier_call_chain+0x41/0x80
[92146.548556] [<
c105d23f>] blocking_notifier_call_chain+0x1f/0x30
[92146.548563] [<
c131a684>] acpi_lid_send_state+0x78/0xa4
[92146.548569] [<
c131aa9e>] acpi_button_notify+0x3b/0xf1
[92146.548577] [<
c12df56a>] ? acpi_os_execute+0x17/0x19
[92146.548582] [<
c12e591a>] ? acpi_ec_sync_query+0xa5/0xbc
[92146.548589] [<
c12e2b82>] acpi_device_notify+0x16/0x18
[92146.548595] [<
c12f4904>] acpi_ev_notify_dispatch+0x38/0x4f
[92146.548600] [<
c12df0e8>] acpi_os_execute_deferred+0x20/0x2b
[92146.548607] [<
c1051208>] process_one_work+0x128/0x3f0
[92146.548613] [<
c1564f73>] ? common_interrupt+0x33/0x38
[92146.548618] [<
c104f8c0>] ? wake_up_worker+0x30/0x30
[92146.548624] [<
c12df0c8>] ? acpi_os_wait_events_complete+0x1e/0x1e
[92146.548629] [<
c10524f9>] worker_thread+0x119/0x3b0
[92146.548634] [<
c10523e0>] ? manage_workers+0x240/0x240
[92146.548640] [<
c1056e84>] kthread+0x94/0xa0
[92146.548647] [<
c1060000>] ? ftrace_raw_output_sched_stat_runtime+0x70/0xf0
[92146.548652] [<
c15649b7>] ret_from_kernel_thread+0x1b/0x28
[92146.548658] [<
c1056df0>] ? kthread_create_on_node+0xc0/0xc0
three different modeset flags are introduced in this patch
MODESET_ON_LID_OPEN: do modeset on next lid open event
MODESET_DONE: modeset already done
MODESET_SUSPENDED: suspended, only do modeset when system is resumed
In this way,
1. when lid is closed, MODESET_ON_LID_OPEN is set so that
we'll do modeset on next lid open event.
2. when lid is opened, MODESET_DONE is set
so that duplicate lid open events will be ignored.
3. when system suspends, MODESET_SUSPENDED is set.
In this case, we will not do modeset on any lid events.
Plus, locking mechanism is also introduced to avoid racing.
Signed-off-by: Zhang Rui <rui.zhang@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Ben Widawsky [Sat, 2 Feb 2013 00:41:14 +0000 (16:41 -0800)]
drm/i915: Fix RC6VIDS encode/decode
The RC6 VIDS has a linear ramp starting at 250mv, which means any values
below 250 are invalid. The old buggy macros tried to adjust for this to
be more flexible, but there is no need. As Dan pointed out the ENCODE
only ever has one value. The only invalid value for decode is an input
of 0 which means something is really wonky, and the cases where DECODE
are used either don't matter (debug values), or would be implicitly
correct (the check for less than 450).
This patch makes simpler, easier to read macros which are actually
correct. Maybe this patch can actually fix some bugs now.
Thanks to Dan for catching this. /me hides
Cc: stable@kernel.org
Reported-by: Dan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Daniel Vetter [Wed, 13 Feb 2013 10:37:48 +0000 (20:37 +1000)]
Revert "drm: Add EDID_QUIRK_FORCE_REDUCED_BLANKING for ASUS VW222S"
This reverts commit
6f33814bd4d9cfe76033a31b1c0c76c960cd8e4b.
The quirk cause a regression, and it looks like the original bug was
simply a lack of FIFO bandwidth on the i915G of the reporter. Which
should eventually be fixed as soon as we get around to implemented
DSPARB FIFO reassignment on gen 3.
Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=52281
Cc: stable@vger.kernel.org
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Fri, 8 Feb 2013 04:02:32 +0000 (14:02 +1000)]
Merge branch 'for-airlied' of git://people.freedesktop.org/~mlankhorst/linux into drm-next
TTM reservations changes, preparing for new reservation mutex system.
* 'for-airlied' of git://people.freedesktop.org/~mlankhorst/linux:
drm/ttm: unexport ttm_bo_wait_unreserved
drm/nouveau: use ttm_bo_reserve_slowpath in validate_init, v2
drm/ttm: use ttm_bo_reserve_slowpath_nolru in ttm_eu_reserve_buffers, v2
drm/ttm: add ttm_bo_reserve_slowpath
drm/ttm: cleanup ttm_eu_reserve_buffers handling
drm/ttm: remove lru_lock around ttm_bo_reserve
drm/nouveau: increase reservation sequence every retry
drm/vmwgfx: always use ttm_bo_is_reserved
Daniel Kurtz [Thu, 27 Dec 2012 01:01:46 +0000 (01:01 +0000)]
drm: make frame duration time calculation more precise
It is a bit more precise to compute the total number of pixels first and
then divide, rather than multiplying the line pixel count by the
already-rounded line duration.
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Bjorn Helgaas [Fri, 4 Jan 2013 19:10:42 +0000 (19:10 +0000)]
drm/pci: Use PCI Express Capability accessors
Use PCI Express Capability access functions to simplify this code a bit.
For non-PCIe devices or pre-PCIe 3.0 devices that don't implement the Link
Capabilities 2 register, pcie_capability_read_dword() reads a zero.
Since we're only testing whether the bits we care about are set, there's no
need to mask out the other bits we *don't* care about.
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Bjorn Helgaas [Fri, 4 Jan 2013 19:10:37 +0000 (19:10 +0000)]
drm/pci: Set all supported speeds in speed cap mask for pre-3.0 devices
For devices that conform to PCIe r3.0 and have a Link Capabilities 2
register, we test and report every bit in the Supported Link Speeds Vector
field. For a device that supports both 2.5GT/s and 5.0GT/s, we set both
DRM_PCIE_SPEED_25 and DRM_PCIE_SPEED_50 in the returned mask.
For pre-r3.0 devices, the Link Capabilities 0010b encoding
(PCI_EXP_LNKCAP_SLS_5_0GB) means that both 5.0GT/s and 2.5GT/s are
supported, so set both DRM_PCIE_SPEED_25 and DRM_PCIE_SPEED_50 in this
case as well.
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Bjorn Helgaas [Fri, 4 Jan 2013 19:10:32 +0000 (19:10 +0000)]
drm/pci: Use the standard #defines for PCIe Link Capability bits
Use the standard #defines rather than bare numbers for the PCIe Link
Capabilities speed bits.
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Thierry Reding [Mon, 14 Jan 2013 16:05:56 +0000 (16:05 +0000)]
drm: Allow vblank support without DRIVER_HAVE_IRQ
Drivers that register interrupt handlers without the DRM core helpers
don't initialize the .irq_enabled field and drm_dev_to_irq() may fail
when called on them. This shouldn't preclude them from implementing
the vblank IOCTL.
Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Aaron Plattner [Tue, 15 Jan 2013 20:47:44 +0000 (20:47 +0000)]
drm/radeon: use prime helpers
Simplify the Radeon prime implementation by using the default behavior provided
by drm_gem_prime_import and drm_gem_prime_export.
v2:
- Rename functions to radeon_gem_prime_get_sg_table and
radeon_gem_prime_import_sg_table.
- Delete the now-unused vmapping_count variable.
Signed-off-by: Aaron Plattner <aplattner@nvidia.com>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: David Airlie <airlied@linux.ie>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Aaron Plattner [Tue, 15 Jan 2013 20:47:43 +0000 (20:47 +0000)]
drm/nouveau: use prime helpers
Simplify the Nouveau prime implementation by using the default behavior provided
by drm_gem_prime_import and drm_gem_prime_export.
v2: Rename functions to nouveau_gem_prime_get_sg_table and
nouveau_gem_prime_import_sg_table.
Signed-off-by: Aaron Plattner <aplattner@nvidia.com>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: David Airlie <airlied@linux.ie>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Aaron Plattner [Tue, 15 Jan 2013 20:47:42 +0000 (20:47 +0000)]
drm: add prime helpers
Instead of reimplementing all of the dma_buf functionality in every driver,
create helpers drm_prime_import and drm_prime_export that implement them in
terms of new, lower-level hook functions:
gem_prime_pin: callback when a buffer is created, used to pin buffers into GTT
gem_prime_get_sg_table: convert a drm_gem_object to an sg_table for export
gem_prime_import_sg_table: convert an sg_table into a drm_gem_object
gem_prime_vmap, gem_prime_vunmap: map and unmap an object
These hooks are optional; drivers can opt in by using drm_gem_prime_import and
drm_gem_prime_export as the .gem_prime_import and .gem_prime_export fields of
struct drm_driver.
v2:
- Drop .begin_cpu_access. None of the drivers this code replaces implemented
it. Having it here was a leftover from when I was trying to include i915 in
this rework.
- Use mutex_lock instead of mutex_lock_interruptible, as these three drivers
did. This patch series shouldn't change that behavior.
- Rename helpers to gem_prime_get_sg_table and gem_prime_import_sg_table.
Rename struct sg_table* variables to 'sgt' for clarity.
- Update drm.tmpl for these new hooks.
v3:
- Pass the vaddr down to the driver. This lets drivers that just call vunmap on
the pointer avoid having to store the pointer in their GEM private structures.
- Move documentation into a /** DOC */ comment in drm_prime.c and include it in
drm.tmpl with a !P line. I tried to use !F lines to include documentation of
the individual functions from drmP.h, but the docproc / kernel-doc scripts
barf on that file, so hopefully this is good enough for now.
- apply refcount fix from commit
be8a42ae60addd8b6092535c11b42d099d6470ec
("drm/prime: drop reference on imported dma-buf come from gem")
Signed-off-by: Aaron Plattner <aplattner@nvidia.com>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: David Airlie <airlied@linux.ie>
Signed-off-by: Dave Airlie <airlied@redhat.com>