Marek Olšák [Tue, 21 Jun 2016 19:13:00 +0000 (21:13 +0200)]
gallium/radeon: use r600_resource_reference
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Vedran Miletić <vedran@miletic.net>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Jason Ekstrand [Thu, 23 Jun 2016 21:22:03 +0000 (14:22 -0700)]
nir: Add a NIR_VALIDATE environment variable
It defaults to true so default behavior doesn't change but it allows you to
do NIR_VALIDATE=false if you don't want validation. Disabling validation
can substantially speed up shader compiles so you frequently want to turn
it off if compiler invariants aren't in question.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Axel Davy [Tue, 14 Jun 2016 21:24:24 +0000 (23:24 +0200)]
st/nine: Use offset_units_unscaled
offset_units_unscaled enables proper support
for depth bias for gallium nine. Use it
if available.
Solves issues with some games using depth bias.
For example:
https://github.com/iXit/Mesa-3D/issues/220
Signed-off-by: Axel Davy <axel.davy@ens.fr>
Axel Davy [Tue, 14 Jun 2016 21:13:26 +0000 (23:13 +0200)]
r600g: Implement POLYGON_OFFSET_UNITS_UNSCALED
Empirical tests show that the polygon offset
behaviour is entirely determined by the content of
the PA_SU_POLY_OFFSET states, and not by the depth buffer
format bound.
PA_SU_POLY_OFFSET seems to directly set the parameters of
the polygon offset formula, and setting 0 for
PA_SU_POLY_OFFSET_DB_FMT_CNTL (ie setting the unorm depth
bias behaviour with a scale of 2^0 = 1.0f) gives the unscaled
behaviour.
Signed-off-by: Axel Davy <axel.davy@ens.fr>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Axel Davy [Tue, 14 Jun 2016 20:41:50 +0000 (22:41 +0200)]
radeonsi: Implement POLYGON_OFFSET_UNITS_UNSCALED
Empirical tests show that the polygon offset
behaviour is entirely determined by the content of
the PA_SU_POLY_OFFSET states, and not by the depth buffer
format bound.
PA_SU_POLY_OFFSET seems to directly set the parameters of
the polygon offset formula, and setting 0 for
PA_SU_POLY_OFFSET_DB_FMT_CNTL (ie setting the unorm depth
bias behaviour with a scale of 2^0 = 1.0f) gives the unscaled
behaviour.
Signed-off-by: Axel Davy <axel.davy@ens.fr>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Axel Davy [Tue, 14 Jun 2016 20:32:04 +0000 (22:32 +0200)]
radeon: Remove useless pa_su_poly_offset_db_fmt_cntl
pa_su_poly_offset_db_fmt_cntl usages were removed in
previous patches.
Signed-off-by: Axel Davy <axel.davy@ens.fr>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Axel Davy [Tue, 14 Jun 2016 20:30:11 +0000 (22:30 +0200)]
r600g: move PA_SU_POLY_OFFSET_DB_FMT_CNTL to poly offset states for evergreen
Emit PA_SU_POLY_OFFSET_DB_FMT_CNTL with the other poly_offset states.
This will be useful to implement
PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED.
v2: Increase the num_dw field for the poly offset atom
Signed-off-by: Axel Davy <axel.davy@ens.fr>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Axel Davy [Tue, 14 Jun 2016 20:22:50 +0000 (22:22 +0200)]
r600g: move PA_SU_POLY_OFFSET_DB_FMT_CNTL to poly offset states for r600
Emit PA_SU_POLY_OFFSET_DB_FMT_CNTL with the other poly_offset states.
This will be useful to implement
PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED.
v2: Increase the num_dw field for the poly offset atom
Signed-off-by: Axel Davy <axel.davy@ens.fr>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Axel Davy [Tue, 14 Jun 2016 20:04:41 +0000 (22:04 +0200)]
radeonsi: move PA_SU_POLY_OFFSET_DB_FMT_CNTL to poly offset states
Emit PA_SU_POLY_OFFSET_DB_FMT_CNTL with rasterizer poly_offset states.
This will be useful to implement
PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED.
Signed-off-by: Axel Davy <axel.davy@ens.fr>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Axel Davy [Mon, 13 Jun 2016 20:28:32 +0000 (22:28 +0200)]
gallium: Add a cap for offset_units_unscaled
D3D9 has a different behaviour for depth bias.
For OGL/D3D1X, the depth bias unit is the
minimal resolvable value for the depth buffer,
which depends on the format (and has different
behaviour for float depth buffers).
For D3D9, the depth bias unit is 1.0f.
Signed-off-by: Axel Davy <axel.davy@ens.fr>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Jordan Justen [Sun, 12 Jun 2016 01:16:47 +0000 (18:16 -0700)]
i965: Skip update_texture_surface when the plane doesn't exist
Reported-by: Grazvydas Ignotas <notasas@gmail.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=96607
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Cc: Kristian Høgsberg <krh@bitplanet.net>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Chad Versace <chad.versace@intel.com>
Kenneth Graunke [Thu, 9 Jun 2016 19:36:55 +0000 (12:36 -0700)]
i965: Validate a few SEND-from-GRF requirements.
We recently had a mistake where we emitted SEND instructions with EOT
set, but from g107 rather than g112-g127. Adding validation code should
prevent these sorts of problems from slipping back in.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Kenneth Graunke [Thu, 23 Jun 2016 00:15:13 +0000 (17:15 -0700)]
i965: Delete send-from-GRF only opcodes from implied_mrf_writes().
These only exist post-Sandybridge, and always use send-from-GRF.
So inst->base_mrf will be -1, and we will have already returned 0.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Kenneth Graunke [Thu, 23 Jun 2016 00:14:05 +0000 (17:14 -0700)]
i965: Drop unnecessary inst->base_mrf = -1 assignments.
These are now unnecessary, as base_mrf is -1 by default.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Kenneth Graunke [Thu, 23 Jun 2016 00:01:12 +0000 (17:01 -0700)]
i965: Set fs_inst::base_mrf = -1 by default.
On MRF platforms, we need to set base_mrf to the first MRF value we'd
like to use for the message. On send-from-GRF platforms, we set it to
-1 to indicate that the operation doesn't use MRFs.
As MRF platforms are becoming increasingly a thing of the past, we've
forgotten to bother with this. It makes more sense to set it to -1 by
default, so we don't have to think about it for new code.
I searched the code for every instance of 'mlen =' in brw_fs*cpp, and
it appears that all MRF-based messages correctly program a base_mrf.
Forgetting to set base_mrf = -1 can confuse the register allocator,
causing it to think we have a large fake-MRF region. This ends up
moving the send-with-EOT registers earlier, sometimes even out of
the g112-g127 range, which is illegal. For example, this fixes
illegal sends in Piglit's arb_gpu_shader_fp64-layout-std430-fp64-shader,
which had SSBO messages with mlen > 0 but base_mrf == 0.
Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Kenneth Graunke [Sun, 19 Jun 2016 06:40:21 +0000 (23:40 -0700)]
i965: Drop unused return value from intel_finalize_mipmap_tree().
The old return type of GLuint was wonky - it should have been bool.
But nothing actually uses the return value anyway, so we can just drop
that and make it a void function.
In theory, it might make sense to ask whether the texture validated
successfully, but just checking intel_obj->mt != NULL works for that.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Kenneth Graunke [Sun, 19 Jun 2016 06:36:59 +0000 (23:36 -0700)]
i965: Move contents of brw_tex.c into intel_tex_validate.c.
brw_tex.c is a tiny file containing a single function. It's closely
tied to the validation logic in intel_tex_validate.c, so it makes sense
to put both in the same file.
While we're at it, update the function to our modern style.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Marek Olšák [Fri, 24 Jun 2016 00:17:38 +0000 (02:17 +0200)]
radeonsi: fix fractional odd tessellation spacing for Polaris
ported from Vulkan (and no source explains why this is needed)
Cc: 12.0 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Thu, 23 Jun 2016 22:03:26 +0000 (00:03 +0200)]
radeonsi: set some VGT context registers on SI-CI
the kernel sets them, but other UMDs can change them
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Thu, 23 Jun 2016 21:55:24 +0000 (23:55 +0200)]
radeonsi: optimize rendering to linear color buffers
loosely ported from Vulkan
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Thu, 23 Jun 2016 21:26:25 +0000 (23:26 +0200)]
radeonsi: set almost optimal settings in SC_MODE_CNTL_1
ported from Vulkan
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Thu, 23 Jun 2016 20:24:07 +0000 (22:24 +0200)]
gallium/radeon: let drivers specify SC_MODE_CNTL_1 fields
radeonsi will set more fields
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Thu, 23 Jun 2016 19:42:39 +0000 (21:42 +0200)]
gallium/radeon: disable complicated point clipping against user clip planes
Nothing in the GL spec says that we should expand points to triangles.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Fri, 24 Jun 2016 00:22:42 +0000 (02:22 +0200)]
radeonsi: fix a compute shader hang with big threadgroups on SI & CI
ported from Vulkan
Cc: 12.0 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Ilia Mirkin [Fri, 24 Jun 2016 02:33:59 +0000 (22:33 -0400)]
nvc0: when mapping directly, provide accurate xfer info + start
We were ignoring the incoming box parameters, and were providing totally
bogus stride/layer stride, and other bits, for when a non-full-surface
map was requested.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Tested-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Cc: <mesa-stable@lists.freedesktop.org>
Ilia Mirkin [Fri, 24 Jun 2016 02:27:40 +0000 (22:27 -0400)]
st/mesa: don't assume that the whole surface gets mapped
Under some circumstances, the driver may choose to return a temporary
surface instead of a pointer to the original. Make sure to pass the
actual view volume to be mapped to the transfer function rather than
adjusting the map pointer after-the-fact.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Nicolai Hähnle [Thu, 23 Jun 2016 23:11:09 +0000 (01:11 +0200)]
radeonsi: drop the DRAW_PREAMBLE packet on Polaris
It will be removed from the firmware for the Polaris.
Cc: 12.0 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Thu, 23 Jun 2016 13:00:53 +0000 (15:00 +0200)]
radeonsi: use DRAW_(INDEX_)INDIRECT_MULTI on Polaris
The non-MULTI variants will be removed in Polaris firmware.
Cc: 12.0 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Francesco Ansanelli [Thu, 23 Jun 2016 17:56:09 +0000 (19:56 +0200)]
st/mesa: handle negative _ColorDrawBufferIndexes values correctly
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Wed, 22 Jun 2016 09:22:33 +0000 (11:22 +0200)]
winsys/radeon: add guard pages when R600_DEBUG=check_vm is enabled
This should help flush out GPU VM faults.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Wed, 22 Jun 2016 09:22:33 +0000 (11:22 +0200)]
winsys/amdgpu: add guard pages when R600_DEBUG=check_vm is enabled
This should help flush out GPU VM faults.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Mon, 20 Jun 2016 18:24:03 +0000 (20:24 +0200)]
radeonsi: report a failure to parse dmesg instead of asserting
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Mon, 20 Jun 2016 15:19:28 +0000 (17:19 +0200)]
radeon: check VM faults from DMA flush
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Mon, 20 Jun 2016 14:47:06 +0000 (16:47 +0200)]
radeonsi: move gfx fence wait out of si_check_vm_faults
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Mon, 20 Jun 2016 14:30:29 +0000 (16:30 +0200)]
radeonsi: extract IB and bo list saving into separate functions
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Wed, 22 Jun 2016 15:36:18 +0000 (17:36 +0200)]
st/mesa: fix readpixels regression with MESA_pack_invert
Fixes an error introduced in commit
3948cd37973696dc319170877382676809659465.
Reported-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Marek Olšák [Tue, 21 Jun 2016 21:28:46 +0000 (23:28 +0200)]
radeonsi: set LLVM denormal flags
- make sure FP32 denormals will stay disabled in LLVM in the future
(the current default is disabled)
- tell LLVM that FP64 denormals are enabled
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Marek Olšák [Tue, 21 Jun 2016 20:45:29 +0000 (22:45 +0200)]
radeonsi: emit 1/sqrt for RSQ
We don't need the clamped version and we don't have to use any intrinsic.
Stats on Tonga:
15382 shaders in 9128 tests
Totals:
SGPRS: 1230560 -> 1230560 (0.00 %)
VGPRS: 469577 -> 462504 (-1.51 %)
Code Size:
22089908 ->
21730052 (-1.63 %) bytes
LDS: 598 -> 598 (0.00 %) blocks
Scratch: 283648 -> 281600 (-0.72 %) bytes per wave
Max Waves: 125664 -> 126969 (1.04 %)
Wait states: 0 -> 0 (0.00 %)
Totals from affected shaders:
SGPRS: 547280 -> 547280 (0.00 %)
VGPRS: 269132 -> 262059 (-2.63 %)
Code Size:
15709604 ->
15349748 (-2.29 %) bytes
LDS: 198 -> 198 (0.00 %) blocks
Scratch: 74752 -> 72704 (-2.74 %) bytes per wave
Max Waves: 47840 -> 49145 (2.73 %)
Wait states: 0 -> 0 (0.00 %)
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Jan Vesely [Wed, 15 Jun 2016 23:41:22 +0000 (19:41 -0400)]
r600g: Enable FMA on chips that support it
v2: Merge with PIPE_SHADER_CAP_DOUBLES
Add CHIP_HEMLOCK
v3: only set the instruction on EG and CM
Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Marek Olšák [Sat, 11 Jun 2016 15:28:52 +0000 (17:28 +0200)]
gallium/u_queue: allow the execute function to differ per job
so that independent types of jobs can use the same queue.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Thu, 16 Jun 2016 23:33:12 +0000 (01:33 +0200)]
gallium/u_queue: reduce the number of mutexes by 2
by converting semaphores to condvars and using the main mutex
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Sun, 12 Jun 2016 11:36:39 +0000 (13:36 +0200)]
gallium/u_queue: add an option to name threads
for debugging
v2: correct the snprintf use
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Sat, 11 Jun 2016 13:40:28 +0000 (15:40 +0200)]
gallium/u_queue: add an option to have multiple worker threads
independent jobs don't have to be stuck on only one thread
v2: use CALLOC & FREE
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Sat, 11 Jun 2016 15:51:22 +0000 (17:51 +0200)]
gallium/u_queue: rewrite util_queue_fence to allow multiple waiters
Checking "signalled" is first done without a mutex, then with a mutex.
Also, checking without waiting doesn't lock the mutex. This is racy, but
should be safe.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Sun, 12 Jun 2016 10:54:42 +0000 (12:54 +0200)]
gallium/u_queue: use a ring instead of a stack
and allow specifying its size in util_queue_init.
v2: use CALLOC & FREE
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Jordan Justen [Wed, 22 Jun 2016 17:34:08 +0000 (17:34 +0000)]
i965: Preserve the internal format of the dri image
Since the OpenGLES API is strict about the internal format matching
the for many operations, we need to preserve it.
See _mesa_es3_error_check_format_and_type in
src/mesa/main/glformats.c.
Fixes ES2-CTS.gtf.GL2ExtensionTests.egl_image.egl_image
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=96351
Reported-by: Mark Janes <mark.a.janes@intel.com>
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Cc: Kristian Høgsberg <krh@bitplanet.net>
Cc: Chad Versace <chad.versace@intel.com>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Chad Versace <chad.versace@intel.com>
Chad Versace [Wed, 22 Jun 2016 16:17:41 +0000 (09:17 -0700)]
anv: Add anv_render_pass_attachment::store_op
Will be needed for resolving auxiliary surfaces.
I didn't add anv_render_pass_attachment::stencil_store_op, as the driver
would likely never use it, as stencil surfaces never have auxiliary
surfaces.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Gurkirpal Singh [Thu, 23 Jun 2016 10:24:11 +0000 (15:54 +0530)]
gbm: Fix comments
Reviewed-by: Chad Versace <chad.versace@intel.com>
Eric Engestrom [Thu, 23 Jun 2016 11:00:44 +0000 (12:00 +0100)]
gbm: doc fixes
Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Chad Versace <chad.versace@intel.com>
Giuseppe Bilotta [Thu, 23 Jun 2016 17:20:18 +0000 (19:20 +0200)]
Remove wrongly repeated words in comments
Clean up misrepetitions ('if if', 'the the' etc) found throughout the
comments. This has been done manually, after grepping
case-insensitively for duplicate if, is, the, then, do, for, an,
plus a few other typos corrected in fly-by
v2:
* proper commit message and non-joke title;
* replace two 'as is' followed by 'is' to 'as-is'.
v3:
* 'a integer' => 'an integer' and similar (originally spotted by
Jason Ekstrand, I fixed a few other similar ones while at it)
Signed-off-by: Giuseppe Bilotta <giuseppe.bilotta@gmail.com>
Reviewed-by: Chad Versace <chad.versace@intel.com>
Brian Paul [Wed, 22 Jun 2016 23:24:12 +0000 (17:24 -0600)]
svga: update some comments in svga_buffer_handle()
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Brian Paul [Wed, 22 Jun 2016 23:19:58 +0000 (17:19 -0600)]
svga: add a const qualifier in svga_buffer_upload_piecewise()
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Brian Paul [Wed, 22 Jun 2016 23:18:17 +0000 (17:18 -0600)]
svga: minor code refactor for svga_buffer_upload_command()
Put the HBS code into a separate function.
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Brian Paul [Wed, 22 Jun 2016 22:51:15 +0000 (16:51 -0600)]
svga: minor code simplification in svga_context_finish()
Signed-off-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Kenneth Graunke [Wed, 22 Jun 2016 18:25:26 +0000 (11:25 -0700)]
i965: Implement rasterizer discard via SOL unless required for queries.
We currently use CL_INVOCATION_COUNT for the GL_PRIMITIVES_GENERATED
query, which involves passing all primitives to the clipper. When
rasterizer discard is enabled, we program the clipper in REJECT_ALL
mode, rather than using the SOL stage's "Rendering Disable" feature.
See commit
f09b91f78247409f54c975f56cb10d5f350fe64e for an explanation
of why we implement GL_PRIMITIVES_GENERATED this way.
Apparently the SOL stage's "Rendering Disable" feature is a lot faster
than having the clipper reject all primitives. It's safe to use when
no GL_PRIMITIVES_GENERATED query is active, as we don't care about
CL_INVOCATION_COUNT incrementing.
This patch makes us use SO_RENDERING_DISABLE when no query is active,
but continues falling back to the clipper in REJECT_ALL mode when the
queries are enabled. It brings back the perf_debug for the clipper
case (which I removed in commit
1f9445ff57b, thinking it wasn't useful).
Improves performance in Gl32GSCloth by 84.8303% +/- 2.07132% (n = 10)
on my Broadwell GT2 laptop.
Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Kenneth Graunke [Wed, 22 Jun 2016 07:33:46 +0000 (00:33 -0700)]
i965: Combine 3DSTATE_STREAMOUT emitters and genX_sol_state atoms.
They're basically the same. Let's avoid the code duplication.
v2: Fix SO_BUFFER_ENABLE stuff to only happen on Gen < 8 (caught
by Jason Ekstrand).
Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Kenneth Graunke [Sat, 30 Apr 2016 00:57:46 +0000 (17:57 -0700)]
glsl: Don't constant propagate arrays.
Constant propagation on arrays doesn't make a lot of sense. If the
array is only accessed with constant indexes, then opt_array_splitting
would split it up. Otherwise, we have variable indexing. If there's
multiple accesses, then constant propagation would end up replicating
the data.
The lower_const_arrays_to_uniforms pass creates uniforms for each
ir_constant with array type that it encounters. This means that it
creates redundant uniforms for each copy of the constant, which means
uploading too much data. It can even mean exceeding the maximum number
of uniform components, causing link failures.
We could try and teach the pass to de-duplicate the data by hashing
constants, but it makes more sense to avoid duplicating it in the first
place. We should promote constant arrays to uniforms, then propagate
the uniform access.
Fixes the TressFX shaders from Tomb Raider, which exceeded the maximum
number of uniform components by a huge margin and failed to link.
On Broadwell:
total instructions in shared programs: 9067702 -> 9068202 (0.01%)
instructions in affected programs: 10335 -> 10835 (4.84%)
helped: 10 (Hoard, Shadow of Mordor, Amnesia: The Dark Descent)
HURT: 20 (Natural Selection 2)
loops in affected programs: 4 -> 0
The hurt programs appear to no longer have a constarray uniform, as
all constants were successfully propagated. Apparently before this
patch, we successfully unrolled a loop containing array access, but
only after promoting constant arrays to uniforms. With this patch,
we unroll it first, so all array access is direct, and the array
is split up, and individual constants are propagated. This seems
better.
Cc: mesa-stable@lists.freedesktop.org
Reported-by: Karol Herbst <nouveau@karolherbst.de>
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
Kenneth Graunke [Sat, 30 Apr 2016 01:05:26 +0000 (18:05 -0700)]
glsl: Make lower_const_arrays_to_uniforms work directly on constants.
There's really no point in looking at ir_dereference_array of a
constant. It also misses cases like:
(assign () (var_ref tmp) (constant (array ...) ...))
No changes in shader-db, but keeps it working after the next commit.
Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
Kenneth Graunke [Sat, 30 Apr 2016 04:12:15 +0000 (21:12 -0700)]
i965: Copy propagate before doing variable index lowering.
The scalar backend currently doesn't support variable indexing on
temporary arrays, but it does support it on uniform arrays, and
some stages support it for input arrays. Make sure these are
propagated through before exploding indirects into piles of
if-ladders unnecessarily.
On Broadwell, no instruction count change in shader-db.
total cycles in shared programs:
80675652 ->
80674928 (-0.00%)
cycles in affected programs: 649972 -> 649248 (-0.11%)
helped: 386
HURT: 165
This will help avoid code quality regressions in a future commit.
Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
Kenneth Graunke [Wed, 22 Jun 2016 00:42:59 +0000 (17:42 -0700)]
glsl: Propagate invariant/precise after lowering const arrays.
The new uniform may need precise as well.
Fixes copy propagation of constant array uniforms in Tomb Raider shaders.
Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
Kenneth Graunke [Mon, 20 Jun 2016 18:20:51 +0000 (11:20 -0700)]
glsl: Split arrays even in the presence of whole-array copies.
Previously, we failed to split constant arrays. Code such as
int[2] numbers = int[](1, 2);
would generates a whole-array assignment:
(assign () (var_ref numbers)
(constant (array int 4) (constant int 1) (constant int 2)))
opt_array_splitting generally tried to visit ir_dereference_array nodes,
and avoid recursing into the inner ir_dereference_variable. So if it
ever saw a ir_dereference_variable, it assumed this was a whole-array
read and bailed. However, in the above case, there's no array deref,
and we can totally handle it - we just have to "unroll" the assignment,
creating assignments for each element.
This was mitigated by the fact that we constant propagate whole arrays,
so a dereference of a single component would usually get the desired
single value anyway. However, I plan to stop doing that shortly;
early experiments with disabling constant propagation of arrays
revealed this shortcoming.
This patch causes some arrays in Gl32GSCloth's geometry shaders to be
split, which allows other optimizations to eliminate unused GS inputs.
The VS then doesn't have to write them, which eliminates the entire VS
(5 -> 2 instructions). It still renders correctly.
No other change in shader-db.
v2: Drop !AOA check and improve a comment (feedback from Tim Arceri).
Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
Kenneth Graunke [Mon, 20 Jun 2016 23:48:02 +0000 (16:48 -0700)]
glsl: Make constant propagation's folder not propagate into an LHS.
opt_constant_propagation.cpp contains constant folding code which can
actually do constant propagation in some cases. It was happily
propagating constants into the left-hand-side of assignments.
For example,
(assign () (var_ref temp) (constant ...))
would brilliantly be turned into:
(assign () (constant ...) (constant ....))
This is a bigger hammer than necessary - it prevents propagation
into the left-hand-side altogether. We could certainly do better
someday. Notably, the constant propagation pass itself already
takes this approach - it's just the constant propagation pass's
built-in constant folding code (which actually propagates, too)
that was broken.
No change in shader-db, but prevents regressions after future commits.
It seems plausible that this could be hit today, but I haven't seen it
happen.
Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
Topi Pohjolainen [Wed, 18 May 2016 13:18:59 +0000 (16:18 +0300)]
i965/blorp: Disable vertex element swizzling
Without vertex elements originating directly from vertex fetcher
are not passed to wm-state correctly.
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Topi Pohjolainen [Mon, 16 May 2016 07:18:53 +0000 (10:18 +0300)]
i965/blorp: Let program data tell if push constants are needed
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Topi Pohjolainen [Wed, 18 May 2016 13:09:49 +0000 (16:09 +0300)]
i965/blorp: Use prog data counters to guide wm/ps setup
just as core upload logic does.
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Topi Pohjolainen [Sun, 15 May 2016 08:34:37 +0000 (11:34 +0300)]
i965/blorp: Use prog data counters to guide sf/sbe setup
just as core upload logic does.
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Ardinartsev Nikita [Thu, 23 Jun 2016 01:28:11 +0000 (18:28 -0700)]
i965: Avoid division by zero.
Fixes regression introduced by
af5ca43f2676bff7499f93277f908b681cb821d0
Cc: "12.0 11.2" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=95419
Tim Rowley [Tue, 14 Jun 2016 23:54:34 +0000 (17:54 -0600)]
swr: [rasterizer core] fix dependency bug
Never be dependent on "draw 0", instead have a bool that makes the draw
dependent on the previous draw or not dependent at all.
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
Tim Rowley [Tue, 14 Jun 2016 23:02:11 +0000 (17:02 -0600)]
swr: [rasterizer core] use wrap-around safe compares for dependency checking
Move drawIDs from 64-bit to 32-bit to increase perf.
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
Tim Rowley [Tue, 14 Jun 2016 18:57:31 +0000 (12:57 -0600)]
swr: [rasterizer jitter] add support for component packing for 'odd' formats
Add early-out if no components are enabled. Add asserts.
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
Tim Rowley [Tue, 14 Jun 2016 16:25:02 +0000 (10:25 -0600)]
swr: [rasterizer core] track whether GS outputs viewport array index
So we can skip the index gather in PA.
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
Tim Rowley [Mon, 13 Jun 2016 15:19:38 +0000 (09:19 -0600)]
swr: [rasterizer core] GS viewport array index attribute
Only adds the attribute mapping to the jitter; no implementation yet.
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
Tim Rowley [Fri, 10 Jun 2016 17:31:16 +0000 (11:31 -0600)]
swr: [rasterizer core] conservative rasterization frontend support
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
Tim Rowley [Fri, 10 Jun 2016 16:18:45 +0000 (10:18 -0600)]
swr: [rasterizer core] stop single threaded crash exit crash
Function static destructors were getting called by exit
handlers before context teardown.
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
Tim Rowley [Thu, 9 Jun 2016 21:17:49 +0000 (15:17 -0600)]
swr: [rasterizer jitter] small fetch jit cleanup
Handle SGV stores separate from the stream fetch code.
Because of this change, there is a potential to jit an extra unused store.
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
Tim Rowley [Tue, 7 Jun 2016 19:03:27 +0000 (13:03 -0600)]
swr: [rasterizer core] remove old comment
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
Tim Rowley [Tue, 7 Jun 2016 01:13:22 +0000 (19:13 -0600)]
swr: [rasterizer jitter] cleanup supporting different llvm versions
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
Tim Rowley [Thu, 2 Jun 2016 21:24:34 +0000 (15:24 -0600)]
swr: [rasterizer jitter] unitialized component fix in fetch jit
Was trying to store an extra uninitialized component.
Only affects component packing, which isn't enabled (yet).
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
Tim Rowley [Wed, 1 Jun 2016 02:01:40 +0000 (20:01 -0600)]
swr: [rasterizer] add support for building avx512 version
Currently, most code paths between AVX2 and AVX512 are identical
(see changes to knobs.h).
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
Tim Rowley [Fri, 27 May 2016 22:17:47 +0000 (16:17 -0600)]
swr: [rasterizer common] fix include for Intel compiler
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
Tim Rowley [Thu, 26 May 2016 16:51:48 +0000 (10:51 -0600)]
swr: [rasterizer common] workaround clang for windows __cpuid() bug
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
Tim Rowley [Fri, 17 Jun 2016 02:09:35 +0000 (21:09 -0500)]
swr: push/pop DEBUG macro around llvm includes
llvm redefines DEBUG; adding push/pop prevents a undefined reference
to debug_refcnt_state in llvm-3.7+.
v2: add undef DEBUG
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
Jose Fonseca [Thu, 23 Jun 2016 10:18:21 +0000 (11:18 +0100)]
include: Require MSVC 2013 Update 4.
Earlier MSVC 2013 releases have troubles compiling some of our C99 code,
so make sure we have Update 4 to avoid confusion.
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Brian Paul <brianp@vmware.com>
Brian Paul [Mon, 20 Jun 2016 18:41:23 +0000 (12:41 -0600)]
svga: rename svga_surface_copy() to svga_resource_copy_region()
To be consistent with the pipe_context function name.
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Brian Paul [Mon, 20 Jun 2016 18:39:55 +0000 (12:39 -0600)]
svga: don't copy blit_info into local var
There's no reason for doing so.
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Brian Paul [Mon, 20 Jun 2016 19:00:28 +0000 (13:00 -0600)]
gallium/util: fix some 4-space indentation in blitter code
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Charmaine Lee [Tue, 21 Jun 2016 17:12:22 +0000 (10:12 -0700)]
svga: fix texture array update regression
With commit fb9fe35, we start using transfer_inline_write
for memcpy TexSubImage path, but that triggers a regression with
texture array in the svga driver.
With this patch, the direct map code will update the texture array
correctly.
Fixes VMware bug 1679293.
Tested with MTT piglit, glretrace, conform.
Reviewed-by: Brian Paul <brianp@vmware.com>
Charmaine Lee [Mon, 16 May 2016 22:12:57 +0000 (15:12 -0700)]
svga: fix index/vertex buffer surface reference at draw
Currently with the SetVertexBuffers optimization, we avoid emitting
redundant DXSetVertexBuffers commands. However, these buffers surfaces
will still need to be referenced, otherwise, in the case of linux,
the subsequent surface discard map will map to the existing mob instead
of a new one, causing rendering artifacts.
With this patch, we'll call resource_rebind() to reference the resources
even if we are avoiding the actual set command. This fixes the
rendering artifacts in the window title area running with unity in
Ubuntu 14.04
Tested with piglit, glretrace.
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Sinclair Yeh <syeh@vmware.com>
Charmaine Lee [Tue, 3 May 2016 01:17:48 +0000 (18:17 -0700)]
svga: fix vertex buffer references in the hw state
This patch fixes three issues with vertex buffer references:
(1) Instead of copy the vertex buffer resource handles to the hw state
in the context structure, use pipe_resource_reference to properly
reference the vertex buffer resources in the context.
(2) Make sure to unbind those unused vertex buffer resources.
(3) Force to rebind the vertex buffer resources at the first draw of each
command buffer to make sure the vertex buffer resources are paged in.
Reviewed-by: Brian Paul <brianp@vmware.com>
Charmaine Lee [Tue, 3 May 2016 01:12:24 +0000 (18:12 -0700)]
svga: fix index buffer reference in the hw state
Instead of copy the index buffer resource handle to the hw state in
the context structure, use pipe_resource_reference to properly reference
the index buffer resource in the context.
Reviewed-by: Brian Paul <brianp@vmware.com>
Timothy Arceri [Wed, 22 Jun 2016 02:41:28 +0000 (12:41 +1000)]
glsl/mesa: stop duplicating geom and tcs layout values
We already store these in gl_shader and gl_program here we
remove it from gl_shader_program and just use the values
from gl_shader.
This will allow us to keep the shader cache restore code as
simple as it can be while making it somewhat clearer where these
values originate from.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Timothy Arceri [Wed, 22 Jun 2016 02:41:27 +0000 (12:41 +1000)]
glsl/mesa: stop duplicating tes layout values
We already store this in gl_shader and gl_program here we
remove it from gl_shader_program and just use the values
from gl_shader.
This will allow us to keep the shader cache restore code as
simple as it can be while making it somewhat clearer where these
values originate from.
V2: remove unnecessary NULL check
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Iago Toral <itoral@igalia.com>
Edward O'Callaghan [Wed, 22 Jun 2016 10:42:30 +0000 (20:42 +1000)]
.mailmap: Fixup my email address
Signed-off-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Christian Gmeiner [Mon, 20 Jun 2016 07:44:22 +0000 (09:44 +0200)]
st/mesa: expose EXT_vertex_array_bgra when supported by backend
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Jason Ekstrand [Thu, 16 Jun 2016 22:26:54 +0000 (15:26 -0700)]
anv: Use different BOs for different scratch sizes and stages
This solves a race condition where we can end up having different stages
stomp on each other because they're all trying to scratch in the same BO
but they have different views of its layout.
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
Jason Ekstrand [Thu, 16 Jun 2016 21:58:25 +0000 (14:58 -0700)]
genxml: Make ScratchSpaceBasePointer an address instead of an offset
While we're here, we also fixup MEDIA_VFE_STATE and rename the field in
3DSTATE_VS on gen6-7.5 to be consistent with the others.
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
Jason Ekstrand [Thu, 16 Jun 2016 21:43:41 +0000 (14:43 -0700)]
anv: Add an allocator for scratch buffers
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
Jason Ekstrand [Tue, 7 Jun 2016 18:37:46 +0000 (11:37 -0700)]
genxml: Put append counter fields before MCS in RENDER_SURFACE_STATE on gen7
The pack header generation scripts can't handle the case where you have
two addresses in the same dword; they just take whatever is the last one.
This meant that the MCS address wasn't properly getting handled. Since we
don't care about append counters, we can just re-arrange the XML for now.
Reviewed-by: Chad Versace <chad.versace@intel.com>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
Jason Ekstrand [Thu, 9 Jun 2016 20:56:16 +0000 (13:56 -0700)]
anv,isl: Lower storage image formats in anv
ISL was being a bit too clever for its own good and lowering the format for
us. This is all well and good *if* we always want to lower it. However,
the GL driver selectively lowers the format depending on whether the
surface is write-only or not.
Reviewed-by: Chad Versace <chad.versace@intel.com>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
Jason Ekstrand [Fri, 10 Jun 2016 17:45:43 +0000 (10:45 -0700)]
isl/state: Allow for full 31-bit buffer texture sizes
Ivy Bridge and above can handle up to 2^31 elements for RAW buffer
surfaces.
Reviewed-by: Chad Versace <chad.versace@intel.com>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>