John Paul Adrian Glaubitz [Mon, 16 May 2022 17:56:19 +0000 (10:56 -0700)]
[sanitizer] Don't use newfstatat for Linux on SPARC
Linux on SPARC uses fstatat64 instead.
Reviewed By: MaskRay
Differential Revision: https://reviews.llvm.org/D125572
Utkarsh Saxena [Mon, 16 May 2022 09:40:49 +0000 (11:40 +0200)]
Optimise findRefs for XRefs and docHighlights
Reduces time spent in findRef by 66%.
Differential Revision: https://reviews.llvm.org/D125675
Robert Suderman [Mon, 16 May 2022 18:08:49 +0000 (11:08 -0700)]
[mlir][tosa] Use math.ctlz intrinsic for tosa.clz
We were custom counting per bit for the clz instruction. Math dialect
now has an intrinsic to do this in one instruction. Migrated to this
instruction and fixed a minor bug math-to-llvm for the intrinsic.
Reviewed By: mravishankar
Differential Revision: https://reviews.llvm.org/D125592
zhijian [Mon, 16 May 2022 18:29:37 +0000 (14:29 -0400)]
[AIX] fixed llvm-ar can not read empty big archive correctly.
Summary:
llvm-ar can not read empty big archive correctly. it output error as
error: unable to load 'empty.a': truncated or malformed archive (characters in size field in archive member header are not all decimal numbers: '<bigaf>'
Reviewers: James Henderson
Differential Revision: https://reviews.llvm.org/D124017
Stanislav Mekhanoshin [Wed, 11 May 2022 20:04:17 +0000 (13:04 -0700)]
[AMDGPU] Revert wide LDS DMA support.
This reverts
ffbee7acdcaaf, see also bug 37653 which it was fixing.
The bug claims this is an undocumented feature which actually works.
In the reality it is documented as not working for a good reason.
It likely does something, but it is useless anyway. These instructions
write into the LDS. The LDS address is:
M0 + inst_offset + (TIDinWave * 4).
For a store wider than a DWORD neighboring lanes will overwrite each
other.
Differential Revision: https://reviews.llvm.org/D125409
Utkarsh Saxena [Mon, 16 May 2022 12:06:22 +0000 (14:06 +0200)]
Add documentHighlight in clangd check for performance measurements.
Differential Revision: https://reviews.llvm.org/D125682
Alex Bradbury [Mon, 16 May 2022 17:47:25 +0000 (18:47 +0100)]
[WebAssembly][TableGen][NFCI] Use getValueAsBit rather than converting TableGen 'bit' to string
The logic around IsCanonical previously used getAsString and compared to
"1". Just using getValueAsBit is simpler.
Jakub Kuderski [Mon, 16 May 2022 17:43:35 +0000 (13:43 -0400)]
[mlir:toy][NFC] Remove unnecessary trailing return type
In this instance, the trailing return type does not improve readability
as it repeats what is returned in the same line.
Reviewed By: rriddle
Differential Revision: https://reviews.llvm.org/D125697
Fangrui Song [Mon, 16 May 2022 17:42:43 +0000 (10:42 -0700)]
[Driver] Change "zlib not installed" diagnostic to "zlib not enabled"
The former is a bit misleading and a user may try installing zlib which
will not help.
Fangrui Song [Mon, 16 May 2022 17:34:01 +0000 (10:34 -0700)]
[docs] Re-generate ClangCommandLineReference.rst
Rahman Lavaee [Fri, 13 May 2022 17:32:13 +0000 (10:32 -0700)]
[llvm-objdump] Let --symbolize-operands symbolize basic block addresses based on the SHT_LLVM_BB_ADDR_MAP section.
`--symbolize-operands` already symbolizes branch targets based on the disassembly. When the object file is created with `-fbasic-block-sections=labels` (ELF-only) it will include a SHT_LLVM_BB_ADDR_MAP section which maps basic blocks to their addresses. In such case `llvm-objdump` can annotate the disassembly based on labels inferred on this section.
In contrast to the current labels, SHT_LLVM_BB_ADDR_MAP-based labels are created for every machine basic block including empty blocks and those which are not branched into (fallthrough blocks).
The old logic is still executed even when the SHT_LLVM_BB_ADDR_MAP section is present to handle functions which have not been received an entry in this section.
Reviewed By: jhenderson, MaskRay
Differential Revision: https://reviews.llvm.org/D124560
Adrian Prantl [Mon, 16 May 2022 17:05:38 +0000 (10:05 -0700)]
Remove stale file from modulemap
David Green [Mon, 16 May 2022 17:00:30 +0000 (18:00 +0100)]
[AArch64] Predicate SSHLL;SCVTF patterns behind UseAlternateSExtLoadCVTF32
There have been some patterns in the AArch64 backend to optimize code of
the form:
ldrsh w8, [x0]
scvtf s0, w8
to:
ldr h0, [x0]
sshll v0.4s, v0.4h, #0
scvtf s0, s0
The idea is to remove the GRP->FPR move, but in reality is making code
larger and slower (or the same) on all the cpus I tried.
This patch adds the UseAlternateSExtLoadCVTF32 predicate similar to
nearby related pattern.
Differential Revision: https://reviews.llvm.org/D125470
Sanjay Patel [Mon, 16 May 2022 16:29:47 +0000 (12:29 -0400)]
[InstCombine] invert canonicalization for cast of signbit test
The existing transform was wrong in 3 ways:
1. It created an extra instruction when the source and dest types don't match.
2. It did not account for an extra use of the icmp, so could create 2 extra insts.
3. It favored bit hacks over icmp (icmp generally has better analysis).
This fixes #54692 (modeled by the PhaseOrdering tests).
This is a minimal step to fix the bug, but we should likely invert
the sibling transform for the "is negative" pattern too.
The backend should be able to invert this back to a shift if that
leads to better codegen.
Sanjay Patel [Mon, 16 May 2022 16:26:48 +0000 (12:26 -0400)]
[InstCombine] add tests for zext-of-signbit test; NFC
Craig Topper [Mon, 16 May 2022 16:28:09 +0000 (09:28 -0700)]
[AArch64][ARM][RISCV][X86] Add test cases for PR55484. NFC
This bug is in generic DAG combine and easily reproducible on many
targets.
Reviewed By: david-arm
Differential Revision: https://reviews.llvm.org/D125640
Craig Topper [Mon, 16 May 2022 16:27:43 +0000 (09:27 -0700)]
[TargetLowering] Expand the last stage of i16 popcnt using shift+add+and instead of mul+shift.
If we use multiply it would be with 0x0101 which is 1 more than a power
of 2. On some targets we would expand this to shl+add. By avoiding the
multiply earlier, we can generate better code.
Note, PowerPC doesn't do the shl+add expansion of multiply so one of
the tests increased in instruction count.
Limiting to scalars because it almost always increased the number of
instructions in vector tests.
Reviewed By: RKSimon
Differential Revision: https://reviews.llvm.org/D125638
Craig Topper [Sun, 15 May 2022 18:45:42 +0000 (11:45 -0700)]
[DAGCombiner] Fix incorrect indentation. NFC
Philip Reames [Mon, 16 May 2022 16:15:26 +0000 (09:15 -0700)]
[RISCV] Add further trace output to InsertVSETLVI
Hongtao Yu [Fri, 13 May 2022 05:08:18 +0000 (22:08 -0700)]
[llvm-profgen] Update callsite body samples by summing up all call target samples.
Current profile generation caculcates callsite body samples and call target samples separately. The former is done based on LBR range samples while the latter is done based on branch samples. Note that there's a subtle difference. LBR ranges is formed from two consecutive branch samples. Therefore the last entry in a LBR record will not be counted towards body samples while there's still a chance for it to be counted towards call targets if it is a function call. I'm making sense of the call body samples by updating it to the aggregation of call targets.
Reviewed By: wenlei
Differential Revision: https://reviews.llvm.org/D122609
Matthias Springer [Mon, 16 May 2022 15:02:00 +0000 (17:02 +0200)]
[mlir][bufferize] Better user control of layout maps
This changes replaces the `fully-dynamic-layout-maps` options (which was badly named) with two new options:
* `unknown-type-conversion` controls the layout maps on buffer types for which no layout map can be inferred.
* `function-boundary-type-conversion` controls the layout maps on buffer types inside of function signatures.
Differential Revision: https://reviews.llvm.org/D125615
Ellis Hoag [Mon, 16 May 2022 14:13:07 +0000 (07:13 -0700)]
[InstrProf][NFC] Save profile bias to function map
Add a map from functions to load instructions that compute the profile bias. Previously we assumed that if the first instruction in the function was a load instruction, then it must be computing the bias. This was likely to work out because functions usually start with the `llvm.instrprof.increment` instruction, but optimizations could change this. For example, inlining into a non-profiled function.
Reviewed By: phosek
Differential Revision: https://reviews.llvm.org/D114319
Sanjay Patel [Mon, 16 May 2022 15:11:51 +0000 (11:11 -0400)]
[IR] create and use helper functions that test the signbit; NFCI
Philip Reames [Mon, 16 May 2022 14:48:57 +0000 (07:48 -0700)]
[LiveIntervals] Add range accessors for value numbers [nfc]
Simon Pilgrim [Mon, 16 May 2022 15:19:03 +0000 (16:19 +0100)]
[polly] Remove 'using namespace llvm/polly' from ScopGraphPrinter.h header.
As mentioned on D123678 this appears to be causing namespace resolution issues on some versions of gcc.
David Green [Mon, 16 May 2022 14:50:39 +0000 (15:50 +0100)]
[AArch64] Update check lines in arm64-scvt.ll. NFC
Sanjay Patel [Mon, 16 May 2022 14:21:55 +0000 (10:21 -0400)]
[PhaseOrdering] add tests for cmp + boolean/bitwise logic; NFC
The tests (see C++ source in #54692) have multiple potential
optimizations/canonicalizations, but we should be consistent
since they are logically identical.
Sanjay Patel [Mon, 16 May 2022 13:59:31 +0000 (09:59 -0400)]
[InstCombine] fix test name; NFC
The bug number was typo'd when it was added for D86243.
Alexey Bataev [Mon, 16 May 2022 13:43:00 +0000 (06:43 -0700)]
[SLP]Check if the root of the buildvector has one use only.
The root of the buildvector can have only one use, otherwise it can be
treated only as a final element of the previous buildvector sequence.
Nikita Popov [Fri, 13 May 2022 14:35:43 +0000 (16:35 +0200)]
[ValueTracking] Handle and/or on RHS of isImpliedCondition()
isImpliedCondition() currently handles and/or on the LHS, but not
on the RHS, resulting in asymmetric behavior. This patch adds two
new implication rules:
* LHS ==> (RHS1 || RHS2) if LHS ==> RHS1 or LHS ==> RHS2
* LHS ==> !(RHS1 && RHS2) if LHS ==> !RHS1 or LHS ==> !RHS2
Differential Revision: https://reviews.llvm.org/D125551
Florian Hahn [Mon, 16 May 2022 14:27:22 +0000 (15:27 +0100)]
[LAA,LV] Add initial support for pointer-diff memory checks.
This patch adds initial support for a pointer diff based runtime check
scheme for vectorization. This scheme requires fewer computations and
checks than the existing full overlap checking, if it is applicable.
The main idea is to only check if source and sink of a dependency are
far enough apart so the accesses won't overlap in the vector loop. To do
so, it is sufficient to compute the difference and compare it to the
`VF * UF * AccessSize`. It is sufficient to check
`(Sink - Src) <u VF * UF * AccessSize` to rule out a backwards
dependence in the vector loop with the given VF and UF. If Src >=u Sink,
there is not dependence preventing vectorization, hence the overflow
should not matter and using the ULT should be sufficient.
Note that the initial version is restricted in multiple ways:
1. Pointers must only either be read or written, by a single
instruction (this allows re-constructing source/sink for
dependences with the available information)
2. Source and sink pointers must be add-recs, with matching steps
3. The step must be a constant.
3. abs(step) == AccessSize.
Most of those restrictions can be relaxed in the future.
See https://github.com/llvm/llvm-project/issues/53590.
Reviewed By: dmgreen
Differential Revision: https://reviews.llvm.org/D119078
Joe Nash [Fri, 13 May 2022 16:55:16 +0000 (12:55 -0400)]
[AMDGPU] Mark sendmsg hasSideEffects. NFC
Address the FIXME by marking the sendmsg instructions with
hasSideEffects.
Reviewed By: foad
Differential Revision: https://reviews.llvm.org/D125569
Jay Foad [Fri, 18 Feb 2022 17:24:50 +0000 (17:24 +0000)]
[AMDGPU] Shrink MAD/FMA to MADAK/MADMK/FMAAK/FMAMK on GFX10
On GFX10 VOP3 instructions can have a literal operand, so the conversion
from VOP3 MAD/FMA to VOP2 MADAK/MADMK/FMAAK/FMAMK will not happen in
SIFoldOperands. The only benefit of the VOP2 form is code size, so do it
in SIShrinkInstructions instead.
Differential Revision: https://reviews.llvm.org/D125567
Nikita Popov [Mon, 16 May 2022 14:04:11 +0000 (16:04 +0200)]
[ConstantRange] Add toKnownBits() method
Add toKnownBits() method to mirror fromKnownBits(). We know the
top bits that are constant between min and max.
The return value for an empty range is chosen to be conservative.
Joe Nash [Tue, 19 Apr 2022 19:38:35 +0000 (15:38 -0400)]
[AMDGPU] gfx11 BUF Instructions
Includes MachineCode layer support and tests, and MIR tests not requiring
CodeGen pass changes.
Includes a small change in SMInstructions.td to correct encoded bits.
Contributors:
Petar Avramovic <Petar.Avramovic@amd.com>
Dmitry Preobrazhensky <dmitry.preobrazhensky@amd.com>
Depends on D125316
Patch 6/N for upstreaming of AMDGPU gfx11 architecture.
Reviewed By: dp, Petar.Avramovic
Differential Revision: https://reviews.llvm.org/D125319
Stephen Long [Mon, 16 May 2022 13:59:40 +0000 (06:59 -0700)]
[MSVC] Add support for pragma alloc_text
`#pragma alloc_text` is a MSVC pragma that names the code section where functions should be placed. It only
applies to functions with C linkage.
https://docs.microsoft.com/en-us/cpp/preprocessor/alloc-text?view=msvc-170
Reviewed By: aaron.ballman
Differential Revision: https://reviews.llvm.org/D125011
Mehdi Amini [Mon, 16 May 2022 09:50:18 +0000 (09:50 +0000)]
Apply clang-tidy fixes for llvm-qualified-auto in LinalgInterfaces.cpp (NFC)
Mehdi Amini [Mon, 16 May 2022 09:49:11 +0000 (09:49 +0000)]
Apply clang-tidy fixes for performance-move-const-arg in SerializeToHsaco.cpp (NFC)
Nathan James [Mon, 16 May 2022 13:42:43 +0000 (14:42 +0100)]
[clang-tidy][NFC] Reimplement SimplifyBooleanExpr with RecursiveASTVisitors
Reimplement the matching logic using Visitors instead of matchers.
Benchmarks from running the check over SemaCodeComplete.cpp
Before 0.20s, After 0.04s
Reviewed By: aaron.ballman
Differential Revision: https://reviews.llvm.org/D125026
Liqin.Weng [Mon, 16 May 2022 13:30:58 +0000 (13:30 +0000)]
[CodeGen] Use ArrayRef in TargetLowering functions
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D123656
Louis Dionne [Fri, 6 May 2022 19:43:18 +0000 (15:43 -0400)]
[runtimes] Generalize how we reorder projects
This way, we could use it for LLVM_ENABLE_PROJECTS too if desired.
Differential Revision: https://reviews.llvm.org/D125121
Liqin.Weng [Mon, 16 May 2022 12:53:32 +0000 (12:53 +0000)]
[RISCV] remove useless code
When legality check for vectoring reduction, hasVInstructions() check be unneeded. RISCV can only loop vectorization with hasVInstructions()
Reviewed By: kito-cheng, craig.topper
Differential Revision: https://reviews.llvm.org/D125460
Louis Dionne [Wed, 11 May 2022 15:06:28 +0000 (11:06 -0400)]
[runtimes] Introduce object libraries
This is a variant of D116689 rebased on top of the new (proposed) ABI
refactoring in D120727. It should conserve the basic properties of the
original patch by @phosek, except it also allows cleaning up the merging
of libc++abi into libc++ from the libc++ side.
Differential Revision: https://reviews.llvm.org/D125393
Nathan Sidwell [Fri, 13 May 2022 10:52:49 +0000 (03:52 -0700)]
[clang][NFC] Cleanup some coroutine tests
I noticed these two tests emit a warning about a missing
unhandled_exception. That's irrelevant to what is being tested, but
is unnecessary noise.
Reviewed By: dblaikie
Differential Revision: https://reviews.llvm.org/D125535
Haojian Wu [Mon, 16 May 2022 11:38:13 +0000 (13:38 +0200)]
[AST] Cleanup on getting the underlying decl of using-shdow decl.
This should be a NFC cleanup. It removes a unnecessary loop to get the underlying
decl, and add an assertion.
The underlying decl of a using-shadow decl is always the original declaration
has been brought into the scope, clang never builds a nested using-shadow
decl (see Sema::BuildUsingShadowDecl).
Reviewed By: sammccall
Differential Revision: https://reviews.llvm.org/D123422
Biplob Mishra [Mon, 16 May 2022 11:43:12 +0000 (12:43 +0100)]
[InstCombine] Combine instructions of type or/and where AND masks can be combined.
The patch simplifies some of the patterns as below
(A | (B & C0)) | (B & C1) -> A | (B & C0|C1)
((B & C0) | A) | (B & C1) -> (B & C0|C1) | A
In some scenarios like byte reverse on half word, we can see this pattern multiple times and this conversion can optimize these patterns.
Differential Revision: https://reviews.llvm.org/D124119
Bradley Smith [Tue, 10 May 2022 12:25:38 +0000 (12:25 +0000)]
[DAGCombine] Support splat_vector nodes in (and (extload)) dagcombine
Differential Revision: https://reviews.llvm.org/D125367
Tim Northover [Mon, 16 May 2022 10:59:51 +0000 (11:59 +0100)]
AArch64: support ISel for fence instructions
Only the most conservative of the DAG patterns matched, leaving GISel with "dmb
ish" everywhere which is inefficient.
David Spickett [Mon, 9 May 2022 10:58:21 +0000 (10:58 +0000)]
[lldb][NFC] Simplify GenerateOptionUsage
Once we get into the if block we know the value of only_print_args.
Move some variables closer to point of use.
Depends on D125218
Reviewed By: JDevlieghere
Differential Revision: https://reviews.llvm.org/D125219
David Spickett [Mon, 9 May 2022 10:50:03 +0000 (10:50 +0000)]
[lldb][NFC] Make cmd a reference in GenerateOptionUsage
Nowhere in lldb do we call this with a null pointer.
If we did, the first line of the function would fault anyway.
Reviewed By: JDevlieghere
Differential Revision: https://reviews.llvm.org/D125218
Sheng [Mon, 16 May 2022 10:38:39 +0000 (18:38 +0800)]
[ADT] Adopt the new casting infrastructure for PointerUnion
Reviewed By: lattner, bzcheeseman
Differential Revision: https://reviews.llvm.org/D125609
Abinav Puthan Purayil [Thu, 12 May 2022 17:05:52 +0000 (22:35 +0530)]
[GlobalISel] Handle constant splat in funnel shift combine
This change adds the constant splat versions of m_ICst() (by using
getBuildVectorConstantSplat()) and uses it in
matchOrShiftToFunnelShift(). The getBuildVectorConstantSplat() name is
shortened to getIConstantSplatVal() so that the *SExtVal() version would
have a more compact name.
Differential Revision: https://reviews.llvm.org/D125516
Abinav Puthan Purayil [Fri, 13 May 2022 10:58:05 +0000 (16:28 +0530)]
[AMDGPU][GlobalISel] Pre-commit tests for D125516
Differential Revision: https://reviews.llvm.org/D125539
Simon Pilgrim [Mon, 16 May 2022 10:24:13 +0000 (11:24 +0100)]
[X86][AVX] Add test showing poor expansion of bit-reversal permutation shuffles
Reported here: https://discourse.llvm.org/t/ir-alternatives-to-freeze-to-selectively-prevent-compiler-from-combining-shufflevectors/62521
Yeting Kuo [Mon, 16 May 2022 03:56:31 +0000 (11:56 +0800)]
[SelectionDAG] Make getNode which uses single element SDVTList pass SDNodeFlags.
The patch make users not need to know getNode with SDNodeFlags argument may not
pass its flags.
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D125659
David Green [Mon, 16 May 2022 10:08:47 +0000 (11:08 +0100)]
[AArch64] Handle 64bit vectors in tryCombineFixedPointConvert
Under some situations we can visit 64bit vector extract elements in
tryCombineFixedPointConvert, where an assert fires as they are expected
to have been converted to 128bit. Turn the assert into an if statement,
bailing out and letting the extract be handled first.
Also invert some ifs, using early exits to reduce indentation.
Fixes #55417
Denis Antrushin [Fri, 13 May 2022 10:55:26 +0000 (17:55 +0700)]
[StatepointLowering] Properly handle local and non-local relocates of the same value.
FunctionLoweringInfo::StatepointRelocationMaps map is used to pass GC pointer
lowering information from statepoint to gc.relocate which may appear ini
different block.
D124444 introduced different lowering for local and non-local relocates.
Local relocates use SDValue and non-local relocates use value exported to VReg.
But I overlooked the fact that StatepointRelocationMap is indexed not by
GCRelocate instruction, but by derived pointer. This works incorrectly when
we have two relocates (one local and another non-local) of the same value,
because they need different relocation records.
This patch fixes the problem by recording relocation information per relocate
instruction, not per derived pointer. This way, each gc.relocate can be lowered
differently.
Reviewed By: skatkov
Differential Revision: https://reviews.llvm.org/D125538
owenca [Sun, 15 May 2022 08:37:23 +0000 (01:37 -0700)]
[clang-format][NFC] Don't call mightFitOnOneLine() unnecessarily
Clean up UnwrappedLineParser for RemoveBracesLLVM to avoid calling
mightFitOnOneLine() as much as possible.
Differential Revision: https://reviews.llvm.org/D125626
Tobias Ribizel [Mon, 16 May 2022 09:17:15 +0000 (11:17 +0200)]
[clangd] parse all make_unique-like functions in preamble
I am working on support for forwarding parameter names in make_unique-like functions, first for inlay hints, later maybe for signature help.
For that to work generically, I'd like to parse all of these functions in the preamble. Not sure how this impacts performance on large codebases though.
Reviewed By: sammccall
Differential Revision: https://reviews.llvm.org/D124688
Nicolas Abram Lujan [Mon, 16 May 2022 08:51:51 +0000 (10:51 +0200)]
[llvm-c] Add functions for enabling and creating opaque pointers
This is based on https://reviews.llvm.org/D125168 which adds a
wrapper to allow use of opaque pointers from the C API.
I added an opaque pointer mode test to echo.ll, and to fix assertions
that forbid the use of mixed typed and opaque pointers that were
triggering in it I had to also add wrappers for setOpaquePointers()
and isOpaquePointer().
I also changed echo.ll to remove a bitcast i32* %x to i8*, because
passing it through llvm-as and llvm-dis was generating a
%0 = bitcast ptr %x to ptr, but when building that same bitcast in
echo.cpp it was getting elided by IRBuilderBase::CreateCast
(https://github.com/llvm/llvm-project/blob/
08ac66124874d70dab63c731da0244f9e29ef168/llvm/include/llvm/IR/IRBuilder.h#L1998-L1999).
Differential Revision: https://reviews.llvm.org/D125183
Jay Foad [Fri, 18 Feb 2022 17:52:24 +0000 (17:52 +0000)]
[AMDGPU] SIShrinkInstructions: change static functions to methods
This is a mechanical change to avoid passing MRI and TII around
explicitly. NFC.
Differential Revision: https://reviews.llvm.org/D125566
Jay Foad [Mon, 21 Feb 2022 15:50:19 +0000 (15:50 +0000)]
[AMDGPU] Extract SIInstrInfo::removeModOperands. NFC.
Make this an externally callable function for use in a future patch.
Differential Revision: https://reviews.llvm.org/D125565
Haojian Wu [Thu, 5 May 2022 12:10:18 +0000 (14:10 +0200)]
[pseudo] Support parsing variant target symbols.
With this patch, we're able to parse smaller chunks of C++ code (statement,
declaration), rather than translation-unit.
The start symbol is listed in the grammar in a form of `_ :=
statement`, each start symbol has a dedicated state (`_ := • statement`).
We create and track all these separate states in the LRTable. When we
start parsing, we lookup the corresponding state to start the parser.
LR pasing table changes with this patch:
- number of states: 1467 -> 1471
- number of actions: 82891 -> 83578
- size of the table (bytes): 334248 -> 336996
Differential Revision: https://reviews.llvm.org/D125006
Nikita Popov [Tue, 10 May 2022 14:34:11 +0000 (16:34 +0200)]
[ControlHeightReduction] Freeze condition when converting select to branch
While select conditions can be poison, branch on poison is
immediate UB. As such, we need to freeze the condition when
converting a select into a branch.
Differential Revision: https://reviews.llvm.org/D125398
Diana Picus [Mon, 2 May 2022 11:41:07 +0000 (11:41 +0000)]
[flang] Install Fortran_main library
At the moment the Fortran_main library is not installed, so it cannot be
found by the driver when run from an install directory. This patch fixes
the issue by replacing llvm_add_library with add_flang_library, which
already contains all the proper incantations for installing a library.
It also enhances add_flang_library to support a STATIC arg which forces
the library to be static even when BUILD_SHARED_LIBS is on.
Differential Revision: https://reviews.llvm.org/D124759
Co-authored-by: Dan Palermo <Dan.Palermo@amd.com>
Nikita Popov [Thu, 12 May 2022 10:42:45 +0000 (12:42 +0200)]
[FastISel] Fix load folding for registers with fixups
FastISel tries to fold loads into the single using instruction.
However, if the register has fixups, then there may be additional
uses through an alias of the register.
In particular, this fixes the problem reported at
https://reviews.llvm.org/D119432#3507087. The load register is
(at the time of load folding) only used in a single call instruction.
However, selection of the bitcast has added a fixup between the
load register and the cross-BB register of the bitcast result.
After fixups are applied, there would now be two uses of the load
register, so load folding is not legal.
Differential Revision: https://reviews.llvm.org/D125459
Gregory Fong [Mon, 16 May 2022 08:08:24 +0000 (10:08 +0200)]
[clang-format] fix alignment w/o binpacked args
The combination of
- AlignConsecutiveAssignments.Enabled = true
- BinPackArguments = false
would result in the first continuation line of a braced-init-list being
improperly indented (missing a shift) when in a continued function call.
Indentation was also wrong for braced-init-lists continuing a
direct-list-initialization. Check for opening braced lists in
continuation and ensure that the correct shift occurs.
Fixes https://github.com/llvm/llvm-project/issues/55360
Reviewed By: curdeius
Differential Revision: https://reviews.llvm.org/D125162
Kirill Bobyrev [Mon, 16 May 2022 08:17:40 +0000 (10:17 +0200)]
[clangd] NFC: Rename field to be compatible with the function name
David Sherwood [Thu, 10 Mar 2022 14:22:34 +0000 (14:22 +0000)]
[LoopVectorize] Permit tail-folding for low trip counts using scalable vectors
When the loop vectoriser encounters a known low trip count it tries
to create a single predicated loop in order to get the benefit of
vectorisation and eliminate the scalar tail. However, until now the
vectoriser prevented the use of scalable vectors in this case due
to concerns in the past about stability. I believe that tail-folded
loops using scalable vectors are now sufficiently well tested that
we can enable this. For the same reason I've also enabled it when
optimising for code size too.
Tests added here:
Transforms/LoopVectorize/AArch64/sve-low-trip-count.ll
Transforms/LoopVectorize/AArch64/sve-tail-folding-optsize.ll
Transforms/LoopVectorize/RISCV/low-trip-count.ll
Differential Revision: https://reviews.llvm.org/D121595
Kirill Bobyrev [Mon, 16 May 2022 08:13:38 +0000 (10:13 +0200)]
[clangd] Include Cleaner: ignore headers with IWYU export pragmas
Disable the warnings with `IWYU pragma: export` or `begin_exports` +
`end_exports` until we have support for these pragmas. There are too many
false-positive warnings for the headers that have the correct pragmas for now
and it makes the user experience very unpleasant.
Reviewed By: sammccall
Differential Revision: https://reviews.llvm.org/D125468
stk [Mon, 16 May 2022 08:01:09 +0000 (10:01 +0200)]
Add ThreadPriority::Low, and use QoS class Utility on Mac
On Apple Silicon Macs, using a Darwin thread priority of PRIO_DARWIN_BG seems to
map directly to the QoS class Background. With this priority, the thread is
confined to efficiency cores only, which makes background indexing take forever.
Introduce a new ThreadPriority "Low" that sits in the middle between Background
and Default, and maps to QoS class "Utility" on Mac. Make this new priority the
default for indexing. This makes the thread run on all cores, but still lowers
priority enough to keep the machine responsive, and not interfere with
user-initiated actions.
I didn't change the implementations for Windows and Linux; on these systems,
both ThreadPriority::Background and ThreadPriority::Low map to the same thread
priority. This could be changed as a followup (e.g. by using SCHED_BATCH for Low
on Linux).
See also https://github.com/clangd/clangd/issues/1119.
Reviewed By: sammccall, dgoldman
Differential Revision: https://reviews.llvm.org/D124715
Kito Cheng [Mon, 16 May 2022 08:00:23 +0000 (16:00 +0800)]
[RISCV][NFC] Fix build issue
Marek Kurdej [Fri, 13 May 2022 09:27:35 +0000 (11:27 +0200)]
[clang-format] Fix PointerAlignment: Right not working with tab indentation.
Fixes https://github.com/llvm/llvm-project/issues/55407.
Given configuration:
```
UseTab: Always
PointerAlignment: Right
AlignConsecutiveDeclarations: true
```
Before, the pointer was misaligned in this code:
```
void f() {
unsigned long long big;
char *ptr; // misaligned
int i;
}
```
That was due to the fact that when handling right-aligned pointers, the Spaces were changed but StartOfTokenColumn was not.
Also, a tab was used not only for indentation but for spacing too when using `UseTab: ForIndentation` config option:
```
void f() {
unsigned long long big;
char *ptr; // \t after char
int i;
}
```
Reviewed By: owenpan
Differential Revision: https://reviews.llvm.org/D125528
Kito Cheng [Wed, 11 May 2022 15:39:13 +0000 (23:39 +0800)]
[RISCV][NFC] Refactor RISC-V vector intrinsic utils.
This patch is preparation for D111617, use class/struct/enum rather than char/StringRef to present internal information as possible, that provide more compact way to store those info and also easier to serialize/deserialize.
And also that improve readability of the code, e.g. "v" vs TypeProfile::Vector.
Reviewed By: khchen
Differential Revision: https://reviews.llvm.org/D124730
LLVM GN Syncbot [Mon, 16 May 2022 06:42:42 +0000 (06:42 +0000)]
[gn build] Port
0a0d6489ef2e
Jim Lin [Mon, 16 May 2022 02:26:32 +0000 (10:26 +0800)]
[Mips] Implement hasDivRemOp()
SDIVREM and UDIVREM can be customized lowered in MipsSE.
Fix https://github.com/llvm/llvm-project/issues/54991.
Reviewed By: sdardis
Differential Revision: https://reviews.llvm.org/D124980
Jim Lin [Mon, 16 May 2022 02:22:50 +0000 (10:22 +0800)]
[DivRemPairs][Mips] Pre-commit test for Mips target
Copied from PowerPC.
Reviewed By: sdardis
Differential Revision: https://reviews.llvm.org/D124979
serge-sans-paille [Mon, 9 May 2022 12:18:58 +0000 (14:18 +0200)]
[clang] Prevent folding of non-const compound expr
When a non-const compound statement is used to initialize a constexpr pointer,
the pointed value is not const itself and cannot be folded at codegen time.
This matches GCC behavior for compound literal expr arrays.
Fix issue #39324.
Differential Revision: https://reviews.llvm.org/D124038
bzcheeseman [Fri, 13 May 2022 22:34:51 +0000 (18:34 -0400)]
[LLVM][Casting.h] Add trivial self-cast
Casting from a type to itself should always be possible. Make this simple for all users, and add tests to ensure we keep being able to do this. Ref: https://reviews.llvm.org/D125543
Reviewed By: rriddle
Differential Revision: https://reviews.llvm.org/D125590
jacquesguan [Thu, 12 May 2022 08:20:02 +0000 (08:20 +0000)]
[RISCV][NFC] Replace for-each with array argument call.
This patch replaces some for-each set with the new arrayref argument API, since it already used an array in defination, I think this change won't cause any ambiguity.
Differential Revision: https://reviews.llvm.org/D125455
Chuanqi Xu [Fri, 13 May 2022 05:59:46 +0000 (13:59 +0800)]
[Diagnostic] Warn if the size argument of memset is character literal
zero
Closing https://github.com/llvm/llvm-project/issues/55402
Reviewed By: efriedma
Differential Revision: https://reviews.llvm.org/D125521
Zakk Chen [Mon, 16 May 2022 01:10:14 +0000 (18:10 -0700)]
[RISCV] Fix incorrect use of tail agnostic vslideup.
We need to use tail undisturbed for vslideup to implement
vector insert operation correctly.
Ideally, we cound use the tail agnostic when insert subvector
or element at the end of the vector. This will be in follow-up
patch.
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D125545
Matthias Springer [Sun, 15 May 2022 23:53:51 +0000 (01:53 +0200)]
[mlir][bufferize] Infer memref types when possible
Instead of recomputing memref types from tensor types, try to infer them when possible. This results in more precise layout maps.
Differential Revision: https://reviews.llvm.org/D125614
Simon Pilgrim [Sun, 15 May 2022 20:51:14 +0000 (21:51 +0100)]
[X86] Move combineAddOrSubToADCOrSBB earlier. NFC.
Make it easier to reuse in X86 ADD/SUB combines in an upcoming patch.
Florian Hahn [Sun, 15 May 2022 20:52:07 +0000 (21:52 +0100)]
[LV] Set SCEVCheckCond to nullptr whenever it was used.
Under some circumstances, SCEVExpander will insert new instructions when
expanding a predicate, but the final result of the expansion can be a
false constant.
In those cases, the expanded instructions may later be used by other
expansions, e.g. the trip count. This may trigger an assertion during
SCEVExpander cleanup. To avoid this, always mark the result as used.
Fixes #55100.
Simon Pilgrim [Sun, 15 May 2022 20:28:20 +0000 (21:28 +0100)]
[X86] Adjust fadd costs to match SoG
znver1/2 models were incorrectly modelling these on fpupipe 0 instead of 2/3 and znver1 ymm variants also require double pumping.
Now matches AMD SoG, Agner and instlatx64 numbers.
Thanks to @fabian-r for the report
Alexey Lapshin [Thu, 12 May 2022 18:48:14 +0000 (21:48 +0300)]
[DWARFLinker][NFC] cleanup AddressManager interface.
this review is extracted from D86539
1. delete areRelocationsResolved() method.
2. rename hasLiveMemoryLocation() -> isLiveVariable()
hasLiveAddressRange() -> isLiveSubprogram().
Differential Revision: https://reviews.llvm.org/D125492
Daniel Kiss [Sun, 15 May 2022 19:42:07 +0000 (21:42 +0200)]
Revert "[libunwind][AArch64] Add support for DWARF expression for RA_SIGN_STATE."
This reverts commit
f6366ef7f4f3cf1182fd70e0c50a9fa54374b612.
Andrzej Warzynski [Sun, 15 May 2022 17:53:09 +0000 (17:53 +0000)]
[flang][nfc] Fix driver method names overridden by the plugins
After the recent re-factoring of the driver code
(https://reviews.llvm.org/D125007), `ExecuteAction` was renamed as
`executeAction`. This patch updates the examples in Flang accordingly.
If you set `FLANG_BUILD_EXAMPLES` to `On` when building Flang, then the
refactoring from D125007 would have caused build failures for you. This
patch fixes that.
This is fairly straightforward and fixes buildbot failures, so I'm
sending this without a review.
Craig Topper [Sun, 15 May 2022 17:30:24 +0000 (10:30 -0700)]
[SLP] Fix misspelling of 'analyzed'. NFC
Craig Topper [Sun, 15 May 2022 04:16:02 +0000 (21:16 -0700)]
[RISCV] Add M extension command lines to ctlz-cttz-ctpop.ll. NFC
ctpop and cttz default expansion both end up using a multiply. This
can either use a mul instruction or libcall. Make sure we test both
cases.
Craig Topper [Sun, 15 May 2022 04:08:54 +0000 (21:08 -0700)]
[RISCV] Improve test coverage in ctlz-cttz-ctpop.ll. NFC
Add more i8/16 tets.
Add ctlz_zero_undef tests.
Simon Pilgrim [Sun, 15 May 2022 16:05:19 +0000 (17:05 +0100)]
[X86] Add test coverage for PR44915 / Issue #44260
Simon Pilgrim [Sun, 15 May 2022 15:58:12 +0000 (16:58 +0100)]
[X86] Add checks to illegal-insert.ll
Simon Pilgrim [Sun, 15 May 2022 14:53:31 +0000 (15:53 +0100)]
[X86] lowerShuffleAsLanePermuteAndSHUFP always succeeds, so just return the result. NFC.
Florian Hahn [Sun, 15 May 2022 14:51:26 +0000 (15:51 +0100)]
[VPlan] Improve printing of VPReplicateRecipe with calls.
Suggested as part of D124718.
Simon Pilgrim [Sun, 15 May 2022 14:35:09 +0000 (15:35 +0100)]
[X86] Pull out repeated isShuffleMaskInputInPlace calls. NFC.
Simon Pilgrim [Sun, 15 May 2022 13:57:58 +0000 (14:57 +0100)]
[X86] lowerV4I64Shuffle - try harder to lower to PERMQ(BLENDD(V1,V2)) pattern
Simon Pilgrim [Sun, 15 May 2022 13:31:32 +0000 (14:31 +0100)]
[X86] Add shuffles showing failure to use PERMUTE(BLEND(X,Y))
One AVX2+ targets we have a immediate VPERMQ/PD cross-lane permute thats better than relying on a pair of VPERM2F128 cross-lanes to feed a blend.
Reported on discourse
Simon Pilgrim [Sun, 15 May 2022 12:03:03 +0000 (13:03 +0100)]
[X86] Adjust tests for vector widening to use freeze(poison)
I incorrectly used freeze(undef) in rG1b07bd9034bd