Carlo Caione [Thu, 24 Jan 2019 08:54:37 +0000 (08:54 +0000)]
net: phy: realtek: Introduce quirk to mark RXC not stoppable
When EEE is supported by the PHY and the driver allows it, libphy in the
kernel is configuring the PHY to stop receiving the xMII clock while it
is signaling LPI. While this (usually) works fine in the kernel this is
causing issues in U-Boot when rebooting from the linux kernel with this
bit set (without having the possibility to reset the PHY) where the PHY
suddenly stops working.
A new quirk is introduced to unconditionally reset this bit. If the
quirk is not enabled using the proper configuration symbol, the PHY state
is not changed.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Carlo Caione [Fri, 8 Feb 2019 17:25:08 +0000 (17:25 +0000)]
cmd: mdio: Switch to generic helpers when accessing the registers
Switch to use the generic helpers to access the MMD registers so that we
can used the same command also for C45 PHYs, C22 PHYs with direct and
indirect access and PHYs implementing a custom way to access the
registers.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Carlo Caione [Fri, 8 Feb 2019 17:25:07 +0000 (17:25 +0000)]
net: phy: ti: use generic helpers to access MMD registers
Now that generic helpers are available, use those instead of relying on
ti specific functions.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Carlo Caione [Fri, 8 Feb 2019 17:25:06 +0000 (17:25 +0000)]
net: phy: Add generic helpers to access MMD PHY registers
Two new helper functions (phy_read_mmd() and phy_write_mmd()) are added
to allow access to the MMD PHY registers.
The MMD PHY registers can be accessed by several means:
1. Using two new MMD access function hooks in the PHY driver. These
functions can be implemented when the PHY driver does not support the
standard IEEE Compatible clause 45 access mechanism described in clause
22 or if the PHY uses its own non-standard access mechanism.
2. Direct access for C45 PHYs and C22 PHYs when accessing the reachable
DEVADs.
3. The standard clause 45 access extensions to the MMD registers through
the indirection registers (clause 22) in all the other cases.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Tom Rini [Tue, 7 May 2019 13:38:00 +0000 (09:38 -0400)]
Merge branch 'master' of git://git.denx.de/u-boot-sh
- RZ/A1 addition.
- Old board removal.
Tom Rini [Tue, 7 May 2019 13:37:11 +0000 (09:37 -0400)]
Merge branch 'master' of git://git.denx.de/u-boot-socfpga
- Assorted stratix10 fixes.
- DDR driver DM migration.
Chris Brandt [Wed, 23 Aug 2017 19:53:59 +0000 (14:53 -0500)]
ARM: dts: renesas: Add RZ/A1 GR-Peach board
Add board code and DTs for Renesas RZ/A1 SoC-based GR-Peach,
which is a cheap development platform with RZ/A1H SoC. The
DTs are imported from Linux 5.0.11, commit
d5a2675b207d .
Currently supported are UART, ethernet and RPC SPI. The board
can be booted from RPC SPI by writing the u-boot.bin binary
to the beginning of the SPI NOR, e.g. using the "sf" command.
The board can also be booted via JTAG by setting text base to
0x20020000, loading u-boot.bin there via JTAG and executing it
from that address.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Chris Brandt <chris.brandt@renesas.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Chris Brandt [Wed, 23 Aug 2017 19:53:59 +0000 (14:53 -0500)]
ARM: dts: renesas: Add RZ/A1 platform code
Add platform code and DTs for Renesas RZ/A1 R7S72100 SoC.
Distinguishing feature of this SoC is that it has up to
10 MiB of on-SoC static RAM (SRAM).
The DTs are imported from Linux 5.0.11, commit
d5a2675b207d .
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Chris Brandt <chris.brandt@renesas.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Marek Vasut [Sat, 4 May 2019 16:52:33 +0000 (18:52 +0200)]
spi: rpc: Add support for operation without clock framework
Add ifdeffery to allow operation without the clock framework
enabled. This is required on RZ/A1, as it does not have clock
driver yet.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Chris Brandt <chris.brandt@renesas.com>
Cc: Jagan Teki <jagan@amarulasolutions.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Marek Vasut [Wed, 1 May 2019 22:03:26 +0000 (00:03 +0200)]
net: sh_eth: Add support for operation without clock framework
Add ifdeffery to allow operation without the clock framework
enabled. This is required on RZ/A1, as it does not have clock
driver yet.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Chris Brandt <chris.brandt@renesas.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Marek Vasut [Wed, 1 May 2019 16:20:48 +0000 (18:20 +0200)]
net: sh_eth: Add RZ/A1 support
Add support for RZ/A1 SoC specifics.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Chris Brandt <chris.brandt@renesas.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Marek Vasut [Wed, 1 May 2019 16:20:00 +0000 (18:20 +0200)]
serial: sh: Add RZ/A1 support
Add support for RZ/A1 SoC specifics.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Chris Brandt <chris.brandt@renesas.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Marek Vasut [Sat, 4 May 2019 15:30:58 +0000 (17:30 +0200)]
timer: renesas: Add RZ/A1 R7S72100 OSTM timer driver
Add OSTM timer driver for RZ/A1 SoC. The IP is very different
from the R-Car Gen2/Gen3 one already present in the tree, hence
a custom driver.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Chris Brandt <chris.brandt@renesas.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Marek Vasut [Sat, 4 May 2019 12:17:10 +0000 (14:17 +0200)]
pinctrl: renesas: Add RZ/A1 R7S72100 pin control driver
Add pin control driver for RZ/A1 SoC. The IP is very different
from the R-Car Gen2/Gen3 one already present in the tree, hence
a custom driver.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Chris Brandt <chris.brandt@renesas.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Marek Vasut [Sat, 4 May 2019 14:00:17 +0000 (16:00 +0200)]
gpio: renesas: Add RZ/A1 R7S72100 GPIO driver
Add GPIO driver for RZ/A1 SoC. The IP is very different from the
R-Car Gen2/Gen3 one already present in the tree, hence a custom
driver.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Chris Brandt <chris.brandt@renesas.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Marek Vasut [Sat, 4 May 2019 11:28:04 +0000 (13:28 +0200)]
sh: 7785: Remove CPU support
There are no more boards using this CPU and there is no prospect
of any boards showing up soon, remove it.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Chris Brandt <chris.brandt@renesas.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Cc: Vladimir Zapolskiy <vz@mleia.com>
Cc: Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
Marek Vasut [Sat, 4 May 2019 11:21:07 +0000 (13:21 +0200)]
sh: sh7785lcr: Remove the board
Last change to this board was done in 2016, it uses non-DM USB
with no prospects of ever being converted to DM USB, drop it.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Chris Brandt <chris.brandt@renesas.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Cc: Vladimir Zapolskiy <vz@mleia.com>
Cc: Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
Marek Vasut [Sat, 4 May 2019 11:31:06 +0000 (13:31 +0200)]
sh: 7724: Remove CPU support
There are no more boards using this CPU and there is no prospect
of any boards showing up soon, remove it.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Chris Brandt <chris.brandt@renesas.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Cc: Vladimir Zapolskiy <vz@mleia.com>
Cc: Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
Marek Vasut [Sat, 4 May 2019 11:24:51 +0000 (13:24 +0200)]
sh: ecovec: Remove the board
Last change to this board was done in 2016, it uses non-DM USB
with no prospects of ever being converted to DM USB, drop it.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Chris Brandt <chris.brandt@renesas.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Cc: Vladimir Zapolskiy <vz@mleia.com>
Cc: Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
Marek Vasut [Sat, 4 May 2019 11:30:05 +0000 (13:30 +0200)]
sh: sh7757lcr: Fix copy-paste error in README
Update the README to use the correct defconfig.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Chris Brandt <chris.brandt@renesas.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Cc: Vladimir Zapolskiy <vz@mleia.com>
Cc: Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
Tom Rini [Mon, 6 May 2019 11:18:51 +0000 (07:18 -0400)]
Merge branch 'master' of git://git.denx.de/u-boot-sh
- Various pinctrl / gpio fixes for R-Car
Tom Rini [Mon, 6 May 2019 11:18:28 +0000 (07:18 -0400)]
Merge branch 'master' of git://git.denx.de/u-boot-spi
- Important spi-mem fix
Ang, Chee Hong [Fri, 3 May 2019 08:18:27 +0000 (01:18 -0700)]
ARM: socfpga: stratix10: Probe FPGA status before bridge enable
Send CONFIG_STATUS and RECONFIG_STATUS mailbox commands to Secure
Device Manager (SDM) to get the status of FPGA and make sure the
FPGA is in user mode before enable the bridge.
Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
Ang, Chee Hong [Fri, 3 May 2019 08:19:08 +0000 (01:19 -0700)]
ARM: socfpga: stratix10: Disable FPGA2SOC reset
Software must never reset FPGA2SOC bridge. This bridge must only be
reset by POR/COLD/WARM reset. Asserting the FPGA2SOC reset by software
can cause the SoC to lock-up if there are traffics being drived into
FPGA2SOC bridge.
Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
Ley Foon Tan [Mon, 6 May 2019 01:56:01 +0000 (09:56 +0800)]
arm: socfpga: Move Stratix 10 SDRAM driver to DM
Convert Stratix 10 SDRAM driver to device model.
Get rid of call to socfpga_per_reset() and use reset
framework.
SPL is changed from calling function in SDRAM driver
directly to just probing UCLASS_RAM.
Move sdram_s10.h from arch to driver/ddr/altera directory.
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Ley Foon Tan [Mon, 6 May 2019 01:56:00 +0000 (09:56 +0800)]
arm: dts: Stratix10: Add SDRAM node
Add SDRAM device tree node.
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Ley Foon Tan [Mon, 6 May 2019 01:55:59 +0000 (09:55 +0800)]
ddr: altera: Compile ALTERA SDRAM in SPL only
Compile ALTERA_SDRAM driver in SPL only.
Rename ALTERA_SDRAM to SPL_ALTERA_SDRAM.
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Tom Rini [Sun, 5 May 2019 16:25:39 +0000 (12:25 -0400)]
Merge branch '2019-05-05-master-imports'
- Various assorted fixes
- btrfs zstd compression support
- Enable hardware DDR levelling on am43xx platforms.
- pl310 cache controller driver
Philip Molloy [Sun, 31 Mar 2019 03:44:57 +0000 (03:44 +0000)]
env: add missing newline
Signed-off-by: Philip Molloy <philip@philipmolloy.com>
Marcel Ziswiler [Thu, 2 May 2019 15:14:30 +0000 (17:14 +0200)]
board: toradex: drop support.arm maintainer email
Drop Toradex ARM Support <support.arm@toradex.com> from maintainer email
list as this just clogs our support ticketing system.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Acked-by: Stefan Agner <stefan.agner@toradex.com>
Marek Behún [Thu, 2 May 2019 13:29:12 +0000 (15:29 +0200)]
cmd: pxe: add board specific PXE default path
The list of PXE default paths contains ARCH and SOC specific paths, but
one PXE server can serve different board with the same ARCH and SOC.
This is the case for Turris Omnia and Turris Mox, where ARCH=arm and
SOC=mvebu.
If CONFIG_SYS_BOARD is defined, also try "default-$ARCH-$SOC-$BOARD"
path.
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Adam Ford [Tue, 30 Apr 2019 10:21:42 +0000 (05:21 -0500)]
ARM: da850evm: Enable da850-ohci USB host controller
The DA850 EVM has one USB 1.1 OHCI Host controller. With the
host controller now support DM_USB, this patch enables
the respective functions for the da850evm.
Signed-off-by: Adam Ford <aford173@gmail.com>
Adam Ford [Tue, 30 Apr 2019 10:21:41 +0000 (05:21 -0500)]
usb: ohci: ohci-da8xx: Enable da850-ohci driver with DM support
This patch reuses some former code for the hawkboard, combines it
with some some similar DM_USB compatible code for the OHCI driver,
and enables the use of the da850's OHCI controller with DM_USB
compatibility.
Signed-off-by: Adam Ford <aford173@gmail.com>
Marek Behún [Mon, 29 Apr 2019 20:40:45 +0000 (22:40 +0200)]
fs: btrfs: add zstd decompression support
This adds decompression support for Zstandard, which has been included
in Linux btrfs driver for some time.
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Marek Behún [Mon, 29 Apr 2019 20:40:44 +0000 (22:40 +0200)]
lib: add Zstandard decompression support
Add the zstd library from Linux kernel (only decompression support).
There are minimal changes to build with U-Boot, otherwise the files are
identical to Linux commit
dc35da16 from March 2018, the files had not
been touched since in kernel. Also SPDX lincese tags were added.
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Marek Behún [Mon, 29 Apr 2019 20:40:43 +0000 (22:40 +0200)]
lib: Add xxhash support
This adds the xxhash support from Linux. Files are almost identical to
those added to Linux in commit
5d240522 ("lib: Add xxhash module") (they
haven't been touched since in Linux). The only difference is to add some
includes to be compatible with U-Boot. Also SPDX lincese tags were
added.
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Brad Griffis [Mon, 29 Apr 2019 04:29:33 +0000 (09:59 +0530)]
board: ti: am43xx: Enable hardware leveling
Remove the RDLVL_MASK, RDLVLGATE_MASK, WRLVL_MASK & enable
PHY_INVERT_CLKOUT to enable Hardware leveling for am437x
as recommended by EMIF Tools app note:
http://www.ti.com/lit/an/sprac70/sprac70.pdf
Signed-off-by: Brad Griffis <bgriffis@ti.com>
Signed-off-by: Keerthy <j-keerthy@ti.com>
Brad Griffis [Mon, 29 Apr 2019 04:29:32 +0000 (09:59 +0530)]
arm: mach-omap2: am33xx: ddr: update value for ext_phy_ctrl_36
for suspend/resume robustness
update value for ext_phy_ctrl_36 for suspend/resume robustness
with hardware leveling enabled.
Match recommended values from EMIF Tools app note:
http://www.ti.com/lit/an/sprac70/sprac70.pdf
Signed-off-by: Brad Griffis <bgriffis@ti.com>
Signed-off-by: Keerthy <j-keerthy@ti.com>
Brad Griffis [Mon, 29 Apr 2019 04:29:31 +0000 (09:59 +0530)]
arm: mach-omap2: am33xx: Disable EMIF_DEVOFF immediately before hw leveling
In case of RTC+DDR resume, need to restore EMIF context
before initiating hardware leveling.
Signed-off-by: Brad Griffis <bgriffis@ti.com>
[j-keerthy@ti.com Fixed the am335x build issues]
Signed-off-by: Keerthy <j-keerthy@ti.com>
Brad Griffis [Mon, 29 Apr 2019 04:29:30 +0000 (09:59 +0530)]
arm: mach-omap2: am33xx: Enable HW Leveling in the rtc+ddr path
Enable HW leveling in RTC+DDR path. The mandate is to enable
HW leveling bit and then wait for 1 ms before accessing any
register.
Signed-off-by: Brad Griffis <bgriffis@ti.com>
Signed-off-by: Keerthy <j-keerthy@ti.com>
Brad Griffis [Mon, 29 Apr 2019 04:29:29 +0000 (09:59 +0530)]
arm: mach-omap2: am33xx: ddr: Add 1ms delay to avoid L3 error
Add 1ms delay to avoid L3 timeout error during suspend resume.
Signed-off-by: Brad Griffis <bgriffis@ti.com>
Signed-off-by: Keerthy <j-keerthy@ti.com>
Brad Griffis [Mon, 29 Apr 2019 04:29:28 +0000 (09:59 +0530)]
arm: mach-omap2: am33xx: ddr: programming of EXT_PHY_CTRL1 and EXT_PHY_CTRL1_SHADOW
Adjust DQS skew in case where invert_clkout=1 is used.
Match recommended values from EMIF Tools app note:
http://www.ti.com/lit/an/sprac70/sprac70.pdf
Signed-off-by: Brad Griffis <bgriffis@ti.com>
Signed-off-by: Keerthy <j-keerthy@ti.com>
Heinrich Schuchardt [Fri, 26 Apr 2019 16:39:00 +0000 (18:39 +0200)]
lib/display_options: avoid illegal memory access
display_options_get_banner_priv() overwrites bytes before the start of the
buffer if the buffer size is less then 3. This case occurs in the Sandbox
when executing the `ut_print` command.
Correctly handle small buffer sizes. Adjust the print unit test to catch
when bytes before the buffer are overwritten.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Jean-Jacques Hiblot [Fri, 26 Apr 2019 13:21:26 +0000 (15:21 +0200)]
configs: am335x_evm: enable SPL_FIT_IMAGE_TINY
The size of the SPL for the am335x_evm is constrained. There is no need
to have advanced SPL FIT features, so keep the SPL FIT support tiny.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Jean-Jacques Hiblot [Fri, 26 Apr 2019 13:21:25 +0000 (15:21 +0200)]
spl: fit: Always enable tracking of os-type if SPL_OS_BOOT is enabled
FIT_IMAGE_TINY is used to reduce the size of the SPL by removing os-type
tracking and recording the loadables into the loaded FDT. When this option
is enabled, it is assumed that the next stage firmware is u-boot.
However this does not play well with the SPL_OS_BOOT option that enables
loading different type of next stage firmware, like the OS itself.
When SPL_OS_BOOT is used, do not disable os-tracking. The added footprint
is about 300 Bytes.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Simon Goldschmidt [Thu, 25 Apr 2019 19:22:39 +0000 (21:22 +0200)]
spl: fix linker size check off-by-one errors
This fixes SPL linker script size checks for 3 lds files where the size
checks were implemented as "x < YYY_MAX_SIZE".
Fix the size checks to be "x <= YYY_MAX_SIZE" instead.
Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Dinh Nguyen [Tue, 23 Apr 2019 21:55:06 +0000 (16:55 -0500)]
configs: socfpga: add imply pl310 cache controller
Select the PL310 UCLASS_CACHE driver for SoCFPGA.
Reviewed-by: Marek Vasut <marex@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Dinh Nguyen [Tue, 23 Apr 2019 21:55:05 +0000 (16:55 -0500)]
ARM: socfpga: use the pl310 driver to configure the cache
Find the UCLASS_CACHE driver to configure the cache controller's
settings.
Reviewed-by: Marek Vasut <marex@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Dinh Nguyen [Tue, 23 Apr 2019 21:55:04 +0000 (16:55 -0500)]
dm: cache: add the pl310 cache controller driver
Add a PL310 cache controller driver that is usually found on
ARMv7(32-bit) devices. The driver configures the cache settings that can
be found in the device tree files.
This initial revision only configures basic settings(data & instruction
prefetch, shared-override, data & tag latency). I believe these are the
settings that affect performance the most. Comprehensive settings can be
done by the OS.
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Dinh Nguyen [Tue, 23 Apr 2019 21:55:03 +0000 (16:55 -0500)]
dm: cache: Create a uclass for cache
The cache UCLASS will be used for configure settings that can be found
in a CPU's L2 cache controller.
Add a uclass and a test for cache.
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Dinh Nguyen [Tue, 23 Apr 2019 21:55:02 +0000 (16:55 -0500)]
ARM: pl310: Add macro's for handling tag and data latency mask
Add the PL310 macros for latency control setup, read and write bits.
Reviewed-by: Marek Vasut <marex@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Dinh Nguyen [Tue, 23 Apr 2019 21:55:01 +0000 (16:55 -0500)]
Documentation: dts: Add pl310 cache controller dts documentation
Linux commit
8ecd7f5970c5 ("ARM: 8483/1: Documentation: l2c: Rename
l2cc to l2c2x0")
Linux docs:
Documentation/devicetree/bindings/arm/l2c2x0.txt
Copied from Linux kernel v5.0.
"The documentation in the l2cc.txt is specific to the L2 cache
controllers L2C210/L2C220/L2C310 (also known as PL210/PL220/PL310
and variants) and not generic as the file name implies. It's not
valid for integrated L2 controllers as found in e.g.
Cortex-A15/A7/A57/A53."
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Vignesh Raghavendra [Mon, 22 Apr 2019 16:13:33 +0000 (21:43 +0530)]
board: ti: am654: select SYS_DISABLE_DCACHE_OPS for arm64 build
AM654 SoC is IO coherent wrt A53 cores, therefore enable
SYS_DISABLE_DCACHE_OPS to avoid cache operations in A53
SPL/U-Boot.
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Vignesh Raghavendra [Mon, 22 Apr 2019 16:13:32 +0000 (21:43 +0530)]
arch: armv8: Provide a way to disable cache maintenance ops
On AM654 SoC(arm64) which is IO coherent and has L3 Cache, cache
maintenance operations being done to support non-coherent platforms
causes issues.
For example, here is how U-Boot prepares/handles a buffer to receive
data from a device (DMA Write). This may vary slightly depending on the
driver framework:
Start DMA to write to destination buffer
Wait for DMA to be done (dma_receive()/dma_memcpy())
Invalidate destination buffer (invalidate_dcache_range())
Read from destination buffer
The invalidate after the DMA is needed in order to read latest data from
memory that’s updated by DMA write. Also, in case random prefetch has
pulled in buffer data during the “wait for DMA” before the DMA has
written to it. This works well for non-coherent architectures.
In case of coherent architecture with L3 cache, DMA write would directly
update L3 cache contents (assuming cacheline is present in L3) without
updating the DDR memory. So invalidate after “wait for DMA” in above
sequence would discard latest data and read will cause stale data to be
fetched from DDR. Therefore invalidate after “wait for DMA” is not
always correct on coherent architecture.
Therefore, provide a Kconfig option to disable cache maintenance ops on
coherent architectures. This has added benefit of improving the
performance of DMA transfers as we no longer need to invalidate/flush
individual cache lines(especially for buffer thats several KBs in size).
In order to facilitate use of same Kconfig across different
architecture, I have added the symbol to top level arch/Kconfig file.
Patch currently disables cache maintenance ops for arm64 only.
flush_dcache_all() and invalidate_dcache_all() are exclusively used
during enabling/disabling dcache and hence are not disabled.
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Alex Kiernan [Thu, 18 Apr 2019 20:34:55 +0000 (20:34 +0000)]
Refactor IMAGE_ENABLE_VERIFY to handle builds without SPL verification
If building with SPL_LOAD_FIT_FULL and FIT_SIGNATURE, but without
SPL_FIT_SIGNATURE then the build fails with:
common/built-in.o: In function `fit_image_verify_with_data':
common/image-fit.c:1220: undefined reference to `fit_image_verify_required_sigs'
common/image-fit.c:1244: undefined reference to `fit_image_check_sig'
common/built-in.o: In function `fit_image_load':
common/image-fit.c:1857: undefined reference to `fit_config_verify'
Refactor so that host builds still depend on FIT_SIGNATURE, but target
builds check FIT_SIGNATURE/SPL_FIT_SIGNATURE dependent on the build.
Signed-off-by: Alex Kiernan <alex.kiernan@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tom Rini [Sun, 5 May 2019 00:02:31 +0000 (20:02 -0400)]
Merge tag 'mips-pull-2019-05-03' of git://git.denx.de/u-boot-mips
- mscc: small fixes, enhance network support for Serval, Luton and Ocelot
- mt7620: rename arch to more generic name mtmips
- mips: pass initrd addresses via DT as physical addresses
Tom Rini [Sun, 5 May 2019 00:02:16 +0000 (20:02 -0400)]
Merge tag 'mmc-2019-5-3' of https://github.com/MrVan/u-boot
Tom Rini [Sat, 4 May 2019 23:58:09 +0000 (19:58 -0400)]
Merge branch '2019-05-04-master-imports'
- Remove dead code from davinci
- Migrate CONFIG_SUPPORT_EMMC_BOOT
Marek Vasut [Mon, 18 Mar 2019 03:49:21 +0000 (04:49 +0100)]
cmd: mmc: Make Mode: printout consistent
The "Mode :" line is the only one in "mmc info" output that has a
space in front of the colon. Drop the space to make it consistent
with the rest of the output, e.g.:
=> mmc dev 1 ; mmc info
switch to partitions #0, OK
mmc1 is current device
Device: sd@
ee160000
Manufacturer ID: 3
OEM: 5344
Name: SL08G
Bus Speed:
50000000
Mode : SD High Speed (50MHz)
^------------------------------ Remove this space
Rd Block Len: 512
SD version 3.0
High Capacity: Yes
Capacity: 7.4 GiB
Bus Width: 1-bit
Erase Group Size: 512 Bytes
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
CC: Tom Rini <trini@konsulko.com>
Marek Vasut [Sat, 13 Apr 2019 09:42:34 +0000 (11:42 +0200)]
net: ravb: Avoid unsupported internal delay mode for R-Car E3/D3
According to the R-Car Gen3 Hardware Manual Rev 1.50 of Nov 30, 2018, the
TX clock internal delay mode isn't supported on R-Car E3 (r8a77990) or D3
(r8a77995).
Avoid setting the APSR:TDM bit on these SoCs. Moreover, only set APSR:TDM
when the DT explicitly specifies RGMII ID or TXID mode instead of setting
it unconditionally when the PHY link speed is 1000 Mbit/s.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Marek Vasut [Sun, 21 Apr 2019 20:14:11 +0000 (22:14 +0200)]
ARM: rmobile: Always select pin control drivers on Gen3
To assure the pins on R-Car Gen3 SoCs are configured correctly, always
select pin control drivers on Gen3 SoCs.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Marek Vasut [Sun, 21 Apr 2019 20:46:25 +0000 (22:46 +0200)]
pinctrl: renesas: Remove sh_pfc_config_mux_for_gpio()
This function is now replaced by common pin controller GPIO configuration
functionality, drop it.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Alex Kiernan <alex.kiernan@gmail.com>
Cc: Christoph Muellner <christoph.muellner@theobroma-systems.com>
Cc: Eugeniu Rosca <roscaeugeniu@gmail.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Patrick DELAUNAY <patrick.delaunay@st.com>
Cc: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Cc: Simon Glass <sjg@chromium.org>
Marek Vasut [Sun, 21 Apr 2019 20:46:25 +0000 (22:46 +0200)]
gpio: renesas: Migrate to pinctrl GPIO accessors
Switch to generic pin controller API for configuring pins as GPIOs
instead of using the ad-hoc call into the R-Car PFC driver. Moreover,
add .free() implementation for the GPIO controller.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Alex Kiernan <alex.kiernan@gmail.com>
Cc: Christoph Muellner <christoph.muellner@theobroma-systems.com>
Cc: Eugeniu Rosca <roscaeugeniu@gmail.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Patrick DELAUNAY <patrick.delaunay@st.com>
Cc: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Cc: Simon Glass <sjg@chromium.org>
Marek Vasut [Sun, 21 Apr 2019 20:46:25 +0000 (22:46 +0200)]
pinctrl: renesas: Implement gpio_request_enable/gpio_disable_free
Implement the gpio_request_enable/gpio_disable_free callbacks to let
the GPIO driver call the pin control framework and let it reconfigure
pins as GPIOs.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Alex Kiernan <alex.kiernan@gmail.com>
Cc: Christoph Muellner <christoph.muellner@theobroma-systems.com>
Cc: Eugeniu Rosca <roscaeugeniu@gmail.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Patrick DELAUNAY <patrick.delaunay@st.com>
Cc: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Cc: Simon Glass <sjg@chromium.org>
Marek Vasut [Sun, 21 Apr 2019 20:46:25 +0000 (22:46 +0200)]
pinctrl: renesas: Set pin type in sh_pfc_config_mux_for_gpio
Add missing cfg->type = PINMUX_TYPE_GPIO upon successfully setting pin
as a GPIO to retain the pin configuration information.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Alex Kiernan <alex.kiernan@gmail.com>
Cc: Christoph Muellner <christoph.muellner@theobroma-systems.com>
Cc: Eugeniu Rosca <roscaeugeniu@gmail.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Patrick DELAUNAY <patrick.delaunay@st.com>
Cc: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Cc: Simon Glass <sjg@chromium.org>
Marek Vasut [Sun, 21 Apr 2019 21:57:23 +0000 (23:57 +0200)]
pinctrl: gpio: Add callback for configuring pin as GPIO
Add callback to configure, and de-configure, pin as a GPIO on the
pin controller side. This matches similar functionality in Linux
and aims to replace the ad-hoc implementations present in U-Boot.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Alex Kiernan <alex.kiernan@gmail.com>
Cc: Christoph Muellner <christoph.muellner@theobroma-systems.com>
Cc: Eugeniu Rosca <roscaeugeniu@gmail.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Patrick DELAUNAY <patrick.delaunay@st.com>
Cc: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Cc: Simon Glass <sjg@chromium.org>
Marek Vasut [Tue, 2 Oct 2018 18:40:58 +0000 (20:40 +0200)]
ARM: renesas: Configure DRAM size from ATF DT fragment
The ATF can pass additional information via the first four registers,
x0...x3. The R-Car Gen3 with mainline ATF, register x1 contains pointer
to a device tree with platform information. Parse this device tree and
extract DRAM size information from it. This is useful on systems where
the DRAM size can vary between configurations.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Ismael Luceno Cortes [Mon, 18 Mar 2019 12:27:32 +0000 (12:27 +0000)]
cmd: clk: Handle ENODEV from clk_get_rate
clk_get_rate may return -ENODEV if the clock isn't valid.
Also, make the error cases go through a single path.
Fixes: ff8eee0330a6 ("cmd: clk: Add trivial implementation of clock dump
for DM")
Signed-off-by: Ismael Luceno <ismael.luceno@silicon-gears.com>
Reviewed-by: Matthias Brugger <mbrugger@suse.com>
Reviewed-by: Marek Vasut <marek.vasut@gmail.com>
Robert P. J. Day [Sun, 14 Apr 2019 10:20:55 +0000 (06:20 -0400)]
delete Kbuild "select" of long-dead SPL_DISABLE_OF_CONTROL
>From way back in 2015:
commit
dffb86e468c8e02ba77283989aefef214d904dc5
Author: Masahiro Yamada <yamada.masahiro@socionext.com>
Date: Wed Aug 12 07:31:54 2015 +0900
of: flip CONFIG_SPL_DISABLE_OF_CONTROL into CONFIG_SPL_OF_CONTROL
As we discussed a couple of times, negative CONFIG options make our
life difficult; CONFIG_SYS_NO_FLASH, CONFIG_SYS_DCACHE_OFF, ...
and here is another one.
Now, there are three boards enabling OF_CONTROL on SPL:
- socfpga_arria5_defconfig
- socfpga_cyclone5_defconfig
- socfpga_socrates_defconfig
This commit adds CONFIG_SPL_OF_CONTROL for them and deletes
CONFIG_SPL_DISABLE_OF_CONTROL from the other boards to invert
the logic.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Alex Kiernan [Wed, 1 May 2019 07:58:27 +0000 (07:58 +0000)]
Convert CONFIG_SUPPORT_EMMC_BOOT to Kconfig
This converts the following to Kconfig:
CONFIG_SUPPORT_EMMC_BOOT
As requested by Michal Simek <michal.simek@xilinx.com>, these boards
have no eMMC so CONFIG_SUPPORT_EMMC_BOOT has not been migrated:
xilinx_zynqmp_zc1275_revB
xilinx_zynqmp_zc1751_xm018_dc4
xilinx_zynqmp_zc1751_xm019_dc5
xilinx_zynqmp_zcu100_revC
xilinx_zynqmp_zcu102_rev1_0
xilinx_zynqmp_zcu102_revA
xilinx_zynqmp_zcu102_revB
xilinx_zynqmp_zcu104_revA
xilinx_zynqmp_zcu104_revC
xilinx_zynqmp_zcu106_revA
xilinx_zynqmp_zcu111_revA
Signed-off-by: Alex Kiernan <alex.kiernan@gmail.com>
Acked-by: Lukasz Majewski <lukma@denx.de>
Acked-by: Patrick Delaunay <patrick.delaunay@st.com>
Acked-by: Ramon Fried <ramon.fried@gmail.com>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Tested-by: Sébastien Szymanski <sebastien.szymanski@armadeus.com>
Bartosz Golaszewski [Mon, 29 Apr 2019 16:37:12 +0000 (18:37 +0200)]
arm: davinci: remove leftover code for dm* SoCs
The support for DaVinci DM* SoCs has been dropped a while ago. There's
still a lot of leftover code in mach-davinci though. Entirely remove
certain files and modify the common code to no longer reference
unsupported chips.
Note: all DaVinci platforms supported in u-boot now define SOC_DA8XX
but not all define SOC_DA850 (e.g. omapl138). We can safely remove
all ifdefs for the former, but let's leave the ones for the latter.
Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
Bartosz Golaszewski [Mon, 29 Apr 2019 16:37:11 +0000 (18:37 +0200)]
usb: musb_hcd: remove unnecessary ifdefs for dm* SoCs
The support for DaVinci DM* SoCs has been dropped. The ifdefs in the
musb_hcd driver are no longer needed. Remove them.
Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
Acked-by: Marek Vasut <marex@denx.de>
Bartosz Golaszewski [Mon, 29 Apr 2019 16:37:10 +0000 (18:37 +0200)]
nand: davinci: remove dead code for dm644x
The support for DaVinci DM* SoCs has been dropped. The code that used
to be relevant to dm644x is no longer needed. Remove it.
Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
Bartosz Golaszewski [Mon, 29 Apr 2019 16:37:09 +0000 (18:37 +0200)]
arm: davinci: remove dead code for PHYs used by DaVinci DM* boards
The support for DaVinci DM* boards has been dropped a while ago. The
code for all those PHYs is no longer used and they have their own
proper PHY drivers in drivers/net/phy anyway. Remove all dead code.
Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
Bartosz Golaszewski [Mon, 29 Apr 2019 16:37:08 +0000 (18:37 +0200)]
net: davinci_emac: drop support for unused PHYs
The boards with SoCs from the DaVinci DM* family used to come with
different PHYs that needed special support implemented in mach-davinci.
Since the support for these chips has long been removed, we can now
drop this unnused code from the emac driver.
Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
Tom Rini [Fri, 3 May 2019 18:23:01 +0000 (14:23 -0400)]
Merge git://git.denx.de/u-boot-socfpga
- Misc MMC, FPGA bridge, general SoCFPGA fixes
Tom Rini [Fri, 3 May 2019 18:22:38 +0000 (14:22 -0400)]
Merge git://git.denx.de/u-boot-usb
- DaVinci updates
Tom Rini [Fri, 3 May 2019 18:22:23 +0000 (14:22 -0400)]
Merge git://git.denx.de/u-boot-marvell
- Fix in kwbimage (return code checking) (Young Xiao)
- Misc updates to Turris Omnia (Marek)
Adam Ford [Sun, 28 Apr 2019 21:45:26 +0000 (16:45 -0500)]
ARM: davinci: Remove unused functions from header
There are a few functions defined in the header file, but they are
not referenced by any Davinci code. In order to make a general
function in the future with static function declarations, this
patch will remove the references all together.
Signed-off-by: Adam Ford <aford173@gmail.com>
Adam Ford [Sun, 28 Apr 2019 21:45:25 +0000 (16:45 -0500)]
usb: ohci: Re-enable commented out delay
There is a delay function that was commented out. This patch
re-enables it, because it will be needed for da850 ohci support.
Signed-off-by: Adam Ford <aford173@gmail.com>
Horatiu Vultur [Wed, 1 May 2019 11:17:00 +0000 (13:17 +0200)]
net: mscc: ocelot: Update DTS for Luton pcb90
Update device tree for luton to add support for luton pcb90.
This pcb has 24 ports from which 12 ports are connected to
SerDes6G.
Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Horatiu Vultur [Wed, 1 May 2019 11:16:59 +0000 (13:16 +0200)]
board: mscc: luton: Update MSCC Luton board
Implement method board_phy_config to configure the external phys
on the pcb90.
Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Horatiu Vultur [Wed, 1 May 2019 11:16:58 +0000 (13:16 +0200)]
net: mscc: luton: Update network driver for pcb90
Update Luton network driver to have support also for pcb90. The pcb90
has 24 ports from which 12 ports are connected to SerDes6G.
Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Weijie Gao [Tue, 30 Apr 2019 03:13:58 +0000 (11:13 +0800)]
mips: rename mach-mt7620 to mach-mtmips
Currently mach-mt7620 contains only support for mt7628. To avoid confusion,
rename mach-mt7620 to mach-mtmips, which means MediaTek MIPS platforms.
MT7620 and MT7628 should be distinguished by SOC_MT7620 and SOC_MT7628
because they do not share the same lowlevel codes.
Dependencies of four drivers are changed to SOC_MT7628 as these drivers
are only used by MT7628.
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
Horatiu Vultur [Wed, 24 Apr 2019 09:27:59 +0000 (11:27 +0200)]
net: mscc: ocelot: Update DTS for Ocelot pcb120.
Update device tree for ocelot to add support for ocelot pcb120.
Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Horatiu Vultur [Wed, 24 Apr 2019 09:27:58 +0000 (11:27 +0200)]
board: mscc: ocelot: Update MSCC Ocelot board.
Implement method board_phy_config to configure the phy for pcb120.
Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Horatiu Vultur [Wed, 24 Apr 2019 09:27:57 +0000 (11:27 +0200)]
net: mscc: ocelot: Update network driver for pcb120
Update Ocelot network driver to have support also for pcb120.
Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Horatiu Vultur [Wed, 24 Apr 2019 15:21:29 +0000 (17:21 +0200)]
arch: mips: Update initrd_start and initrd_end
Microsemi SoC defines CONFIG_SYS_SDRAM_BASE to be 0x80000000, which
represents the start of kseg0 and represents a virtual address. Meaning
that the initrd_start and initrd_end point somewhere kseg0.
When these parameters are passed to linux kernel through DT
they are pointing somewhere in kseg0 which is a virtual address but linux
kernel expects the addresses to be physical addresses(in kuseg) because
it is converting the physical address to a virtual one.
Therefore update the uboot to pass the physical address of initrd_start
and initrd_end by converting them using the function virt_to_phys before
setting up the DT.
Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Robert P. J. Day [Wed, 17 Apr 2019 20:13:45 +0000 (16:13 -0400)]
MSCC: delete obsolete reference to MSCC_BITBANG_SPI_GPIO
Remove "select MSCC_BITBANG_SPI_GPIO" since Kbuild option was deleted
back in commit
ace9c103df2875d2b435dbd7b36618020edfd1c0:
commit
ace9c103df2875d2b435dbd7b36618020edfd1c0
Author: Lars Povlsen <lars.povlsen@microchip.com>
Date: Tue Jan 8 10:38:35 2019 +0100
mips: gpio: mscc: Obsoleted gpio-mscc-bitbang-spi.c
Horatiu Vultur [Thu, 11 Apr 2019 12:11:35 +0000 (14:11 +0200)]
configs: mscc_serval: Add network support
Update default config to use network driver for Serval SoCs.
Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Horatiu Vultur [Thu, 11 Apr 2019 12:11:34 +0000 (14:11 +0200)]
net: mscc: serval: Add ethernet nodes for Serval
Add ethernet nodes for Serval SoCs family. There are 2 pcb in this
family: pcb105 and pcb106.
Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Horatiu Vultur [Thu, 11 Apr 2019 12:11:33 +0000 (14:11 +0200)]
board: mscc: serval: Update MSCC Serval boards
In Serval SoC family there are 2 different pcb, both of them have the same
phy, but with different version. Therefore implement board_phy_config
and set all the phys in the same way.
Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Horatiu Vultur [Thu, 11 Apr 2019 12:11:32 +0000 (14:11 +0200)]
net: Add MSCC Serval network driver.
Add network driver for Microsemi Ethernet switch.
It is present on Serval SoCs.
Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Horatiu Vultur [Mon, 15 Apr 2019 09:56:37 +0000 (11:56 +0200)]
board: mscc: serval: Fix board detect
When detecting the board, it was reading a register in the GPIO page of
the phy and based on that value it was making a decision. The bug was that
after the GPIO page for the first phy was set it was not reseted back.
Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Horatiu Vultur [Mon, 15 Apr 2019 09:56:36 +0000 (11:56 +0200)]
mips: mscc: serval: Fix reset
In case the ddr training was failing, it couldn't reset, it was just
hanging. Therefore reimplement it, so when ddr training is failing
it would call _machine_restart, which power downs the DDR and does
a force reset.
Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Faiz Abbas [Tue, 16 Apr 2019 17:36:58 +0000 (23:06 +0530)]
mmc: sdhci: Add Support for ADMA2
The Standard Host Controller Interface (SDHCI) specification version
3.00 adds support for Advanced DMA (ADMA) for both 64 and 32 bit widths
of DMA. ADMA2 uses a table of descriptors for aggregating DMA requests.
This significantly improves read and write throughput.
Add Support for the same.
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Faiz Abbas [Tue, 16 Apr 2019 17:36:57 +0000 (23:06 +0530)]
mmc: sdhci: Move DMA handling to prepare_dma() function
In preparation for addition of ADMA2 support, cleanup SDMA handling by
moving it to a new sdhci_prepare_dma() function. Also add a flags field
in sdhci_host to indicate if DMA is enabled.
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Ye Li [Mon, 7 Jan 2019 09:10:27 +0000 (09:10 +0000)]
mmc: fsl_esdhc: Fix wp_enable issue
The wp-gpios property is used for gpio, if this is set, the WP pin is muxed
to gpio function, can't be used as internal WP checking. However the codes
remain to use internal WP checking.
This patch changes to examine the "fsl,wp-controller" for enabling internal WP
checking, and "wp-gpios" for muxing to gpio.
Signed-off-by: Ye Li <ye.li@nxp.com>
Ye Li [Mon, 7 Jan 2019 03:18:06 +0000 (03:18 +0000)]
mmc: fsl_esdhc: fix sd/mmc ddr mode clock setting issue
When sd/mmc work at DDR mode, like HS400/HS400ES/DDR52/DDR50 mode,
the output clock rate is half of the internal clock rate.
This patch set the DDR_EN bit first for DDR mode, hardware divide
the usdhc clock automatically, then follow the original sdr clock
setting method.
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Tom Rini [Fri, 3 May 2019 11:30:55 +0000 (07:30 -0400)]
Merge branch '2019-05-03-master-imports'
- Various btrfs fixes
- Various TI platform fixes
- Other fixes (cross build, taurus update, Kconfig help text)