Alyssa Rosenzweig [Tue, 25 Jun 2019 20:30:17 +0000 (13:30 -0700)]
panfrost: Update copyright identifiers
"Collabora, Ltd." should be listed in lieu of simply "Collabora"
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Suggested-by: Daniel Stone <daniels@collabora.com>
Alyssa Rosenzweig [Tue, 18 Jun 2019 16:02:35 +0000 (09:02 -0700)]
panfrost/midgard: Reorder to permit constant bias
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Tue, 18 Jun 2019 16:02:20 +0000 (09:02 -0700)]
panfrost/midgard: Add helper to encode constant bias
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Tue, 18 Jun 2019 16:06:25 +0000 (09:06 -0700)]
panfrost/midgard: Handle negative immediate bias
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Rob Clark [Wed, 26 Jun 2019 15:25:55 +0000 (08:25 -0700)]
freedreno: correct batch_depends_on() logic
Signed-off-by: Rob Clark <robdclark@chromium.org>
Rob Clark [Tue, 25 Jun 2019 18:21:28 +0000 (11:21 -0700)]
freedreno: drop unused arg from fd_batch_flush()
The `force` arg has been unused for a while.. but apparently I forgot to
garbage collect it.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Timothy Arceri [Wed, 26 Jun 2019 13:02:12 +0000 (23:02 +1000)]
st/glsl: fix silly regression finding gs/tes variants
Fixes:
d19fe5e67a39 ("st/glsl: support clamping color outputs in compat for gs/tes")
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Timothy Arceri [Tue, 25 Jun 2019 10:53:15 +0000 (20:53 +1000)]
st/glsl: support clamping color outputs in compat for gs/tes
This support requires the driver to be a NIR driver as we use the
NIR lowering pass to do the clamping.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Timothy Arceri [Tue, 25 Jun 2019 06:33:22 +0000 (16:33 +1000)]
nir: add tess support to nir_lower_clamp_color_outputs()
This will be used to add compat profile support for higher GL
versions.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Sagar Ghuge [Mon, 24 Jun 2019 22:10:53 +0000 (15:10 -0700)]
glsl: Fix round64 conversion function
Fix round64 function to handle round to nearest even cases specially
with positive and negative numbers with fraction part 0.5.
v2: 1) Simplify unused bits (Elie Tournier)
Fixes:
KHR-GL45.gpu_shader_fp64.builtin.round_dvec2
KHR-GL45.gpu_shader_fp64.builtin.round_dvec3
KHR-GL45.gpu_shader_fp64.builtin.round_dvec4
KHR-GL45.gpu_shader_fp64.builtin.roundeven_double
KHR-GL45.gpu_shader_fp64.builtin.roundeven_dvec2
KHR-GL45.gpu_shader_fp64.builtin.roundeven_dvec3
KHR-GL45.gpu_shader_fp64.builtin.roundeven_dvec4
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Elie Tournier <elie.tournier@collabora.com>
Acked-by: Anuj Phogat <anuj.phogat@gmail.com>
Alyssa Rosenzweig [Tue, 25 Jun 2019 20:42:58 +0000 (13:42 -0700)]
panfrost/ci: Add RK3288 flipflops I don't want to deal with right now
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Mon, 24 Jun 2019 17:16:33 +0000 (10:16 -0700)]
panfrost/ci: Update failures list
A ton of tests were fixed by this series. A few were incorrectly passing
before (QualityError, for instance) and now are explicitly failing. A
few legitimate regressions but overwhelmingly positive.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Mon, 24 Jun 2019 20:17:28 +0000 (13:17 -0700)]
panfrost/ci: Set MESA_GLES_VERSION_OVERRIDE=3.0
Fixes cube map tests due to disagreements between Mesa, dEQP, and the
spec...
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Cc: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Alyssa Rosenzweig [Mon, 24 Jun 2019 22:06:47 +0000 (15:06 -0700)]
panfrost/ci: Run full set of mipmap tests
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Tue, 25 Jun 2019 14:01:52 +0000 (07:01 -0700)]
panfrost: Advertise support for other 8-bit UNORM formats
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Tue, 25 Jun 2019 15:57:55 +0000 (08:57 -0700)]
panfrost: Use pipe_surface->format directly in blitter
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Tue, 25 Jun 2019 15:51:48 +0000 (08:51 -0700)]
panfrost: Invert swizzle for rendering
Fixes rendering to e.g. alpha textures.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Mon, 24 Jun 2019 21:53:54 +0000 (14:53 -0700)]
panfrost: Honour first_layer...last_layer when sampling
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Mon, 24 Jun 2019 21:39:37 +0000 (14:39 -0700)]
panfrost: Use the sampler_view target (not the textures)
u_blitter gets "special treatment" and uses this mechanism to cast
cube maps to 2D textures in order to texelFetch them.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Mon, 24 Jun 2019 21:39:25 +0000 (14:39 -0700)]
panfrost/midgard: Assert guard texelFetch against cubemaps
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Mon, 24 Jun 2019 21:13:20 +0000 (14:13 -0700)]
panfrost: Zero pixels in any axis is zero pixels total
Multiplication, not addition, so switch the logic operator.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Mon, 24 Jun 2019 20:53:44 +0000 (13:53 -0700)]
panfrost: Respect mip level when wallpapering
Fixes DATA_INVALID_FAULT raised when wallpapering while rendering to a
mipmap.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Mon, 24 Jun 2019 17:35:03 +0000 (10:35 -0700)]
panfrost/midgard: Fixup NIR texture op
In a vertex shader, a tex op should map to txl, as there *must* be a LOD
given to the hardware (implicitly or explicitly).
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Mon, 24 Jun 2019 16:16:11 +0000 (09:16 -0700)]
panfrost: Support (non-)seamless cube maps
Identify the seamless cubemap bit and passthrough the Gallium state
rather than setting unconditionally.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Mon, 24 Jun 2019 14:08:52 +0000 (07:08 -0700)]
panfrost: Merge checksum buffer with main BO
This is similar to the AFBC merge; now all (non-imported) buffers use a
common backing buffer. Reenables checksumming, eliminating a performance
regression.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Sun, 23 Jun 2019 18:29:46 +0000 (11:29 -0700)]
panfrost/decode: Limit MRT blend count
I thought I already fixed this. Maybe that was a dream...? Then again, I
might be dreaming now.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Sun, 23 Jun 2019 18:20:00 +0000 (11:20 -0700)]
panfrost: Clamp tile coordinates before job submission
Fixes TILE_RANGE_FAULT raised on some tests in
dEQP-GLES3.functional.fbo.blit.*
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Sun, 23 Jun 2019 18:05:10 +0000 (11:05 -0700)]
panfrost: Use dedicated u_blitter context for wallpapers
The main ctx->blitter instance should be reserved for blits originated
from Gallium (like mipmap generation). Since wallpapering is
conceptually different -- wallpaper blits can be triggered by Gallium
blits -- the blitter pipes must be separate to avoid potential u_blitter
recursion.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Sat, 22 Jun 2019 00:39:02 +0000 (17:39 -0700)]
panfrost: Sanity check layer
It doesn't make sense to try to render to multiple array elements at
once.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Sat, 22 Jun 2019 00:27:05 +0000 (17:27 -0700)]
panfrost: Divide array_size by 6 for cubemaps
Addresses the disparity between Mali and Gallium definitions of
array_size.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Sat, 22 Jun 2019 00:23:49 +0000 (17:23 -0700)]
panfrost: Use get_texture_address for framebuffer computations
Allows for sharing some code as well as theoretically allowing cubemap
rendering.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Fri, 21 Jun 2019 21:54:44 +0000 (14:54 -0700)]
panfrost: Merge AFBC slab with BO backing
Rather than tracking AFBC memory "specially", just use the same codepath
as linear and tiled. Less things to mess up, I figure. This allows us to
use the standard setup_slices() call with AFBC resources, allowing
mipmapped AFBC resources.
Unfortunately, we do have to disable AFBC (and checksumming) in the
meantime to avoid functional regressions, as we don't know _a priori_ if
we'll need to access a resource from software (which is not yet hooked
up with AFBC) and we don't yet have routines to switch the layout of a
BO at runtime.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Fri, 21 Jun 2019 21:41:14 +0000 (14:41 -0700)]
panfrost: Z/S can't be tiled
As far as we know, Utgard-style tiling only works for color render
targets, not depth/stencil, so ensure we don't try to tile it (rather
than compress or plain old linear) and drive ourselves into a corner.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Fri, 21 Jun 2019 21:26:19 +0000 (14:26 -0700)]
panfrost: Enable mipmapping
Now the autogeneration of mipmaps is working (via u_blitter), we can
finally enable mipmaps!
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Fri, 21 Jun 2019 21:25:59 +0000 (14:25 -0700)]
panfrost: Enable blitting
Now that all the prerequisites breaking u_blitter are fixed, we can
finally hook up panfrost_blit.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Sun, 23 Jun 2019 18:49:49 +0000 (11:49 -0700)]
panfrost: Allow texelFetch for wallpaper blits
We just implemented the routine; we may as well use it.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Fri, 21 Jun 2019 23:17:34 +0000 (16:17 -0700)]
panfrost/midgard: Implement texelFetch (2D only)
txf instructions can result from blits, so handle them rather than
crash. Only works for 2D textures (not even 2D array texture) due to a
register allocation constraint that may not be sorted for a while.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Fri, 21 Jun 2019 20:59:51 +0000 (13:59 -0700)]
panfrost: Skip flushes only for wallpapers, not any blit
We need the flush from u_blitter for a normal blit (e.g. for mipmaps);
it's only wallpaper-related blits that are special-cased.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Fri, 21 Jun 2019 20:57:42 +0000 (13:57 -0700)]
panfrost: Handle generate_mipmap ourselves
To avoid interference with the wallpaper code, we need to do some state
tracking when generating mipmaps. In particular, we need to mark the
generated layers as invalid before generating the mipmap, so we don't
try to backblit them if they already had content.
Likewise, we need to flush both before and after generating a mipmap
since our usual set_framebuffer_state flushing isn't quite there yet.
Ideally better optimizations would save the flush but I digress.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Fri, 21 Jun 2019 23:58:48 +0000 (16:58 -0700)]
panfrost: Disable mipmapping if necessary
If a mipfilter is not set, it's legal to have an incomplete mipmap; we
should handle this accordingly. An "easy way out" is to rig the LOD
clamps.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Kenneth Graunke [Mon, 24 Jun 2019 22:09:51 +0000 (15:09 -0700)]
intel/blorp: Disable sampler state prefetching on Gen11
Sampler state prefetching is broken on Gen11, and WA_160668216 says
to disable it. Apparently sampler state prefetching also has basically
zero impact on performance, so we don't need to worry there.
i965, anv, and iris already handle this correctly, but we missed BLORP.
Ideally the kernel should globally disable this by writing SARCHKMD, at
which point we wouldn't have to worry about it. But let's be defensive
and handle it ourselves too.
v2: separate out from BTP workaround in case we change that eventually
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com> [v1]
Jason Ekstrand [Tue, 25 Jun 2019 19:26:56 +0000 (14:26 -0500)]
anv/descriptor_set: Only write texture swizzles if we have an image view
When immutable samplers are set we call write_image_view with a NULL
image view. This causes issues on IVB where we have to fake texture
swizzling.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110999
Fixes:
d2aa65eb18 "anv: Emulate texture swizzle in the shader when..."
Chia-I Wu [Mon, 24 Jun 2019 17:47:59 +0000 (10:47 -0700)]
virgl: add VIRGL_DEBUG_XFER
When set, do as requested and skip any transfer optimization.
Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-By: Gert Wollny <gert.wollny@collabora.com>
Reviewed-By: Alexandros Frantzis <alexandros.frantzis@collabora.com>
Chia-I Wu [Mon, 24 Jun 2019 17:45:36 +0000 (10:45 -0700)]
virgl: add VIRGL_DEBUG_SYNC
When set, wait after every each flush.
Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-By: Gert Wollny <gert.wollny@collabora.com>
Reviewed-By: Alexandros Frantzis <alexandros.frantzis@collabora.com>
Chia-I Wu [Mon, 24 Jun 2019 17:30:52 +0000 (10:30 -0700)]
virgl: fix the value of VIRGL_DEBUG_BGRA_DEST_SWIZZLE
VIRGL_DEBUG_BGRA_DEST_SWIZZLE should use bit 3. Make some cosmetic
changes as well.
Fixes:
a478e56fbd33fa23503b63d41265a1c2f3253ed2
virgl: Add debug flag to bypass driconf to enable the BGRA tweaks
Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-By: Gert Wollny <gert.wollny@collabora.com>
Reviewed-By: Alexandros Frantzis <alexandros.frantzis@collabora.com>
Samuel Pitoiset [Tue, 25 Jun 2019 15:57:45 +0000 (17:57 +0200)]
radv: rename and re-document cache flush flags
SMEM and VMEM caches are L0 on gfx10. Ported from RadeonSI.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Tue, 25 Jun 2019 14:17:17 +0000 (16:17 +0200)]
radv: set DISABLE_CONSTANT_ENCODE_REG to 1 for Raven2
Ported from RadeonSI, will be emitted for GFX10 too.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Mon, 24 Jun 2019 16:40:29 +0000 (18:40 +0200)]
radv: clear CMASK layers instead of the whole buffer on GFX8
This reduces the size of fill operations needed to clear CMASK
for layered color textures.
GFX9 unsupported for now.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Mon, 24 Jun 2019 10:18:01 +0000 (12:18 +0200)]
radv: clear FMASK layers instead of the whole buffer on GFX8
This reduces the size of fill operations needed to clear FMASK
for layered color textures.
GFX9 unsupported for now.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Mon, 24 Jun 2019 15:03:28 +0000 (17:03 +0200)]
radv: always initialize levels without DCC as fully expanded
This fixes a rendering issue with RoTR/DXVK.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Sergii Romantsov [Tue, 18 Jun 2019 14:07:21 +0000 (17:07 +0300)]
i965: leaking of upload-BO with push constants
In case of any enabled VS members from: uses_firstvertex,
uses_baseinstance, uses_drawid, uses_is_indexed_draw
leaks may happens.
Call gen6_upload_push_constants allocates
stage_stat->push_const_bo. It than takes pointer from
push_const_bo to draw_params_bo (in the call
brw_prepare_shader_draw_parameters by brw_upload_data)
and do reference which finally haven't got unreferenced.
Fixes leak:
136 bytes in 1 blocks are definitely lost in loss record 6 of 13
at 0x4C31B25: calloc (in /usr/lib/valgrind/vgpreload_memcheck-amd64-linux.so)
by 0xC2B64B7: bo_alloc_internal (brw_bufmgr.c:596)
by 0xC2B6748: brw_bo_alloc (brw_bufmgr.c:672)
by 0xC314BB3: brw_upload_space (intel_upload.c:88)
by 0xC2EBBC5: gen6_upload_push_constants (gen6_constant_state.c:155)
by 0xC9E4FA6: gen9_upload_vs_push_constants (genX_state_upload.c:3300)
by 0xC2E0EDA: check_and_emit_atom (brw_state_upload.c:540)
by 0xC2E0EDA: brw_upload_pipeline_state (brw_state_upload.c:659)
by 0xC2E0FF1: brw_upload_render_state (brw_state_upload.c:681)
by 0xC2C5D2D: brw_draw_single_prim (brw_draw.c:1052)
by 0xC2C62CB: brw_draw_prims (brw_draw.c:1175)
by 0xC488AD1: vbo_exec_vtx_flush (vbo_exec_draw.c:386)
by 0xC485270: vbo_exec_FlushVertices_internal (vbo_exec_api.c:652)
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reported-by: Yevhenii Kolesnikov <yevhenii.kolesnikov@globallogic.com>
Signed-off-by: Sergii Romantsov <sergii.romantsov@globallogic.com>
Juan A. Suarez Romero [Tue, 25 Jun 2019 11:02:37 +0000 (13:02 +0200)]
docs: update calendar, add news item and link release notes for X.Y.Z
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Juan A. Suarez Romero [Tue, 25 Jun 2019 11:01:56 +0000 (13:01 +0200)]
docs: fix some typos in 19.0.7 release notes
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Juan A. Suarez Romero [Tue, 25 Jun 2019 10:56:10 +0000 (12:56 +0200)]
docs: add sha256 checksums for 19.1.1
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
(cherry picked from commit
d54dc24d6d6ad9ce4fbebd5f9a69a92633504c40)
Juan A. Suarez Romero [Tue, 25 Jun 2019 10:43:49 +0000 (12:43 +0200)]
docs: add release notes for 19.1.1
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
(cherry picked from commit
22eddd8b9d4d905237494c9841e65e4c073ab514)
Tapani Pälli [Mon, 24 Jun 2019 11:36:28 +0000 (14:36 +0300)]
intel/compiler: silence a warning of using different enum type
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Eric Engestrom [Sat, 22 Jun 2019 14:53:36 +0000 (15:53 +0100)]
egl: replace dead vfunc with an error
st/egl used to support eglCreatePbufferFromClientBuffer, but now that
it's gone, any call to it would segfault.
Let's return a nice error instead.
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Eric Engestrom [Fri, 14 Jun 2019 15:08:44 +0000 (16:08 +0100)]
egl: delete unused vfuncs
Nobody ever uses these, so let's just hard code them instead.
If an EGL driver ever comes around that needs them they're trivial to
re-add.
Suggested-by: Emil Velikov <emil.velikov@collabora.com>
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Eric Engestrom [Sat, 22 Jun 2019 15:09:48 +0000 (16:09 +0100)]
egl: drop empty eglfallbacks.c
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Eric Engestrom [Sat, 22 Jun 2019 21:33:00 +0000 (22:33 +0100)]
egl: move eglGetSyncAttrib() fallback to eglapi.c
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Eric Engestrom [Sat, 22 Jun 2019 21:32:50 +0000 (22:32 +0100)]
egl: move eglSwapInterval() fallback to eglapi.c
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Eric Engestrom [Sat, 22 Jun 2019 21:32:26 +0000 (22:32 +0100)]
egl: move eglSurfaceAttrib() fallback to eglapi.c
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Eric Engestrom [Sat, 22 Jun 2019 21:31:53 +0000 (22:31 +0100)]
egl: move eglQuerySurface() fallback to eglapi.c
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Eric Engestrom [Sat, 22 Jun 2019 21:31:26 +0000 (22:31 +0100)]
egl: move eglQueryContext() fallback to eglapi.c
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Eric Engestrom [Sat, 22 Jun 2019 21:31:00 +0000 (22:31 +0100)]
egl: move eglGetConfigAttrib() fallback to eglapi.c
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Eric Engestrom [Sat, 22 Jun 2019 21:30:23 +0000 (22:30 +0100)]
egl: move eglChooseConfig() fallback to eglapi.c
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Eric Engestrom [Sat, 22 Jun 2019 21:29:46 +0000 (22:29 +0100)]
egl: move eglGetConfigs() fallback to eglapi.c
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Rob Clark [Mon, 24 Jun 2019 22:06:13 +0000 (15:06 -0700)]
freedreno/a5xx: fix batch leak in fd5 blitter path
Fixes:
3d198926a48 freedreno: use fd_bc_alloc_batch instead of fd_batch_create.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Marek Olšák [Wed, 19 Jun 2019 23:12:24 +0000 (19:12 -0400)]
radeonsi: don't set spi_ps_input_* for monolithic shaders
The driver doesn't use these values and ac_rtld has assertions
expecting the value of 0.
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Marek Olšák [Tue, 18 Jun 2019 23:06:57 +0000 (19:06 -0400)]
radeonsi: rename and re-document cache flush flags
SMEM and VMEM caches are L0 on gfx10.
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Marek Olšák [Fri, 24 May 2019 23:56:17 +0000 (19:56 -0400)]
radeonsi: fix AMD_DEBUG=nofmask
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Marek Olšák [Thu, 20 Jun 2019 02:24:51 +0000 (22:24 -0400)]
radeonsi: flatten the switch for DPBB tunables
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Marek Olšák [Wed, 19 Jun 2019 23:00:50 +0000 (19:00 -0400)]
radeonsi: set the calling convention for inlined function calls
otherwise the behavior is undefined
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Nicolai Hähnle [Fri, 21 Sep 2018 13:38:42 +0000 (15:38 +0200)]
radeonsi: refactor si_update_vgt_shader_config
We'll have to extend this at some point, and using a bitfield union in
this way makes it easier to get the right index without excessive
branching.
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Nicolai Hähnle [Sun, 16 Jun 2019 23:24:29 +0000 (01:24 +0200)]
amd/rtld: update the ELF representation of LDS symbols
The initial prototype used a processor-specific symbol type, but
feedback suggests that an approach using processor-specific section
name that encodes the alignment analogous to SHN_COMMON symbols is
preferred.
This patch keeps both variants around for now to reduce problems
with LLVM compatibility as we switch branches around.
This also cleans up the error reporting in this function.
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Marek Olšák [Thu, 20 Jun 2019 01:47:46 +0000 (21:47 -0400)]
ac/surface: remove addrlib_family_rev_id
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Dylan Baker [Mon, 24 Jun 2019 23:24:05 +0000 (16:24 -0700)]
docs: update calendar, add news item and link release notes for 19.0.7
Dylan Baker [Mon, 24 Jun 2019 23:21:34 +0000 (16:21 -0700)]
docs: Add SHA256 sums for 19.0.7
Dylan Baker [Mon, 24 Jun 2019 21:56:04 +0000 (14:56 -0700)]
Docs add 19.0.7 release notes
Ian Romanick [Thu, 20 Jun 2019 22:48:48 +0000 (15:48 -0700)]
glsl: Don't increase the iteration count when there are no terminators
Incrementing the iteration count was intended to fix an off-by-one error
when the first terminator was superseded by a later terminator. If
there is no first terminator or later terminator, there is no off-by-one
error. Incrementing the loop count creates one. This can be seen in
loops like:
do {
if (something) {
// No breaks or continues here.
}
} while (false);
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Tested-by: Abel Briggs <abelbriggs1@hotmail.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110953
Fixes:
646621c66da ("glsl: make loop unrolling more like the nir unrolling path")
Eric Anholt [Wed, 5 Jun 2019 22:15:07 +0000 (15:15 -0700)]
freedreno: Only upload the used part of UBO0 to the constant buffer.
We were pessimistically uploading all of it in case of indirection,
but we can just bump that when we encounter indirection.
total constlen in shared programs: 2529623 -> 2485933 (-1.73%)
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Reviewed-by: Rob Clark <robdclark@gmail.com>
Eric Anholt [Wed, 5 Jun 2019 17:34:52 +0000 (10:34 -0700)]
freedreno: Stop treating UBO 0 specially in UBO uploading.
ir3_nir_analyze_ubo_ranges() has already told us how much of cb0 we
need to upload (all of it, since it will lower indirect UBO 0 accesses
from load_ubo back to indirection on the constant buffer).
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Reviewed-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Sun, 23 Jun 2019 19:52:05 +0000 (12:52 -0700)]
freedreno: Clamp UBO uploads to the constlen decided by the shader.
If the NIR-level analysis decided to move UBO loads to the constant
file, but the backend decided not to load those constants, we could
upload past the end of constlen. This is particularly relevant for
pre-a6xx, where we emit a different constlen between bin and render
variants.
(Fix by Rob, commit message by anholt)
Reviewed-by: Eric Anholt <eric@anholt.net>
Alyssa Rosenzweig [Fri, 21 Jun 2019 19:44:56 +0000 (12:44 -0700)]
panfrost: Allow up to 16 UBOs
This is the hardware max, as far as I can tell.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Fri, 21 Jun 2019 18:56:28 +0000 (11:56 -0700)]
panfrost: DRY between shader stage setup
Just a little spring cleanup, extending UBOs to vertex shaders in the
process.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Thu, 20 Jun 2019 22:51:31 +0000 (15:51 -0700)]
panfrost/midgard: Implement UBO reads
UBOs and uniforms now use a common code path with an explicit `index`
argument passed, enabling UBO reads.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Thu, 20 Jun 2019 23:51:08 +0000 (16:51 -0700)]
panfrost: Handle disabled/empty UBOs
Prevents an assert(0) later in this (not so edge) case. We still have to
have a dummy there.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Thu, 20 Jun 2019 23:41:39 +0000 (16:41 -0700)]
panfrost: Identify "uniform buffer count" bits
We've known about this for a while, but it was never formally in the
machine header files / decoder, so let's add them in.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Thu, 20 Jun 2019 23:32:06 +0000 (16:32 -0700)]
panfrost: Upload UBOs
Now that all the counting is sorted, it's a matter of passing along a
GPU address and going.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Thu, 20 Jun 2019 23:21:48 +0000 (16:21 -0700)]
panfrost: Allow for dynamic UBO count
We already uploaded UBOs, but only a fixed number (1) for uniforms;
let's upload as many as we compute we need.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Thu, 20 Jun 2019 23:16:07 +0000 (16:16 -0700)]
panfrost: Report UBO count
We look at the highest set bit in the UBO enable mask to work out the
maximum indexable UBO, i.e. the UBO count as we need to report to the
hardware.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Thu, 20 Jun 2019 23:07:57 +0000 (16:07 -0700)]
panfrost: Constant buffer refactor
We refactor panfrost_constant_buffer to mirror v3d's constant buffer
handling, to enable UBOs as well as a single set of uniforms.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Mon, 24 Jun 2019 18:53:58 +0000 (11:53 -0700)]
panfrost: Replace varyings for point sprites
This doesn't handle Y-flipping, but it's good enough to render the stars
in Neverball.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Mon, 24 Jun 2019 18:01:05 +0000 (11:01 -0700)]
panfrost: Track point sprites in fragment shader key
In preparation for lowering point sprites, track them like we track
alpha testing state.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Caio Marcelo de Oliveira Filho [Sat, 22 Jun 2019 07:25:48 +0000 (00:25 -0700)]
i965: Move resources lowering after NIR linking
Those either depend on information filled by the NIR linking steps OR
are restricted by those:
- gl_nir_lower_samplers: depends on UniformStorage being set by the
linker.
- brw_nir_lower_image_load_store: After
6981069fc80 "i965: Ignore
uniform storage for samplers or images, use binding info" we want
this pass to happen after gl_nir_lower_samplers.
- gl_nir_lower_buffers: depends on UniformBlocks and
SharedStorageBlocks being set by the linker.
For the regular GLSL code path, those datastructures are filled
earlier. For NIR linking code path we need to generate the nir_shader
first then process it -- and currently the processing works with all
shaders together. So move the passes out of brw_create_nir into its
own function, called by the brwProgramStringNotify and
brw_link_shader().
This patch prepares ground for ARB_gl_spirv, that will make use of NIR
linker.
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Caio Marcelo de Oliveira Filho [Sat, 22 Jun 2019 00:11:54 +0000 (17:11 -0700)]
glsl/nir: Fix copying 64-bit values in uniform storage
The iterator `i` already walks the right amount now that is
incremented by `dmul`, so no need to `* 2`. Fixes invalid memory
access in upcoming ARB_gl_spirv tests.
Failure bisected by Arcady Goldmints-Orlov.
Fixes:
b019fe8a5b6 "glsl/nir: Fix handling of 64-bit values in uniform storage"
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Caio Marcelo de Oliveira Filho [Fri, 21 Jun 2019 23:55:08 +0000 (16:55 -0700)]
glsl/nir: Fix copying vector constant values
For n_columns == 1, we have a vector which is handled by the else
case. Fixes invalid memory access in upcoming ARB_gl_spirv tests.
Failure bisected by Arcady Goldmints-Orlov.
Fixes:
81e51b412e9 "nir: Make nir_constant a vector rather than a matrix"
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Daniel Schürmann [Fri, 25 Jan 2019 15:24:55 +0000 (16:24 +0100)]
amd/common: lower bitfield_extract to ubfe/ibfe.
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Daniel Schürmann [Fri, 25 Jan 2019 15:08:38 +0000 (16:08 +0100)]
amd/common: lower bitfield_insert to bfm & bitfield_select
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Daniel Schürmann [Thu, 13 Jun 2019 09:34:01 +0000 (11:34 +0200)]
nir: introduce lowering of bitfield_insert to bfm and a new opcode bitfield_select.
bitfield_select is defined as:
bitfield_select(mask, base, insert) = (mask & base) | (~mask & insert)
matching the behavior of AMD's BFI instruction.
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>