Rob Clark [Fri, 9 Dec 2016 18:12:51 +0000 (13:12 -0500)]
freedreno/a5xx: misc fix
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Fri, 9 Dec 2016 18:10:03 +0000 (13:10 -0500)]
freedreno/a5xx: fix (at least some) vtx formats
Swap/component-order doesn't seem to be quite what that is. At least
blob was always setting it to XYZW ('11') but we weren't. Causing
problems w/ formats like sint16.. Hard-coding this instead at least
seems to get glamor working.
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Thu, 8 Dec 2016 19:39:58 +0000 (14:39 -0500)]
freedreno/a5xx: more formats
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Wed, 7 Dec 2016 22:15:43 +0000 (17:15 -0500)]
freedreno/a5xx: fixup caps
Might not be 100% accurate, mostly just copy from a4xx to get started.
We are defn lying about occlusion query at this point (not implemented
yet) but need it to expose anything higher than gl1.4 (glamor needs
gl2.1)
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Wed, 7 Dec 2016 20:21:56 +0000 (15:21 -0500)]
freedreno/a5xx: fix random faults on first sysmem draw
Not sure what this event is, but blob writes it.. and it seems to solve
random write faults at mystery address that would sometimes happen on
first BYPASS draw.
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Wed, 7 Dec 2016 20:20:48 +0000 (15:20 -0500)]
freedreno: update generated headers
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Wed, 7 Dec 2016 15:17:17 +0000 (10:17 -0500)]
freedreno/a5xx: fix stride/size for mem->gmem blits
<brownpaperbag>these should be the in-GMEM dimensions</brownpaperbag>
Signed-off-by: Rob Clark <robdclark@gmail.com>
Dave Airlie [Wed, 30 Nov 2016 03:29:05 +0000 (03:29 +0000)]
radv/winsys: consolidate request->fence code
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Dave Airlie [Thu, 1 Dec 2016 00:44:45 +0000 (00:44 +0000)]
radv: handle fence allocation failing
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Bas Nieuwenhuizen [Fri, 16 Dec 2016 22:10:31 +0000 (23:10 +0100)]
radv: Don't bail out on pipeline create failure.
The spec says we have to try to create all, and only set failed
pipelines to VK_NULL_HANDLE. If one of them fails, we have to return
an error, but as far as I can see, the spec does not care which of
the suberrors.
Fixes
dEQP-VK.api.object_management.alloc_callback_fail_multiple.compute_pipeline
dEQP-VK.api.object_management.alloc_callback_fail_multiple.graphics_pipeline
Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Ilia Mirkin [Sun, 27 Nov 2016 21:09:55 +0000 (16:09 -0500)]
spirv/nir: add support for ImageGatherExtended
The strategy is to do the same thing that the GLSL lower_offset_arrays
pass does - create 4 separate texture gather ops, one per offset, and
read in the results from each gather's w component to recreate the
desired result.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Francisco Jerez [Thu, 15 Dec 2016 21:34:02 +0000 (13:34 -0800)]
anv: Fix uniform and storage buffer offset alignment limits.
This fixes a regression in a bunch of image store vulkan CTS tests
from commit
ad38ba113491869ab0dffed937f7b3dd50e8a735, which started
using OWORD block read messages to implement UBO loads. The reason
for the failure is that we were giving bogus buffer alignment limits
to the application (1B), so the CTS would happily come back with
descriptor sets pointing at not even word-aligned uniform buffer
addresses.
Surprisingly the sampler messages used to fetch pull constants before
that commit were able to cope with the non-texel aligned addresses,
but the dataport messages used to fetch pull constants after that
commit and the ones used to access storage buffers (before and after
the same commit) aren't as permissive with unaligned addresses.
Cc: <mesa-stable@lists.freedesktop.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=99097
Reported-by: Mark Janes <mark.a.janes@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Thomas Helland [Thu, 15 Dec 2016 22:36:54 +0000 (23:36 +0100)]
nir: Remove nir_array from lower_locals_to_regs
We do nothing but initialize it, add to it, and delete it.
This is a fallout from removing constant initializer support.
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Bruce Cherniak [Tue, 13 Dec 2016 01:24:59 +0000 (19:24 -0600)]
swr: Implement fence attached work queues for deferred deletion.
Work can now be added to fences and triggered by fence completion. This
allows for deferred resource deletion, and other asynchronous tasks.
Reviewed-by: George Kyriazis <george.kyriazis@intel.com>
Timothy Arceri [Thu, 15 Dec 2016 23:17:33 +0000 (10:17 +1100)]
nir: Turn imov/fmov of undef into undef
Reverting the previous attempt at this
a5502a721fd30fd resulted in
the following Vulkan test failing.
dEQP-VK.glsl.return.return_in_dynamic_loop_dynamic_vertex
This time we use the num_components from the alu dest rather than
num_inputs to the op to determine the size of the undef.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Cc: "13.0" <mesa-stable@lists.freedesktop.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=99100
Eric Engestrom [Thu, 8 Dec 2016 00:30:34 +0000 (00:30 +0000)]
egl/x11: cleanup init code
No functional change, just rewriting it in an easier-to-understand way.
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Iago Toral Quiroga [Wed, 14 Dec 2016 09:05:44 +0000 (10:05 +0100)]
nir/lower_tex: fix number of components in replace_gradient_with_lod()
We should make the dest in the textureLod() operation have the same number
of components as the destination in the original textureGrad()
Fixes regression in ES3-CTS.gtf.GL3Tests.shadow
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=99072
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Timothy Arceri [Thu, 15 Dec 2016 05:51:13 +0000 (16:51 +1100)]
Revert "nir: Turn imov/fmov of undef into undef."
This reverts commit
6aa730000fea84a14b49828a4bb30761d43903bf.
This was changing the size of the undef to always be 1 (the number of inputs
to imov and fmov) which is wrong, we could be moving a vec4 for example.
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Cc: "13.0" <mesa-stable@lists.freedesktop.org>
Kenneth Graunke [Wed, 14 Dec 2016 07:47:05 +0000 (23:47 -0800)]
i965/vec4: Fix TCS output reads with non-zero component qualifiers.
We want to perform the URB read to a vec4 temporary, with no writemask,
then issue a MOV to swizzle the data and store it to the actual
destination, using the final writemask.
We were doing this wrong. For example, let's say we wanted to read
a vec2 stored in components 2-3 of a vec4. We would generate a URB
read message of:
SEND <actual destination>.XY <header with mask set to XY>
MOV <actual destination>.XY <actual destination>.ZW
This doesn't work, because the URB message reads the .XY components
of the vec4, rather than the ZW. It writes to the right place, but
with the wrong data. Then the MOV comes along and overwrites it
with data that didn't even come from the URB at all.
Instead we want to do:
SEND <temporary> <header with mask set to ZW>
MOV <actual destination>.XY <temporary>.ZW
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Francisco Jerez [Fri, 9 Dec 2016 06:14:59 +0000 (22:14 -0800)]
i965/disasm: Decode dataport constant cache control fields.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Francisco Jerez [Wed, 22 Apr 2015 18:37:46 +0000 (21:37 +0300)]
i965/fs: Remove the FS_OPCODE_SET_SIMD4X2_OFFSET virtual opcode.
Not used anymore. It was just a scalar MOV.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Francisco Jerez [Fri, 9 Dec 2016 03:08:33 +0000 (19:08 -0800)]
i965/fs: Drop useless access mode override from pull constant generator code.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Francisco Jerez [Fri, 9 Dec 2016 03:18:00 +0000 (19:18 -0800)]
i965/fs: Fetch one cacheline of pull constants at a time.
Asking the DC for less than one cacheline (4 owords) of data for
uniform pull constants is suboptimal because the DC cannot request
less than that from L3, resulting in wasted bandwidth and unnecessary
message dispatch overhead, and exacerbating the IVB L3 serialization
bug. The following table summarizes the overall framerate improvement
(with statistical significance of 5% and sample size ~10) from the
whole series up to this patch for several benchmarks and hardware
generations:
| SKL | BDW | HSW
SynMark2 OglShMapPcf | 24.63% ±0.45% | 4.01% ±0.70% | 10.31% ±0.38%
GfxBench4 gl_manhattan31 | 5.93% ±0.35% | 3.92% ±0.31% | 6.62% ±0.22%
GfxBench4 gl_4 | 2.52% ±0.44% | 1.23% ±0.10% | N/A
Unigine Valley | 0.83% ±0.17% | 0.23% ±0.05% | 0.74% ±0.45%
Note that there are two versions of the Manhattan demo shipped with
GfxBench4, one of them is the original gl_manhattan demo which doesn't
use UBOs, so this patch will have no effect on it, and another one is
the gl_manhattan31 demo based on GL 4.3/GLES 3.1, which this patch
benefits as shown above.
I haven't observed any statistically significant regressions in the
benchmarks I have at hand. Note that the comparatively huge
improvement on SKL in the OglShMapPcf test case is due to the combined
effect of this patch and the register pressure benefit on SKL+ of
"i965/fs: Switch to the constant cache for uniform pull constants.",
part of the same series.
Going up to 8 oword blocks would improve performance of pull constants
even more, but at the cost of some additional bandwidth and register
pressure, so it would have to be done on-demand based on the number of
constants actually used by the shader.
v2: Fix for Gen4 and 5.
v3: Non-trivial rebase. Rework to allow the visitor specifiy
arbitrary pull constant block sizes.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Francisco Jerez [Fri, 9 Dec 2016 04:05:18 +0000 (20:05 -0800)]
i965/fs: Expose arbitrary pull constant load sizes to the IR.
Change the FS generator to ask the dataport for enough owords worth of
constants to fill the execution size of the instruction -- Which means
that the visitor now needs to set the execution size correctly for
uniform pull constant load instructions, which we were kind of
neglecting until now.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Francisco Jerez [Fri, 9 Dec 2016 03:58:25 +0000 (19:58 -0800)]
i965: Factor out oword block read and write message control calculation.
We'll need roughly the same logic in other places and it would be
annoying to duplicate it. Instead factor it out into a function-like
macro that takes the number of dwords per block (which will prove more
convenient than taking the same value in owords or some other unit).
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Francisco Jerez [Wed, 26 Oct 2016 21:25:06 +0000 (14:25 -0700)]
i965/fs: Switch to the constant cache for uniform pull constants.
This reverts to using the oword block read messages for uniform pull
constant loads, as used to be the case until
4c1fdae0a01b3f92ec03b61aac1d3df5. There are two important differences
though: Now the L3 cacheability bits are set up correctly for UBOs
(since
11f5d8a5d4fbb861ec161f68593e429cbd65d1cd), and we target the
constant cache instead of the data cache. The latter used to get no
L3 way allocation on boot on all platforms that existed at the time,
so oword read messages wouldn't get cached on L3 regardless of the
MOCS bits, what probably explains the apparent slowness of oword
fetches.
Constant cache loads seem to perform better than SIMD4x2 sampler loads
in a number of cases, they alleviate some of the cache thrashing
caused by the competition with textures for the L1/L2 sampler caches,
and they allow fetching up to 128B worth of constants with a single
oword fetch message.
Note that IVB devices suffer from a hardware bug that leads to
serialization of L3 read requests overlapping the same cacheline as
result of a (on IVB buggy) mechanism of the L3 to preserve coherency.
Since read requests for matching cachelines from any L3 client are not
pipelined, throughput may decrease in cases where there are no
non-overlapping requests left in the queue that can be processed
between them.
This situation should be relatively uncommon as long as we make sure
that we don't use the 1/2 oword messages in cases where the shader
intends to read from any other location of the same cacheline at some
other point. This is generally a good idea anyway on all generations
because using the 1 and 2 oword messages is expected to waste
bandwidth since the minimum L3 request size for the DC is exactly 4
owords (i.e. one cacheline). A future commit will have this effect.
I haven't been able to find any real-world example where this would
still result in a regression on IVB, but if someone happens to find
one it shouldn't be too difficult to add an IVB-specific check to have
it fall back to the sampler cache for pull constant loads.
Note that on SKL+ this change has the additional benefit of reducing
the register footprint of pull constant loads. The following table
summarizes the effect of the whole series on several shader-db stats:
Total instructions Total cycles
BWR: 4571248 -> 4568342 (-0.06%)
123375740 ->
123373296 (-0.00%)
ELK: 3989020 -> 3985402 (-0.09%)
98757068 ->
98754058 (-0.00%)
ILK: 6383591 -> 6376787 (-0.11%)
143649910 ->
143648914 (-0.00%)
SNB: 7528395 -> 7501446 (-0.36%)
103503796 ->
102460370 (-1.01%)
IVB: 6949221 -> 6943317 (-0.08%)
60592262 ->
60584422 (-0.01%)
HSW: 6409753 -> 6403702 (-0.09%)
60609070 ->
60604414 (-0.01%)
BDW: 8043467 -> 7976364 (-0.83%)
68427730 ->
68483042 (0.08%)
CHV: 8045019 -> 7977916 (-0.83%)
68297426 ->
68352756 (0.08%)
SKL: 8204037 -> 7939086 (-3.23%)
66583900 ->
65624378 (-1.44%)
Lost->Gained Total spills Total fills
BWR: 5 -> 5 1488 -> 1488 (0.00%) 1957 -> 1957 (0.00%)
ELK: 5 -> 5 1489 -> 1489 (0.00%) 1958 -> 1958 (0.00%)
ILK: 1 -> 4 1449 -> 1449 (0.00%) 1921 -> 1921 (0.00%)
SNB: 0 -> 0 549 -> 549 (0.00%) 52 -> 52 (0.00%)
IVB: 13 -> 3 1271 -> 1271 (0.00%) 1162 -> 1162 (0.00%)
HSW: 11 -> 0 1271 -> 1271 (0.00%) 1162 -> 1162 (0.00%)
BDW: 12 -> 0 1340 -> 1340 (0.00%) 1452 -> 1452 (0.00%)
CHV: 12 -> 0 1340 -> 1340 (0.00%) 1452 -> 1452 (0.00%)
SKL: 0 -> 120 1269 -> 375 (-70.45%) 1563 -> 690 (-55.85%)
v3: Non-trivial rebase.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Francisco Jerez [Thu, 23 Apr 2015 11:36:16 +0000 (14:36 +0300)]
i965: Let the caller of brw_set_dp_write/read_message control the target cache.
brw_set_dp_read_message already had a target_cache argument, but its
interpretation was rather convoluted (on Gen6 the render cache was
used if the caller asked for it, otherwise it was ignored using the
sampler cache instead), and the constant cache wasn't representable at
all. brw_set_dp_write_message used the data cache on Gen7+ except for
RENDER_TARGET_WRITE messages, in which case it would use the render
cache. On Gen6 the render cache was always used.
Instead of the above, provide the shared unit SFID that the caller
expects will be used. Makes no functional changes.
v3: Non-trivial rebase.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Francisco Jerez [Fri, 9 Dec 2016 02:00:17 +0000 (18:00 -0800)]
i965/gen6+: Invalidate constant cache on brw_emit_mi_flush().
In order to make sure that the constant cache is coherent with
previous rendering when we start using it for pull constant loads.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Kenneth Graunke [Mon, 21 Nov 2016 08:11:57 +0000 (00:11 -0800)]
genxml: Make Gen8 3DSTATE_DS SIMD8 enable work like Gen9+.
This will let us avoid ifdefs.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Kenneth Graunke [Mon, 21 Nov 2016 08:09:11 +0000 (00:09 -0800)]
genxml: Rename "DS Function Enable" to "Function Enable".
This makes Gen7/7.5 match Gen8-9.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Chad Versace [Thu, 17 Nov 2016 20:45:26 +0000 (12:45 -0800)]
anv: Reject VkMemoryAllocateInfo::allocationSize == 0
The Vulkan 1.0.33 spec says "allocationSize must be greater than 0".
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Chad Versace [Tue, 13 Dec 2016 22:23:55 +0000 (14:23 -0800)]
egl: Fix crashes in eglCreate*Surface()
Don't dereference a null EGLDisplay.
Fixes tests
dEQP-EGL.functional.negative_api.create_pbuffer_surface
dEQP-EGL.functional.negative_api.create_pixmap_surface
Reviewed-by: Mark Janes <mark.a.janes@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=99038
Cc: "13.0" <mesa-stable@lists.freedesktop.org>
Jason Ekstrand [Tue, 6 Dec 2016 20:03:28 +0000 (12:03 -0800)]
i965/miptree: Use intel_miptree_copy for maps
What we're really doing is copying a texture not blitting it in the sense
of glBlitFramebuffers. Also, the intel_miptree_copy function is capable of
properly handling compressed textures which intel_miptree_blit is not.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=97473
Cc: "13.0" <mesa-stable@lists.freedesktop.org>
Jason Ekstrand [Tue, 6 Dec 2016 20:03:11 +0000 (12:03 -0800)]
i965/blit: Fix the src dimension sanity check in miptree_copy
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Cc: "13.0" <mesa-stable@lists.freedesktop.org>
Lionel Landwerlin [Thu, 8 Dec 2016 12:26:38 +0000 (12:26 +0000)]
docs: add INTEL_conservative_rasterization to relaese notes for 13.1.0
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Lionel Landwerlin [Thu, 8 Dec 2016 12:11:43 +0000 (12:11 +0000)]
main: add INTEL_conservative_rasterization enum query support
v2: add extra parameter (Ilia)
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Lionel Landwerlin [Fri, 9 Dec 2016 16:51:38 +0000 (16:51 +0000)]
glapi: add missing INTEL_conservative_rasterization
v2: put enum directly in gl_API.xml (Ilia)
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Lionel Landwerlin [Thu, 8 Dec 2016 11:00:01 +0000 (11:00 +0000)]
extensions: update INTEL_conservative_rasterization dependencies
Suggested by Ilia.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Lionel Landwerlin [Thu, 8 Dec 2016 11:00:00 +0000 (11:00 +0000)]
main: don't error when enabling conservative rasterization on gles
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Lionel Landwerlin [Mon, 12 Dec 2016 12:30:26 +0000 (12:30 +0000)]
main: use new driver flag for conservative rasterization state
Suggested by Marek.
v2: Use new driver flag (Marek)
v3: Fix i965 comments (Lionel)
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Iago Toral Quiroga [Mon, 12 Dec 2016 12:43:53 +0000 (13:43 +0100)]
nir/lower_tex: lower gradients on shadow cube maps if lower_txd_shadow is set
Even if lower_txd_cube_map isn't. Suggested by Ken to make the flag more
consistent with its name.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Iago Toral Quiroga [Wed, 30 Nov 2016 10:45:59 +0000 (11:45 +0100)]
i965: remove brw_lower_texture_gradients
This has been ported to NIR now so we don'tneed to keep the GLSL IR
lowering any more.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Iago Toral Quiroga [Tue, 13 Dec 2016 09:24:19 +0000 (10:24 +0100)]
i965/nir: enable lowering of texture gradient for shadow samplers
This gets the lowering on the Vulkan driver too, which is required for
hardware that does not have the sample_l_d message (up to IvyBridge).
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Iago Toral Quiroga [Wed, 30 Nov 2016 10:31:01 +0000 (11:31 +0100)]
nir/lower_tex: add lowering for texture gradient on shadow samplers
This is ported from the Intel lowering pass that we use with GLSL IR.
This takes care of lowering texture gradients on shadow samplers other
than cube maps. Intel hardware requires this for gen < 8.
v2 (Ken):
- Use the helper function to retrieve ddx/ddy
- Swizzle away size components we are not interested in
v3:
- Get rid of the ddx/ddy helper and use nir_tex_instr_src_index
instead (Ken, Eric)
v4:
- Add a 'continue' statement if the lowering makes progress because it
replaces the original texture instruction
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> (v3)
Iago Toral Quiroga [Wed, 30 Nov 2016 08:44:20 +0000 (09:44 +0100)]
i965/nir: enable lowering of texture gradient for cube maps
This gets the lowering on the Vulkan driver too.
Fixes Vulkan CTS cube map texture gradient tests in:
dEQP-VK.glsl.texture_functions.texturegrad.*
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Iago Toral Quiroga [Wed, 30 Nov 2016 08:40:43 +0000 (09:40 +0100)]
nir/lower_tex: add lowering for texture gradient on cube maps
This is ported from the Intel lowering pass that we use with GLSL IR.
The NIR pass only handles cube maps, not shadow samplers, which are
also lowered for gen < 8 on Intel hardware. We will add support for
that in a later patch, at which point we should be able to remove
the GLSL IR lowering pass.
v2:
- added a helper to retrieve ddx/ddy parameters (Ken)
- No need to make size.z=1.0, we are only using component x anyway (Iago)
v3:
- Get rid of the ddx/ddy helper and use nir_tex_instr_src_index
instead (Ken, Eric)
v4:
- When emitting the textureLod operation, copy all texture parameters
from the original textureGrad() (except for ddx/ddy) using a loop
- Add a 'continue' statement if the lowering makes progress because it
replaces the original texture instruction
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> (v3)
Iago Toral Quiroga [Wed, 30 Nov 2016 11:42:54 +0000 (12:42 +0100)]
nir/lower_tex: generalize get_texture_size()
This was written specifically for RECT samplers. Make it more generic so
we can call this from the gradient lowerings too.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Ilia Mirkin [Mon, 12 Dec 2016 13:32:38 +0000 (08:32 -0500)]
treewide: s/comparitor/comparator/
git grep -l comparitor | xargs sed -i 's/comparitor/comparator/g'
Just happened to notice this in a patch that was sent and included one
of the tokens in question.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Acked-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Ian Romanick [Mon, 5 Dec 2016 19:51:54 +0000 (11:51 -0800)]
nir: Only float and double types can be matrices
In 19a541f (nir: Get rid of nir_constant_data) a number of places that
operated on nir_constant::values were mechanically converted to operate
on the whole array without regard for the base type. Only
GLSL_TYPE_FLOAT and GLSL_TYPE_DOUBLE can be matrices, so only those
types can have data in the non-0 array element.
See also b870394.
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Cc: Iago Toral Quiroga <itoral@igalia.com>
Tim Rowley [Mon, 12 Dec 2016 18:50:18 +0000 (12:50 -0600)]
swr: [rasterizer core/memory] StoreTile: AVX512 progress
Fixes to 128-bit formats.
Reviwed-by: Bruce Cherniak <bruce.cherniak@intel.com>
Matt Turner [Wed, 30 Nov 2016 01:33:30 +0000 (17:33 -0800)]
nir: Move fsat outside of fmin/fmax if second arg is 0 to 1.
instructions in affected programs: 550 -> 544 (-1.09%)
helped: 6
cycles in affected programs: 6952 -> 6850 (-1.47%)
helped: 6
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Matt Turner [Mon, 28 Nov 2016 23:21:51 +0000 (15:21 -0800)]
i965/fs: Reject copy propagation into SEL if not min/max.
We shouldn't ever see a SEL with conditional mod other than GE (for max)
or L (for min), but we might see one with predication and no conditional
mod.
total instructions in shared programs: 8241806 -> 8241902 (0.00%)
instructions in affected programs: 13284 -> 13380 (0.72%)
HURT: 62
total cycles in shared programs:
84165104 ->
84166244 (0.00%)
cycles in affected programs: 75364 -> 76504 (1.51%)
helped: 10
HURT: 34
Fixes generated code in at least Sanctum 2, Borderlands 2, Goat
Simulator, XCOM: Enemy Unknown, and Shogun 2.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92234
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Matt Turner [Mon, 28 Nov 2016 18:48:53 +0000 (10:48 -0800)]
i965/fs: Add unit tests for copy propagation pass.
Pretty basic, but it's a start.
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Matt Turner [Mon, 28 Nov 2016 18:45:08 +0000 (10:45 -0800)]
i965/fs: Rename opt_copy_propagate -> opt_copy_propagation.
Matches the vec4 backend, cmod propagation, and saturate propagation.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Nicolai Hähnle [Wed, 30 Nov 2016 11:26:49 +0000 (12:26 +0100)]
radeonsi: shrink the GSVS ring to account for the reduced item sizes
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Wed, 30 Nov 2016 11:25:45 +0000 (12:25 +0100)]
radeonsi: shrink each vertex stream to the actually required size
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Tue, 29 Nov 2016 16:41:59 +0000 (17:41 +0100)]
radeonsi: use a single descriptor for the GSVS ring
We can hardcode all of the fields for swizzling in the geometry shader.
The advantage is that we use fewer descriptor slots and we no longer have to
update any of the (ring) descriptors when the geometry shader changes.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Wed, 30 Nov 2016 10:33:25 +0000 (11:33 +0100)]
radeonsi: pack GS output components for each vertex stream contiguously
Note that the memory layout of one vertex stream inside one "item" (= memory
written by one GS wave) on the GSVS ring is:
t0v0c0 ... t15v0c0 t0v1c0 ... t15v1c0 ... t0vLc0 ... t15vLc0
t0v0c1 ... t15v0c1 t0v1c1 ... t15v1c1 ... t0vLc1 ... t15vLc1
...
t0v0cL ... t15v0cL t0v1cL ... t15v1cL ... t0vLcL ... t15vLcL
t16v0c0 ... t31v0c0 t16v1c0 ... t31v1c0 ... t16vLc0 ... t31vLc0
t16v0c1 ... t31v0c1 t16v1c1 ... t31v1c1 ... t16vLc1 ... t31vLc1
...
t16v0cL ... t31v0cL t16v1cL ... t31v1cL ... t16vLcL ... t31vLcL
...
t48v0c0 ... t63v0c0 t48v1c0 ... t63v1c0 ... t48vLc0 ... t63vLc0
t48v0c1 ... t63v0c1 t48v1c1 ... t63v1c1 ... t48vLc1 ... t63vLc1
...
t48v0cL ... t63v0cL t48v1cL ... t63v1cL ... t48vLcL ... t63vLcL
where tNN indicates the thread number, vNN the vertex number (in the order of
EMIT_VERTEX), and cNN the output component (vL and cL are the last vertex and
component, respectively).
The vertex streams are laid out sequentially.
The swizzling by 16 threads is hard-coded in the way the VGT generates the
offset passed into the GS copy shader, and the jump every 16 threads is
calculated from VGT_GSVS_RING_OFFSET_n and VGT_GSVS_RING_ITEMSIZE in a way
that makes it difficult to deviate from this layout (at least that's what
I've experimentally confirmed on VI after first trying to go the simpler
route of just interleaving the vertex streams).
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Fri, 2 Dec 2016 20:20:49 +0000 (21:20 +0100)]
radeonsi: do not write non-existent components through the GSVS ring
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Tue, 29 Nov 2016 15:27:10 +0000 (16:27 +0100)]
radeonsi: only write values belonging to the stream when emitting GS vertex
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Tue, 29 Nov 2016 15:25:21 +0000 (16:25 +0100)]
radeonsi: generate an explicit switch instruction over vertex streams
SimplifyCFG generates a switch instruction anyway when all four streams
are present, but is simultaneously not smart enough to eliminate some
redundant jumps that it generates.
The generated assembly is still a bit silly, probably because the
control flow annotation doesn't know how to handle a switch with uniform
condition.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Tue, 29 Nov 2016 15:03:56 +0000 (16:03 +0100)]
radeonsi: fetch only outputs of current vertex stream from the GSVS ring
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Tue, 29 Nov 2016 14:55:00 +0000 (15:55 +0100)]
radeonsi: only export from GS copy shader for vertex stream 0
When running the copy shader for vertex streams != 0, the SX does not need
any data from us (there is no rasterization for the higher vertex streams,
only streamout).
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Tue, 29 Nov 2016 14:53:19 +0000 (15:53 +0100)]
radeonsi: do not export VS outputs from vertex streams != 0
This affects for GS copy shaders. When an output is meant for vertex
stream != 0, then we don't have to make it available to the pixel
shader.
There is a minor inefficiency here because the GLSL varying packing pass
does not group varyings of the same vertex stream together, but it
shouldn't be important in practice.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Tue, 29 Nov 2016 13:23:05 +0000 (14:23 +0100)]
radeonsi: pull iteration over vertex streams into GS copy shader logic
The iteration is not needed for normal vertex shaders.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Tue, 29 Nov 2016 14:36:08 +0000 (15:36 +0100)]
radeonsi: group streamout writes by vertex stream
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Tue, 29 Nov 2016 14:09:14 +0000 (15:09 +0100)]
radeonsi: load the streamout buf descriptors closer to their use
LLVM can still decide to hoist the loads since they're marked invariant.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Tue, 29 Nov 2016 12:23:21 +0000 (13:23 +0100)]
radeonsi: extract writing of a single streamout output
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Tue, 29 Nov 2016 11:59:48 +0000 (12:59 +0100)]
radeonsi: separate the call to si_llvm_emit_streamout from exports
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Tue, 29 Nov 2016 14:43:44 +0000 (15:43 +0100)]
radeonsi: plumb the output vertex_stream through to si_shader_output_values
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Tue, 29 Nov 2016 11:55:19 +0000 (12:55 +0100)]
radeonsi: rename members of si_shader_output_values
Be a bit more verbose and avoid confusion in future patches.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Tue, 6 Dec 2016 20:03:03 +0000 (21:03 +0100)]
radeonsi: fix an off-by-one error in the bounds check for max_vertices
The spec actually says that calling EmitStreamVertex is undefined when
you exceed max_vertices. But we do need to avoid trampling over memory
outside the GSVS ring.
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Tue, 29 Nov 2016 15:33:31 +0000 (16:33 +0100)]
radeonsi: do not kill GS with memory writes
Vertex emits beyond the specified maximum number of vertices are supposed to
have no effect, which is why we used to always kill GS that reached the limit.
However, if the GS also writes to memory (SSBO, atomics, shader images), then
we must keep going and only skip the vertex emit itself.
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Mon, 28 Nov 2016 19:30:41 +0000 (20:30 +0100)]
radeonsi: update all GSVS ring descriptors for new buffer allocations
Fixes GL45-CTS.gtf40.GL3Tests.transform_feedback3.transform_feedback3_geometry_instanced.
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Tue, 29 Nov 2016 11:38:48 +0000 (12:38 +0100)]
st/glsl_to_tgsi: plumb the GS output stream qualifier through to TGSI
Allow drivers to emit GS outputs in a smarter way.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Fri, 2 Dec 2016 20:20:16 +0000 (21:20 +0100)]
tgsi/scan: collect information about output usagemasks
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Tue, 29 Nov 2016 13:22:20 +0000 (14:22 +0100)]
tgsi/scan: collect information about output vertex streams
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Tue, 29 Nov 2016 13:21:55 +0000 (14:21 +0100)]
gallium: extract individual streamout output structure
So that we can pass pointers to individual array entries around.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Wed, 7 Dec 2016 10:27:25 +0000 (11:27 +0100)]
tgsi: add Stream{X,Y,Z,W} fields to tgsi_declaration_semantic
This is for geometry shader outputs. Without it, drivers have no way of
knowing which stream each output is intended for, and have to
conservatively write all outputs to all streams.
Separate stream numbers for each component are required due to output
packing.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Wed, 30 Nov 2016 09:38:55 +0000 (10:38 +0100)]
glsl: remember per-component vertex streams for packed varyings
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Grazvydas Ignotas [Sun, 11 Dec 2016 19:57:44 +0000 (21:57 +0200)]
i965/blorp: fix release build unused variable warning
Signed-off-by: Grazvydas Ignotas <notasas@gmail.com>
Reviewed-by: Eduardo Lima Mitev <elima@igalia.com>
Edward O'Callaghan [Mon, 5 Dec 2016 23:43:17 +0000 (10:43 +1100)]
virgl: Fix a strict-aliasing violation in the encoder
As per the C spec, it is illegal to alias pointers to different
types. This results in undefined behaviour after optimization
passes, resulting in very subtle bugs that happen only on a
full moon..
Use a memcpy() as a well defined coercion between the double
to uint64_t interpretations of the memory.
V.2: Use static_assert() instead of assert().
V.3: Use C99 compat STATIC_ASSERT() over C11 static_assert().
Signed-off-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Acked-by: Dave Airlie <airlied@redhat.com>
Kenneth Graunke [Sun, 11 Dec 2016 06:13:05 +0000 (22:13 -0800)]
i965: Print out cycle estimates at the start of block annotations.
We now print
START B15 <-B14 (42774 cycles)
indicating that we estimate B15 will take 42,774 cycles. Printing
this should make it easier where time is spent in the program.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Kenneth Graunke [Sat, 10 Dec 2016 00:16:53 +0000 (16:16 -0800)]
mesa: Return LINEAR encoding for winsys FBO depth/stencil.
GetFramebufferAttachmentParameteriv should return GL_LINEAR for the
window system default framebuffer's GL_DEPTH or GL_STENCIL attachments
when there are zero depth or stencil bits.
The GL 4.5 spec's GetFramebufferAttachmentParameteriv section says:
"If the value of FRAMEBUFFER_ATTACHMENT_OBJECT_TYPE is not NONE,
these queries apply to all other framebuffer types:
[...]
If attachment is not a color attachment, or no data storage or texture
image has been specified for the attachment, then params will contain
the value LINEAR."
Note that we already return LINEAR for the case where there is an actual
depth or stencil renderbuffer attached. In the case modified by this
patch, FRAMEBUFFER_ATTACHMENT_OBJECT_TYPE returns FRAMEBUFFER_DEFAULT
rather than NONE.
Fixes a CTS test when run in a visual without depth / stencil buffers:
GL45-CTS.gtf30.GL3Tests.framebuffer_srgb.framebuffer_srgb_default_encoding
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Grazvydas Ignotas [Sat, 10 Dec 2016 19:10:46 +0000 (21:10 +0200)]
intel/aubinator: fix 32bit shift overflow warning
Doesn't look like this can work on 32bit, just rids of annoying
warning.
Signed-off-by: Grazvydas Ignotas <notasas@gmail.com>
Reviewed-by: Eduardo Lima Mitev <elima@igalia.com>
Grazvydas Ignotas [Sat, 10 Dec 2016 19:10:48 +0000 (21:10 +0200)]
anv: fix release build unused variable warnings
Signed-off-by: Grazvydas Ignotas <notasas@gmail.com>
Reviewed-by: Eduardo Lima Mitev <elima@igalia.com>
Grazvydas Ignotas [Sat, 10 Dec 2016 19:10:05 +0000 (21:10 +0200)]
radv/ac: some fix maybe-uninitialized warnings
Mark some paths unreachable so that compiler knows variables are
initialized in all valid paths.
Signed-off-by: Grazvydas Ignotas <notasas@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Grazvydas Ignotas [Sat, 10 Dec 2016 19:10:04 +0000 (21:10 +0200)]
radv/meta: use VK_NULL_HANDLE for handles
Otherwise we get 32bit warnings because handle is plain uint64_t there
and NULL is not suited to initialize that.
Signed-off-by: Grazvydas Ignotas <notasas@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Grazvydas Ignotas [Sat, 10 Dec 2016 19:10:03 +0000 (21:10 +0200)]
radv: fix release build unused variable warnings
Just mark with MAYBE_UNUSED.
Signed-off-by: Grazvydas Ignotas <notasas@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Grazvydas Ignotas [Sat, 10 Dec 2016 19:10:47 +0000 (21:10 +0200)]
softpipe: fix release build unused variable warning
Signed-off-by: Grazvydas Ignotas <notasas@gmail.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Grazvydas Ignotas [Sat, 10 Dec 2016 19:10:45 +0000 (21:10 +0200)]
radeonsi: fix release build unused variable warnings
Signed-off-by: Grazvydas Ignotas <notasas@gmail.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Chad Versace [Sat, 10 Dec 2016 00:22:52 +0000 (16:22 -0800)]
i965/mt: Disable HiZ when sharing depth buffer externally (v2)
intel_miptree_make_shareable() discarded and disabled CCS. Fix it so
that it discards and disables HiZ too.
Fixes dEQP-EGL.functional.image.render_multiple_contexts.gles2_renderbuffer_depth16_depth_buffer
on Skylake.
v2: Actually do what the commit message says. Discard the HiZ buffer.
Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=98329
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Cc: Nanley Chery <nanley.g.chery@intel.com
Cc: Haixia Shi <hshi@chromium.org>
Cc: mesa-stable@lists.freedesktop.org
Chad Versace [Sat, 10 Dec 2016 00:18:11 +0000 (16:18 -0800)]
i965/mt: Disable aux surfaces after making miptree shareable
The entire goal of intel_miptree_make_shareable() is to permanently
disable the miptree's aux surfaces. So set
intel_mipmap_tree:disable_aux_buffers after the function's done with
discarding down the aux surfaces.
References: https://bugs.freedesktop.org/show_bug.cgi?id=98329
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Cc: Nanley Chery <nanley.g.chery@intel.com
Cc: Haixia Shi <hshi@chromium.org>
Cc: mesa-stable@lists.freedesktop.org
Jason Ekstrand [Fri, 9 Dec 2016 17:34:50 +0000 (09:34 -0800)]
spirv: Use a simpler and more correct implementaiton of tanh()
The new implementation is more correct because it clamps the incoming value
to 10 to avoid floating-point overflow. It also uses a much reduced
version of the formula which only requires 1 exp() rather than 2. This
fixes all of the dEQP-VK.glsl.builtin.precision.tanh.* tests.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Cc: "13.0" <mesa-dev@lists.freedesktop.org>
Jason Ekstrand [Fri, 9 Dec 2016 17:33:05 +0000 (09:33 -0800)]
glsl: Use a simpler formula for tanh
The formula we have used in the past is a trivial reduction from the
definition by simply multiplying both the numerator and denominator of the
formula by 2. However, multiplying by e^x, you can further reduce it.
This allows us to get rid of one side of the clamp and two of exponential
functions which should make it faster. The new formula still passes the
dEQP precision tests for tanh so it should be fine.
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Edward O'Callaghan [Fri, 9 Dec 2016 14:40:40 +0000 (01:40 +1100)]
anv: Clean up some unused variables
Following on from the spirit of commit
011e5570f.
Signed-off-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Tim Rowley [Wed, 7 Dec 2016 23:04:20 +0000 (17:04 -0600)]
swr: [rasterizer common/core/jitter] fetch support for GL_FIXED
v2: use fmul(1/65536) instead of fdiv(65535)
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
Emil Velikov [Mon, 5 Dec 2016 19:02:29 +0000 (19:02 +0000)]
configure: cleanup GLX_USE_TLS handling
Mesa requires ax_pthread_ok = yes, thus we can fold/rewrite the
conditional to follow the more common "if test" pattern.
No functional change intended.
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Emil Velikov [Mon, 5 Dec 2016 19:02:28 +0000 (19:02 +0000)]
configure: enable glx-tls by default
In the (not too) distant future we'd want to remove this option and
effectively drop the other codepath(s) we have in our dispatch.
Linux distributions have been using --enable-glx-tls for a number of
years. Some/most BSD platforms still don't support this, yet this should
serve as an encouragement to move things forwards.
Note: we had many bug reports were opened due to the wrong default
option. See the list below for details.
v2:
- Correct default option in help string (Andreas)
- Add bugzilla references.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=70623
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=72902
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=73778
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89043
Cc: Jean-Sébastien Pédron <dumbbell@FreeBSD.org>
Cc: Jonathan Gray <jsg@jsg.id.au>
Cc: mesa-maintainers@lists.freedesktop.org
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Andreas Boll <andreas.boll.dev@gmail.com>
Emil Velikov [Mon, 5 Dec 2016 16:11:21 +0000 (16:11 +0000)]
docs: document how to (self-) reject stable patches
Document what has been the unofficial way to self-reject stable patches.
Namely: drop the mesa-stable tag and push the commit.
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>