radv/gfx11: don't create fmask copy/expand pipelines

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19375>

ac/nir: lower gfx11 vertex parameter exports

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19228>

aco: don't split swizzled store_buffer_amd on GFX9+

This isn't necessary.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19228>

nir,ac/nir,aco,radv: replace has_input_*_amd with more general intrinsics

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19228>

radv: do not unconditionally disable NGG streamout lowering in NIR

This is still always disabled because use_ngg_streamout is FALSE
but it will be turned on at some point.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19317>

radv: lower NIR intrinsics for NGG streamout

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19317>

radv: call nir_io_add_intrinsic_xfb_info() after IO lowering

This is needed for NGG streamout which gets the XFB info directly
from intrinsics.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19317>

radv/llvm: prevent emitting streamout outputs for NGG

They are directly emitted from NIR.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19317>

aco: remove invalid assertions for NGG streamout

Streamout outputs are directly emitted from NIR now.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19317>

aco: implement NIR intrinsics for NGG streamout

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19317>

aco: create a new builder variant for ds_add_rtn

This instruction can use 1 definition and 3 operands.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19317>

radv: Handle attribute ring intrinsic correctly with LLVM.

Again, if we don't set progress to false we get fun stuff.

Fixes: 8bf1aa1b76b ("radv: add lowering for nir_intrinsic_load_ring_attr_{offset}_amd")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19404>

radv: Handle GSVS ring intrinsic correctly with LLVM.

If we don't set progress to false we get a mess as a replacement is
still attempted.

Fixes: 382831c9865 ("radv,nir: add intrinsics for streamout and GS copy shaders")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19404>

radv: Use correct types for loading the rings with LLVM.

Ring descriptors are v4i32, not i8.

Fixes: cb117cdc96c ("radv/llvm: use ac_build_gep0_type to get args types")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19404>

panfrost: Enable Mali-T620

Support of this GPU is now good enough to enable it

Signed-off-by: Anton Bambura <jenneron@protonmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19408>

r600: Print MOVA_INT dest on Cayman

On Cayman the index registers can be written too, so print it.

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19397>

r600: Only count ALU registers that are not clause local

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19397>

r600: declare for counter locally and fix signed/unsigned warning

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19397>

Revert "radv: add a pointer to radv_shader_binary in radv_shader"

This is actually not necessary because we compile and upload binaries
directly from libraries with GPL. This introduced random double free
crashes because binaries were potentially freed by concurrent threads.

Root cause found by Ishi.

This reverts commit f8d887527aab641bd291f08850755197b6c2c1d7.

Reviewed-by: Tatsuyuki Ishi <ishitatsuyuki@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19383>

winsys/amdgpu: clamp up the alignment if zero

Zero alignment buffers is a valid alignment and is
used for the cases when there is no special alignment
enforced due to hardware requirement.

Clamp up the buffer alignment of such buffers to
gart_page_size. Screenshot app uses such buffers
with zero alignment which is returned NULL by winsys
and failed and hence failed to capture.

Signed-off-by: Sunil Khatri <sunil.khatri@amd.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19314>

freedreno/fdl: Increase alignment for UBWC images

From empirical tests (on a660) R8G8 with UBWC enabled requires 256b
alignment, otherwise there would be a GPU fault during blits.

Set alignment to 4096 for all UBWC images since that's what blob does
and this area is heavily undertested.

Fixes GPU fault in Borderlands 3 running through DXVK.

cc: mesa-stable

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19298>

pvr: setup buffer and image format feature bits

Note, this also fixes a case where image usage and format feature flags were
being mixed. This was noticed as part of the conversion to format feature 2
flags.

Signed-off-by: Frank Binns <frank.binns@imgtec.com>
Reviewed-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19372>

aco: Use opsel for the third operand.

Foz-DB Navi21:
Totals from 2 (0.00% of 134913) affected shaders:
CodeSize: 7788 -> 7772 (-0.21%)
Instrs: 1305 -> 1303 (-0.15%)
Latency: 7175 -> 7163 (-0.17%)
InvThroughput: 2082 -> 2078 (-0.19%)
Copies: 57 -> 55 (-3.51%)

Signed-off-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19380>

radv: implement transform feedback queries with NGG streamout

The control bit is written to the upper bits because GDS counters
are 32-bits only, this allows to re-use the existing query shader.

Tested on GFX10.3.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19325>

hasvk: remove some unused functions

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19368>

anv: remove some unused functions

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19368>

radv: Speculatively tune RT pipelines for GFX11.

With ACO not supporting VOPD and the high number of SALU instructions,
we're likely better off using wave64 until we can actually benchmark
this and fix these issues.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19288>

anv: remove shader fp64 inspection after parsing

Unfortunately some crucible tests are using all floating point widths
in a single shader and specializing a variable to select what code
path to use for a particular supported floating point width. This is
reporting errors in the validation layers.

Remove the validation for now.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes 8c4c4c3ee1a2 ("anv: Add softtp64 workaround")

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Reviewed-by: Mykhailo Skorokhodov <mykhailo.skorokhodov@globallogic.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19401>

nouveau: enable PIPE_CAP_UMA when appropriate

Signed-off-by: Yusuf Khan <yusisamerican@gmail.com>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18172>

radv: Use PLOC for BVH building

Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19292>

radv: Add PLOC shader

Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19292>

radv: Add REF as a typename macro to .clang-format

Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19292>

radv: Add global sync utilities

Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19292>

radv/rt: Track number of inactive leaf nodes

To avoid emitting nodes with only invalid children in PLOC.

Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19292>

radv/rt: Dispatch internal converter indirectly

Preparation for using the converter with PLOC.

Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19292>

radv/rt: Fix internal converter synchronization

Fixes: e83e4faf ("radv: Only emit parents from parents that actually end up in the tree.")
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19292>

radv: Add radv_indirect_unaligned_dispatch

Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19292>

radv: Use a struct for AABBs

Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19292>

radv: Make the number of internal nodes be written on the GPU.

Opens the door of algorithms with a variable number of nodes.

Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19292>

radv: Add BVH IR header.

To include GPU state passed between stages but not in a node.

Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19292>

radv: Rename emulated float helpers

Use only conversion functions now.

Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19292>

util: glsl2spirv.py: ensure '#endif' is printed in new line

Fixes the following building errors:

In file included from ../src/intel/vulkan/anv_pipeline_cache.c:34:
src/intel/vulkan/float64_spv.h:3316:3: error: expected identifier or '('
};#endif // FLOAT64_SPV_H
  ^
src/intel/vulkan/float64_spv.h:1:2: error: unterminated conditional directive
 ^
../src/intel/vulkan/anv_pipeline_cache.c:59:17: error: use of undeclared identifier 'anv_shader_bin_serialize'; did you mean 'anv_shader_bin_deserialize'?
   .serialize = anv_shader_bin_serialize,
                ^~~~~~~~~~~~~~~~~~~~~~~~
                anv_shader_bin_deserialize
../src/intel/vulkan/anv_pipeline_cache.c:41:1: note: 'anv_shader_bin_deserialize' declared here
anv_shader_bin_deserialize(struct vk_device *device,
^
../src/intel/vulkan/anv_pipeline_cache.c:59:17: error: incompatible pointer types initializing 'bool (*)(struct vk_pipeline_cache_object *, struct blob *)' with an expression of type 'struct vk_pipeline_cache_object *(struct vk_device *, const void *, size_t, struct blob_reader *)' (aka 'struct vk_pipeline_cache_object *(struct vk_device *, const void *, unsigned long, struct blob_reader *)') [-Werror,-Wincompatible-pointer-types]
   .serialize = anv_shader_bin_serialize,
                ^~~~~~~~~~~~~~~~~~~~~~~~
4 errors generated.

Fixes: 9786d9e ("util: Add glsl2spirv.py script")
Reviewed-by: Mykhailo Skorokhodov <mykhailo.skorokhodov@globallogic.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19394>

r300: update r400 tests

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19395>

zink: enable renderpass optimizing for turnip jobs

this should catch regressions, at the least

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19077>

zink: use tc renderpass tracking to optimize renderpasses

this massively improves performance on tiling gpus

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19077>

zink: add a context flag to indicate when blitter is running

...or blitter-like functionality

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19077>

util/tc: implement renderpass tracking

this allows tc to track metadata for framebuffer attachments so that
drivers can optimize their renderpasses

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19077>

util/tc: split out dsa and fs state cso handling

no functional changes

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19077>

util/tc: split out flush and deferred flush calls

it's useful to be able to separate these, and deferred flushes can also consume
slightly less memory

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19077>

ci/d3d12: Update quick_shader results with 24 fixes from !19128

Suggested-by: Jesse Natalie <jenatali@microsoft.com>
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19128>

nir/lower_int64: Implement lowering of 64-bit integer to 64-bit float conversions.

This involves computing the significand with a 64-bit precision type,
and implementing the normalization and packing manually instead of
relying on u2f32, since the significand can no longer be represented
as a 32-bit integer.  This fixes 64-bit integer to 64-bit float
conversions on devices that support 64-bit float natively but lack
64-bit integer support, like Intel MTL hardware.

Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com> (v1)
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19128>

nir/lower_int64: Enable lowering of 64-bit float to 64-bit integer conversions.

The existing code for this appears to work okay for conversions
involving 64-bit floats, relax the assert and enable the lowering
path.  This fixes 64-bit float to 64-bit integer integer conversions
on devices that have native support for 64-bit floats but lack 64-bit
integer support, like Intel MTL hardware.

Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19128>

asahi: Identify counts for compute kernels

In the same place as for vertex/fragment.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19265>

radeonsi: force the MSAA resolve shader to use 1 clause for MSAA loads

LLVM can't keep consecutive loads in a clause.

Using the optimization barrier for sample indices produces the optimal code.
Deduced by trial and error.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Mihai Preda <mhpreda@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19243>

nir: add nir_intrinsic_optimization_barrier_vgpr_amd for LLVM

We need this for the MSAA resolve shader.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Mihai Preda <mhpreda@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19243>

panfrost: Add lots of perf_debug annotations

Should make it easier to diagnose performance issues in the future.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19358>

panfrost: Enable rendering to 16-bit and 32-bit

Bifrost onwards handle this in hardware, and the Midgard lowering isn't
too terrible. Enable the format, otherwise desktop GL apps such as
Hacknet try to render to the format and get an incomplete framebuffer.

Cc stable because apparently we've been advertising this format
unintentionally as a result of some other interaction? Unclear how
Hacknet is hitting this, maybe it's an app bug. Shrug, it's not a big
deal regardless.

Additionally, we need to restrict texturing from 32-bit normalized due
to a restriction added with the v7 pixel format fiasco. That means
restricting rendering to 32-bit normalized on v7 onwards.

Closes: #7251
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Tested-by: Dang Huynh <danct12@disroot.org>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19358>

panfrost/ci: Disable trace-based testing

Trace-based testing has not worked for Panfrost. It was a neat
experiment, and I'm glad we tried it, but the results have been mostly
negative for the driver. Disable the trace-based tests.

For testing that specific API features work correctly, we run the
conformance tests (dEQP), which are thorough for OpenGL ES. For big GL
features, we run Piglit, and if there are big GL features that we are
not testing adequately, we should extend Piglit for these. For
fine-grained driver correctness, we are already covered.

Where trace-based testing can fit in is as a smoke test, ensuring that
the overall rendering of complex scenes does not regress. In principle,
that's a lovely idea, but the current implementation has not worked out
for Panfrost thus far. The crux of the issue is that the trace based
tests are based on checksums, not fuzzy-compared reference images. That
requires updating checksums any time rendering changes. However, a
rendering change to a trace is NOT a regression. The behaviour of OpenGL
is specified very loosely. For a given trace, there are many different
valid checksums. That means that correct changes to core code frequently
fail CI after running through the rest of CI, only because a checksum
changed in a still correct way. That's a pain to deal with, exacerbated
by rebase pains, and provides negative value to the project. Some recent
examples of this I've hit in the past two weeks alone:

   panfrost: Enable rendering to 16-bit and 32-bit
   4b49241f7d7 ("panfrost: Use proper formats for pntc varying")
   ac2964dfbd1 ("nir: Be smarter fusing ffma")

The last example were virgl traces, but were especially bad: due to a
rebase fail, I had to update traces /twice/, wasting two full runs of
pre-merge CI across *all* hardware. This was extremely wasteful.

The value of trace-based testing is as a smoke test to check that traces
still render correctly. That is useful, but it turns out that checksums
are the wrong way to go about it. A better implementation would be
storing only a single reference image from a software rasterizer per
trace. No driver-specific references would be stored. That reference
image must never change, provided the trace never changes. CI would then
check rendered results against that image with tolerant fuzzy
comparisons. That tolerance matches with the fuzzy comparison that the
human eye would do when investigating a checksum change anyway. Yes, the
image comparison JavaScript will now report that
0 pixels changed within the tolerance, but there's nothing a human eye
can do with that information other than an error prone copypaste of new
checksums back in the yaml file and kicking it back to CI, itself a
waste of time.

Finally, in the time we've had trace-based testing alongside the
conformance tests, I cannot remember a single actual regression in one
of my commits the trace jobs have identified that the conformance tests
have not also identified. By contrast, the conformance test coverage has
prevented the merge of a number of actual regressions, with very few
flakes or xfail changes, and I am grateful we have that coverage. That
means the value added from the trace jobs is close to zero, while the
above checksum issues means that the cost is tremendous, even ignoring
the physical cost of the extra CI jobs.

If you work on trace-based testing and would like to understand how it
could adapted to be useful for Panfrost, see my recommendations above.
If you work on CI in general and would like to improve Panfrost's CI
coverage, what we need right now is not trace-based testing, it's
GLES3.1 conformance runs on MediaTek MT8192 or MT8195. That hardware is
already in the Collabora LAVA lab, but it's not being used for Mesa CI
as the required kernel patches haven't made their way to mainline yet
and nobody has cherry-picked them to the gfx-ci kernel. If you are a
Collaboran and interested in improving Panfrost CI, please ping
AngeloGioacchino for information on which specific patches need to be
backported or cherry-picked to our gfx-ci kernel. Thank you.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Acked-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19358>

nir: Add way to create passthrough TCS without VS nir

In the case of disk-cache hits, radeonsi no longer has the nir shader
around.  So add a way to create a passthrough TCS with just the VS
output locations.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7567
Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19382>

docs: Update features.txt

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19388>

gallium: Only use Asahi's software path on macOS

On macOS, we don't have DRM or any real WSI, so Asahi has to pretend to be a
software rasterizer to load. On Linux, we do have DRM and proper WSI, so we
don't want that. For faking Asahi devices on Linux, we should use drm-shim
instead. This makes sure we don't accidentally load Asahi on non-M1 Linux.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15940>

gallium: Stub support for Asahi + DRM

Copy-paste a pile of winsys code from panfrost and find-and-replace the name to
asahi. This should contain all the glue code needed for asahi+kmsro.

The kernel driver is under way (led by Asahi Lina, not me), but it's not
wred up here. My goal was rather to run shader-db, which expects a
render node, which means drm-shim, which means DRM loader support. With
this patch and a trivial drm-shim, shader-db runs.

In general I am reticent to touch UABI related code when the UABI hasn't been
finalized upstream, or started design at all, hence the RFC. Realistically this
patch assumes the following about the future UABI:

0. It will be a DRM driver. This is nonnegotiable.

1. The render node will be named "asahi". The other reasonable name would be
   "apple", which I'm using for the display controller (not yet upstream, but
   getting close).

2. Display and rendering will be split in the kernel, requiring kmsro in
   userspace, as agreed in past discussions.

   The 3D accelerator (AGX) and the display controller (DCP) are completely
   orthogonal blocks with separate lineages. True, Apple A14 (~= M1) has AGX and
   DCP together, and it seems like all the chips that will get upstream support
   will have this for the forseeable future. Nevertheless, it's a historical
   coincidence. Apple A12 had an AGX block with a pre-DCP Apple display
   controller, which would use a completely different display driver. Older SoCs
   had a PowerVR block with an Apple shader core, with a pre-DCP Apple display
   controller. Even older SoCs had a pure PowerVR block (+ Apple display).

   The AGX and DCP kernel drivers are not expected to share any nontrivial code.
   We don't gain anything by bundling them together. Likewise, the many
   codec blocks are completely orthogonal. This is all standard practice
   for Arm SoCs.

   It is true that AGX has never been used with a non-Apple display
   controller; it is highly unlikely this would change (either by AGX
   licensing out or something like Mali-DP getting licensed in). But
   an extra kmsro user doesn't actually add more complexity to Mesa, so
   shrug.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Eric Engestrom <eric@igalia.com> [meson, ack on gallium]
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15940>

r600/sfn: Add .clang-format file and apply style

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19379>

nir/algebraic: add vec8/16 cmp lowering

Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19150>

nir/algebraic: generalize vector_cmp lowering

Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19150>

nir/algebraic: support CL vector accessors

Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19150>

nir/algebraic: add 8 and 64 bit urol and uror lowering

Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19150>

panfrost,asahi: Support ARB_buffer_storage

After a great deal of spec lawyering in #dri-devel, I am convinced this
is probably okay for the same reasons as v3d and freedreno. The batch
reordering and flush deferral optimizations are seemingly still ok. The
requirement that writes are visible "immediately" in the spec actually
means "in the subsequent [OpenGL] command" for the CPU -> GPU direction,
which avoids pitfalls where PERSISTENT|COHERENT could be used as a
"doorbell". With that understanding, the extension doesn't actually
require anything special for tilers other than coherency at GPU submit
boundaries, which is true for any driver that does not use a sync ioctl.

After this commit, the remaining drivers that don't set the CAP are
d3d12, softpipe, etnaviv, and i915g. I am unsure about d3d12, but the
latter 3 could probbaly enable it trivially for the same reason.

v2: Don't use copy_resource path for persistent mappings (Emma). Emma
explained on GitLab:

   I don't think you should have the copy_resource path taken for
   PIPE_RESOURCE_FLAG_MAP_PERSISTENT BOs.  Imagine the user has a
   general-purpose BO they're streaming stuff into and doing draws that
   they keep persistently mapped until wrapping.  They call some GL
   function on the same buffer that does a fallback write map on the BO
   (u_default_buffer_subdata, util_resource_copy_region, whatever) -- the
   buffer is in use, copy triggers, allocates a new BO.  Whoops, the user's
   pointer for streaming writes is now freed.

Closes: #7570
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19351>

gallium/util: add a helper for get_timestamp

Signed-off-by: Yusuf Khan <yusisamerican@gmail.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19334>

aco: insert waitcnt before/after ds_ordered_count

The LLVM backend does this when lowering ordered_xfb_counter_add_amd. I
guess there is some missing dependency checking or something.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19345>

aco: add storage_gds

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19345>

zink: Lazily allocate the dummy surfaces.

glmark2 -b texture --fullscreen drops from 141MB of BOs to 85MB on turnip.
Still 29MB more than freedreno (due to a pile of extra fullscreen rgba8
images)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19126>

zink: No need to use a 2-sample dummy image for bindless without null descs.

This appears to be some leftover copy and paste or something, should be
1-sample just like other dummy usages.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19126>

iris: Do not export iris_bo_wait()

It has a single user, so no need to export it.

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19359>

iris: Drop duplicated errno handling in iris_bo_wait()

Both code paths already do this handling, so no need to this again in
iris_bo_wait().

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19359>

iris: Nuke pci_id from iris_screen

We have the same information in devinfo.

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19359>

intel/perf: Use intel_device_info functions to compute subslice and eu totals

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19359>

d3d12: Don't align already-aligned size in `d3d12_bufmgr_create_buffer`

This is handled by `pb_cache_manager_create_buffer`.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19082>

gallium/pipe: Align allocation size in `pb_cache_manager_create_buffer`

Some drivers have minimum buffer size or alignment requirements. When a
buffer is created using pb_cache_manager_create_buffer, the cache is
first checked for a compatible buffer to return instead. If the
requested buffer size is less than
(minimum buffer size) / (mgr->size_factor), no buffer in the cache
is _ever_ applicable.
The alignment is used to determine the true allocation size when
evaluating against cached buffers.

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19082>

freedreno/ci: Small bit of xfails cleanup

Minor resorting to group similar edgeflags fails together.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19236>

freedreno: Enable GL_ARB_enhanced_layouts

Seems like ir3 already supports everything that was needed, according to
piglit.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19236>

freedreno/a6xx: Enable GL_ARB_texture_mirror_clamp_to_edge

It was already supported, might as well turn it on.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19236>

freedreno/a6xx: Support GL_ARB_viewport_array + gl43

Support multiple viewports and bump supported GLSL version now that we
tick all the boxes.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19236>

freedreno: Move guardband calc to bind time

No point in re-calculating this at emit time.  Even more so when there
are multiple viewports.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19236>

freedreno: Massage scissor state at bind time

All the generations want maxx/maxy to be inclusive rather than
exclusive, so shift the subtract-one nonsense to bind time rather
than emit time.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19236>

freedreno: support multiple viewports

Core plumbing to have multiple viewport support.  Each viewport has it's
own scissor state.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19236>

freedreno/a6xx: Support AMD_vertex_shader_layer

Another thing we already supported but didn't set the cap.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19236>

freedreno/a6xx: Fix buffer size clamping

Fixes spec@arb_texture_buffer_object@texture-buffer-size-clamp@* which
we start hitting after exposing glsl420

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19236>

freedreno/ir3: Drop unused view_zero/layer_zero lowering

Previous patch removed the only remaining user.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19236>

freedreno/a6xx: Move layer_zero handling to interp state

We can just bake this into the program state, rather than making it a
shader variant.  Turnip had already switched to this approach so it will
let us drop ir3 lowering for this.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19236>

freedreno: Don't advertise TGSI support for GS/tess

tgsi_to_nir doesn't support these, and we long ago removed support for
consuming TGSI without tgsi_to_nir.  So don't claim to support this.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19236>

Revert "mesa/st: ARB_vertex_attrib_64bit depend on glsl>=410"

Turns out this change was unnecessary

This reverts commit 533b87dff09a0434cd2c0c22718d117501e17915.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19236>

ac/nir/ngg: fix emitting streamout output by using packed location

In RadeonSI, they are packed but not in RADV, so don't rely on driver
locations.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19343>

rusticl/kernel: fix more 32 bit problems

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19353>

radv: move nir_opt_idiv_const/nir_lower_idiv after NGG lowering

NGG streamout lowering creates some idiv instructions that need to be
lowered.

No fossil-db results because it's currently broken.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19364>

radv/llvm: fix dual source blending on GFX11

Untested but this should be similar to RadeonSI.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19367>

radv: fix VRS limit when attachmentFragmentShadingRate is disabled

Can be reproduced on GFX10.3 with RADV_DEBUG=nohiz.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19374>

zink: don't double-deref bindless texture arrays in shaders

these are already dereferenced

Fixes: b2fcb34e976 ("zink: rework sampler emission")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19377>

iris: Fix enablement of protected contexts

I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS needs to set otherwise
i915 will ignore the extensions.

Fixes: 57a1d13279c6 ("iris: enable protected contexts")
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19373>

v3dv: split event implementation to a separate file

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19366>