anv: Claim to be a discrete GPU if has_lmem

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5599>

intel/dev: Set has_local_mem for DG1

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5599>

anv: Allocate scratch and workaround BO in local memory

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5599>

anv: Allocate BO in appropriate region

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5599>

anv: Wrapper around I915_GEM_CREATE_EXT_MEMORY_REGIONS

v2 (Jordan Justin):
 - add anv_gem_stubs.c impl

v3 (Jason Ekstrand):
 - Use the upstream uAPI
 - Rework the interface a bit

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5599>

anv: Query memory region info

Create additional memory type with DEVICE_LOCAL_BIT if we have local
memory region aviable.

v2 (Jason Ekstrand):
 - Don't leak mem_regions if the second ioctl fails

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5599>

iris: Map with WC on non-LLC platforms.

Reworks:
 * Jordan: Required rework following
   f62724ccacf ("iris: Pick a single mmap mode (WB/WC) at BO allocation time")

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5599>

iris/bufmgr: Add flag to allocate from local memory.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5599>

iris/bufmgr: Add new set of buckets for local memory.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5599>

iris/bufmgr: Query memory region info.

v2 (Jason Ekstrand):
 - Don't leak meminfo if the ioctl fails on the second pass

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5599>

iris/bufmgr: Align vma addresses to 64K for local memory

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5599>

intel/devinfo: Add has_local_mem

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5599>

include/drm-uapi: bump headers

From drm-next at the following commit:

  commit 2a7005c8a3982ba27fab237d85c27da446484e9c (HEAD)
  Merge: 0666cba1f5b2b 47c65b3853f88
  Author: Dave Airlie <airlied@redhat.com>
  Date:   Fri Jun 11 13:34:42 2021 +1000

      Merge tag 'drm-intel-gt-next-2021-06-10' of...

Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5599>

radv: Implement VK_EXT_acquire_drm_display

Signed-off-by: Simon Zeni <simon@bl4ckb0ne.ca>
Reviewed-by: Simon Ser <contact@emersion.fr>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11014>

vulkan/wsi: Implement VK_EXT_acquire_drm_display

Implements the two functions defined in the extension
VK_EXT_acquire_drm_display, vkAcquireDrmDisplayEXT and vkGetDrmDisplayEXT.

Signed-off-by: Simon Zeni <simon@bl4ckb0ne.ca>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Simon Ser <contact@emersion.fr>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11014>

vulkan/wsi: add drm_fd param to wsi_display_get_connector

Modifies the signature on `wsi_display_get_connector` to retrieve the
connector of an arbitrary DRM FD instead of the one taken from the
wsi_display.

Signed-off-by: Simon Zeni <simon@bl4ckb0ne.ca>
Reviewed-by: Simon Ser <contact@emersion.fr>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11014>

docs/isl: Improve the bit[6] swizzling section of the tiling chapter

Suggested-by: Luis Strano <luis.strano@intel.com>
Acked-by: Luis Strano <luis.strano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11479>

isl,docs: Add a chapter on AUX state tracking

We also update and improve the docs in isl.h which get pulled into this
new chapter.

Acked-by: Luis Strano <luis.strano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11479>

isl,iris: Move the extra_aux_surf logic into iris

This gets rid of the awkward interface for isl_surf_get_ccs_surf where
we passed it two aux surfaces and it was supposed to fill out the second
one based on whether or not the first one already had stuff in it.
Instead, we now pass it three well-labled surfaces: surf,
hiz_or_mcs_surf, and ccs_surf which have obvious meanings.  This does
mean that iris has to carry a bit of logic and we have to flip
parameters around in all the callers.  But the resulting interface is
much cleaner.

Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11479>

isl: Take a hiz_or_mcs_surf in isl_surf_supports_ccs

Whether or not a surface supports CCS on Tigerlake and later is
dependent not only on the main surface but also on the MCS or HiZ
surface, if any.  We were doing some of these checks in
isl_get_ccs_surf based on the extra_aux parameter but not as many as we
probably should.  In particular, we were really only checking HiZ
conditions and nothing for MCS.  It also meant that, in spite of the
symmetry in names, the checks in isl_surf_get_ccs_surf were more
complete than in isl_surf_supports_ccs.

Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11479>

isl: Assert some iris invariants in isl_surf_get_ccs_surf

The only driver which calls isl_surf_get_ccs_surf with extra_aux != NULL
is iris and it always calls it with two aux surfaces and never calls it
for CCS twice.  We can turn those checks into asserts.

Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11479>

asahi: Fix macOS macro.

Fixes: 26b19bda306 ("asahi: Add device abstraction")
Fixes: 55c0956fd00 ("asahi: Add (clean room) IOKit uABI header")
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11569>

libgl-gdi: add missing include

Without this, I get the following error if I try to compile Zink without
any other drivers:

src/gallium/targets/libgl-gdi/libgl_gdi.c(210): error C2037: left of
'flush_frontbuffer' specifies undefined struct/union 'pipe_screen'

Fixes: fdfe4a4d307 ("libgl-gdi: add zink support")
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Acked-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11536>

zink: remove some needless moltenvk details

This removes a macro that we don't need, and removes a comment about a
detail that we don't care about in that location.

Acked-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Acked-by: Hoe Hao Cheng <haochengho12907@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11554>

zink: do not store moltenvk functions in screen

These functions are only used once anyway, no need to store them and
make the rest of Zink care.

Acked-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Acked-by: Hoe Hao Cheng <haochengho12907@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11554>

zink: remove unused moltenvk functions

These functions were added, but never used. Let's get rid of them.

Fixes: c2cb2dd3bc6 ("zink: Added support for MacOS MoltenVK APIs.")
Acked-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Acked-by: Hoe Hao Cheng <haochengho12907@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11554>

zink: unbreak moltenvk code

These functions don't exist in the Khronos XML, so we don't generate
dispatch-table entries for them. So let's not try to call them in that
way.

Fixes: 55748681032 ("zink: use the dispatch tables")
Acked-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Acked-by: Hoe Hao Cheng <haochengho12907@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11554>

zink: remove unused function-pointers

We also forgot to remove these when we stoped using them, more stuff to
delete, yeah!

Fixes: 55748681032 ("zink: use the dispatch tables")
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Hoe Hao Cheng <haochengho12907@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11554>

zink: drop unused macros

We stopped using these without removing them, let's tidy that bit up.

Fixes: 55748681032 ("zink: use the dispatch tables")
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Hoe Hao Cheng <haochengho12907@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11554>

crocus: fix another printf specifier.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11570>

crocus/gfx6: always be dirtying gs attachments for xfb

This fixes hangs seen with xfb and the deqp test

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11567>

crocus: Avoid replacing backing storage for buffers with no contents

Ported 97e9de17952d1382512007e4745c25b9c9106a46 from iris

    We might get asked to pitch the storage on a buffer that already has
    no meaningful contents.  In this case, the existing buffer is as good
    as a new one.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11567>

crocus: dirty blend state more often.

The blend state depends on wm_prog_data dual_src and it also
depends on the cbuf formats in can_emit_logic_op.

Dirty it in the correct places.

Fixes:
dEQP-GLES3.functional.fbo.invalidate*

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11567>

crocus/gfx6: fix sampler view first level.

The gfx6 state needs to dirty sampler state so that BaseMipLevel
gets updated properly.

Fixes:
dEQP-GLES3.functional.texture.mipmap.cube.base_level.*

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11567>

intel/genxml: fix gfx6 GS SVB_INDEX encoding

This seems to match what the docs + 965 traces say

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11567>

crocus/query: poll the syncobj in the no wait situation

In the no wait, poll the syncobj and bail if it's hasn't signalled.
This fixes a bunch of deqp xfb tests on sandybridge

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11567>

vl/dri3: Don't leak regions on the X server

I can't tell from a quick read whether this clip region is actually just
the bounding box so could be skipped entirely. But the old code never
destroyed it, which means we'd leak a couple hundred bytes on the X
server side for every SwapBuffers until the client dies of XID
exhaustion, which is somewhere north of 2GB for typical systems so you
may or may not just run out of memory first.

Create the region at swap time and stash it in the drawable state.

Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11461>

loader/dri3: Don't churn through xfixes regions in SwapBuffers

Regions are not expensive objects on the server side, it's very slightly
cheaper to update an existing one than to create a new one, and we can
garbage collect them when the drawable is destroyed. Worse, XID reuse
bugs exist, so the more we can do to not churn through XIDs the better.

Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11461>

loader/dri3: Properly initialize the XFIXES extension

The server starts off assuming the only XFIXES request the client might
known is FixesQueryVersion, and based on the version number the client
supplies it unlocks additional requests. If you forget to do this then
xcb_xfixes_create_region will throw BadRequest and you will be very
confused. libXfixes would hide this for you in extension setup but xcb
is not so forgiving.

Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11461>

radeonsi: optimize set_inlinable_constants when they don't change

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11509>

ac/gpu_info: adjust the condition for use_late_alloc

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11509>

radeonsi: don't use NGG culling on 1 RB chips

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11509>

radeonsi: remove incorrect comment about hangs in gfx10_ngg_gs_emit_epilogue

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11509>

radeonsi: if shader culling culls all vertices, cull the primitive exports too

This was overlooked. It benefits triangle strips the most due to
GS fast launch.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11509>

radeonsi: document why VBO descriptors in user SGPRs are beneficial

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11509>

lavapipe: implement multidraw ext

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11533>

zink: use depth/stencil-only layouts for depth/stencil-only formats

just kidding, this is banned by spec

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11389>

util: add work around for the game We Happy Few

This is another Unreal engine game that requires the
allow_glsl_cross_stage_interpolation_mismatch workaround.

Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4966

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11558>

ci/i915g: Skip the piglit glx tests since we're not running X.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11559>

i915g: Finish out blend factor overrides for both RGBx and A8.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11559>

i915g: Fix bad naming of depth texture formats.

Now matches classic's i915_reg.h and the spec.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11559>

ir3/ra: Fix corner case in collect handling

I ran into this when accidentally changing the scheduling order in the
hl2 trace.

Fixes: 0ffcb19 ("ir3: Rewrite register allocation")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11469>

ir3: Remove IR3_REG_DEST

This was needed because code iterating the regs array needed to know
what was a destination and what wasn't, but now we have separate srcs
and dsts arrays so it's not needed.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11469>

ir3: Remove regs array

Now that everything is converted over, switch to separate src/dst
arrays.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11469>

ir3/frontend: Switch to srcs/dsts arrays

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11469>

ir3/opts: Switch to srcs/dsts arrays

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11469>

ir3/validate: Switch to srcs/dsts arrays

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11469>

ir3/print: Switch to srcs/dsts arrays

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11469>

ir3/legalize: Switch to srcs/dsts arrays

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11469>

ir3/array_to_ssa: Switch to srcs/dsts arrays

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11469>

ir3/parser: Switch to srcs/dsts arrays

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11469>

ir3/ra: Switch to srcs/dsts arrays

RA was manually fiddling with regs to copy over the parallel copy code,
which has to be done in a different way, but if we switch this all over
at once it shouldn't be a problem.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11469>

ir3/core: Switch to srcs/dsts arrays

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11469>

ir3/sched: Convert to srcs/dsts arrays

Also change the indexing in ir3_delayslots, so it's finally sane! To do
this we also have to change foreach_ssa_src_n to index srcs instead of
regs, so that the indexing stays in sync.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11469>

freedreno/tests: Convert to srcs/dsts

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11469>

freedreno/isa: Convert to srcs/dsts

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11469>

ir3: Add srcs/dsts arrays to ir3_instruction

Initially these will shadow regs, so that we can transition things
before getting rid of regs.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11469>

ir3/legalize: Construct branch properly

Don't just yeet stuff into regs without updating regs_count, etc. This
will break horribly during the transition otherwise.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11469>

ir3: Add separate src/dst count in ir3_instr

srcs and dsts will be in separate arrays, so we need everything creating
it to give a separate source and dest max count.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11469>

ir3: Split ir3_reg_create() into ir3_{src,dst}_create()

Right now they are basically the same, but in the future they will
append to different arrays.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11469>

ir3: Make ir3_instruction::address a normal register

This fixes an annoying mismatch in the indices between foreach_ssa_src_n
and ir3_delayslots(), and lets us remove a bunch of other special cases.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11469>

ir3: Add is_reg_special()

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11469>

ir3: Validate that ir3_register::instr is correct

Catch the mistake fixed in the previous commit.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11469>

ir3: Update ir3_register::instr when cloning instructions

We happened to not clone any SSA instructions, but we will once address
instructions start counting as SSA. Fix this oversight.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11469>

ir3: Split read-modify-write array dests in two

Instructions that operate on an array read the previous state of the
array, modify it, and write a new array, at least conceptually before
RA. Previously the same register specified the previous state and acted
as the new state, but this meant that it was both a source and
destination which meant that it was getting in the way of splitting up
sources and destinations. Break out the source into a separate register,
and use the new tied-src infrastructure to share code with a6xx atomics.
With this, there are basically no more special cases for arrays in RA.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11469>

ir3: Make tied sources/destinations part of the IR

Previously this was hard-coded for a6xx atomic instructions. However
we'll need a way for array destinations to point to the source with the
previous value of the array when we split them up. This is conceptually
the same as tied source/destinations for a6xx atomics, except that array
writes sometimes won't have a previous value to point to. So move this
into the IR so that it can be more dynamic. As a bonus we can move the
knowledge of a6xx atomics out of RA, where it's out-of-place, and into
the a6xx-specific code that creates them.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11469>

amd/ci: add hawaii-specific skip and fail lists

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10424>

pan/mdg: Add 16 bytes of padding to the end of shaders

Fixes INSTR_INVALID_PC faults when a shader ends on a 16MB boundary.

Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11551>

anv: fix emitting dynamic primitive topology

Initial implementation missed various fields that derive from the
primitive topology. This patch fixes 3DSTATE_RASTER/3DSTATE_SF,
3DSTATE_CLIP and 3DSTATE_WM (gen7.x) emission in the dynamic case.

Fixes: f6fa4a80000 ("anv: add support for dynamic primitive topology change")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4924
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11379>

Revert "ci: disable panfrost t760 jobs"

Both our T760 machines took a dive in beautiful synchronicity last
night, were recovered early this morning.

This reverts commit 854d93f73d6064a13ddc13dddf74c8c760cda1d4.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11555>

iris: take a reference to memobj bo in iris_resource_from_memobj

v2: and remove it from iris_memobj_create_from_handle ... (Nanley)

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4969
Fixes: 772dc50d162 ("iris: hook up resource creation from memory object")
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11552>

radeonsi: disable ngg culling on llvm < 12

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4874
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
CC: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11362>

anv: bound checks buffer memory binding in debug builds

Validation layers should warn you about this
(VUID-VkBindBufferMemoryInfo-size-01037) but this would be useful for
zink debugging.

Requested by Zmike.

v2: Also check memoryOffset (Jason)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11542>

intel/fs: Implement Wa_14013745556 on TGL+.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11433>

intel/fs: Fix synchronization of accumulator-clearing W/A move on TGL+.

Right now the accumulator-clearing move emitted by the generator for
Wa_14010017096 inherits the SWSB field from the previous instruction.
This can lead to redundant synchronization, or possibly more serious
issues if the previous instruction had a TGL_SBID_SET SWSB
synchronization mode.  Take the SWSB synchronization information from
the IR.

Fixes: a27542c5ddec8 ("intel/compiler: Clear accumulator register before EOT")
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11433>

intel/fs: Teach IR about EOT instruction writing the accumulator implicitly on TGL+.

This is unlikely to have had any negative side effect on the original
TGL, but will lead to issues on XeHP+ if the software scoreboard pass
isn't able to synchronize the accumulator writes.

Fixes: a27542c5ddec8 ("intel/compiler: Clear accumulator register before EOT")
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11433>

intel/fs: Add SWSB dependency annotations for cross-pipeline WaR data hazards on XeHP+.

In cases where an in-order instruction is overwriting a register
previously read by another in-order instruction, drop the dependency
iff the previous read is guaranteed to have occurred from the same
in-order pipeline.  This should only have an effect on XeHP+ since
previous Xe platforms only had one in-order FPU pipeline.

The previous workaround we were using for this treated all ordered
read dependencies as write dependencies to avoid noise from our
simulation environment.  Relative to our previous workaround this
improves performance of GFXBench5 gl_tess by ~7% on a DG2 system
among other single-digit percentual FPS improvements.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11433>

intel/fs: Implement Wa_22012725308 for cross-pipe accumulator data hazard.

The hardware fails to provide the expected data coherency guarantees
for accumulator registers when accessed from multiple FPU pipelines.
Fix this by tracking implicit accumulator accesses just like we do for
regular GRF registers, but instead of adding synchronization
annotations for any dependency we only do it for dependencies with a
pipeline mismatch, since the hardware should be able to guarantee
proper synchronization for matching pipelines.

Note that this workaround handles RaW and WaW dependencies in addition
to the WaR dependencies described in the hardware bug report even
though cross-pipeline RaW accumulator dependencies should be extremely
rare, since chances are the hardware will also hang if we ever hit
such a condition.  This only affects XeHP+, since all FPU instructions
are executed as a single in-order pipeline on earlier Xe platforms.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11433>

intel/fs: Track single accumulator in scoreboard lowering pass.

This change reduces the precision of the scoreboard data structure for
accumulator registers, because the rules determining the aliasing of
accumulator registers are non-trivial and poorly documented (e.g. acc0
overlaps the storage of acc1 when the former is accessed with an
integer type).  We could implement those rules but it wouldn't have
any practical benefit since we currently only use acc0-1, and for the
most part we can rely on the hardware's accumulator dependency
tracking.  Instead make our lives easier by representing it as a
single register.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11433>

intel/fs/xehp: Assert that the compiler is sending all 3 coords for cubemaps.

As required by HSDES:14013363432.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11433>

freedreno/ci: Use TU_IGNORE_CONFORMANCE_WARNING to reduce warnings

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11543>

tu: Provide a toggle to avoid warnings about unsupported devices

In the CI, we have such devices, and this message is printed many
hundreds of times. This results in a useless spam which makes it
difficult to see real issues.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11543>

meson/crocus: add prefer-crocus option.

This just allows picking crocus without having to set the env var.

Acked-by: Alyssa Rosenzweig <alyssa@collabora.com>
Acked-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11353>

mesa: unreference zombie buffers when creating buffers to lower memory usage

This fixes an issue where one context only creates buffers while another
context only destroys buffers. Only the creating context can release its
buffers and the destroying context only turns them into zombie buffers.

This fix makes the creating context release its zombie buffers.
It's not a plot from an apocalyptic movie.

Fixes: e014e3b6be6 "mesa: don't count buffer references for the context that created them"
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4840

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11514>

crocus: fix batch state bo leak

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11547>

crocus: fix vertex buffer leak on screen end.

this was stopping the screen from being cleaned up as well

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11547>

crocus: free context state properly.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11547>

zink: ci updates

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10973>

zink: remove primconvert

this is no longer used

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10973>

zink: export supported primitive restart types

this is now handled by gallium, so the codepath can be dropped

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10973>