Md Abdullah Shahneous Bari [Fri, 31 Mar 2023 21:02:25 +0000 (14:02 -0700)]
[mlir][spirv] Add OpExtension "SPV_INTEL_bfloat16_conversion"
Add Intel-specific "SPV_INTEL_bfloat16_conversion" extension and
capability (Bfloat16ConversionINTEL), and
two ops (OpConvertFToBF16INTEL, OpConvertBF16ToFINTEL)
that are introduced by this extension.
These ops allow BF16 to Float conversion and vice-versa.
Reference Specification:
https://github.com/KhronosGroup/SPIRV-Registry/blob/main/extensions/INTEL/SPV_INTEL_bfloat16_conversion.asciidoc
Reviewed By: antiagainst
Differential Revision: https://reviews.llvm.org/D147087
Florian Hahn [Fri, 31 Mar 2023 20:50:39 +0000 (21:50 +0100)]
[LV] Improve test added in
74dee4791a2.
Adjust test so it triggers a case missed in the original version
of D147260.
Alex Langford [Tue, 28 Mar 2023 21:00:13 +0000 (14:00 -0700)]
[lldb] Move ObjectFileJIT to lldbExpression
In the spirit of not having lldbExpression rely on plugins, this move
makes the most sense. ObjectFileJIT is not really a "plugin" in the
sense that without it, expression evaluation doesn't work at all. This
is different than something like ObjectFileELF where lldb can still
technically debug non-ELF targets without it. For that reason, moving
ObjectFileJIT into Expression where it will be used in conjunction with
IRExecutionUnit makes the most sense.
Differential Revision: https://reviews.llvm.org/D147084
Mingming Liu [Fri, 31 Mar 2023 04:55:41 +0000 (21:55 -0700)]
[AutoFDO]Merge called target in body samples when flattening profiles
- Body samples could have call targets, merge them as well.
Differential Revision: https://reviews.llvm.org/D147297
Florian Hahn [Fri, 31 Mar 2023 20:15:13 +0000 (21:15 +0100)]
[LV] Add test with predicated load where EltSize % Align != 0.
Craig Topper [Fri, 31 Mar 2023 20:08:10 +0000 (13:08 -0700)]
[RISCV] Add named constants for rounding mode to tablegen. NFC
Instead of hardcoding the values, uses name constants to improve
readability.
Reviewed By: asb
Differential Revision: https://reviews.llvm.org/D147352
Craig Topper [Fri, 31 Mar 2023 20:06:26 +0000 (13:06 -0700)]
[RISCV] Collapse loadfp32imm/loadfp64imm/loadfp16imm to a single Operand in tablegen
They were identical except for the type passed to Operand, but
I don't think that type is used for anything with the way its
being used today.
Simon Pilgrim [Fri, 31 Mar 2023 20:09:57 +0000 (21:09 +0100)]
[X86] vector-reduce-and-bool.ll - add AVX1OR2 check-prefix and make AVX a common check-prefix
Simon Pilgrim [Fri, 31 Mar 2023 19:54:22 +0000 (20:54 +0100)]
[X86] vector-compare-all_of.ll - add AVX1OR2 check-prefix and make AVX a common check-prefix
Joseph Huber [Fri, 31 Mar 2023 17:26:56 +0000 (12:26 -0500)]
[OpenMP] Add CMake option to disable `libarcher` support
The support for `libarcher` can sometimes cause problems when running
tests or building. We want an option to turn this off when we are not
directly testing `libarcher`.
Reviewed By: jplehr
Differential Revision: https://reviews.llvm.org/D147343
Philip Reames [Fri, 31 Mar 2023 19:41:21 +0000 (12:41 -0700)]
{tests] Rerun autogen to reduce a diff [nfc]
Siva Chandra Reddy [Fri, 31 Mar 2023 19:36:18 +0000 (19:36 +0000)]
[libc][Obvious] Add a missing dep and fix an incorrect dep.
Jun Sha (Joshua) [Fri, 31 Mar 2023 19:15:05 +0000 (12:15 -0700)]
[RISCV] Fix Zfa fceil/ffloor codegen bugs
D143982 confused ceil and floor. Ceil should use fround instructions with 'rup' and floor should use 'rdn'.
Differential Revision: https://reviews.llvm.org/D146516
Craig Topper [Fri, 31 Mar 2023 18:57:31 +0000 (11:57 -0700)]
[RISCV] Fix formatting in RISCVInstrInfoZfa.td. NFC
Extracted from D146516.
Haowei Wu [Fri, 31 Mar 2023 18:27:18 +0000 (11:27 -0700)]
Revert "[Assignment Tracking] Enable by default"
This reverts commit
aa32490bfe0b957c4f5583e14304f5e34b2b9bce, which
breaks llvm runtimes builds on armv7 linux.
Lang Hames [Fri, 31 Mar 2023 04:57:03 +0000 (21:57 -0700)]
[ORC] Fix a typo in __objc_imageinfo section name.
Lang Hames [Fri, 31 Mar 2023 04:53:35 +0000 (21:53 -0700)]
[JITLink] Fix bug in LinkGraph::createMutableContentBlock overload.
Creating zero-filled blocks should use allocateBuffer to allocate the block's
content buffer, rather than allocateContent. (allocateContent interpreted what
would have been the size argument as a single-element ArrayRef and allocated a
single byte).
Simon Pilgrim [Fri, 31 Mar 2023 17:35:31 +0000 (18:35 +0100)]
[DAG] Add SelectionDAG::SplitScalar helper
Similar to the existing SelectionDAG::SplitVector helper, this helper creates the EXTRACT_ELEMENT nodes for the LO/HI halves of the scalar source.
Differential Revision: https://reviews.llvm.org/D147264
Benjamin Kramer [Fri, 31 Mar 2023 17:31:25 +0000 (19:31 +0200)]
[bazel] Add missing dependency after
9884eb149e612
Jez Ng [Fri, 31 Mar 2023 17:19:48 +0000 (13:19 -0400)]
[lld-macho] Gate category checking behind --check-category-conflicts
@oontvoo reports that the current implementation crashes on a bunch of
their builds. Let's leave it disabled by default for now.
Reviewed By: #lld-macho, oontvoo
Differential Revision: https://reviews.llvm.org/D147341
wlei [Fri, 31 Mar 2023 17:15:51 +0000 (10:15 -0700)]
Fix a missing checksum field
Leonard Chan [Fri, 31 Mar 2023 17:03:18 +0000 (17:03 +0000)]
"Reland "[hwasan] Provide aliases for c allocation functions for Fuchsia"
This reverts commit
7b6c0ce9c6c1e2cc3076e787e0e8d9a43bc2bfcc.
See if this works on the android builder this time by keeping the
original WRAP declaration.
Guozhi Wei [Fri, 31 Mar 2023 16:58:41 +0000 (16:58 +0000)]
[AARCH64] Enable STORE of v4i8 to help more vectorization opportunities
For the attached test case, currently llvm generates instructions to load/or/store the bytes one by one. Although NEON doesn't support v4i8 natively, we can promote it to v4i16 and operate on v4i16 vectors. So this patch override getStoreMinimumVF and specify the minimum VF for i8 vector is v4i8.
Differential Revision: https://reviews.llvm.org/D145614
Jonas Devlieghere [Fri, 31 Mar 2023 16:45:06 +0000 (09:45 -0700)]
[dsymutil] Add a new automatic verification mode
This patch a new verification mode called "auto" that runs the DWARF
verifier on the input and if the input is valid, also runs the DWARF
verifier on the output. The goal is to catch cases where dsymutil turns
valid DWARF into invalid DWARF. This patch makes this verification mode
the default when assertions or expensive checks are enabled.
Differential revision: https://reviews.llvm.org/D147203
Ben Langmuir [Thu, 30 Mar 2023 22:47:53 +0000 (15:47 -0700)]
[clang][deps] Remove -coverage-data-file and -coverage-notes-file from modules
When not performing codegen, we can strip the coverage-data-file and
coverage-notes-file options to improve canonicalization.
rdar://
107443796
Differential Revision: https://reviews.llvm.org/D147282
Jonas Devlieghere [Fri, 31 Mar 2023 00:43:18 +0000 (17:43 -0700)]
[dwarfdump] Fix .debug_line verification for DWARF 5
DWARF 5 uses a 0-based index while previous versions use a 1-based
index. Fix the verifier and add a test.
Differential revision: https://reviews.llvm.org/D147202
Oleg Shyshkov [Thu, 30 Mar 2023 21:18:21 +0000 (23:18 +0200)]
[mlir][scf] Create constants for tiling in parent with isolated region.
FuncOp is IsolatedFromAbove, so this change doesn't alter current behaviour, but the current code fails if the tile op is in an op with IsolatedFromAbove trait.
An alternative would be to create constant in the same region where they're used a rely on CSE to figure out where to move them.
Differential Revision: https://reviews.llvm.org/D147273
Mikhail R. Gadelha [Fri, 31 Mar 2023 16:21:23 +0000 (13:21 -0300)]
[libc] Enable more headers for riscv
Reviewed By: sivachandra
Differential Revision: https://reviews.llvm.org/D146203
Mikhail R. Gadelha [Fri, 31 Mar 2023 15:58:58 +0000 (12:58 -0300)]
[RISCV] Lower inline asm m with offset to register+imm.
As part of D145584, we noticed that llvm was generating suboptimal code
for constraint m when the operand can be be lowered to reg+imm form: it
was being selected as a single register rather than register+imm. This
caused an unnecessary 'addi' to be gen for each m constraint.
This patch changes llvm to select register+imm. This might generate code
that cannot be assembled, but matches gcc's behavior.
Reviewed By: craig.topper, kito-cheng
Differential Revision: https://reviews.llvm.org/D146245
LLVM GN Syncbot [Fri, 31 Mar 2023 16:12:58 +0000 (16:12 +0000)]
[gn build] Port
a084854266ca
Philip Reames [Fri, 31 Mar 2023 15:49:44 +0000 (08:49 -0700)]
[LV] Add tests for non-constant stride pointer inductions
Reduced from the case which triggered the revert of
498aa534f472, and then generalized to cover both expansion paths.
Piotr Zegar [Fri, 31 Mar 2023 15:28:12 +0000 (15:28 +0000)]
[clang-tidy] Add readability-operators-representation check
Check helps enforce consistent token representation for binary, unary and
overloaded operators in C++ code. The check supports both traditional and
alternative representations of operators.
Reviewed By: carlosgalvezp
Differential Revision: https://reviews.llvm.org/D144522
Roy Sundahl [Thu, 23 Mar 2023 17:53:11 +0000 (10:53 -0700)]
[sanitizers] Explainer about dyld and weak overrides on Darwin. (NFC)
Explain in the release notes that the Darwin dynamic linker (dyld) requires
that at least one weak symbol be present in any mach-o file that defines an
intended override of a sanitizer dylib weak reference.
rdar://
103453678
Reviewed By: thetruestblue
Differential Revision: https://reviews.llvm.org/D146745
Roy Sundahl [Thu, 23 Mar 2023 15:49:43 +0000 (08:49 -0700)]
[utils] Give git a dummy email address when cherry picking.
Git wants an email address these days. (Also a nit typo.)
Reviewed By: XiaodongLoong
Differential Revision: https://reviews.llvm.org/D146728
Jay Foad [Fri, 31 Mar 2023 15:47:03 +0000 (16:47 +0100)]
[PowerPC] Fix UNSUPPORTED syntax in addr-label.ll
Alex Brachet [Fri, 31 Mar 2023 15:18:35 +0000 (15:18 +0000)]
[libc] Fix UBSan error after D147171
Differential Revision: https://reviews.llvm.org/D147258
Nikita Popov [Fri, 31 Mar 2023 14:56:56 +0000 (16:56 +0200)]
[ValueTracking] Fix incorrect computeConstantRange() arguments
The second argument is ForSigned, not UseInstrInfo.
Nikita Popov [Fri, 31 Mar 2023 14:54:45 +0000 (16:54 +0200)]
[InstCombine] Add extra test for non-overflowing usub.sat (NFC)
Same as the existing one, but with both nuw and nsw on the add.
Jie Fu [Fri, 31 Mar 2023 14:52:46 +0000 (22:52 +0800)]
[InstCombine] Fix -Wimplicit-fallthrough in InstCombinerImpl::visitCallInst (NFC)
/data/llvm-project/llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp:3078:3: error: unannotated fall-through between switch labels [-Werror,-Wimplicit-fallthrough]
default:
^
/data/llvm-project/llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp:3078:3: note: insert 'break;' to avoid fall-through
default:
^
break;
1 error generated.
Simon Pilgrim [Fri, 31 Mar 2023 14:44:41 +0000 (15:44 +0100)]
[X86] MatchVectorAllZeroTest - add support for icmp(bitcast(icmp_ne(X,Y)),0) vector reduction patterns
Many allof/anyof/noneof reduction patterns are canonicalized by bitcasting a vXi1 vector comparison result to iN and compared against 0/-1.
This patch adds support for recognizing a icmp_ne vector comparison against 0, which matches an 'whole vectors are equal' comparison pattern.
There are a few more steps to follow in future patches - we need to add support to MatchVectorAllZeroTest for comparing against -1 (in some cases), and this initial refactoring of LowerVectorAllZero to LowerVectorAllEqual needs to be extended so we can fully merge with the similar combineVectorSizedSetCCEquality code (which deals with scalar integer memcmp patterns).
Another step towards Issue #53419
Differential Revision: https://reviews.llvm.org/D147243
Stefan Pintilie [Fri, 31 Mar 2023 14:14:29 +0000 (10:14 -0400)]
[NFC][PowerPC] Marked the addr-label.ll test unsupported on PowerPC.
The addr-label.ll test uses the following setup:
define ptr @test1() nounwind {
entry:
ret ptr blockaddress(@test1b, %test_label)
}
define i32 @test1b() nounwind {
entry:
ret i32 -1
test_label:
br label %ret
ret:
ret i32 -1
}
However, according to the LLVM Reference guide for blockaddress()
"This value only has defined behavior when used as an operand to the
‘indirectbr’ or for comparisons against null." For this test the value
is just returned as a pointer from test1().
On PowerPC this test has unreliable results as the order in which
passes are run can make this test pass or fail. If the %test_label
in test1b() is removed before a number of passes are completed on
test1() then this test will fail on PowerPC.
I have marked this test as UNSUPPORTED on PowerPC.
David Green [Fri, 31 Mar 2023 14:38:27 +0000 (15:38 +0100)]
[InterleaveAccess] Check that binop shuffles have an undef second operand
It is expected that shuffles that we hoist through binops only have a single
vector operand, the other being undef/poison. The checks for
isDeInterleaveMaskOfFactor check that all the elements come from inside the
first vector, but with non-canonical shuffles the second operand could still
have a value. Add a quick check to make sure it is UndefValue as expected, to
make sure we don't run into problems with BinOpShuffles not using BinOps.
Fixes #61749
Differential Revision: https://reviews.llvm.org/D147306
Nikita Popov [Fri, 31 Mar 2023 11:27:02 +0000 (13:27 +0200)]
[InstCombine] Fold more intrinsics over selects
Move this handling to a centralized place and extend it to handle
saturating add/sub intrinsics.
I originally wanted to make this fully generic rather than
whitelist based, because this is legal and likely profitable for all
speculatable intrinsics. The caveat is that for vector selects,
the intrinsic can't perform cross-lane operations like a shuffle
or reduction, which we don't really expose as a generic property
right now. So for now I'm just extending the list.
Timm Bäder [Thu, 26 Jan 2023 13:07:46 +0000 (14:07 +0100)]
[clang][Interp] Check This pointer without creating InterpFrame
The InterpFrame was only created so early so we could use getThis().
However, we need to know the Function when creating the InterpFrame and
in the case of virtual functions, we need to determine what function to
call at interpretation time.
Get the This pointer ourselves and just create the InterpFrame later.
Differential Revision: https://reviews.llvm.org/D142617
Nikita Popov [Fri, 31 Mar 2023 14:09:23 +0000 (16:09 +0200)]
[InstCombine] Add additional test cases for folding intrinsic into select (NFC)
Test cross-lane intrinsics with vector selects.
Nikita Popov [Fri, 31 Mar 2023 14:10:30 +0000 (16:10 +0200)]
[InstCombine] Regenerate test checks (NFC)
Qiongsi Wu [Fri, 31 Mar 2023 13:47:07 +0000 (09:47 -0400)]
[AIX][CodeGen] Renaming mroptr to xcoff-mroptr
This patch renames the `mroptr` option to `mxcoff-roptr` to indicate in the option itself that it is xcoff specific.
Reviewed By: hubert.reinterpretcast
Differential Revision: https://reviews.llvm.org/D147161
Jay Foad [Thu, 30 Mar 2023 16:31:33 +0000 (17:31 +0100)]
[AMDGPU] Don't bother to use OffsetMode to define Real SMEM instructions
Various Real classes took an OffsetMode parameter, but only used it
to extract the suffix for the name of the corresponding pseudo. I found
this confusing because you couldn't usefully define and use a different
OffsetMode here, e.g. one with different operand types to affect how the
instruction was printed.
Overall I think it's simpler to just pass in the suffixed pseudo name
directly.
Differential Revision: https://reviews.llvm.org/D147242
Jay Foad [Wed, 29 Mar 2023 14:11:08 +0000 (15:11 +0100)]
[AMDGPU] Do not reserve 16-bit registers
There should be no need to reserve all SGPR hi16/lo16 halves, or all
AGPR hi16 halves. This should be done by marking the corresponding
register classes as not allocatable instead.
Differential Revision: https://reviews.llvm.org/D147158
Timm Bäder [Tue, 24 Jan 2023 11:11:45 +0000 (12:11 +0100)]
[clang][Interp] Handle TypeTraitExprs
Differential Revision: https://reviews.llvm.org/D142448
Nikita Popov [Fri, 31 Mar 2023 11:37:08 +0000 (13:37 +0200)]
[InstCombine] Add additional test for folding intrinsic into select (NFC)
Timm Bäder [Mon, 16 Jan 2023 10:13:52 +0000 (11:13 +0100)]
[clang][Interp] Fix double-printing InterpFrame::describe()
Differential Revision: https://reviews.llvm.org/D141831
Florian Hahn [Fri, 31 Mar 2023 13:24:43 +0000 (14:24 +0100)]
[AArch64] Add cost model tests for fshl intrinsics.
Tests for D147322.
OCHyams [Fri, 31 Mar 2023 13:17:52 +0000 (14:17 +0100)]
[Assignment Tracking] Remove assertion from DbgAssignIntrinsic::setAddress
Follow up to https://reviews.llvm.org/D146987.
Remove assertion that the Value must be a pointer type. This fires in
real-world examples e.g. by codegenprepare introducing ptrtoint conversions.
The buildbots have not caught up yet but without this change the test
compiler-rt/test/ubsan/TestCases/TypeCheck/vptr.cpp fails with an ICE.
Timm Bäder [Sun, 15 Jan 2023 08:27:11 +0000 (09:27 +0100)]
[clang][Interp] Fix binary comma operators
We left the result of RHS on the stack in case DiscardResult was true.
Differential Revision: https://reviews.llvm.org/D141784
Joseph Huber [Fri, 31 Mar 2023 12:28:08 +0000 (07:28 -0500)]
[libc][NFC] Adjust some CMake messages for the GPU build
Summary:
This disables the MPFR warning on the GPU since we can't support it
anyway. Also fixes a misspelled message.
Aaron Ballman [Fri, 31 Mar 2023 12:20:09 +0000 (08:20 -0400)]
Fix a simple think-o; NFC
This was using a bitwise OR of two boolean member variables, now it's
using a logical OR instead.
Benjamin Kramer [Fri, 31 Mar 2023 12:20:01 +0000 (14:20 +0200)]
[bazel] Port
9d2b84ef6232
Leandro Lupori [Tue, 28 Mar 2023 14:28:56 +0000 (14:28 +0000)]
[flang] Don't fold operation when shapes differ
When folding a binary operation between two array constructors, it
is necessary to check if each value contained in the left operand
has the same rank and shape as the one on the right.
Otherwise, lowering would end up with an operation between values
of different ranks/shapes, which could result in a crash.
For instance, the following code was crashing the compiler:
integer :: x(4), y(2, 2), z(4)
z = (/x/) + (/y/)
Fixes #60229
Reviewed By: klausler, jeanPerier
Differential Revision: https://reviews.llvm.org/D147181
tyb0807 [Thu, 30 Mar 2023 20:40:51 +0000 (20:40 +0000)]
[mlir] Fix casting of leading unit dims for vector.insert
When dropping leading unit dims of vector.insert's operands and creating
a new vector.insert, its new position rank should be computed explicitly
in two steps: first based on the numbers of leading unit dims dropped
from the vector.insert's destination, then based on the numbers of
leading unit dims dropped from its source.
Reviewed By: pifon2a
Differential Revision: https://reviews.llvm.org/D147280
Tobias Gysi [Fri, 31 Mar 2023 11:45:21 +0000 (11:45 +0000)]
[mlir][llvm] Import pointer data layout specification.
The revision moves the data layout parsing into a separate file
and extends it to support pointer data layout specifications.
Additionally, it also produces more precise warnings and error
messages.
Reviewed By: Dinistro, definelicht
Differential Revision: https://reviews.llvm.org/D147170
Nikita Popov [Fri, 31 Mar 2023 11:46:16 +0000 (13:46 +0200)]
[InstCombine] Remove min/max special case when folding into select
Now that we canonicalize to min/max intrinsics, we no longer need
to guard against this here.
In fact, it seems like the issue from PR46271 was the final push
for introducing the intrinsics in the first place...
Vir Narula [Fri, 31 Mar 2023 11:40:04 +0000 (12:40 +0100)]
[Matrix] Add special case dot product lowering
Add special case to matrix lowering for dot products. Normal matrix lowering if optimized for either row-major or column-major, which results in many `shufflevector` instructions being generated for one vector. We work around this in our special case. We can also use vector-reduce adds instead of sequential adds to sum the result of the element-wise multiplication, which takes advantage of SIMD instructions.
Reviewed By: fhahn, thegameg
Differential Revision: https://reviews.llvm.org/D131125
OCHyams [Fri, 31 Mar 2023 11:22:02 +0000 (12:22 +0100)]
[Assignment Tracking] Enable by default
See https://discourse.llvm.org/t/rfc-enable-assignment-tracking/69399
This sets the `-Xclang -fexperimental-assignment-tracking` flag to the value
`enabled` which means it will be enabled so long as none of the following are
true: it's an LTO build, LLDB debugger tuning has been specified, or it's an O0
build (no work is done in any case if -g is not specified or -gmlt is used).
Reviewed By: jmorse
Differential Revision: https://reviews.llvm.org/D146987
OCHyams [Fri, 31 Mar 2023 11:06:35 +0000 (12:06 +0100)]
[Assignment Tracking][SROA] Handle DIArgList in migrateDebugInfo
If the to-be-split dbg.assign has a `DIArgList` and a new `Value` has been
requested then use a kill-location for the new dbg.assign. We can't simply
replace the value component (a `DIArgList`) with the new `Value` as that would
leave the `DIExpression` in an invalid state (`DW_OP_LLVM_arg` operands with no
arglist).
Reviewed By: jmorse
Differential Revision: https://reviews.llvm.org/D147312
Nikita Popov [Fri, 31 Mar 2023 11:29:43 +0000 (13:29 +0200)]
[InstCombine] Regenerate test checks (NFC)
Florian Hahn [Fri, 31 Mar 2023 11:32:40 +0000 (12:32 +0100)]
[Matrix] Update most dot tests using vXi64 to vXi32.
Update dot-product-int.ll tests to use mostly i32 instead of i64;
there's no mul.2d instruction, so vector versions of v2i64 cannot be
lowered efficiently.
Timm Bäder [Sat, 14 Jan 2023 18:24:49 +0000 (19:24 +0100)]
[clang][Interp] Fix record initialization via CallExpr subclasses
We can't just use VisitCallExpr() here, as that doesn't handle CallExpr
subclasses such as CXXMemberCallExpr.
Differential Revision: https://reviews.llvm.org/D141772
Stefan Gränitz [Fri, 31 Mar 2023 10:48:16 +0000 (12:48 +0200)]
[Orc] Drop arch check in the DebugObjectManagerPlugin for ELF
Tested this with the new AArch32 backend on armv7l and it works without issues in GDB. The size of the load-address field is only 32-bit here, but we implicitly account for it by writing a ELFT::uint which is:
https://github.com/llvm/llvm-project/blob/release/16.x/llvm/include/llvm/Object/ELFTypes.h#L57
So, instead of adding a newly supported machine type, let's just drop this restriction althogether.
Dominik Adamski [Thu, 30 Mar 2023 13:42:53 +0000 (08:42 -0500)]
[MLIR][OpenMP][Flang] Set OpenMP target attributes in MLIR module
Scope of changes:
1) Add attribute to OpenMP MLIR dialect which stores target cpu and
target features
2) Store target information in MLIR module
Differential Revision: https://reviews.llvm.org/D146612
Reviewed By: kiranchandramohan
Co-authored-by: Kiran Chandramohan <kiran.chandramohan@arm.com>
Ingo Müller [Thu, 30 Mar 2023 12:40:46 +0000 (12:40 +0000)]
[mlir] Use GenericAdaptor to simplify 1:N type conversion API.
For 1:N type conversion, there is a 1:N relationship between the
original operands and the converted operands. The same is true for the
results. The previous design passed an instance of a "mapping" class
into each pattern that helped with handling this 1:N correspondance.
However, this was still rather manual and, in particular, it required
the use of magic constants for the indices of the different operands.
This commits uses the generated GenericAdaptor class that is generated
for each op class in order to simplify this relationship further. The
GenericAdaptor allows to wrap around a list of arbitrary types for each
operand (via templating); for 1:N type conversion, this allows the
operand accessors of the adaptor class to return a ValueRange that
corresponds to the N values in the converted types. Patterns can thus
use the named accessors instead of magic constants, which eliminates a
common class of errors.
This commit further simplifies the API that patterns need to implement
by making the operand and result type mappings part of the adaptor.
Since many patterns only need one of the two (or even neither), this
reduces the number of unnecessary arguments in many cases.
Reviewed By: springerm
Differential Revision: https://reviews.llvm.org/D147225
pvanhout [Fri, 31 Mar 2023 10:26:27 +0000 (12:26 +0200)]
Revert "[AMDGPU] Select v_sat_pk_u8_i16"
This reverts commit
64b45db34a0cd979dae9ca3016e9da517e57b987.
Reason: the patterns are wrong which can result in a miscompilation.
However, fixing the pattern is not trivial due to how i8 values
are handled, and due to the additional type-checking performed by
D147127: trunc/smax/smin are all defined as int ops in the DAG
despite them working on vectors too.
As this is not a much-needed pattern, I prefer reverting for now
until I can find time to properly rewrite the pattern.
Nicolas Vasilache [Fri, 31 Mar 2023 10:22:03 +0000 (03:22 -0700)]
[mlir][Transform] NFC - Fix spurious reflows
Nikita Popov [Fri, 31 Mar 2023 10:18:02 +0000 (12:18 +0200)]
[Local] Handle size mismatch between pointer/int in copyRangeMetadata()
SROA may convert a wide integer load into a narrow pointer load,
make sure we don't crash. It would not be legal to transfer the
metadata in this case.
LLVM GN Syncbot [Fri, 31 Mar 2023 10:15:05 +0000 (10:15 +0000)]
[gn build] Port
868654e5495c
Alexey Lapshin [Wed, 29 Mar 2023 10:58:21 +0000 (12:58 +0200)]
[DWARFLinkerParallel] Add StringPool class.
This patch is extracted from D96035. It adds StringPool class.
StringPool allows to store strings in parallel. It also allows
to have string data associated with the concrete string.
Reviewed By: JDevlieghere
Differential Revision: https://reviews.llvm.org/D140841
Jay Foad [Fri, 31 Mar 2023 10:10:25 +0000 (11:10 +0100)]
[AMDGPU] Fix whitespace after D147216
David Green [Fri, 31 Mar 2023 10:08:50 +0000 (11:08 +0100)]
Revert "[IVDescriptors] Add pointer InductionDescriptors with non-constant strides"
Multiple errors have being reported on
https://reviews.llvm.org/rG498aa534f472d28db893aa9a8627d0b46e17f312
Reverting until the correctness issues can be resolved.
We are also seeing a lot of performance differences from the patch. Some are
looking good, but some are looking pretty bad.
Stefan Gränitz [Fri, 31 Mar 2023 09:05:58 +0000 (11:05 +0200)]
[Orc] Add RequireDebugSections option in the DebugObjectManagerPlugin
Sometimes it's useful to be able and debug code even without actual debug info, e.g. for setting breakpoints on function names.
This patch adds a new API option to make it possible in Orc.
The existing API and behavior remains unchanged: non-debug objects are not passed to exectuors.
Stefan Gränitz [Fri, 31 Mar 2023 09:59:55 +0000 (11:59 +0200)]
[Orc] Reflow comment and improve name after fix (NFC)
Luo, Yuanke [Fri, 31 Mar 2023 09:49:42 +0000 (17:49 +0800)]
[Coverity] Initialize pointer memeber.
Simon Pilgrim [Fri, 31 Mar 2023 09:34:10 +0000 (10:34 +0100)]
ARMFrameLowering.cpp - fix MSVC "result of 32-bit shift implicitly converted to 64 bits" warning. NFC.
Benjamin Kramer [Fri, 31 Mar 2023 09:32:53 +0000 (11:32 +0200)]
[Orc] Avoid unused variable warning in builds without asserts
DebugObjectManagerPlugin.cpp:372:8: error: unused variable 'ItInserted' [-Werror,-Wunused-variable]
auto ItInserted = Sections.try_emplace(Name, std::move(Section));
^
Benjamin Kramer [Fri, 31 Mar 2023 09:02:42 +0000 (11:02 +0200)]
[mlir] Add REQUIRES: asserts to test that uses -debug-only
That flag only exists when assertions are enabled.
Stefan Gränitz [Fri, 31 Mar 2023 08:43:29 +0000 (10:43 +0200)]
[Orc] Refactor debug section requirements into a more flexible flags field (NFC)
When the initial DebugObjectManagerPlugin landed, it was not clear whether we will have more patching requirements for debug section. Also, there were no other use-cases for debug object flags.
Adding options to the plugin gives us a use-case and we can re-use the field for it. This commit only refactors the infrastructure in preparation for two more patches to come.
Stefan Gränitz [Fri, 31 Mar 2023 08:21:35 +0000 (10:21 +0200)]
[Orc] Filter sections for debug load-address patching upfront
Originally, the DebugObjectManagerPlugin recorded all sections and filtered some of them for load-address patching.
Then we spotted problems with duplicate section names and started additional filtering upfront (see
b26f45e5a49ae363164e7dbbf57eadd9e78d612c).
This seems the better approach. Let's go for it and stop filtering in two locations.
Stefan Gränitz [Fri, 31 Mar 2023 07:56:23 +0000 (09:56 +0200)]
[Orc] Skip sections with duplicate names in DebugObjectManagerPlugin
Compiler-generated section names can clash. Examples are group sections or profile counter sections.
We don't need to abort debug registration for the entire LinkGraph in such a case.
Instead, let's skip the relevant sections and add a note to the debug log.
Jay Foad [Wed, 29 Mar 2023 09:36:03 +0000 (10:36 +0100)]
[TableGen] Enable "Type set is empty for each HW mode" error in non-debug builds
Differential Revision: https://reviews.llvm.org/D147127
Andrzej Warzynski [Fri, 31 Mar 2023 07:47:02 +0000 (07:47 +0000)]
[mlir][sparse-compiler] Fix typo in a test
This patch fixes a type that was introduced in
https://reviews.llvm.org/D146917 and that triggered buildbot failure:
* https://lab.llvm.org/buildbot#builders/220/builds/18225
This is rather straightforward (and fixes a bogus test failure), hence
sending without a review.
Serguei Katkov [Fri, 31 Mar 2023 07:28:07 +0000 (14:28 +0700)]
[InstCombine] Add tests for min(a,b) +/* max(a,b) pattern.
Nicolas Vasilache [Fri, 31 Mar 2023 07:29:20 +0000 (00:29 -0700)]
[mlir][Transform] NFC - Make debug logging more actionnable
Nicolas Vasilache [Wed, 29 Mar 2023 16:06:53 +0000 (09:06 -0700)]
[mlir][Linalg] Fix Generalize transform
Generalize used to fail on ops that have a null region builder.
This is incorrect, the test should be whether the op has a region or not.
In the future we may want to support 0-region ops with a region builder.
Differential Revision: https://reviews.llvm.org/D147166
Andrzej Warzynski [Sat, 25 Mar 2023 20:01:34 +0000 (20:01 +0000)]
[mlir-cpu-runner] Add support for `-mattr` and `-march` flags
This patch adds support for `-mattr` and `-march` in mlir-cpu-runner.
With this change, one should be able to consistently use mlir-cpu-runner
for MLIR's integration tests (instead of e.g. resorting to lli when some
additional flags are needed). This is demonstrated in
concatenate_dim_1.mlir.
In order to support the new flags, this patch makes sure that
MLIR's ExecutionEngine/JITRunner (that mlir-cpu-runner is built on top of):
* takes into account the new command line flags when creating
TargetMachine,
* avoids recreating TargetMachine if one is already available,
* creates LLVM's DataLayout based on the previously configured
TargetMachine.
This is necessary in order to make sure that the command line
configuration is propagated correctly to the backend code generator.
A few additional updates are made in order to facilitate this change,
including support for debug dumps from JITRunner.
Differential Revision: https://reviews.llvm.org/D146917
Jie Fu [Fri, 31 Mar 2023 07:29:23 +0000 (15:29 +0800)]
[flang] Remove unused variable 'nullBoxTy' in ConvertExpr.cpp (NFC)
/data/llvm-project/flang/lib/Lower/ConvertExpr.cpp:728:10: error: unused variable 'nullBoxTy' [-Werror,-Wunused-variable]
auto nullBoxTy = builder.getRefType(fir::BoxType::get(noneTy));
^
1 error generated.
Martin Storsjö [Thu, 30 Mar 2023 10:31:58 +0000 (13:31 +0300)]
[ARM] Handle generating SEH unwind info for t2STR_PRE/t2LDR_POST
This fixes compiling some uncommon cases.
Differential Revision: https://reviews.llvm.org/D147212
Jean Perier [Fri, 31 Mar 2023 07:13:52 +0000 (09:13 +0200)]
[flang] Fix context less NULL() lowering
The current context less lowering of NULL is producing invalid code
(can lead to reading outside of allocated memory): it is casting
a simple pointer to a descriptor address.
Later, reads are made to this descriptor. It used to be "OK" when
fir.load of fir.box were no-ops, but this was incorrect, and the
fir.load codegen is known doing a copy, and read the whole descriptor
data, not only the base address.
The previous patch that allowed fir.box<None> allocation, this
code fix this by allocating an actual fir.box<None>.
Note: this is still an overkill way to lower foo(null()). HLFIR
lowering always contextualize NULL() lowering leading to much simpler
code:
```
%absent = fir.absent fir.box<T>
fir.call @foo(%absent)
```
Differential Revision: https://reviews.llvm.org/D147239
Jean Perier [Fri, 31 Mar 2023 07:12:43 +0000 (09:12 +0200)]
[flang] allow allocation of scalar TYPE(*) descriptors
Currently, it is OK to have alloca/store/and reboxed to
fir.box<!fir.array<?xnone>> and fir.class<none>, but not simple
fir.box<none>.
This restriction is a legacy from a time where it was thought TYPE(*)
descriptor size would not be statically known, but the way polymorphism
was implemented actually allows knowing its size: a scalar descriptor
with an addendum (in case it is a derived type).
Note that this assumes fir.box<none> are always scalars. There are currently
a few cast from ranked descriptor to !fir.box<None> around runtime calls.
These are simple casts before runtime call, so there are no load/stores
to the resulting fir.box<None> and it is OK.
When assumed rank are supported, some legacy usage of fir.box<none> as the "any"
descriptor in the runtime interface will be replaced to avoid any issues there.
This change will be required to fix an undefined behavior with NULL() that
requires allocation of a fir.box<None>.
Differential Revision: https://reviews.llvm.org/D147237
Jean Perier [Fri, 31 Mar 2023 07:07:29 +0000 (09:07 +0200)]
[flang] move ASSOCIATED intrinsic optional TARGET handling
ASSOCIATED intrinsic TARGET handling is weird for OPTIONAL, because as
opposed to other intrinsic arguments, OPTIONAL allocatable and pointers
may be absent when passed to it, and a diassociated pointer TARGET is not
the same as when TARGET is not provided. Hence, it needs custom
handling in lowering.
The handling was done late (in genIntrinsicCall, without the semantic
context), and assumed it would be possible to retrieve the optionality
aspects, but this is brittle, and hard to share with HLFIR.
Move it in CustomIntrinsicCall that is intended to deal with these
corner case.
Also avoid using fir.box<None> as the related fir.if result, and used
the correct fir.box/fir.class type for the target: using a fir.box<None>
here is risky since fir.box<None> are now meant for scalar TYPE(*), and
the TARGET may be ranked.
Move the introduction of the fir.box<None> around the runtime (when
assumed rank are supported, these will become !fir.box<!fir.array<..xNone>>).
Differential Revision: https://reviews.llvm.org/D147224
Ben Shi [Fri, 31 Mar 2023 01:34:37 +0000 (09:34 +0800)]
[LoongArch] Optimize additions with immediates
Reviewed By: SixWeining, xen0n
Differential Revision: https://reviews.llvm.org/D147222
Ben Shi [Thu, 30 Mar 2023 07:56:10 +0000 (15:56 +0800)]
[LoongArch][NFC] Add tests of additions with immediates (for D147222)
Reviewed By: SixWeining, xen0n, XiaodongLoong
Differential Revision: https://reviews.llvm.org/D147221