Fangrui Song [Fri, 6 Sep 2019 09:23:17 +0000 (09:23 +0000)]
[yaml2obj] Rename SHOffset (e_shoff) field to SHOff. NFC
`struct Elf*_Shdr` has a field `sh_offset`, named `ShOffset` in
llvm::ELFYAML::Section. Rename SHOffset (e_shoff) to SHOff to prevent confusion.
Reviewed By: grimar
Differential Revision: https://reviews.llvm.org/D67254
llvm-svn: 371185
Matthias Gehre [Fri, 6 Sep 2019 08:56:30 +0000 (08:56 +0000)]
Reland [LifetimeAnalysis] Support more STL idioms (template forward declaration and DependentNameType)
Reland after https://reviews.llvm.org/D66806 fixed the false-positive diagnostics.
Summary:
This fixes inference of gsl::Pointer on std::set::iterator with libstdc++ (the typedef for iterator
on the template is a DependentNameType - we can only put the gsl::Pointer attribute
on the underlaying record after instantiation)
inference of gsl::Pointer on std::vector::iterator with libc++ (the class was forward-declared,
we added the gsl::Pointer on the canonical decl (the forward decl), and later when the
template was instantiated, there was no attribute on the definition so it was not instantiated).
and a duplicate gsl::Pointer on some class with libstdc++ (we first added an attribute to
a incomplete instantiation, and then another was copied from the template definition
when the instantiation was completed).
We now add the attributes to all redeclarations to fix thos issues and make their usage easier.
Reviewers: gribozavr
Subscribers: Szelethus, xazax.hun, cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D66179
llvm-svn: 371182
Raphael Isemann [Fri, 6 Sep 2019 08:40:31 +0000 (08:40 +0000)]
[lldb][NFC] Remove Args::StripSpaces
This just reimplemented llvm::StringRef::[r/l]trim().
llvm-svn: 371181
Raphael Isemann [Fri, 6 Sep 2019 08:39:53 +0000 (08:39 +0000)]
[lldb][NFC] Extend ArgsTest
llvm-svn: 371180
Sam Parker [Fri, 6 Sep 2019 08:24:41 +0000 (08:24 +0000)]
[ARM] MVE Tail Predication
The MVE and LOB extensions of Armv8.1m can be combined to enable
'tail predication' which removes the need for a scalar remainder
loop after vectorization. Lane predication is performed implicitly
via a system register. The effects of predication is described in
Section B5.6.3 of the Armv8.1-m Arch Reference Manual, the key points
being:
- For vector operations that perform reduction across the vector and
produce a scalar result, whether the value is accumulated or not.
- For non-load instructions, the predicate flags determine if the
destination register byte is updated with the new value or if the
previous value is preserved.
- For vector store instructions, whether the store occurs or not.
- For vector load instructions, whether the value that is loaded or
whether zeros are written to that element of the destination
register.
This patch implements a pass that takes a hardware loop, containing
masked vector instructions, and converts it something that resembles
an MVE tail predicated loop. Currently, if we had code generation,
we'd generate a loop in which the VCTP would generate the predicate
and VPST would then setup the value of VPR.PO. The loads and stores
would be placed in VPT blocks so this is not tail predication, but
normal VPT predication with the predicate based upon a element
counting induction variable. Further work needs to be done to finally
produce a true tail predicated loop.
Because only the loads and stores are predicated, in both the LLVM IR
and MIR level, we will restrict support to only lane-wise operations
(no horizontal reductions). We will perform a final check on MIR
during loop finalisation too.
Another restriction, specific to MVE, is that all the vector
instructions need operate on the same number of elements. This is
because predication is performed at the byte level and this is set
on entry to the loop, or by the VCTP instead.
Differential Revision: https://reviews.llvm.org/D65884
llvm-svn: 371179
Kang Zhang [Fri, 6 Sep 2019 08:16:18 +0000 (08:16 +0000)]
[CodeGen] Do the Simple Early Return in block-placement pass to optimize the blocks
Summary:
Fix a bug of not update the jump table and recommit it again.
In `block-placement` pass, it will create some patterns for unconditional we can do the simple early retrun.
But the `early-ret` pass is before `block-placement`, we don't want to run it again.
This patch is to do the simple early return to optimize the blocks at the last of `block-placement`.
Reviewed By: efriedma
Differential Revision: https://reviews.llvm.org/D63972
llvm-svn: 371177
Raphael Isemann [Fri, 6 Sep 2019 07:54:47 +0000 (07:54 +0000)]
[lldb][NFC] Remove unused Args::GetArgumentQuoteCharAtIndex
llvm-svn: 371176
Simon Atanasyan [Fri, 6 Sep 2019 07:23:02 +0000 (07:23 +0000)]
[mips] Make another set of test cases more tolerant to exact symbol addresses. NFC
llvm-svn: 371174
David Zarzycki [Fri, 6 Sep 2019 07:12:36 +0000 (07:12 +0000)]
[CMake] LLVM_COMPILE_FLAGS also applies to C files
LLVM_COMPILE_FLAGS also applies to C files, otherwise tuning flags,
etc. won't be picked up.
https://reviews.llvm.org/D67171
llvm-svn: 371173
Raphael Isemann [Fri, 6 Sep 2019 07:11:14 +0000 (07:11 +0000)]
[lldb] Remove xcode bot from website listing and fix link to sanitized
llvm-svn: 371172
Mikael Holmen [Fri, 6 Sep 2019 06:55:54 +0000 (06:55 +0000)]
[MIR] Change test case to read from stdin instead of file
The
;CHECK: bb
;CHECK-NEXT: %namedVReg1353:_(p0) = COPY $d0
parts of the test case failed when the tests were placed in a directory
including "bb" in the path, since the full path of the file is then
output in the
; ModuleID = '/repo/bb/
line which the CHECK matched on and then the CHECK-NEXT failed.
llvm-svn: 371171
Craig Topper [Fri, 6 Sep 2019 06:02:17 +0000 (06:02 +0000)]
[X86] Add tests for extending and truncating between v16i8 and v16i64 with min-legal-vector-width=256.
It looks like we might be able to do these in fewer steps, but
I'm not sure.
llvm-svn: 371170
Craig Topper [Fri, 6 Sep 2019 06:02:13 +0000 (06:02 +0000)]
[X86] Prevent passing vectors of __int128 as <X x i128> in llvm IR
As far as I can tell, gcc passes 256/512 bit vectors __int128 in memory. And passes a vector of 1 _int128 in an xmm register. The backend considers <X x i128> as an illegal type and will scalarize any arguments with that type. So we need to coerce the argument types in the frontend to match to avoid the illegal type.
I'm restricting this to change to Linux and NetBSD based on the
how similar ABI changes have been handled in the past.
PS4, FreeBSD, and Darwin are unaffected. I've also added a
new -fclang-abi-compat version to restore the old behavior.
This issue was identified in PR42607. Though even with the types changed, we still seem to be doing some unnecessary stack realignment.
llvm-svn: 371169
Craig Topper [Fri, 6 Sep 2019 06:02:06 +0000 (06:02 +0000)]
[X86] Pre-commit vector of __int128 test cases for D64672.
llvm-svn: 371168
Craig Topper [Fri, 6 Sep 2019 05:50:46 +0000 (05:50 +0000)]
[X86] Fix bad indentation. NFC
llvm-svn: 371167
Aleksandr Urakov [Fri, 6 Sep 2019 05:37:03 +0000 (05:37 +0000)]
[Windows] Add support of watchpoints to `ProcessWindows`
Summary:
This patch adds support of watchpoints to the old `ProcessWindows` plugin.
The `ProcessWindows` plugin uses the `RegisterContext` to set and reset
watchpoints. The `RegisterContext` has some interface to access watchpoints,
but it is very limited (e.g. it is impossible to retrieve the last triggered
watchpoint with it), that's why I have implemented a slightly different
interface in the `RegisterContextWindows`. Moreover, I have made the
`ProcessWindows` plugin responsible for search of a vacant watchpoint slot,
because watchpoints exist per-process (not per-thread), then we can place
the same watchpoint in the same slot in different threads. With this scheme
threads don't need to have their own watchpoint lists, and it simplifies
identifying of the last triggered watchpoint.
Reviewers: asmith, stella.stamenova, amccarth
Reviewed By: amccarth
Subscribers: labath, zturner, leonid.mashinskiy, abidh, JDevlieghere, lldb-commits
Tags: #lldb
Differential Revision: https://reviews.llvm.org/D67168
llvm-svn: 371166
Alex Brachet [Fri, 6 Sep 2019 03:31:42 +0000 (03:31 +0000)]
Fix rL371162 again
llvm-svn: 371164
Alex Brachet [Fri, 6 Sep 2019 02:56:48 +0000 (02:56 +0000)]
Fix failing test from rL371162
llvm-svn: 371163
Alex Brachet [Fri, 6 Sep 2019 02:27:55 +0000 (02:27 +0000)]
[yaml2obj] Make e_phoff and e_phentsize 0 if there are no program headers
Summary: It says [[ http://www.sco.com/developers/gabi/latest/ch4.eheader.html | here ]] that if there are no program headers than e_phoff should be 0, but currently it is always set after the header. GNU's `readelf` (but not `llvm-readelf`) complains about this: `readelf: Warning: possibly corrupt ELF header - it has a non-zero program header offset, but no program headers`.
Reviewers: jhenderson, grimar, MaskRay, rupprecht
Reviewed By: jhenderson, grimar, MaskRay
Subscribers: hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D67054
llvm-svn: 371162
Nico Weber [Fri, 6 Sep 2019 01:22:13 +0000 (01:22 +0000)]
gn build: Merge r371159
llvm-svn: 371161
Fangrui Song [Fri, 6 Sep 2019 01:18:01 +0000 (01:18 +0000)]
Update SHT_LLVM_PART_EHDR test after r371157
llvm-svn: 371160
Jonas Devlieghere [Fri, 6 Sep 2019 01:13:32 +0000 (01:13 +0000)]
[MC] Fix undefined behavior in MCInstPrinter::formatHex
Passing INT64_MIN to MCInstPrinter::formatHex triggers undefined
behavior because the negation of -
9223372036854775808 cannot be
represented in type 'int64_t' (aka 'long long'). This patch puts a
workaround in place to just print the hex value directly.
A possible alternative involves using a small helper functions that uses
(implementation) defined conversions to achieve the desirable value:
static int64_t helper(int64_t V) {
auto U = static_cast<uint64_t>(V);
return V < 0 ? -U : U;
}
The underlying problem is that MCInstPrinter::formatHex(int64_t) returns
a format_object<int64_t> and should really return a
format_object<uint64_t>. However, that's not possible because formatImm
needs to be able to print both as decimal (where a signed is required)
and hex (where we'd prefer to always have an unsigned).
format_object<int64_t> formatImm(int64_t Value) const {
return PrintImmHex ? formatHex(Value) : formatDec(Value);
}
Differential revision: https://reviews.llvm.org/D67236
llvm-svn: 371159
Alina Sbirlea [Fri, 6 Sep 2019 00:58:03 +0000 (00:58 +0000)]
Cleanup test.
llvm-svn: 371158
Fangrui Song [Fri, 6 Sep 2019 00:53:28 +0000 (00:53 +0000)]
[llvm-readobj][yaml2obj] Support SHT_LLVM_SYMPART, SHT_LLVM_PART_EHDR and SHT_LLVM_PART_PHDR
See http://lists.llvm.org/pipermail/llvm-dev/2019-February/130583.html
and D60242 for the lld partition feature.
This patch:
* Teaches yaml2obj to parse the 3 section types.
* Teaches llvm-readobj/llvm-readelf to dump the 3 section types.
There is no test for SHT_LLVM_DEPENDENT_LIBRARIES in llvm-readobj. Add
it as well.
Reviewed By: thakis
Differential Revision: https://reviews.llvm.org/D67228
llvm-svn: 371157
Matt Arsenault [Fri, 6 Sep 2019 00:36:10 +0000 (00:36 +0000)]
AMDGPU/GlobalISel: Avoid repeating 32-bit type lists
llvm-svn: 371156
Matt Arsenault [Fri, 6 Sep 2019 00:36:06 +0000 (00:36 +0000)]
AMDGPU/GlobalISel: Fix load/store of types in other address spaces
There should probably be a size only matcher.
llvm-svn: 371155
Matt Arsenault [Fri, 6 Sep 2019 00:05:58 +0000 (00:05 +0000)]
GlobalISel/TableGen: Fix handling of EXTRACT_SUBREG constraints
This was only using the correct register constraints if this was the
final result instruction. If the extract was a sub instruction of the
result, it would attempt to use GIR_ConstrainSelectedInstOperands on a
COPY, which won't work. Move the handling to
createAndImportSubInstructionRenderer so it works correctly.
I don't fully understand why runOnPattern and
createAndImportSubInstructionRenderer both need to handle these
special cases, and constrain them with slightly different methods. If
I remove the runOnPattern handling, it does break the constraint when
the final result instruction is EXTRACT_SUBREG.
llvm-svn: 371150
Matt Arsenault [Thu, 5 Sep 2019 23:54:35 +0000 (23:54 +0000)]
AMDGPU: Allow getMemOperandWithOffset to analyze stack accesses
Report soffset as a base register if the scratch resource can be
ignored.
llvm-svn: 371149
Matt Arsenault [Thu, 5 Sep 2019 23:40:14 +0000 (23:40 +0000)]
AMDGPU: Fix emitting multiple stack loads for stack passed workitems
The same stack is loaded for each workitem ID, and each use. Nothing
prevents you from creating multiple fixed stack objects with the same
offsets, so this was creating a load for each unique frame index,
despite them being the same offset. Re-use the same frame index so the
loads are CSEable.
llvm-svn: 371148
Eli Friedman [Thu, 5 Sep 2019 23:40:03 +0000 (23:40 +0000)]
[AArch64] Add testcase for codegen for sdiv by 2.
llvm-svn: 371147
Matt Arsenault [Thu, 5 Sep 2019 23:39:21 +0000 (23:39 +0000)]
InstCombine: Fix crash on icmp of gep with addrspacecasted null
llvm-svn: 371146
Jonas Devlieghere [Thu, 5 Sep 2019 23:36:57 +0000 (23:36 +0000)]
[Reproducer] Add a `cont` to ModuleCXX.test
On more than one occasion I've found this test got stuck during replay
while waiting for a packet from debugserver when the debugger was in the
process of being destroyed. For some reason it's more prevalent on the
downstream Swift fork. Adding a cont mitigates the problem while I
investigate.
llvm-svn: 371144
David Blaikie [Thu, 5 Sep 2019 23:33:44 +0000 (23:33 +0000)]
llvm-reduce: Use %python from lit to get the correct/valid python binary for the reduction script
llvm-svn: 371143
Matt Arsenault [Thu, 5 Sep 2019 23:07:10 +0000 (23:07 +0000)]
AMDGPU: Fix Register copypaste error
llvm-svn: 371141
Alina Sbirlea [Thu, 5 Sep 2019 23:00:36 +0000 (23:00 +0000)]
[AliasSetTracker] Correct AAInfo check.
Properly check if NewAAInfo conflicts with AAInfo.
Update local variable and alias set that a change occured when a conflict is found.
Resolves PR42969.
llvm-svn: 371139
Vitaly Buka [Thu, 5 Sep 2019 22:49:34 +0000 (22:49 +0000)]
[SimplifyCFG] Don't SimplifyBranchOnICmpChain with ExtraCase
Summary:
Here we try to avoid issues with "explicit branch" with SimplifyBranchOnICmpChain
which can check on undef. Msan by design reports branches on uninitialized
memory and undefs, so we have false report here.
In general msan does not like when we convert
```
// If at least one of them is true we can MSAN is ok if another is undefs
if (a || b)
return;
```
into
```
// If 'a' is undef MSAN will complain even if 'b' is true
if (a)
return;
if (b)
return;
```
Example
Before optimization we had something like this:
```
while (true) {
bool maybe_undef = doStuff();
while (true) {
char c = getChar();
if (c != 10 && c != 13)
continue
break;
}
// we know that c == 10 || c == 13 if we get here,
// so msan know that branch is not affected by maybe_undef
if (maybe_undef || c == 10 || c == 13)
continue;
return;
}
```
SimplifyBranchOnICmpChain will convert that into
```
while (true) {
bool maybe_undef = doStuff();
while (true) {
char c = getChar();
if (c != 10 && c != 13)
continue;
break;
}
// however msan will complain here:
if (maybe_undef)
continue;
// we know that c == 10 || c == 13, so either way we will get continue
switch(c) {
case 10: continue;
case 13: continue;
}
return;
}
```
Reviewers: eugenis, efriedma
Reviewed By: eugenis, efriedma
Subscribers: hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D67205
llvm-svn: 371138
Matt Arsenault [Thu, 5 Sep 2019 22:44:06 +0000 (22:44 +0000)]
AMDGPU: Avoid constructing new std::vector in initCandidate
Approximately 30% of the time was spent in the std::vector
constructor. In one testcase this pushes the scheduler to being the
second slowest pass.
I'm not sure I understand why these vector are necessary. The default
scheduler initCandidate seems to use some pre-existing vectors for the
pressure.
llvm-svn: 371136
Nico Weber [Thu, 5 Sep 2019 22:40:47 +0000 (22:40 +0000)]
gn build: Merge r371134
llvm-svn: 371135
Francis Visoiu Mistrih [Thu, 5 Sep 2019 22:35:37 +0000 (22:35 +0000)]
[Remarks] Add comparison operators to the Remark object
and related structs.
This also adds tests for the remarks::Remark object in general.
llvm-svn: 371134
Jonas Devlieghere [Thu, 5 Sep 2019 21:43:32 +0000 (21:43 +0000)]
Remove `bugreport` command
The bugreport command exists to create domain-specific bug reports.
Currently it has one implementation for filing bugs on the unwinder. As
far as we can tell, it has never been of use. Although not exactly the
same as the reproducers, it's a bit confusing to have two parallel
command trees for (kind of) the same thing.
Differential revision: https://reviews.llvm.org/D65469
llvm-svn: 371132
Sterling Augustine [Thu, 5 Sep 2019 21:35:05 +0000 (21:35 +0000)]
Add gdb pretty printers for a wide variety of libc++ data structures (take 2).
Summary:
This patch is an exact duplicate of https://reviews.llvm.org/D65609, except
that it uses the newly introduced testing framework to detect if gdb is present
so that the tests won't fail on machines without gdb.
Reviewers: echristo, EricWF
Subscribers: christof, ldionne, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D67238
llvm-svn: 371131
Sterling Augustine [Thu, 5 Sep 2019 21:34:54 +0000 (21:34 +0000)]
Don't assume libcxx_gdb is always set.
libc++abi also uses this file, but doesn't use the same CMakeLists.txt.
llvm-svn: 371130
Jan Korous [Thu, 5 Sep 2019 21:27:25 +0000 (21:27 +0000)]
[ADT] Add makeArrayRef(std::array<>) template specialization
llvm-svn: 371129
Jan Korous [Thu, 5 Sep 2019 21:26:53 +0000 (21:26 +0000)]
[Bitstream] Add BitCodeAbbrev(std::initializer_list) constructor
llvm-svn: 371128
DeForest Richards [Thu, 5 Sep 2019 21:24:47 +0000 (21:24 +0000)]
Docs: Update Community section on homepage
This commit includes the following changes: Adds a Getting Involved section under Community. Moves the Development Process section under Community. Moves Sphinx Quickstart Template and How to submit an LLVM bug report from User Guides section to Getting Involved.
llvm-svn: 371127
Vedant Kumar [Thu, 5 Sep 2019 21:24:23 +0000 (21:24 +0000)]
[libcxx] Codesign test executables if necessary
If LLVM_CODESIGNING_IDENTITY is set, test executables need to be
codesigned.
Differential Revision: https://reviews.llvm.org/D66496
llvm-svn: 371126
David Bolvansky [Thu, 5 Sep 2019 21:09:58 +0000 (21:09 +0000)]
[GSYM][NFC] Fixed -Wdocumentation warning
lib/DebugInfo/GSYM/InlineInfo.cpp:68:12: warning: parameter 'Inline' not found in the function declaration [-Wdocumentation]
llvm-svn: 371125
Nico Weber [Thu, 5 Sep 2019 21:08:50 +0000 (21:08 +0000)]
Implement Microsoft-compatible mangling for decomposition declarations.
Match cl.exe's mangling for decomposition declarations.
Decomposition declarations are considered to be anonymous structs,
and use the same convention as for anonymous struct/union declarations.
Naming confirmed to match https://godbolt.org/z/K2osJa
Patch from Eric Astor <epastor@google.com>!
Differential Revision: https://reviews.llvm.org/D67202
llvm-svn: 371124
Nico Weber [Thu, 5 Sep 2019 20:58:38 +0000 (20:58 +0000)]
gn build: Merge r371121
llvm-svn: 371123
David Bolvansky [Thu, 5 Sep 2019 20:50:48 +0000 (20:50 +0000)]
[Diagnostics] Minor improvements for -Wxor-used-as-pow
Extracted from D66397; implemented suggestion for 2^64; tests revisited.
llvm-svn: 371122
Puyan Lotfi [Thu, 5 Sep 2019 20:44:33 +0000 (20:44 +0000)]
[MIR] MIRNamer pass for improving MIR test authoring experience.
This patch reuses the MIR vreg renamer from the MIRCanonicalizerPass to cleanup
names of vregs in a MIR file for MIR test authors. I found it useful when
writing a regression test for a globalisel failure I encountered recently and
thought it might be useful for other folks as well.
Differential Revision: https://reviews.llvm.org/D67209
llvm-svn: 371121
Sterling Augustine [Thu, 5 Sep 2019 20:44:08 +0000 (20:44 +0000)]
Add testing infrastructure to check if gdb is available for testing.
Reviewers: echristo, EricWF
Subscribers: mgorny, christof, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D67194
llvm-svn: 371120
Nico Weber [Thu, 5 Sep 2019 20:38:24 +0000 (20:38 +0000)]
gn build: Merge r371117
llvm-svn: 371119
Jan Korous [Thu, 5 Sep 2019 20:33:52 +0000 (20:33 +0000)]
[clang][Index] Replace CodegenNameGenerator with ASTNameGenerator
Follow-up to:
3ff8c3b73f6,
d5d15b4c1fd
Should be NFC since the original patch just moved the code.
llvm-svn: 371117
Daniel Sanders [Thu, 5 Sep 2019 20:26:02 +0000 (20:26 +0000)]
[globalisel][knownbits] Account for missing type constraints
Now that we look through copies, it's possible to visit registers that
have a register class constraint but not a type constraint. Avoid looking
through copies when this occurs as the SrcReg won't be able to determine
it's bit width or any known bits.
Along the same lines, if the initial query is on a register that doesn't
have a type constraint then the result is a default-constructed KnownBits,
that is, a 1-bit fully-unknown value.
llvm-svn: 371116
Daniel Sanders [Thu, 5 Sep 2019 20:25:52 +0000 (20:25 +0000)]
[globalisel][knownbits] Correct a typo that prevented a test working as intended
llvm-svn: 371115
Jessica Paquette [Thu, 5 Sep 2019 20:18:34 +0000 (20:18 +0000)]
Recommit "[AArch64][GlobalISel] Teach AArch64CallLowering to handle basic sibling calls"
Recommit basic sibling call lowering (https://reviews.llvm.org/D67189)
The issue was that if you have a return type other than void, call lowering
will emit COPYs to get the return value after the call.
Disallow sibling calls other than ones that return void for now. Also
proactively disable swifterror tail calls for now, since there's a similar issue
with COPYs there.
Update call-translator-tail-call.ll to include test cases for each of these
things.
llvm-svn: 371114
Alexandre Ganea [Thu, 5 Sep 2019 20:12:20 +0000 (20:12 +0000)]
Revert: [DebugInfo] Add debug location to stubs generated by CGDeclCXX and mark them as artificial
llvm-svn: 371113
Jan Korous [Thu, 5 Sep 2019 20:04:11 +0000 (20:04 +0000)]
[AST][NFC] Doc comments for ASTNameGenerator
llvm-svn: 371112
Eli Friedman [Thu, 5 Sep 2019 20:02:38 +0000 (20:02 +0000)]
[IfConversion] Fix diamond conversion with unanalyzable branches.
The code was incorrectly counting the number of identical instructions,
and therefore tried to predicate an instruction which should not have
been predicated. This could have various effects: a compiler crash,
an assembler failure, a miscompile, or just generating an extra,
unnecessary instruction.
Instead of depending on TargetInstrInfo::removeBranch, which only
works on analyzable branches, just remove all branch instructions.
Fixes https://bugs.llvm.org/show_bug.cgi?id=43121 and
https://bugs.llvm.org/show_bug.cgi?id=41121 .
Differential Revision: https://reviews.llvm.org/D67203
llvm-svn: 371111
Sylvestre Ledru [Thu, 5 Sep 2019 19:50:56 +0000 (19:50 +0000)]
doc update: explain that Z3 is only for clang SA - thanks to LebedevRI for the suggestion
llvm-svn: 371110
Sylvestre Ledru [Thu, 5 Sep 2019 19:38:15 +0000 (19:38 +0000)]
document the LLVM_ENABLE_Z3_SOLVER option
llvm-svn: 371109
Roman Lebedev [Thu, 5 Sep 2019 19:13:15 +0000 (19:13 +0000)]
[NFC][InstCombine] Overhaul 'unsigned add overflow' tests, ensure that all 3 patterns have full test coverage
llvm-svn: 371108
Craig Topper [Thu, 5 Sep 2019 18:49:52 +0000 (18:49 +0000)]
[X86] Enable BuildSDIVPow2 for i16.
We're able to use a 32-bit ADD and CMOV here and should work
well with our other i16->i32 promotion optimizations.
llvm-svn: 371107
Francis Visoiu Mistrih [Thu, 5 Sep 2019 18:30:20 +0000 (18:30 +0000)]
[Remarks] Don't serialize metadata if a string table is not used
For YAML remarks with no string table, the mode should not affect the
output.
llvm-svn: 371106
Nico Weber [Thu, 5 Sep 2019 18:15:50 +0000 (18:15 +0000)]
gn build: Merge r371103
llvm-svn: 371105
Craig Topper [Thu, 5 Sep 2019 18:15:07 +0000 (18:15 +0000)]
[X86] Override BuildSDIVPow2 for X86.
As noted in PR43197, we can use test+add+cmov+sra to implement
signed division by a power of 2.
This is based off the similar version in AArch64, but I've
adjusted it to use target independent nodes where AArch64 uses
target specific CMP and CSEL nodes. I've also blocked INT_MIN
as the transform isn't valid for that.
I've limited this to i32 and i64 on 64-bit targets for now and only
when CMOV is supported. i8 and i16 need further investigation to be
sure they get promoted to i32 well.
I adjusted a few tests to enable cmov to demonstrate the new
codegen. I also changed twoaddr-coalesce-3.ll to 32-bit mode
without cmov to avoid perturbing the scenario that is being
set up there.
Differential Revision: https://reviews.llvm.org/D67087
llvm-svn: 371104
Jan Korous [Thu, 5 Sep 2019 18:10:29 +0000 (18:10 +0000)]
[Support] Add writeFileAtomically() to FileUtilities
Differential Revision: https://reviews.llvm.org/D66859
llvm-svn: 371103
Nico Weber [Thu, 5 Sep 2019 18:03:18 +0000 (18:03 +0000)]
gn build: (manually) merge r358706
llvm-svn: 371102
Roman Lebedev [Thu, 5 Sep 2019 17:41:02 +0000 (17:41 +0000)]
[InstCombine] foldICmpBinOp(): consider inverted check in 'unsigned sub overflow' check
A follow-up for r329011.
This may be changed to produce @llvm.sub.with.overflow in a later patch,
but for now just make things more consistent overall.
A few observations stem from this:
* There does not seem to be a similar one-instruction fold for uadd-overflow
* I'm not sure we'll want to canonicalize `B u> A` as `usub.with.overflow`,
so since the `icmp` here no longer refers to `sub`,
reconstructing `usub.with.overflow` will be problematic,
and will likely require standalone pass (similar to DivRemPairs).
https://rise4fun.com/Alive/Zqs
Name: (A - B) u> A --> B u> A
%t0 = sub i8 %A, %B
%r = icmp ugt i8 %t0, %A
=>
%r = icmp ugt i8 %B, %A
Name: (A - B) u<= A --> B u<= A
%t0 = sub i8 %A, %B
%r = icmp ule i8 %t0, %A
=>
%r = icmp ule i8 %B, %A
Name: C u< (C - D) --> C u< D
%t0 = sub i8 %C, %D
%r = icmp ult i8 %C, %t0
=>
%r = icmp ult i8 %C, %D
Name: C u>= (C - D) --> C u>= D
%t0 = sub i8 %C, %D
%r = icmp uge i8 %C, %t0
=>
%r = icmp uge i8 %C, %D
llvm-svn: 371101
Roman Lebedev [Thu, 5 Sep 2019 17:40:49 +0000 (17:40 +0000)]
[InstCombine] foldICmpBinOp(): consider inverted check in 'unsigned add overflow' check
A follow-up for r342004.
This will be changed to produce @llvm.add.with.overflow in a later patch,
but for now just make things more consistent overall.
https://rise4fun.com/Alive/qxE
Name: (Op1 + X) u< Op1 --> ~Op1 u< X
%t0 = add i8 %Op1, %X
%r = icmp ult i8 %t0, %Op1
=>
%n = xor i8 %Op1, -1
%r = icmp ult i8 %n, %X
Name: (Op1 + X) u>= Op1 --> ~Op1 u>= X
%t0 = add i8 %Op1, %X
%r = icmp uge i8 %t0, %Op1
=>
%n = xor i8 %Op1, -1
%r = icmp uge i8 %n, %X
;-------------------------------------------------------------------------------
Name: Op0 u> (Op0 + X) --> X u> ~Op0
%t0 = add i8 %Op0, %X
%r = icmp ugt i8 %Op0, %t0
=>
%n = xor i8 %Op0, -1
%r = icmp ugt i8 %X, %n
Name: Op0 u<= (Op0 + X) --> X u<= ~Op0
%t0 = add i8 %Op0, %X
%r = icmp ule i8 %Op0, %t0
=>
%n = xor i8 %Op0, -1
%r = icmp ule i8 %X, %n
llvm-svn: 371100
Roman Lebedev [Thu, 5 Sep 2019 17:40:37 +0000 (17:40 +0000)]
[InstCombine][NFC] Tests for 'unsigned sub overflow' check
----------------------------------------
Name: unsigned sub, overflow, v0
%sub = sub i8 %x, %y
%ov = icmp ugt i8 %sub, %x
=>
%agg = usub_overflow i8 %x, %y
%sub = extractvalue {i8, i1} %agg, 0
%ov = extractvalue {i8, i1} %agg, 1
Done: 1
Optimization is correct!
----------------------------------------
Name: unsigned sub, no overflow, v0
%sub = sub i8 %x, %y
%ov = icmp ule i8 %sub, %x
=>
%agg = usub_overflow i8 %x, %y
%sub = extractvalue {i8, i1} %agg, 0
%not.ov = extractvalue {i8, i1} %agg, 1
%ov = xor %not.ov, -1
Done: 1
Optimization is correct!
llvm-svn: 371099
Roman Lebedev [Thu, 5 Sep 2019 17:40:28 +0000 (17:40 +0000)]
[InstCombine][NFC] Tests for 'unsigned add overflow' check
----------------------------------------
Name: unsigned add, overflow, v0
%add = add i8 %x, %y
%ov = icmp ult i8 %add, %x
=>
%agg = uadd_overflow i8 %x, %y
%add = extractvalue {i8, i1} %agg, 0
%ov = extractvalue {i8, i1} %agg, 1
Done: 1
Optimization is correct!
----------------------------------------
Name: unsigned add, overflow, v1
%add = add i8 %x, %y
%ov = icmp ult i8 %add, %y
=>
%agg = uadd_overflow i8 %x, %y
%add = extractvalue {i8, i1} %agg, 0
%ov = extractvalue {i8, i1} %agg, 1
Done: 1
Optimization is correct!
----------------------------------------
Name: unsigned add, no overflow, v0
%add = add i8 %x, %y
%ov = icmp uge i8 %add, %x
=>
%agg = uadd_overflow i8 %x, %y
%add = extractvalue {i8, i1} %agg, 0
%not.ov = extractvalue {i8, i1} %agg, 1
%ov = xor %not.ov, -1
Done: 1
Optimization is correct!
----------------------------------------
Name: unsigned add, no overflow, v1
%add = add i8 %x, %y
%ov = icmp uge i8 %add, %y
=>
%agg = uadd_overflow i8 %x, %y
%add = extractvalue {i8, i1} %agg, 0
%not.ov = extractvalue {i8, i1} %agg, 1
%ov = xor %not.ov, -1
Done: 1
Optimization is correct!
llvm-svn: 371098
Cyndy Ishida [Thu, 5 Sep 2019 17:33:44 +0000 (17:33 +0000)]
[TextAPI] update interface file for filtered iter
Summary:
This is a simple change that allows easy iterator semantics for symbols held in interface file.
Not being used, so harmless change right now, but will be once TBD-v4 is submitted.
Reviewers: ributzka, steven_wu
Reviewed By: ributzka
Subscribers: javed.absar, kristof.beyls, dexonsmith, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D67204
llvm-svn: 371097
DeForest Richards [Thu, 5 Sep 2019 17:30:52 +0000 (17:30 +0000)]
Docs: Move Documentation sections to separate pages.
Updates the links on the homepage by moving the User Guides, Programming Documentation, and Subsystem Documentation sections to separate pages. Also changes "Overview" to "About" at the top of the LLVM Docs homepage. This work is part of the Google Season of Docs project.
llvm-svn: 371096
Sanjay Patel [Thu, 5 Sep 2019 17:28:17 +0000 (17:28 +0000)]
[x86] fix horizontal math bug exposed by improved demanded elements analysis (PR43225)
https://bugs.llvm.org/show_bug.cgi?id=43225
llvm-svn: 371095
Craig Topper [Thu, 5 Sep 2019 17:24:34 +0000 (17:24 +0000)]
[X86] Add a FIXME about why the CWD/CDQ/CQO have a bogus implicit def of the A register. NFC
The instructions copy the sign bit of the A register to every bit
of the D register. But they don't write to the A register.
llvm-svn: 371094
Craig Topper [Thu, 5 Sep 2019 17:24:25 +0000 (17:24 +0000)]
[X86] Remove unneeded CHECK lines from a test. NFC
llvm-svn: 371093
Craig Topper [Thu, 5 Sep 2019 17:24:15 +0000 (17:24 +0000)]
[X86] Fix stale comment. NFC
We aren't checking for a concat here. We're just always splitting
256-bit stores.
llvm-svn: 371092
Nico Weber [Thu, 5 Sep 2019 17:22:55 +0000 (17:22 +0000)]
gn build: (manually) merge r371003
llvm-svn: 371091
Adrian McCarthy [Thu, 5 Sep 2019 17:22:30 +0000 (17:22 +0000)]
Fix windows-x86-debug compilation with python enabled using multi-target generator
[Patch by Leonid Mashinskiy]
Visual Studio CMake generator is multi-target and does not define
CMAKE_BUILD_TYPE, so Debug build on VS was failing due selection of release
python library. This patch reverts back some of latest changes and fixes
building by raw VS using CMake expression generators.
Differential Revision: https://reviews.llvm.org/D66994
llvm-svn: 371090
Denis Bakhvalov [Thu, 5 Sep 2019 17:00:32 +0000 (17:00 +0000)]
[MergedLoadStoreMotion] Sink stores to BB with more than 2 predecessors
If we have:
bb5:
br i1 %arg3, label %bb6, label %bb7
bb6:
%tmp = getelementptr inbounds i32, i32* %arg1, i64 2
store i32 3, i32* %tmp, align 4
br label %bb9
bb7:
%tmp8 = getelementptr inbounds i32, i32* %arg1, i64 2
store i32 3, i32* %tmp8, align 4
br label %bb9
bb9: ; preds = %bb4, %bb6, %bb7
...
We can't sink stores directly into bb9.
This patch creates new BB that is successor of %bb6 and %bb7
and sinks stores into that block.
SplitFooterBB is the parameter to the pass that controls
that behavior.
Change-Id: I7fdf50a772b84633e4b1b860e905bf7e3e29940f
Differential: https://reviews.llvm.org/D66234
llvm-svn: 371089
Sanjay Patel [Thu, 5 Sep 2019 16:58:18 +0000 (16:58 +0000)]
[x86] add test for horizontal math bug (PR43225); NFC
llvm-svn: 371088
Alina Sbirlea [Thu, 5 Sep 2019 16:58:15 +0000 (16:58 +0000)]
[MemorySSA] Verify MSSAUpdater exists.
llvm-svn: 371087
Hiroshi Yamauchi [Thu, 5 Sep 2019 16:56:55 +0000 (16:56 +0000)]
[PGO][CHR] Speed up following long, interlinked use-def chains.
Summary:
Avoid visiting an instruction more than once by using a map.
This is similar to https://reviews.llvm.org/rL361416.
Reviewers: davidxl
Reviewed By: davidxl
Subscribers: llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D67198
llvm-svn: 371086
Fangrui Song [Thu, 5 Sep 2019 16:32:31 +0000 (16:32 +0000)]
[ELF] Initialize PhdrEntry::p_align to maxPageSize for PT_LOAD
```
Writer<ELFT>::run
assignFileOffsets
setFileOffset
computeFileOffset
os->ptLoad->p_align may be smaller than config->maxPageSize
setPhdrs
p_align = max(p_align, config->maxPageSize)
```
If we move the config->maxPageSize logic to the constructor of
PhdrEntry, computeFileOffset can be simplified.
Reviewed By: ruiu
Differential Revision: https://reviews.llvm.org/D67211
llvm-svn: 371085
Alina Sbirlea [Thu, 5 Sep 2019 16:25:24 +0000 (16:25 +0000)]
[MemorySSA] Update MemorySSA when removing debug.value calls.
llvm-svn: 371084
Krzysztof Parzyszek [Thu, 5 Sep 2019 16:19:47 +0000 (16:19 +0000)]
[Hexagon] Fix type in HexagonTargetLowering::ReplaceNodeResults
llvm-svn: 371083
Guillaume Chatelet [Thu, 5 Sep 2019 15:44:33 +0000 (15:44 +0000)]
[Alignment][NFC] Change internal representation of TargetLowering.h
Summary:
This is patch is part of a series to introduce an Alignment type.
See this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html
See this patch for the introduction of the type: https://reviews.llvm.org/D64790
Reviewers: courbet
Subscribers: hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D67226
llvm-svn: 371082
Ilya Biryukov [Thu, 5 Sep 2019 15:30:05 +0000 (15:30 +0000)]
[clangd] Initialize int field to zero. NFC
To make sure we do not have uninitialized values and undefined behavior.
llvm-svn: 371081
Alexandre Ganea [Thu, 5 Sep 2019 15:24:49 +0000 (15:24 +0000)]
[DebugInfo] Add debug location to stubs generated by CGDeclCXX and mark them as artificial
Differential Revision: https://reviews.llvm.org/D66328
llvm-svn: 371080
David Candler [Thu, 5 Sep 2019 15:17:25 +0000 (15:17 +0000)]
[ARM] Add support for the s,j,x,N,O inline asm constraints
A number of inline assembly constraints are currently supported by LLVM, but rejected as invalid by Clang:
Target independent constraints:
s: An integer constant, but allowing only relocatable values
ARM specific constraints:
j: An immediate integer between 0 and 65535 (valid for MOVW)
x: A 32, 64, or 128-bit floating-point/SIMD register: s0-s15, d0-d7, or q0-q3
N: An immediate integer between 0 and 31 (Thumb1 only)
O: An immediate integer which is a multiple of 4 between -508 and 508. (Thumb1 only)
This patch adds support to Clang for the missing constraints along with some checks to ensure that the constraints are used with the correct target and Thumb mode, and that immediates are within valid ranges (at least where possible). The constraints are already implemented in LLVM, but just a couple of minor corrections to checks (V8M Baseline includes MOVW so should work with 'j', 'N' and 'O' shouldn't be valid in Thumb2) so that Clang and LLVM are in line with each other and the documentation.
Differential Revision: https://reviews.llvm.org/D65863
Change-Id: I18076619e319bac35fbb60f590c069145c9d9a0a
llvm-svn: 371079
Simon Pilgrim [Thu, 5 Sep 2019 15:07:07 +0000 (15:07 +0000)]
[X86][SSE] EltsFromConsecutiveLoads - ignore non-zero offset base loads (PR43227)
As discussed on D64551 and PR43227, we don't correctly handle cases where the base load has a non-zero byte offset.
Until we can properly handle this, we must bail from EltsFromConsecutiveLoads.
llvm-svn: 371078
Raphael Isemann [Thu, 5 Sep 2019 14:51:23 +0000 (14:51 +0000)]
[lldb][NFC] Add dimensions to pexpect tests failing on sanitizer bot
I'm still unable to reproduce this locally, so let's see if this
is enough to make the bots happy. The missing dimension parameter
seems to be the biggest difference between these tests and
TestIOHandlerCompletion.py which runs just fine on the same bot,
so that's the motivation for trying this out.
llvm-svn: 371077
Alexander Kornienko [Thu, 5 Sep 2019 14:48:31 +0000 (14:48 +0000)]
[clang-tidy] Make most ArgumentCommentCheck options local, as they should be
llvm-svn: 371076
Alexander Kornienko [Thu, 5 Sep 2019 14:48:23 +0000 (14:48 +0000)]
Add a bugprone-argument-comment option: IgnoreSingleArgument.
Summary:
Add bugprone-argument-comment option: IgnoreSingleArgument.
When true, the check will ignore the single argument.
Sometimes, it's not necessary to add comment to single argument.
For example:
> std::string name("Yubo Xie");
> pScreen->SetWidth(1920);
> pScreen->SetHeight(1080);
This option can ignore such single argument in bugprone-argument-comment check.
Reviewers: alexfh
Reviewed By: alexfh
Subscribers: cfe-commits
Tags: #clang
Patch by Yubo Xie.
Differential Revision: https://reviews.llvm.org/D67056
llvm-svn: 371075
Fangrui Song [Thu, 5 Sep 2019 14:25:57 +0000 (14:25 +0000)]
[yaml2obj] Write the section header table after section contents
Linkers (ld.bfd/gold/lld) place the section header table at the very
end. This allows tools to strip it, which is optional in executable/shared objects.
In addition, if we add or section, the size of the section header table
will change. Placing the section header table in the end keeps section
offsets unchanged.
yaml2obj currently places the section header table immediately after the
program header. Follow what linkers do to make offset updating easier.
Reviewed By: grimar
Differential Revision: https://reviews.llvm.org/D67221
llvm-svn: 371074
Guillaume Chatelet [Thu, 5 Sep 2019 14:17:08 +0000 (14:17 +0000)]
[LLVM][Alignment][NFC] Fixing wrong documentation
llvm-svn: 371073
Alexander Kornienko [Thu, 5 Sep 2019 14:13:57 +0000 (14:13 +0000)]
[clang-tidy] Fix bugprone-argument-comment bug: negative literal number is not checked.
Summary:
For example:
```
void foo(int a);
foo(-2);
```
should be fixed as:
```
foo(/*a=*/-2);
```
This change tries to fix this issue.
Reviewers: alexfh, hokein, aaron.ballman
Reviewed By: alexfh, aaron.ballman
Subscribers: xazax.hun, cfe-commits
Tags: #clang, #clang-tools-extra
Patch by Yubo Xie.
Differential Revision: https://reviews.llvm.org/D67084
llvm-svn: 371072
George Rimar [Thu, 5 Sep 2019 14:02:58 +0000 (14:02 +0000)]
[llvm-readelf] - Allow dumping dynamic symbols when there is no program headers.
D62179 introduced a regression. llvm-readelf lose the ability to dump the dynamic symbols
when there is .dynamic section with a DT_SYMTAB, but there are no program headers:
https://reviews.llvm.org/D62179#1652778
Below is a program flow before the D62179 change:
1) Find SHT_DYNSYM.
2) Find there is no PT_DYNAMIC => don't try to parse it.
3) Print dynamic symbols using information about them found on step (1).
And after the change it became:
1) Find SHT_DYNSYM.
2) Find there is no PT_DYNAMIC => find SHT_DYNAMIC.
3) Parse dynamic table, but fail to handle the DT_SYMTAB because of the absence of the PT_LOAD. Report the "Virtual address is not in any segment" error.
This patch fixes the issue. For doing this it checks that the value of DT_SYMTAB was
mapped to a segment. If not - it ignores it.
Differential revision: https://reviews.llvm.org/D67078
llvm-svn: 371071