Kamil Rytarowski [Tue, 9 Oct 2018 11:24:10 +0000 (11:24 +0000)]
Mark MSan fork test as UNSUPPORTED on NetBSD
This test sometimes hangs for unknown reason.
llvm-svn: 344038
Nemanja Ivanovic [Tue, 9 Oct 2018 11:17:47 +0000 (11:17 +0000)]
Fix buildbot failures with the newly added test case (triple was missing).
llvm-svn: 344037
Nemanja Ivanovic [Tue, 9 Oct 2018 10:54:04 +0000 (10:54 +0000)]
[PowerPC] Remove self-copies in pre-emit peephole
There are occasionally instances where AADB rewrites registers in such a way
that a reg-reg copy becomes a self-copy. Such an instruction is obviously
redundant and can be removed. This patch does precisely that.
Note that this will not remove various nop's that we insert (which are
themselves just self-copies). The reason those are left alone is that all of
them have their own opcodes (that just encode to a self-copy).
What prompted this patch is the fact that these self-copies sometimes end up
using registers that make the instruction a priority-setting nop, thereby
having a significant effect on performance.
Differential revision: https://reviews.llvm.org/D52432
llvm-svn: 344036
Kamil Rytarowski [Tue, 9 Oct 2018 10:34:36 +0000 (10:34 +0000)]
Reflect the current reality and disable lsan tests on NetBSD
LSan/NetBSD is still in development (Stop-The-World routine missed).
llvm-svn: 344035
Kamil Rytarowski [Tue, 9 Oct 2018 10:32:01 +0000 (10:32 +0000)]
Use PTHREAD_STACK_MIN conditionally in a test
PTHREAD_STACK_MIN is not available on NetBSD as it's not
clear what the value shall be represented by this constant
on a multiplatform OS.
llvm-svn: 344034
Kadir Cetinkaya [Tue, 9 Oct 2018 10:29:54 +0000 (10:29 +0000)]
[clangd] Mark colon as a safe character when percent-encoding.
Summary: Also change output of percent-encoding to use upper-case letters.
Reviewers: sammccall
Reviewed By: sammccall
Subscribers: ilya-biryukov, ioeric, MaskRay, jkorous, arphaman, cfe-commits
Differential Revision: https://reviews.llvm.org/D53016
llvm-svn: 344033
Guillaume Chatelet [Tue, 9 Oct 2018 10:06:19 +0000 (10:06 +0000)]
[llvm-exegesis] Fix wrong index type.
llvm-svn: 344032
Kristof Umann [Tue, 9 Oct 2018 10:05:08 +0000 (10:05 +0000)]
[analyzer][www] Add more useful links
Differential Revision: https://reviews.llvm.org/D52993
llvm-svn: 344031
Sam McCall [Tue, 9 Oct 2018 10:02:02 +0000 (10:02 +0000)]
[clangd] Fix nondeterministic test
llvm-svn: 344030
Guillaume Chatelet [Tue, 9 Oct 2018 09:33:29 +0000 (09:33 +0000)]
[llvm-exegesis] Fix unused lambda capture.
llvm-svn: 344029
Guillaume Chatelet [Tue, 9 Oct 2018 08:59:10 +0000 (08:59 +0000)]
[llvm-exegesis][NFC] Use accessors for Operand.
Summary:
This moves checking logic into the accessors and makes the structure smaller.
It will also help when/if Operand are generated from the TD files.
Subscribers: tschuett, courbet, llvm-commits
Differential Revision: https://reviews.llvm.org/D52982
llvm-svn: 344028
Aleksandr Urakov [Tue, 9 Oct 2018 08:50:50 +0000 (08:50 +0000)]
[ADT] Force the alignment of the `data` field of `IntervalMap`
Summary:
This patch forces the alignment of the `data` field of `IntervalMap`.
It is because x86 MSVC doesn't apply automatically
(without `__declspec(align(...))`) alignments more than 4 bytes,
even if `alignof` has returned so. Consider the example:
https://godbolt.org/z/zIPa_G
Here `alignof` for both `S0` and `S1` returns `8`, but only `S1` is really
aligned on x86. The explanation of this behavior is here:
https://docs.microsoft.com/en-us/cpp/build/conflicts-with-the-x86-compiler
Reviewers: bkramer, stoklund, hans, rnk
Reviewed By: rnk
Subscribers: dexonsmith, llvm-commits
Differential Revision: https://reviews.llvm.org/D52613
llvm-svn: 344027
Stephen Kelly [Tue, 9 Oct 2018 08:44:28 +0000 (08:44 +0000)]
[ASTMatcher] Add missing imaginaryLiteral
llvm-svn: 344026
Kadir Cetinkaya [Tue, 9 Oct 2018 08:41:12 +0000 (08:41 +0000)]
[clangd] Revert back to previous heuristic for diagnostic range extraction.
Summary: Also add a few new test cases and a special case into handling of empty fixit ranges that collides with location of a diag.
Reviewers: sammccall, ilya-biryukov
Reviewed By: sammccall
Subscribers: ilya-biryukov, ioeric, MaskRay, jkorous, arphaman, cfe-commits
Differential Revision: https://reviews.llvm.org/D52889
llvm-svn: 344025
Eric Liu [Tue, 9 Oct 2018 08:27:31 +0000 (08:27 +0000)]
[clangd] Avoid cache main file status in preamble.
Summary: Main file can certainly change when reusing preamble.
Reviewers: sammccall
Subscribers: ilya-biryukov, MaskRay, jkorous, arphaman, kadircet, cfe-commits
Differential Revision: https://reviews.llvm.org/D52991
llvm-svn: 344024
Stephen Kelly [Tue, 9 Oct 2018 08:24:18 +0000 (08:24 +0000)]
Remove non-existant typeloc matchers from documentation
llvm-svn: 344023
Stephen Kelly [Tue, 9 Oct 2018 08:24:11 +0000 (08:24 +0000)]
Regenerate AST Matcher docs
llvm-svn: 344022
Stephen Kelly [Tue, 9 Oct 2018 08:24:06 +0000 (08:24 +0000)]
Fix indentation
llvm-svn: 344021
Aleksandr Urakov [Tue, 9 Oct 2018 07:44:17 +0000 (07:44 +0000)]
Revert "[ADT] Change the `IntervalMap` alignment assert for x86 MSVC"
This reverts commit
7f9eb168a9a8f5ff4fc931a00aec43e8706afecb.
llvm-svn: 344020
Simon Pilgrim [Tue, 9 Oct 2018 07:42:01 +0000 (07:42 +0000)]
[X86][AVX1] Enable *_EXTEND_VECTOR_INREG lowering of 256-bit vectors
As discussed on D52964, this adds 256-bit *_EXTEND_VECTOR_INREG lowering support for AVX1 targets to help improve SimplifyDemandedBits handling.
Differential Revision: https://reviews.llvm.org/D52980
llvm-svn: 344019
Aleksandr Urakov [Tue, 9 Oct 2018 07:33:09 +0000 (07:33 +0000)]
[ADT] Change the `IntervalMap` alignment assert for x86 MSVC
Summary:
This patch forces the alignment of the `data` field of `IntervalMap`.
It is because x86 MSVC doesn't apply automatically
(without `__declspec(align(...))`) alignments more than 4 bytes,
even if `alignof` has returned so. Consider the example:
https://godbolt.org/z/zIPa_G
Here `alignof` for both `S0` and `S1` returns `8`, but only `S1` is really
aligned on x86. The explanation of this behavior is here:
https://docs.microsoft.com/en-us/cpp/build/conflicts-with-the-x86-compiler
Reviewers: bkramer, stoklund, hans, rnk
Reviewed By: rnk
Subscribers: dexonsmith, llvm-commits
Differential Revision: https://reviews.llvm.org/D52613
llvm-svn: 344018
Gabor Horvath [Tue, 9 Oct 2018 07:28:57 +0000 (07:28 +0000)]
[analyzer] Support Reinitializes attribute in MisusedMovedObject check
Differential Revision: https://reviews.llvm.org/D52983
llvm-svn: 344017
Zinovy Nis [Tue, 9 Oct 2018 05:48:57 +0000 (05:48 +0000)]
[clang-tidy][docs] Update docs for `--check-suffixes`
Differential Revision: https://reviews.llvm.org/D52971
llvm-svn: 344016
Zinovy Nis [Tue, 9 Oct 2018 05:40:03 +0000 (05:40 +0000)]
[clang-tidy] The patch extends the existing command line option -check-suffix
(with alias -check-suffixes) to accept multiple comma-separated FileCheck prefixes.
Usage:
// RUN: %check_clang_tidy -check-suffix=USING-C,USING-D %s misc-unused-using-decls %t -- -- ...
or for the same:
// RUN: %check_clang_tidy -check-suffixes=USING-C,USING-D %s misc-unused-using-decls %t -- -- ...
Differential Revision: https://reviews.llvm.org/D52971
llvm-svn: 344015
Chandler Carruth [Tue, 9 Oct 2018 04:30:23 +0000 (04:30 +0000)]
[CFG Printer] Add support for writing the dot files with a custom
prefix.
Use this to direct these files to a specific location in the test suite
so that we don't write files out to random directories (or fail if the
working directory isn't writable).
llvm-svn: 344014
George Burgess IV [Tue, 9 Oct 2018 03:18:56 +0000 (03:18 +0000)]
Make LocationSize a proper Optional type; NFC
This is the second in a series of changes intended to make
https://reviews.llvm.org/D44748 more easily reviewable. Please see that
patch for more context. The first change being r344012.
Since I was requested to do all of this with post-commit review, this is
about as small as I can make this patch.
This patch makes LocationSize into an actual type that wraps a uint64_t;
users are required to call getValue() in order to get the size now. If
the LocationSize has an Unknown size (e.g. if LocSize ==
MemoryLocation::UnknownSize), getValue() will assert.
This also adds DenseMap specializations for LocationInfo, which required
taking two more values from the set of values LocationInfo can
represent. Hence, heavy users of multi-exabyte arrays or structs may
observe slightly lower-quality code as a result of this change.
The intent is for getValue()s to be very close to a corresponding
hasValue() (which is often spelled `!= MemoryLocation::UnknownSize`).
Sadly, small diff context appears to crop that out sometimes, and the
last change in DSE does require a bit of nonlocal reasoning about
control-flow. :/
This also removes an assert, since it's now redundant with the assert in
getValue().
llvm-svn: 344013
George Burgess IV [Tue, 9 Oct 2018 02:14:33 +0000 (02:14 +0000)]
Use locals instead of struct fields; NFC
This is one of a series of changes intended to make
https://reviews.llvm.org/D44748 more easily reviewable. Please see that
patch for more context.
Since I was requested to do all of this with post-commit review, this is
about as small as I can make it (beyond committing changes to these few
files separately, but they're incredibly similar in spirit, so...)
On its own, this change doesn't make a great deal of sense. I plan on
having a follow-up Real Soon Now(TM) to make the bits here make more
sense. :)
In particular, the next change in this series is meant to make
LocationSize an actual type, which you have to call .getValue() on in
order to get at the uint64_t inside. Hence, this change refactors code
so that:
- we only need to call the soon-to-come getValue() once in most cases,
and
- said call to getValue() happens very closely to a piece of code that
checks if the LocationSize has a value (e.g. if it's != UnknownSize).
llvm-svn: 344012
David Blaikie [Tue, 9 Oct 2018 01:17:27 +0000 (01:17 +0000)]
llvm-link: Improve diagnostic for module-level metadata mismatch
This might produce hard to read/illegible diagnostics for especially
weird/non-trivial module metadata but integers are about all we are
using these days, so seems more useful than not.
Patch based on work by Kristina Brooks - thanks!
Differential Revision: https://reviews.llvm.org/D52952
llvm-svn: 344011
Fangrui Song [Tue, 9 Oct 2018 01:02:56 +0000 (01:02 +0000)]
[Index] Use locations to uniquify function-scope BindingDecl USR
Summary:
This makes BindingDecl's of the same name have different USRs, so that references can be correctly attributed.
int a[1] = {};
{ auto [x] = a; x; }
{ auto [x] = a; x; }
Reviewers: akyrtzi, arphaman, rsmith, hokein
Reviewed By: hokein
Subscribers: cfe-commits
Differential Revision: https://reviews.llvm.org/D52445
llvm-svn: 344010
Thomas Lively [Tue, 9 Oct 2018 00:42:13 +0000 (00:42 +0000)]
[WebAssembly][NFC] Rename test functions for builtins
Reviewers: aheejin, dschuff
Subscribers: sbc100, jgravelle-google, sunfish, jfb, kristina, cfe-commits
Differential Revision: https://reviews.llvm.org/D53007
llvm-svn: 344009
Matthias Braun [Tue, 9 Oct 2018 00:07:34 +0000 (00:07 +0000)]
ExpandPostRAPseudos: Fix alldefsAreDead() not removing operands
One case left around nonsensical operands for the KILL instruction
which the machine verifier checks for nowadays. While this should not
hurt in release builds we should fix the machine verifier errors anyway.
llvm-svn: 344008
Petar Jovanovic [Mon, 8 Oct 2018 23:59:37 +0000 (23:59 +0000)]
[MIPS GlobalISel] Legalize i64 add
Custom legalize s64 G_ADD for MIPS32.
Patch by Petar Avramovic.
Differential Revision: https://reviews.llvm.org/D52652
llvm-svn: 344007
Matthias Braun [Mon, 8 Oct 2018 23:47:35 +0000 (23:47 +0000)]
TwoAddressInstructionPass: Modernize/fix some comments; NFC
llvm-svn: 344006
Matthias Braun [Mon, 8 Oct 2018 23:47:35 +0000 (23:47 +0000)]
PHIElimination: Remove wrong comment; NFC
The comment was contradicting the code. Looking at history the feature
was implemented a day after the comment was written without dropping the
comment.
llvm-svn: 344005
Matthias Braun [Mon, 8 Oct 2018 23:47:34 +0000 (23:47 +0000)]
MachineFunctionPrinterPass: Declare SlotIndexes as used if available; NFC
This makes print-machineinstrs print the slot indexes in more
situations. NFC for normal compilation.
llvm-svn: 344004
Nico Weber [Mon, 8 Oct 2018 23:06:05 +0000 (23:06 +0000)]
lld-link: Implement support for %_PDB% and %_EXT% for /pdbaltpath:.
Warn that references to regular env vars are ignored.
Fixes PR38940.
Differential Revision: https://reviews.llvm.org/D52942
llvm-svn: 344003
Zachary Turner [Mon, 8 Oct 2018 22:56:57 +0000 (22:56 +0000)]
Remove unused variable.
llvm-svn: 344002
Zachary Turner [Mon, 8 Oct 2018 22:38:27 +0000 (22:38 +0000)]
[PDB] fix a bug in global stream name lookup.
When we're looking up a record in the last hash bucket chain, we
need to be careful with the end-offset calculation.
llvm-svn: 344001
Ali Tamur [Mon, 8 Oct 2018 22:25:20 +0000 (22:25 +0000)]
Introduce code_model macros
Summary:
gcc defines macros such as __code_model_small_ based on the user passed command line flag -mcmodel. clang accepts a flag with the same name and similar effects, but does not generate any macro that the user can use. This cl narrows the gap between gcc and clang behaviour.
However, achieving full compatibility with gcc is not trivial: The set of valid values for mcmodel in gcc and clang are not equal. Also, gcc defines different macros for different architectures. In this cl, we only tackle an easy part of the problem and define the macro only for x64 architecture. When the user does not specify a mcmodel, the macro for small code model is produced, as is the case with gcc.
Reviewers: compnerd, MaskRay
Reviewed By: MaskRay
Subscribers: cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D52920
llvm-svn: 344000
Petar Jovanovic [Mon, 8 Oct 2018 22:10:34 +0000 (22:10 +0000)]
[DebugInfo] Fix debug information label tests
Remove the space in the asm check so that the expression is more general
and can also capture MIPS labels which can be surrounded by braces, e.g.:
.4byte ($tmp1) # DW_AT_low_pc
Also change optimization level to O0 because the DW_TAG_label does not
appear on MIPS when -O2 is used.
Patch by Milos Stojanovic.
Differential Revision: https://reviews.llvm.org/D52901
llvm-svn: 343999
Rong Xu [Mon, 8 Oct 2018 22:08:43 +0000 (22:08 +0000)]
[X86] Revert r343993 condition branches folding for three-way conditional codes
Some buildbots failed.
llvm-svn: 343998
Sanjay Patel [Mon, 8 Oct 2018 21:17:20 +0000 (21:17 +0000)]
[DAGCombiner] simplify code for fmul with constant fold; NFCI
llvm-svn: 343997
Marshall Clow [Mon, 8 Oct 2018 20:20:34 +0000 (20:20 +0000)]
Do the math in uniform_int_distribution::operator() as unsigned to prevent UB when overflowing. Also add a UBSAN notification that we're ffine with unsigned overflow. This fixes PR#32617. Thanks to Vincent & Christoph for their help with this issue.
llvm-svn: 343996
Craig Topper [Mon, 8 Oct 2018 20:02:59 +0000 (20:02 +0000)]
[X86] Prefer isTypeLegal over checking isSimple in a DAG combine.
Simple types are a superset of what all in tree targets in LLVM could possibly have a legal type. This means the behavior of using isSimple to check for a supported type for X86 could change over time. For example, this could would change if a v256i1 type was added to MVT in the future.
llvm-svn: 343995
Sanjay Patel [Mon, 8 Oct 2018 19:48:18 +0000 (19:48 +0000)]
[x86] add tests for phaddd/phaddw; NFC
More tests related to PR39195:
https://bugs.llvm.org/show_bug.cgi?id=39195
If we limit the horizontal codegen, it may require different
constraints for FP and integer.
llvm-svn: 343994
Rong Xu [Mon, 8 Oct 2018 18:52:39 +0000 (18:52 +0000)]
[X86] condition branches folding for three-way conditional codes
This patch implements a pass that optimizes condition branches on x86 by
taking advantage of the three-way conditional code generated by compare
instructions.
Currently, it tries to hoisting EQ and NE conditional branch to a dominant
conditional branch condition where the same EQ/NE conditional code is
computed. An example:
bb_0:
cmp %0, 19
jg bb_1
jmp bb_2
bb_1:
cmp %0, 40
jg bb_3
jmp bb_4
bb_4:
cmp %0, 20
je bb_5
jmp bb_6
Here we could combine the two compares in bb_0 and bb_4 and have the
following code:
bb_0:
cmp %0, 20
jg bb_1
jl bb_2
jmp bb_5
bb_1:
cmp %0, 40
jg bb_3
jmp bb_6
For the case of %0 == 20 (bb_5), we eliminate two jumps, and the control height
for bb_6 is also reduced. bb_4 is gone after the optimization.
This optimization is motivated by the branch pattern generated by the switch
lowering: we always have pivot-1 compare for the inner nodes and we do a pivot
compare again the leaf (like above pattern).
This pass currently is enabled on Intel's Sandybridge and later arches. Some
reviewers pointed out that on some arches (like AMD Jaguar), this pass may
increase branch density to the point where it hurts the performance of the
branch predictor.
Differential Revision: https://reviews.llvm.org/D46662
llvm-svn: 343993
Scott Linder [Mon, 8 Oct 2018 18:47:01 +0000 (18:47 +0000)]
[AMDGPU] Legalize VGPR Rsrc operands for MUBUF instructions
Emit a waterfall loop in the general case for a potentially-divergent Rsrc
operand. When practical, avoid this by using Addr64 instructions.
Recommits r341413 with changes to update the MachineDominatorTree when present.
Differential Revision: https://reviews.llvm.org/D51742
llvm-svn: 343992
Simon Pilgrim [Mon, 8 Oct 2018 18:40:50 +0000 (18:40 +0000)]
[X86][AVX2] Enable ZERO_EXTEND_VECTOR_INREG lowering of 256-bit vectors
Some necessary yak shaving before lowering *_EXTEND_VECTOR_INREG 256-bit vectors on AVX1 targets as suggested by D52964.
Differential Revision: https://reviews.llvm.org/D52970
llvm-svn: 343991
Charles Davis [Mon, 8 Oct 2018 18:35:00 +0000 (18:35 +0000)]
[CMake] Link to compiler-rt if LIBUNWIND_USE_COMPILER_RT is ON.
Summary:
If `-nodefaultlibs` is given, we weren't actually linking to it. This
was true irrespective of passing `-rtlib=compiler-rt` (see previous
patch). Now we explicitly link it to handle that case.
I wonder if we should be linking these libraries only if we're using
`-nodefaultlibs`...
Reviewers: beanz
Subscribers: dberris, mgorny, christof, chrib, cfe-commits
Differential Revision: https://reviews.llvm.org/D51657
llvm-svn: 343990
Sanjay Patel [Mon, 8 Oct 2018 18:08:02 +0000 (18:08 +0000)]
[x86] make horizontal binop matching clearer; NFCI
The instructions are complicated, so this code will
probably never be very obvious, but hopefully this
makes it better.
As shown in PR39195:
https://bugs.llvm.org/show_bug.cgi?id=39195
...we need to improve the matching to not miss cases
where we're h-opping on 1 source vector, and that
should be a small patch after this rearranging.
llvm-svn: 343989
Kamil Rytarowski [Mon, 8 Oct 2018 18:04:46 +0000 (18:04 +0000)]
Remove remnant code of using indirect syscall on NetBSD
Summary:
The NetBSD version of internal routines no longer call
the indirect syscall interfaces, as these functions were
switched to lib calls.
Remove the remnant code complication that is no
longer needed after this change. Remove the variations
of internal_syscall, as they were NetBSD specific.
No functional change intended.
Reviewers: vitalybuka, joerg, javed.absar
Reviewed By: vitalybuka
Subscribers: kubamracek, fedor.sergeev, llvm-commits, #sanitizers
Tags: #sanitizers
Differential Revision: https://reviews.llvm.org/D52955
llvm-svn: 343988
Kamil Rytarowski [Mon, 8 Oct 2018 18:04:00 +0000 (18:04 +0000)]
Don't harcode -ldl test/sanitizer_common/TestCases
Summary:
The dl library does not exist on all system and in particular
this breaks build on NetBSD. Make it conditional and
enable only for Linux, following the approach from other
test suites in the same repository.
Reviewers: joerg, vitalybuka
Reviewed By: vitalybuka
Subscribers: kubamracek, llvm-commits, #sanitizers
Tags: #sanitizers
Differential Revision: https://reviews.llvm.org/D52994
llvm-svn: 343987
Robert Lougher [Mon, 8 Oct 2018 18:03:40 +0000 (18:03 +0000)]
[TailCallElim] Enable marking of calls with byval as tails
In r339636 the alias analysis rules were changed with regards to tail calls
and byval arguments. Previously, tail calls were assumed not to alias
allocas from the current frame. This has been updated, to not assume this
for arguments with the byval attribute.
This patch aligns TailCallElim with the new rule. Tail marking can now be
more aggressive and mark more calls as tails, e.g.:
define void @test() {
%f = alloca %struct.foo
call void @bar(%struct.foo* byval %f)
ret void
}
define void @test2(%struct.foo* byval %f) {
call void @bar(%struct.foo* byval %f)
ret void
}
define void @test3(%struct.foo* byval %f) {
%agg.tmp = alloca %struct.foo
%0 = bitcast %struct.foo* %agg.tmp to i8*
%1 = bitcast %struct.foo* %f to i8*
call void @llvm.memcpy.p0i8.p0i8.i64(i8* %0, i8* %1, i64 40, i1 false)
call void @bar(%struct.foo* byval %agg.tmp)
ret void
}
The problematic case where a byval parameter is captured by a call is still
handled correctly, and will not be marked as a tail (see PR7272).
llvm-svn: 343986
Tom Stellard [Mon, 8 Oct 2018 17:49:29 +0000 (17:49 +0000)]
AMDGPU/GlobalISel: Select amdgcn.cvt.pkrtz to 64-bit instructions
Summary: The 32-bit variants do not exist on VI+.
Reviewers: arsenm
Reviewed By: arsenm
Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, rovka, kristof.beyls, dstuttard, tpr, t-tye, llvm-commits
Differential Revision: https://reviews.llvm.org/D52958
llvm-svn: 343985
Kristina Brooks [Mon, 8 Oct 2018 17:29:39 +0000 (17:29 +0000)]
Fix incorrect Twine usage in CFGPrinter
CFGPrinter (-view-cfg, -dot-cfg) invokes an undefined behaviour (dangling
pointer to rvalue) on IR files with branch weights. This patch fixes the
problem caused by Twine initialization and string conversion split into
two statements.
This change fixes the bug 37019. A similar patch to this problem was
provided in the llvmlite project
Patch by mcopik (Marcin Copik).
Differential Revision: https://reviews.llvm.org/D52933
llvm-svn: 343984
Rui Ueyama [Mon, 8 Oct 2018 17:24:29 +0000 (17:24 +0000)]
Fix a broken buildbot.
llvm-svn: 343983
Eric Liu [Mon, 8 Oct 2018 17:22:50 +0000 (17:22 +0000)]
[clang-move] Dump whether a declaration is templated.
llvm-svn: 343982
Kamil Rytarowski [Mon, 8 Oct 2018 17:12:38 +0000 (17:12 +0000)]
Disable TestCases/pthread_mutexattr_get on NetBSD
The pshared feature is unsupported on NetBSD as of today.
llvm-svn: 343981
Kamil Rytarowski [Mon, 8 Oct 2018 17:06:00 +0000 (17:06 +0000)]
Fix Posix/devname_r for NetBSD
NetBSD returns a different type as a return value of
devname_r(3) than FreeBSD and Darwin (int vs char*).
This implies that checking for successful completion of this
function has to be handled differently.
This test used to work well, but was switched to fix Darwin,
which broke NetBSD.
Add a dedicated ifdef for NetBSD and make it functional again
for this OS.
llvm-svn: 343980
Rui Ueyama [Mon, 8 Oct 2018 16:58:59 +0000 (16:58 +0000)]
Avoid unnecessary buffer allocation and memcpy for compressed sections.
Previously, we uncompress all compressed sections before doing anything.
That works, and that is conceptually simple, but that could results in
a waste of CPU time and memory if uncompressed sections are then
discarded or just copied to the output buffer.
In particular, if .debug_gnu_pub{names,types} are compressed and if no
-gdb-index option is given, we wasted CPU and memory because we
uncompress them into newly allocated bufers and then memcpy the buffers
to the output buffer. That temporary buffer was redundant.
This patch changes how to uncompress sections. Now, compressed sections
are uncompressed lazily. To do that, `Data` member of `InputSectionBase`
is now hidden from outside, and `data()` accessor automatically expands
an compressed buffer if necessary.
If no one calls `data()`, then `writeTo()` directly uncompresses
compressed data into the output buffer. That eliminates the redundant
memory allocation and redundant memcpy.
This patch significantly reduces memory consumption (20 GiB max RSS to
15 Gib) for an executable whose .debug_gnu_pub{names,types} are in total
5 GiB in an uncompressed form.
Differential Revision: https://reviews.llvm.org/D52917
llvm-svn: 343979
Nicolai Haehnle [Mon, 8 Oct 2018 16:53:48 +0000 (16:53 +0000)]
AMDGPU: Future-proof {raw,struct}.buffer.atomic intrinsics
Summary:
The ISA is really supposed to support 64-bit atomics as well,
so the data type should be an overload.
Mesa doesn't use these atomics yet, in fact I noticed this
issue while trying to use the atomics from Mesa.
Change-Id: I77f58317a085a0d3eb933cc7e99308c48a19f83e
Reviewers: tpr
Subscribers: kzhuravl, jvesely, wdng, yaxunl, dstuttard, t-tye, jfb, llvm-commits
Differential Revision: https://reviews.llvm.org/D52291
llvm-svn: 343978
Nicolai Haehnle [Mon, 8 Oct 2018 16:53:31 +0000 (16:53 +0000)]
TableGen/CodeGenDAGPatterns: addPredicateFn only once
Summary:
The predicate function is added in InlinePatternFragments, no need to
do it here. As a result, all uses of addPredicateFn are located in
InlinePatternFragments.
Test confirmed that there are no changes to generated files when
building all (non-experimental) targets.
Change-Id: I720e42e045ca596eb0aa339fb61adf6fe71034d5
Reviewers: arsenm, rampitec, RKSimon, craig.topper, hfinkel, uweigand
Subscribers: wdng, llvm-commits
Differential Revision: https://reviews.llvm.org/D51993
llvm-svn: 343977
Xin Tong [Mon, 8 Oct 2018 16:38:00 +0000 (16:38 +0000)]
Fix test case for @r343970
op2 for weakodr symbols is 101 from bcanalyzer.
llvm-svn: 343976
Sanjay Patel [Mon, 8 Oct 2018 16:24:43 +0000 (16:24 +0000)]
[x86] add hadd test with no undefs, remove duplicate tests; NFC
llvm-svn: 343975
Sanjay Patel [Mon, 8 Oct 2018 15:56:28 +0000 (15:56 +0000)]
[x86] simplify hadd tests; NFC
The tests from PR39195 don't use 2 parameters. That's the
root problem for the pattern matching in isHorizontalBinOp().
llvm-svn: 343974
Neil Henning [Mon, 8 Oct 2018 15:49:19 +0000 (15:49 +0000)]
[AMDGPU] Add an AMDGPU specific atomic optimizer.
This commit adds a new IR level pass to the AMDGPU backend to perform
atomic optimizations. It works by:
- Running through a function and finding atomicrmw add/sub or uses of
the atomic buffer intrinsics for add/sub.
- If all arguments except the value to be added/subtracted are uniform,
record the value to be optimized.
- Run through the atomic operations we can optimize and, depending on
whether the value is uniform/divergent use wavefront wide operations
(DPP in the divergent case) to calculate the total amount to be
atomically added/subtracted.
- Then let only a single lane of each wavefront perform the atomic
operation, reducing the total number of atomic operations in flight.
- Lastly we recombine the result from the single lane to each lane of
the wavefront, and calculate our individual lanes offset into the
final result.
Differential Revision: https://reviews.llvm.org/D51969
llvm-svn: 343973
Sid Manning [Mon, 8 Oct 2018 15:32:46 +0000 (15:32 +0000)]
[ELF][HEXAGON] Add R_HEX_GOT_16_X support
Differential Revision: https://reviews.llvm.org/D52909
llvm-svn: 343972
Zachary Turner [Mon, 8 Oct 2018 15:14:05 +0000 (15:14 +0000)]
Don't use back-quotes in a run line.
This works on Windows, but seems to be breaking tests that
use an external shell (e.g. bash) because backquote has special
meaning.
This particular argument wasn't crucial for the test, so I've
just removed it.
llvm-svn: 343971
Xin Tong [Mon, 8 Oct 2018 15:12:48 +0000 (15:12 +0000)]
[ThinLTO] Keep non-prevailing (linkonce|weak)_odr symbols live
Summary:
If we have a symbol with (linkonce|weak)_odr linkage, we do not want
to dead strip it even it is not prevailing.
IR level (linkonce|weak)_odr symbol can become non-prevailing when we mix
ELF objects and IR objects where the (linkonce|weak)_odr symbol in the ELF
object is prevailing and the ones in the IR objects are not. Stripping
them will prevent us from doing optimizations with them.
By not dead stripping them, We will convert these symbols to
available_externally linkage as a result of non-prevailing and eventually
dropping them after inlining.
I modified cache-prevailing.ll to use linkonce linkage as it is
testing whether cache prevailing bit is effective or not, not
we should treat linkonce_odr alive or not
Reviewers: tejohnson, pcc
Subscribers: mehdi_amini, inglorion, eraman, steven_wu, dexonsmith, llvm-commits
Differential Revision: https://reviews.llvm.org/D52893
llvm-svn: 343970
Oliver Stannard [Mon, 8 Oct 2018 14:12:08 +0000 (14:12 +0000)]
[AArch64][v8.5A] Don't create BR instructions in outliner when BTI enabled
When branch target identification is enabled, we can only do indirect
tail-calls through x16 or x17. This means that the outliner can't
transform a BLR instruction at the end of an outlined region into a BR.
Differential revision: https://reviews.llvm.org/D52869
llvm-svn: 343969
Oliver Stannard [Mon, 8 Oct 2018 14:09:15 +0000 (14:09 +0000)]
[AArch64][v8.5A] Restrict indirect tail calls to use x16/17 only when using BTI
When branch target identification is enabled, all indirectly-callable
functions start with a BTI C instruction. this instruction can only be
the target of certain indirect branches (direct branches and
fall-through are not affected):
- A BLR instruction, in either a protected or unprotected page.
- A BR instruction in a protected page, using x16 or x17.
- A BR instruction in an unprotected page, using any register.
Without BTI, we can use any non call-preserved register to hold the
address for an indirect tail call. However, when BTI is enabled, then
the code being compiled might be loaded into a BTI-protected page, where
only x16 and x17 can be used for indirect tail calls.
Legacy code withiout this restriction can still indirectly tail-call
BTI-protected functions, because they will be loaded into an unprotected
page, so any register is allowed.
Differential revision: https://reviews.llvm.org/D52868
llvm-svn: 343968
Oliver Stannard [Mon, 8 Oct 2018 14:04:24 +0000 (14:04 +0000)]
[AArch64][v8.5A] Branch Target Identification code-generation pass
The Branch Target Identification extension, introduced to AArch64 in
Armv8.5-A, adds the BTI instruction, which is used to mark valid targets
of indirect branches. When enabled, the processor will trap if an
instruction in a protected page tries to perform an indirect branch to
any instruction other than a BTI. The BTI instruction uses encodings
which were NOPs in earlier versions of the architecture, so BTI-enabled
code will still run on earlier hardware, just without the extra
protection.
There are 3 variants of the BTI instruction, which are valid targets for
different kinds or branches:
- BTI C can be targeted by call instructions, and is inteneded to be
used at function entry points. These are the BLR instruction, as well
as BR with x16 or x17. These BR instructions are allowed for use in
PLT entries, and we can also use them to allow indirect tail-calls.
- BTI J can be targeted by BR only, and is intended to be used by jump
tables.
- BTI JC acts ab both a BTI C and a BTI J instruction, and can be
targeted by any BLR or BR instruction.
Note that RET instructions are not restricted by branch target
identification, the reason for this is that return addresses can be
protected more effectively using return address signing. Direct branches
and calls are also unaffected, as it is assumed that an attacker cannot
modify executable pages (if they could, they wouldn't need to do a
ROP/JOP attack).
This patch adds a MachineFunctionPass which:
- Adds a BTI C at the start of every function which could be indirectly
called (either because it is address-taken, or externally visible so
could be address-taken in another translation unit).
- Adds a BTI J at the start of every basic block which could be
indirectly branched to. This could be either done by a jump table, or
by taking the address of the block (e.g. the using GCC label values
extension).
We only need to use BTI JC when a function is indirectly-callable, and
takes the address of the entry block. I've not been able to trigger this
from C or IR, but I've included a MIR test just in case.
Using BTI C at function entries relies on the fact that no other code in
BTI-protected pages uses indirect tail-calls, unless they use x16 or x17
to hold the address. I'll add that code-generation restriction as a
separate patch.
Differential revision: https://reviews.llvm.org/D52867
llvm-svn: 343967
Alexander Ivchenko [Mon, 8 Oct 2018 13:40:34 +0000 (13:40 +0000)]
[GlobalIsel][X86] Support G_UDIV/G_UREM/G_SREM
Support G_UDIV/G_UREM/G_SREM. The instruction selection
code is taken from FastISel with only minor tweaks to adapt
for GlobalISel.
Differential Revision: https://reviews.llvm.org/D49781
llvm-svn: 343966
Sanjay Patel [Mon, 8 Oct 2018 12:54:33 +0000 (12:54 +0000)]
[x86] add 16 missed hadd patterns (PR39195); NFC
llvm-svn: 343965
David Carlier [Mon, 8 Oct 2018 12:18:19 +0000 (12:18 +0000)]
[Sanitizer] fix internal_sysctlbyname build for FreeBSD.
llvm-svn: 343964
Haojian Wu [Mon, 8 Oct 2018 10:44:54 +0000 (10:44 +0000)]
[clangd] Update the out-of-date yaml-symbol-file flag in clangd.
Summary:
The flag is stale due to the recent changes of clangd indexer, this
patch renames the flag to "index-file".
Reviewers: sammccall
Subscribers: ilya-biryukov, ioeric, MaskRay, jkorous, arphaman, kadircet, cfe-commits
Differential Revision: https://reviews.llvm.org/D52976
llvm-svn: 343963
Neil Henning [Mon, 8 Oct 2018 10:32:33 +0000 (10:32 +0000)]
[IRBuilder] Fixup CreateIntrinsic to allow specifying Types to Mangle.
The IRBuilder CreateIntrinsic method wouldn't allow you to specify the
types that you wanted the intrinsic to be mangled with. To fix this
I've:
- Added an ArrayRef<Type *> member to both CreateIntrinsic overloads.
- Used that array to pass into the Intrinsic::getDeclaration call.
- Added a CreateUnaryIntrinsic to replace the most common use of
CreateIntrinsic where the type was auto-deduced from operand 0.
- Added a bunch more unit tests to test Create*Intrinsic calls that
weren't being tested (including the FMF flag that wasn't checked).
This was suggested as part of the AMDGPU specific atomic optimizer
review (https://reviews.llvm.org/D51969).
Differential Revision: https://reviews.llvm.org/D52087
llvm-svn: 343962
Francis Visoiu Mistrih [Mon, 8 Oct 2018 10:28:11 +0000 (10:28 +0000)]
[AsmParser] Return an error in the case of empty symbol ref in an expression
The following instruction:
> str q28, [x0, #1*6*4*@]
contains a @ which is parsed as an empty symbol. The parser returns true
but has no error, so the assembler continues by ignoring the
instruction.
Differential Revision: https://reviews.llvm.org/D52645
llvm-svn: 343961
Peter Smith [Mon, 8 Oct 2018 09:38:28 +0000 (09:38 +0000)]
[ARM] Account for implicit IT when calculating inline asm size
When deciding if it is safe to optimize a conditional branch to a CBZ or
CBNZ the offsets of the BasicBlocks from the start of the function are
estimated. For inline assembly the generic getInlineAsmLength() function is
used to get a worst case estimate of the inline assembly by multiplying the
number of instructions by the max instruction size of 4 bytes. This
unfortunately doesn't take into account the generation of Thumb implicit IT
instructions. In edge cases such as when all the instructions in the block
are 4-bytes in size and there is an implicit IT then the size is
underestimated. This can cause an out of range CBZ or CBNZ to be generated.
The patch takes a conservative approach and assumes that every instruction
in the inline assembly block may have an implicit IT.
Fixes pr31805
Differential Revision: https://reviews.llvm.org/D52834
llvm-svn: 343960
Oliver Stannard [Mon, 8 Oct 2018 09:18:48 +0000 (09:18 +0000)]
[AArch64] Fix verifier error when outlining indirect calls
The MachineOutliner for AArch64 transforms indirect calls into indirect
tail calls, replacing the call with the TCRETURNri pseudo-instruction.
This pseudo lowers to a BR, but has the isCall and isReturn flags set.
The problem is that TCRETURNri takes a tcGPR64 as the register argument,
to prevent indiret tail-calls from using caller-saved registers. The
indirect calls transformed by the outliner could use caller-saved
registers. This is fine, because the outliner ensures that the register
is available at all call sites. However, this causes a verifier failure
when the register is not in tcGPR64. The fix is to add a new
pseudo-instruction like TCRETURNri, but which accepts any GPR.
Differential revision: https://reviews.llvm.org/D52829
llvm-svn: 343959
Alex Bradbury [Mon, 8 Oct 2018 09:08:51 +0000 (09:08 +0000)]
[RISCV] Update alu8.ll and alu16.ll test cases
The srli test in alu8.ll was a no-op, as it shifted by 8 bits. Fix this, and
also change the immediate in alu16.ll as shifted by something other than a
poewr of 8 is more interesting.
llvm-svn: 343958
Kristina Brooks [Mon, 8 Oct 2018 09:03:17 +0000 (09:03 +0000)]
[DebugInfo][PDB] Fix a signed/unsigned coversion warning
Fix the following warning when compiling with clang (caused by commit
rL343951):
GlobalsStream.cpp:61:33: warning: comparison of integers of different
signs: 'int' and 'uint32_t'
This also avoids double evaluation of `GlobalsTable.HashBuckets.size()`.
llvm-svn: 343957
Ewan Crawford [Mon, 8 Oct 2018 08:40:45 +0000 (08:40 +0000)]
[InstCombine] Fix incongruous GEP type addrspace
Currently running the @insertelem_after_gep function below through the InstCombine pass with opt produces invalid IR.
Input:
```
define void @insertelem_after_gep(<16 x i32>* %t0) {
%t1 = bitcast <16 x i32>* %t0 to [16 x i32]*
%t2 = addrspacecast [16 x i32]* %t1 to [16 x i32] addrspace(3)*
%t3 = getelementptr inbounds [16 x i32], [16 x i32] addrspace(3)* %t2, i64 0, i64 0
%t4 = insertelement <16 x i32 addrspace(3)*> undef, i32 addrspace(3)* %t3, i32 0
call void @extern_vec_pointers_func(<16 x i32 addrspace(3)*> %t4)
ret void
}
```
Output:
```
define void @insertelem_after_gep(<16 x i32>* %t0) {
%t3 = getelementptr inbounds <16 x i32>, <16 x i32>* %t0, i64 0, i64 0
%t4 = insertelement <16 x i32 addrspace(3)*> undef, i32 addrspace(3)* %t3, i32 0
call void @my_extern_func(<16 x i32 addrspace(3)*> %t4)
ret void
}
```
Which although causes no complaints when produced, isn't valid IR as the insertelement use of the %t3 GEP expects an address space.
```
opt: /tmp/bad.ll:52:73: error: '%t3' defined with type 'i32*' but expected 'i32 addrspace(3)*'
%t4 = insertelement <16 x i32 addrspace(3)*> undef, i32 addrspace(3)* %t3, i32 0
```
I've fixed this by adding an addrspacecast after the GEP in the InstCombine pass, and including a check for this type mismatch to the verifier.
Reviewers: spatel, lebedev.ri
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D52294
llvm-svn: 343956
Alex Bradbury [Mon, 8 Oct 2018 06:24:59 +0000 (06:24 +0000)]
[SelectionDAGBuilder][NFC] Pass LHSTy to getShiftAmountTy rather than RHSTy
r126518 introduced a a type parameter to the getShiftAmountTy target hook. It
produces the type of the shift (RHSTy), parameterised by the type of the value
being shifted (LHSTy). SelectionDAGBuilder::visitShift passed RHSTy rather
than LHSTy and this patch corrects this. The change is a no-op because in LLVM
IR the LHS and RHS types for a shift must be equal anyway.
llvm-svn: 343955
Max Kazantsev [Mon, 8 Oct 2018 05:46:29 +0000 (05:46 +0000)]
[LV] Do not create SCEVs on broken IR in emitTransformedIndex. PR39160
At the point when we perform `emitTransformedIndex`, we have a broken IR (in
particular, we have Phis for which not every incoming value is properly set). On
such IR, it is illegal to create SCEV expressions, because their internal
simplification process may try to prove some predicates and break when it
stumbles across some broken IR.
The only purpose of using SCEV in this particular place is attempt to simplify
the generated code slightly. It seems that the result isn't worth it, because
some trivial cases (like addition of zero and multiplication by 1) can be
handled separately if needed, but more generally InstCombine is able to achieve
the goals we want to achieve by using SCEV.
This patch fixes a functional crash described in PR39160, and as side-effect it
also generates a bit smarter code in some simple cases. It also may cause some
optimality loss (i.e. we will now generate `mul` by power of `2` instead of
shift etc), but there is nothing what InstCombine could not handle later. In
case of dire need, we can support more trivial cases just in place.
Note that this patch only fixes one particular case of the general problem that
LV misuses SCEV, attempting to create SCEVs or prove predicates on invalid IR.
The general solution, however, seems complex enough.
Differential Revision: https://reviews.llvm.org/D52881
Reviewed By: fhahn, hsaito
llvm-svn: 343954
Zachary Turner [Mon, 8 Oct 2018 04:44:12 +0000 (04:44 +0000)]
Fix a -Wsign-compare warning.
llvm-svn: 343953
Zachary Turner [Mon, 8 Oct 2018 04:34:41 +0000 (04:34 +0000)]
Fix a compilation failure on non-MSVC compilers.
llvm-svn: 343952
Zachary Turner [Mon, 8 Oct 2018 04:19:16 +0000 (04:19 +0000)]
[PDB] Add the ability to lookup global symbols by name.
The Globals table is a hash table keyed on symbol name, so
it's possible to lookup symbols by name in O(1) time. Add
a function to the globals stream to do this, and add an option
to llvm-pdbutil to exercise this, then use it to write some
tests to verify correctness.
llvm-svn: 343951
Craig Topper [Mon, 8 Oct 2018 03:12:12 +0000 (03:12 +0000)]
Revert r343948 "[LegalizeDAG] Make one of the ReplaceNode signatures take an ArrayRef instead a pointer to an array. Add assert on size of array. NFC"
The assert is failing some asan tests on the bots.
llvm-svn: 343950
Brian Gesiak [Mon, 8 Oct 2018 03:08:39 +0000 (03:08 +0000)]
[coro]Pass rvalue reference for named local variable to return_value
Summary:
Addressing https://bugs.llvm.org/show_bug.cgi?id=37265.
Implements [class.copy]/33 of coroutines TS.
When the criteria for elision of a copy/move operation are met, but not
for an exception-declaration, and the object to be copied is designated by an
lvalue, or when the expression in a return or co_return statement is a
(possibly parenthesized) id-expression that names an object with automatic
storage duration declared in the body or parameter-declaration-clause of the
innermost enclosing function or lambda-expression, overload resolution to select
the constructor for the copy or the return_value overload to call is first
performed as if the object were designated by an rvalue.
Patch by Tanoy Sinha!
Reviewers: modocache, GorNishanov
Reviewed By: modocache, GorNishanov
Subscribers: cfe-commits
Differential Revision: https://reviews.llvm.org/D51741
llvm-svn: 343949
Craig Topper [Mon, 8 Oct 2018 02:02:08 +0000 (02:02 +0000)]
[LegalizeDAG] Make one of the ReplaceNode signatures take an ArrayRef instead a pointer to an array. Add assert on size of array. NFC
llvm-svn: 343948
Craig Topper [Mon, 8 Oct 2018 00:04:55 +0000 (00:04 +0000)]
[LegalizeDAG] Move legalization of scatter and masked store from LegalizeVectorOps to LegalizeDAG.
This is where we legalize gather and masked load so this is consistent.
Since these ops are always on vectors I've chosen to go with LegalizeDAG since that's what we do for other vector only ops like BUILD_VECTOR, VECTOR_SHUFFLE, etc. The ScalarizeMaskedMemIntrinsic pass should take care of scalarizing these before SelectionDAG so hopefully we don't need to worry about illegally typed scalar ops being emitted in the legalizing. If we did we would need to do this in LegalizeVectorOps so we could get the second type legalization that runs between LegalizeVectorOps and LegalizeDAG.
llvm-svn: 343947
Fangrui Song [Sun, 7 Oct 2018 17:21:08 +0000 (17:21 +0000)]
[clangd] Migrate to LLVM STLExtras range API
llvm-svn: 343946
Sanjay Patel [Sun, 7 Oct 2018 16:30:42 +0000 (16:30 +0000)]
[DAGCombiner] allow undef elts in vector fadd matching
llvm-svn: 343945
Sanjay Patel [Sun, 7 Oct 2018 16:27:50 +0000 (16:27 +0000)]
[x86] add vector fadd with undef elts test; NFC
llvm-svn: 343944
Sanjay Patel [Sun, 7 Oct 2018 16:13:38 +0000 (16:13 +0000)]
[x86] remove redundant tests; NFC
The equivalent tests were added to the file with related folds in rL343941.
llvm-svn: 343943
Sanjay Patel [Sun, 7 Oct 2018 16:05:37 +0000 (16:05 +0000)]
[DAGCombiner] allow undefs when matching vector splats for fmul folds
llvm-svn: 343942
Sanjay Patel [Sun, 7 Oct 2018 16:00:55 +0000 (16:00 +0000)]
[x86] add vector fmul with undef elts tests; NFC
llvm-svn: 343941
Sanjay Patel [Sun, 7 Oct 2018 15:32:06 +0000 (15:32 +0000)]
[DAGCombiner] allow undef elts in vector fabs/fneg matching
This change is proposed as a part of D44548, but we
need this independently to avoid regressions from improved
undef propagation in SimplifyDemandedVectorElts().
llvm-svn: 343940
Sanjay Patel [Sun, 7 Oct 2018 15:18:30 +0000 (15:18 +0000)]
[DAGCombiner] shorten code for bitcast+fabs fold; NFC
llvm-svn: 343939